projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium: replace INLINE with inline
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
63
64
65 #define DEBUG_EXECUTION 0
66
67
68 #define FAST_MATH 0
69
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
74
75 union tgsi_double_channel {
76 double d[TGSI_QUAD_SIZE];
77 unsigned u[TGSI_QUAD_SIZE][2];
78 };
79
80 struct tgsi_double_vector {
81 union tgsi_double_channel xy;
82 union tgsi_double_channel zw;
83 };
84
85 static void
86 micro_abs(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
88 {
89 dst->f[0] = fabsf(src->f[0]);
90 dst->f[1] = fabsf(src->f[1]);
91 dst->f[2] = fabsf(src->f[2]);
92 dst->f[3] = fabsf(src->f[3]);
93 }
94
95 static void
96 micro_arl(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
98 {
99 dst->i[0] = (int)floorf(src->f[0]);
100 dst->i[1] = (int)floorf(src->f[1]);
101 dst->i[2] = (int)floorf(src->f[2]);
102 dst->i[3] = (int)floorf(src->f[3]);
103 }
104
105 static void
106 micro_arr(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
108 {
109 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
110 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
111 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
112 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
113 }
114
115 static void
116 micro_ceil(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src)
118 {
119 dst->f[0] = ceilf(src->f[0]);
120 dst->f[1] = ceilf(src->f[1]);
121 dst->f[2] = ceilf(src->f[2]);
122 dst->f[3] = ceilf(src->f[3]);
123 }
124
125 static void
126 micro_clamp(union tgsi_exec_channel *dst,
127 const union tgsi_exec_channel *src0,
128 const union tgsi_exec_channel *src1,
129 const union tgsi_exec_channel *src2)
130 {
131 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
132 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
133 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
134 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
135 }
136
137 static void
138 micro_cmp(union tgsi_exec_channel *dst,
139 const union tgsi_exec_channel *src0,
140 const union tgsi_exec_channel *src1,
141 const union tgsi_exec_channel *src2)
142 {
143 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
144 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
145 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
146 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
147 }
148
149 static void
150 micro_cos(union tgsi_exec_channel *dst,
151 const union tgsi_exec_channel *src)
152 {
153 dst->f[0] = cosf(src->f[0]);
154 dst->f[1] = cosf(src->f[1]);
155 dst->f[2] = cosf(src->f[2]);
156 dst->f[3] = cosf(src->f[3]);
157 }
158
159 static void
160 micro_d2f(union tgsi_exec_channel *dst,
161 const union tgsi_double_channel *src)
162 {
163 dst->f[0] = (float)src->d[0];
164 dst->f[1] = (float)src->d[1];
165 dst->f[2] = (float)src->d[2];
166 dst->f[3] = (float)src->d[3];
167 }
168
169 static void
170 micro_d2i(union tgsi_exec_channel *dst,
171 const union tgsi_double_channel *src)
172 {
173 dst->i[0] = (int)src->d[0];
174 dst->i[1] = (int)src->d[1];
175 dst->i[2] = (int)src->d[2];
176 dst->i[3] = (int)src->d[3];
177 }
178
179 static void
180 micro_d2u(union tgsi_exec_channel *dst,
181 const union tgsi_double_channel *src)
182 {
183 dst->u[0] = (unsigned)src->d[0];
184 dst->u[1] = (unsigned)src->d[1];
185 dst->u[2] = (unsigned)src->d[2];
186 dst->u[3] = (unsigned)src->d[3];
187 }
188 static void
189 micro_dabs(union tgsi_double_channel *dst,
190 const union tgsi_double_channel *src)
191 {
192 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
193 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
194 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
195 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
196 }
197
198 static void
199 micro_dadd(union tgsi_double_channel *dst,
200 const union tgsi_double_channel *src)
201 {
202 dst->d[0] = src[0].d[0] + src[1].d[0];
203 dst->d[1] = src[0].d[1] + src[1].d[1];
204 dst->d[2] = src[0].d[2] + src[1].d[2];
205 dst->d[3] = src[0].d[3] + src[1].d[3];
206 }
207
208 static void
209 micro_ddx(union tgsi_exec_channel *dst,
210 const union tgsi_exec_channel *src)
211 {
212 dst->f[0] =
213 dst->f[1] =
214 dst->f[2] =
215 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
216 }
217
218 static void
219 micro_ddy(union tgsi_exec_channel *dst,
220 const union tgsi_exec_channel *src)
221 {
222 dst->f[0] =
223 dst->f[1] =
224 dst->f[2] =
225 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
226 }
227
228 static void
229 micro_dmul(union tgsi_double_channel *dst,
230 const union tgsi_double_channel *src)
231 {
232 dst->d[0] = src[0].d[0] * src[1].d[0];
233 dst->d[1] = src[0].d[1] * src[1].d[1];
234 dst->d[2] = src[0].d[2] * src[1].d[2];
235 dst->d[3] = src[0].d[3] * src[1].d[3];
236 }
237
238 static void
239 micro_dmax(union tgsi_double_channel *dst,
240 const union tgsi_double_channel *src)
241 {
242 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
243 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
244 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
245 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
246 }
247
248 static void
249 micro_dmin(union tgsi_double_channel *dst,
250 const union tgsi_double_channel *src)
251 {
252 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
253 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
254 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
255 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
256 }
257
258 static void
259 micro_dneg(union tgsi_double_channel *dst,
260 const union tgsi_double_channel *src)
261 {
262 dst->d[0] = -src->d[0];
263 dst->d[1] = -src->d[1];
264 dst->d[2] = -src->d[2];
265 dst->d[3] = -src->d[3];
266 }
267
268 static void
269 micro_dslt(union tgsi_double_channel *dst,
270 const union tgsi_double_channel *src)
271 {
272 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
273 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
274 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
275 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
276 }
277
278 static void
279 micro_dsne(union tgsi_double_channel *dst,
280 const union tgsi_double_channel *src)
281 {
282 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
283 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
284 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
285 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
286 }
287
288 static void
289 micro_dsge(union tgsi_double_channel *dst,
290 const union tgsi_double_channel *src)
291 {
292 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
293 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
294 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
295 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
296 }
297
298 static void
299 micro_dseq(union tgsi_double_channel *dst,
300 const union tgsi_double_channel *src)
301 {
302 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
303 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
304 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
305 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
306 }
307
308 static void
309 micro_drcp(union tgsi_double_channel *dst,
310 const union tgsi_double_channel *src)
311 {
312 dst->d[0] = 1.0 / src->d[0];
313 dst->d[1] = 1.0 / src->d[1];
314 dst->d[2] = 1.0 / src->d[2];
315 dst->d[3] = 1.0 / src->d[3];
316 }
317
318 static void
319 micro_dsqrt(union tgsi_double_channel *dst,
320 const union tgsi_double_channel *src)
321 {
322 dst->d[0] = sqrt(src->d[0]);
323 dst->d[1] = sqrt(src->d[1]);
324 dst->d[2] = sqrt(src->d[2]);
325 dst->d[3] = sqrt(src->d[3]);
326 }
327
328 static void
329 micro_drsq(union tgsi_double_channel *dst,
330 const union tgsi_double_channel *src)
331 {
332 dst->d[0] = 1.0 / sqrt(src->d[0]);
333 dst->d[1] = 1.0 / sqrt(src->d[1]);
334 dst->d[2] = 1.0 / sqrt(src->d[2]);
335 dst->d[3] = 1.0 / sqrt(src->d[3]);
336 }
337
338 static void
339 micro_dmad(union tgsi_double_channel *dst,
340 const union tgsi_double_channel *src)
341 {
342 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
343 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
344 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
345 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
346 }
347
348 static void
349 micro_dfrac(union tgsi_double_channel *dst,
350 const union tgsi_double_channel *src)
351 {
352 dst->d[0] = src->d[0] - floor(src->d[0]);
353 dst->d[1] = src->d[1] - floor(src->d[1]);
354 dst->d[2] = src->d[2] - floor(src->d[2]);
355 dst->d[3] = src->d[3] - floor(src->d[3]);
356 }
357
358 static void
359 micro_dldexp(union tgsi_double_channel *dst,
360 const union tgsi_double_channel *src0,
361 union tgsi_exec_channel *src1)
362 {
363 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
364 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
365 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
366 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
367 }
368
369 static void
370 micro_dfracexp(union tgsi_double_channel *dst,
371 union tgsi_exec_channel *dst_exp,
372 const union tgsi_double_channel *src)
373 {
374 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
375 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
376 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
377 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
378 }
379
380 static void
381 micro_exp2(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
383 {
384 #if FAST_MATH
385 dst->f[0] = util_fast_exp2(src->f[0]);
386 dst->f[1] = util_fast_exp2(src->f[1]);
387 dst->f[2] = util_fast_exp2(src->f[2]);
388 dst->f[3] = util_fast_exp2(src->f[3]);
389 #else
390 #if DEBUG
391 /* Inf is okay for this instruction, so clamp it to silence assertions. */
392 uint i;
393 union tgsi_exec_channel clamped;
394
395 for (i = 0; i < 4; i++) {
396 if (src->f[i] > 127.99999f) {
397 clamped.f[i] = 127.99999f;
398 } else if (src->f[i] < -126.99999f) {
399 clamped.f[i] = -126.99999f;
400 } else {
401 clamped.f[i] = src->f[i];
402 }
403 }
404 src = &clamped;
405 #endif /* DEBUG */
406
407 dst->f[0] = powf(2.0f, src->f[0]);
408 dst->f[1] = powf(2.0f, src->f[1]);
409 dst->f[2] = powf(2.0f, src->f[2]);
410 dst->f[3] = powf(2.0f, src->f[3]);
411 #endif /* FAST_MATH */
412 }
413
414 static void
415 micro_f2d(union tgsi_double_channel *dst,
416 const union tgsi_exec_channel *src)
417 {
418 dst->d[0] = (double)src->f[0];
419 dst->d[1] = (double)src->f[1];
420 dst->d[2] = (double)src->f[2];
421 dst->d[3] = (double)src->f[3];
422 }
423
424 static void
425 micro_flr(union tgsi_exec_channel *dst,
426 const union tgsi_exec_channel *src)
427 {
428 dst->f[0] = floorf(src->f[0]);
429 dst->f[1] = floorf(src->f[1]);
430 dst->f[2] = floorf(src->f[2]);
431 dst->f[3] = floorf(src->f[3]);
432 }
433
434 static void
435 micro_frc(union tgsi_exec_channel *dst,
436 const union tgsi_exec_channel *src)
437 {
438 dst->f[0] = src->f[0] - floorf(src->f[0]);
439 dst->f[1] = src->f[1] - floorf(src->f[1]);
440 dst->f[2] = src->f[2] - floorf(src->f[2]);
441 dst->f[3] = src->f[3] - floorf(src->f[3]);
442 }
443
444 static void
445 micro_i2d(union tgsi_double_channel *dst,
446 const union tgsi_exec_channel *src)
447 {
448 dst->d[0] = (double)src->i[0];
449 dst->d[1] = (double)src->i[1];
450 dst->d[2] = (double)src->i[2];
451 dst->d[3] = (double)src->i[3];
452 }
453
454 static void
455 micro_iabs(union tgsi_exec_channel *dst,
456 const union tgsi_exec_channel *src)
457 {
458 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
459 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
460 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
461 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
462 }
463
464 static void
465 micro_ineg(union tgsi_exec_channel *dst,
466 const union tgsi_exec_channel *src)
467 {
468 dst->i[0] = -src->i[0];
469 dst->i[1] = -src->i[1];
470 dst->i[2] = -src->i[2];
471 dst->i[3] = -src->i[3];
472 }
473
474 static void
475 micro_lg2(union tgsi_exec_channel *dst,
476 const union tgsi_exec_channel *src)
477 {
478 #if FAST_MATH
479 dst->f[0] = util_fast_log2(src->f[0]);
480 dst->f[1] = util_fast_log2(src->f[1]);
481 dst->f[2] = util_fast_log2(src->f[2]);
482 dst->f[3] = util_fast_log2(src->f[3]);
483 #else
484 dst->f[0] = logf(src->f[0]) * 1.442695f;
485 dst->f[1] = logf(src->f[1]) * 1.442695f;
486 dst->f[2] = logf(src->f[2]) * 1.442695f;
487 dst->f[3] = logf(src->f[3]) * 1.442695f;
488 #endif
489 }
490
491 static void
492 micro_lrp(union tgsi_exec_channel *dst,
493 const union tgsi_exec_channel *src0,
494 const union tgsi_exec_channel *src1,
495 const union tgsi_exec_channel *src2)
496 {
497 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
498 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
499 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
500 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
501 }
502
503 static void
504 micro_mad(union tgsi_exec_channel *dst,
505 const union tgsi_exec_channel *src0,
506 const union tgsi_exec_channel *src1,
507 const union tgsi_exec_channel *src2)
508 {
509 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
510 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
511 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
512 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
513 }
514
515 static void
516 micro_mov(union tgsi_exec_channel *dst,
517 const union tgsi_exec_channel *src)
518 {
519 dst->u[0] = src->u[0];
520 dst->u[1] = src->u[1];
521 dst->u[2] = src->u[2];
522 dst->u[3] = src->u[3];
523 }
524
525 static void
526 micro_rcp(union tgsi_exec_channel *dst,
527 const union tgsi_exec_channel *src)
528 {
529 #if 0 /* for debugging */
530 assert(src->f[0] != 0.0f);
531 assert(src->f[1] != 0.0f);
532 assert(src->f[2] != 0.0f);
533 assert(src->f[3] != 0.0f);
534 #endif
535 dst->f[0] = 1.0f / src->f[0];
536 dst->f[1] = 1.0f / src->f[1];
537 dst->f[2] = 1.0f / src->f[2];
538 dst->f[3] = 1.0f / src->f[3];
539 }
540
541 static void
542 micro_rnd(union tgsi_exec_channel *dst,
543 const union tgsi_exec_channel *src)
544 {
545 dst->f[0] = floorf(src->f[0] + 0.5f);
546 dst->f[1] = floorf(src->f[1] + 0.5f);
547 dst->f[2] = floorf(src->f[2] + 0.5f);
548 dst->f[3] = floorf(src->f[3] + 0.5f);
549 }
550
551 static void
552 micro_rsq(union tgsi_exec_channel *dst,
553 const union tgsi_exec_channel *src)
554 {
555 #if 0 /* for debugging */
556 assert(src->f[0] != 0.0f);
557 assert(src->f[1] != 0.0f);
558 assert(src->f[2] != 0.0f);
559 assert(src->f[3] != 0.0f);
560 #endif
561 dst->f[0] = 1.0f / sqrtf(src->f[0]);
562 dst->f[1] = 1.0f / sqrtf(src->f[1]);
563 dst->f[2] = 1.0f / sqrtf(src->f[2]);
564 dst->f[3] = 1.0f / sqrtf(src->f[3]);
565 }
566
567 static void
568 micro_sqrt(union tgsi_exec_channel *dst,
569 const union tgsi_exec_channel *src)
570 {
571 dst->f[0] = sqrtf(src->f[0]);
572 dst->f[1] = sqrtf(src->f[1]);
573 dst->f[2] = sqrtf(src->f[2]);
574 dst->f[3] = sqrtf(src->f[3]);
575 }
576
577 static void
578 micro_seq(union tgsi_exec_channel *dst,
579 const union tgsi_exec_channel *src0,
580 const union tgsi_exec_channel *src1)
581 {
582 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
583 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
584 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
585 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
586 }
587
588 static void
589 micro_sge(union tgsi_exec_channel *dst,
590 const union tgsi_exec_channel *src0,
591 const union tgsi_exec_channel *src1)
592 {
593 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
594 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
595 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
596 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
597 }
598
599 static void
600 micro_sgn(union tgsi_exec_channel *dst,
601 const union tgsi_exec_channel *src)
602 {
603 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
604 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
605 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
606 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
607 }
608
609 static void
610 micro_isgn(union tgsi_exec_channel *dst,
611 const union tgsi_exec_channel *src)
612 {
613 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
614 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
615 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
616 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
617 }
618
619 static void
620 micro_sgt(union tgsi_exec_channel *dst,
621 const union tgsi_exec_channel *src0,
622 const union tgsi_exec_channel *src1)
623 {
624 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
625 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
626 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
627 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
628 }
629
630 static void
631 micro_sin(union tgsi_exec_channel *dst,
632 const union tgsi_exec_channel *src)
633 {
634 dst->f[0] = sinf(src->f[0]);
635 dst->f[1] = sinf(src->f[1]);
636 dst->f[2] = sinf(src->f[2]);
637 dst->f[3] = sinf(src->f[3]);
638 }
639
640 static void
641 micro_sle(union tgsi_exec_channel *dst,
642 const union tgsi_exec_channel *src0,
643 const union tgsi_exec_channel *src1)
644 {
645 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
646 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
647 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
648 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
649 }
650
651 static void
652 micro_slt(union tgsi_exec_channel *dst,
653 const union tgsi_exec_channel *src0,
654 const union tgsi_exec_channel *src1)
655 {
656 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
657 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
658 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
659 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
660 }
661
662 static void
663 micro_sne(union tgsi_exec_channel *dst,
664 const union tgsi_exec_channel *src0,
665 const union tgsi_exec_channel *src1)
666 {
667 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
668 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
669 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
670 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
671 }
672
673 static void
674 micro_trunc(union tgsi_exec_channel *dst,
675 const union tgsi_exec_channel *src)
676 {
677 dst->f[0] = (float)(int)src->f[0];
678 dst->f[1] = (float)(int)src->f[1];
679 dst->f[2] = (float)(int)src->f[2];
680 dst->f[3] = (float)(int)src->f[3];
681 }
682
683 static void
684 micro_u2d(union tgsi_double_channel *dst,
685 const union tgsi_exec_channel *src)
686 {
687 dst->d[0] = (double)src->u[0];
688 dst->d[1] = (double)src->u[1];
689 dst->d[2] = (double)src->u[2];
690 dst->d[3] = (double)src->u[3];
691 }
692
693 enum tgsi_exec_datatype {
694 TGSI_EXEC_DATA_FLOAT,
695 TGSI_EXEC_DATA_INT,
696 TGSI_EXEC_DATA_UINT,
697 TGSI_EXEC_DATA_DOUBLE
698 };
699
700 /*
701 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
702 */
703 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
704 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
705 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
706 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
707 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
708 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
709
710
711 /** The execution mask depends on the conditional mask and the loop mask */
712 #define UPDATE_EXEC_MASK(MACH) \
713 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
714
715
716 static const union tgsi_exec_channel ZeroVec =
717 { { 0.0, 0.0, 0.0, 0.0 } };
718
719 static const union tgsi_exec_channel OneVec = {
720 {1.0f, 1.0f, 1.0f, 1.0f}
721 };
722
723 static const union tgsi_exec_channel P128Vec = {
724 {128.0f, 128.0f, 128.0f, 128.0f}
725 };
726
727 static const union tgsi_exec_channel M128Vec = {
728 {-128.0f, -128.0f, -128.0f, -128.0f}
729 };
730
731
732 /**
733 * Assert that none of the float values in 'chan' are infinite or NaN.
734 * NaN and Inf may occur normally during program execution and should
735 * not lead to crashes, etc. But when debugging, it's helpful to catch
736 * them.
737 */
738 static inline void
739 check_inf_or_nan(const union tgsi_exec_channel *chan)
740 {
741 assert(!util_is_inf_or_nan((chan)->f[0]));
742 assert(!util_is_inf_or_nan((chan)->f[1]));
743 assert(!util_is_inf_or_nan((chan)->f[2]));
744 assert(!util_is_inf_or_nan((chan)->f[3]));
745 }
746
747
748 #ifdef DEBUG
749 static void
750 print_chan(const char *msg, const union tgsi_exec_channel *chan)
751 {
752 debug_printf("%s = {%f, %f, %f, %f}\n",
753 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
754 }
755 #endif
756
757
758 #ifdef DEBUG
759 static void
760 print_temp(const struct tgsi_exec_machine *mach, uint index)
761 {
762 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
763 int i;
764 debug_printf("Temp[%u] =\n", index);
765 for (i = 0; i < 4; i++) {
766 debug_printf(" %c: { %f, %f, %f, %f }\n",
767 "XYZW"[i],
768 tmp->xyzw[i].f[0],
769 tmp->xyzw[i].f[1],
770 tmp->xyzw[i].f[2],
771 tmp->xyzw[i].f[3]);
772 }
773 }
774 #endif
775
776
777 void
778 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
779 unsigned num_bufs,
780 const void **bufs,
781 const unsigned *buf_sizes)
782 {
783 unsigned i;
784
785 for (i = 0; i < num_bufs; i++) {
786 mach->Consts[i] = bufs[i];
787 mach->ConstsSize[i] = buf_sizes[i];
788 }
789 }
790
791
792 /**
793 * Check if there's a potential src/dst register data dependency when
794 * using SOA execution.
795 * Example:
796 * MOV T, T.yxwz;
797 * This would expand into:
798 * MOV t0, t1;
799 * MOV t1, t0;
800 * MOV t2, t3;
801 * MOV t3, t2;
802 * The second instruction will have the wrong value for t0 if executed as-is.
803 */
804 boolean
805 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
806 {
807 uint i, chan;
808
809 uint writemask = inst->Dst[0].Register.WriteMask;
810 if (writemask == TGSI_WRITEMASK_X ||
811 writemask == TGSI_WRITEMASK_Y ||
812 writemask == TGSI_WRITEMASK_Z ||
813 writemask == TGSI_WRITEMASK_W ||
814 writemask == TGSI_WRITEMASK_NONE) {
815 /* no chance of data dependency */
816 return FALSE;
817 }
818
819 /* loop over src regs */
820 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
821 if ((inst->Src[i].Register.File ==
822 inst->Dst[0].Register.File) &&
823 ((inst->Src[i].Register.Index ==
824 inst->Dst[0].Register.Index) ||
825 inst->Src[i].Register.Indirect ||
826 inst->Dst[0].Register.Indirect)) {
827 /* loop over dest channels */
828 uint channelsWritten = 0x0;
829 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
830 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
831 /* check if we're reading a channel that's been written */
832 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
833 if (channelsWritten & (1 << swizzle)) {
834 return TRUE;
835 }
836
837 channelsWritten |= (1 << chan);
838 }
839 }
840 }
841 }
842 return FALSE;
843 }
844
845
846 /**
847 * Initialize machine state by expanding tokens to full instructions,
848 * allocating temporary storage, setting up constants, etc.
849 * After this, we can call tgsi_exec_machine_run() many times.
850 */
851 void
852 tgsi_exec_machine_bind_shader(
853 struct tgsi_exec_machine *mach,
854 const struct tgsi_token *tokens,
855 struct tgsi_sampler *sampler)
856 {
857 uint k;
858 struct tgsi_parse_context parse;
859 struct tgsi_full_instruction *instructions;
860 struct tgsi_full_declaration *declarations;
861 uint maxInstructions = 10, numInstructions = 0;
862 uint maxDeclarations = 10, numDeclarations = 0;
863
864 #if 0
865 tgsi_dump(tokens, 0);
866 #endif
867
868 util_init_math();
869
870
871 mach->Tokens = tokens;
872 mach->Sampler = sampler;
873
874 if (!tokens) {
875 /* unbind and free all */
876 FREE(mach->Declarations);
877 mach->Declarations = NULL;
878 mach->NumDeclarations = 0;
879
880 FREE(mach->Instructions);
881 mach->Instructions = NULL;
882 mach->NumInstructions = 0;
883
884 return;
885 }
886
887 k = tgsi_parse_init (&parse, mach->Tokens);
888 if (k != TGSI_PARSE_OK) {
889 debug_printf( "Problem parsing!\n" );
890 return;
891 }
892
893 mach->Processor = parse.FullHeader.Processor.Processor;
894 mach->ImmLimit = 0;
895 mach->NumOutputs = 0;
896
897 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
898 !mach->UsedGeometryShader) {
899 struct tgsi_exec_vector *inputs;
900 struct tgsi_exec_vector *outputs;
901
902 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
903 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
904 16);
905
906 if (!inputs)
907 return;
908
909 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
910 TGSI_MAX_TOTAL_VERTICES, 16);
911
912 if (!outputs) {
913 align_free(inputs);
914 return;
915 }
916
917 align_free(mach->Inputs);
918 align_free(mach->Outputs);
919
920 mach->Inputs = inputs;
921 mach->Outputs = outputs;
922 mach->UsedGeometryShader = TRUE;
923 }
924
925 declarations = (struct tgsi_full_declaration *)
926 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
927
928 if (!declarations) {
929 return;
930 }
931
932 instructions = (struct tgsi_full_instruction *)
933 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
934
935 if (!instructions) {
936 FREE( declarations );
937 return;
938 }
939
940 while( !tgsi_parse_end_of_tokens( &parse ) ) {
941 uint i;
942
943 tgsi_parse_token( &parse );
944 switch( parse.FullToken.Token.Type ) {
945 case TGSI_TOKEN_TYPE_DECLARATION:
946 /* save expanded declaration */
947 if (numDeclarations == maxDeclarations) {
948 declarations = REALLOC(declarations,
949 maxDeclarations
950 * sizeof(struct tgsi_full_declaration),
951 (maxDeclarations + 10)
952 * sizeof(struct tgsi_full_declaration));
953 maxDeclarations += 10;
954 }
955 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
956 unsigned reg;
957 for (reg = parse.FullToken.FullDeclaration.Range.First;
958 reg <= parse.FullToken.FullDeclaration.Range.Last;
959 ++reg) {
960 ++mach->NumOutputs;
961 }
962 }
963 memcpy(declarations + numDeclarations,
964 &parse.FullToken.FullDeclaration,
965 sizeof(declarations[0]));
966 numDeclarations++;
967 break;
968
969 case TGSI_TOKEN_TYPE_IMMEDIATE:
970 {
971 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
972 assert( size <= 4 );
973 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
974
975 for( i = 0; i < size; i++ ) {
976 mach->Imms[mach->ImmLimit][i] =
977 parse.FullToken.FullImmediate.u[i].Float;
978 }
979 mach->ImmLimit += 1;
980 }
981 break;
982
983 case TGSI_TOKEN_TYPE_INSTRUCTION:
984
985 /* save expanded instruction */
986 if (numInstructions == maxInstructions) {
987 instructions = REALLOC(instructions,
988 maxInstructions
989 * sizeof(struct tgsi_full_instruction),
990 (maxInstructions + 10)
991 * sizeof(struct tgsi_full_instruction));
992 maxInstructions += 10;
993 }
994
995 memcpy(instructions + numInstructions,
996 &parse.FullToken.FullInstruction,
997 sizeof(instructions[0]));
998
999 numInstructions++;
1000 break;
1001
1002 case TGSI_TOKEN_TYPE_PROPERTY:
1003 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) {
1004 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1005 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1006 }
1007 }
1008 break;
1009
1010 default:
1011 assert( 0 );
1012 }
1013 }
1014 tgsi_parse_free (&parse);
1015
1016 FREE(mach->Declarations);
1017 mach->Declarations = declarations;
1018 mach->NumDeclarations = numDeclarations;
1019
1020 FREE(mach->Instructions);
1021 mach->Instructions = instructions;
1022 mach->NumInstructions = numInstructions;
1023 }
1024
1025
1026 struct tgsi_exec_machine *
1027 tgsi_exec_machine_create( void )
1028 {
1029 struct tgsi_exec_machine *mach;
1030 uint i;
1031
1032 mach = align_malloc( sizeof *mach, 16 );
1033 if (!mach)
1034 goto fail;
1035
1036 memset(mach, 0, sizeof(*mach));
1037
1038 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1039 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1040 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1041
1042 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1043 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1044 if (!mach->Inputs || !mach->Outputs)
1045 goto fail;
1046
1047 /* Setup constants needed by the SSE2 executor. */
1048 for( i = 0; i < 4; i++ ) {
1049 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1050 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1051 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1052 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1053 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1054 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1055 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1056 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1057 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1058 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1059 }
1060
1061 #ifdef DEBUG
1062 /* silence warnings */
1063 (void) print_chan;
1064 (void) print_temp;
1065 #endif
1066
1067 return mach;
1068
1069 fail:
1070 if (mach) {
1071 align_free(mach->Inputs);
1072 align_free(mach->Outputs);
1073 align_free(mach);
1074 }
1075 return NULL;
1076 }
1077
1078
1079 void
1080 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1081 {
1082 if (mach) {
1083 FREE(mach->Instructions);
1084 FREE(mach->Declarations);
1085
1086 align_free(mach->Inputs);
1087 align_free(mach->Outputs);
1088
1089 align_free(mach);
1090 }
1091 }
1092
1093 static void
1094 micro_add(union tgsi_exec_channel *dst,
1095 const union tgsi_exec_channel *src0,
1096 const union tgsi_exec_channel *src1)
1097 {
1098 dst->f[0] = src0->f[0] + src1->f[0];
1099 dst->f[1] = src0->f[1] + src1->f[1];
1100 dst->f[2] = src0->f[2] + src1->f[2];
1101 dst->f[3] = src0->f[3] + src1->f[3];
1102 }
1103
1104 static void
1105 micro_div(
1106 union tgsi_exec_channel *dst,
1107 const union tgsi_exec_channel *src0,
1108 const union tgsi_exec_channel *src1 )
1109 {
1110 if (src1->f[0] != 0) {
1111 dst->f[0] = src0->f[0] / src1->f[0];
1112 }
1113 if (src1->f[1] != 0) {
1114 dst->f[1] = src0->f[1] / src1->f[1];
1115 }
1116 if (src1->f[2] != 0) {
1117 dst->f[2] = src0->f[2] / src1->f[2];
1118 }
1119 if (src1->f[3] != 0) {
1120 dst->f[3] = src0->f[3] / src1->f[3];
1121 }
1122 }
1123
1124 static void
1125 micro_lt(
1126 union tgsi_exec_channel *dst,
1127 const union tgsi_exec_channel *src0,
1128 const union tgsi_exec_channel *src1,
1129 const union tgsi_exec_channel *src2,
1130 const union tgsi_exec_channel *src3 )
1131 {
1132 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1133 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1134 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1135 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1136 }
1137
1138 static void
1139 micro_max(union tgsi_exec_channel *dst,
1140 const union tgsi_exec_channel *src0,
1141 const union tgsi_exec_channel *src1)
1142 {
1143 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1144 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1145 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1146 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1147 }
1148
1149 static void
1150 micro_min(union tgsi_exec_channel *dst,
1151 const union tgsi_exec_channel *src0,
1152 const union tgsi_exec_channel *src1)
1153 {
1154 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1155 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1156 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1157 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1158 }
1159
1160 static void
1161 micro_mul(union tgsi_exec_channel *dst,
1162 const union tgsi_exec_channel *src0,
1163 const union tgsi_exec_channel *src1)
1164 {
1165 dst->f[0] = src0->f[0] * src1->f[0];
1166 dst->f[1] = src0->f[1] * src1->f[1];
1167 dst->f[2] = src0->f[2] * src1->f[2];
1168 dst->f[3] = src0->f[3] * src1->f[3];
1169 }
1170
1171 static void
1172 micro_neg(
1173 union tgsi_exec_channel *dst,
1174 const union tgsi_exec_channel *src )
1175 {
1176 dst->f[0] = -src->f[0];
1177 dst->f[1] = -src->f[1];
1178 dst->f[2] = -src->f[2];
1179 dst->f[3] = -src->f[3];
1180 }
1181
1182 static void
1183 micro_pow(
1184 union tgsi_exec_channel *dst,
1185 const union tgsi_exec_channel *src0,
1186 const union tgsi_exec_channel *src1 )
1187 {
1188 #if FAST_MATH
1189 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1190 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1191 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1192 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1193 #else
1194 dst->f[0] = powf( src0->f[0], src1->f[0] );
1195 dst->f[1] = powf( src0->f[1], src1->f[1] );
1196 dst->f[2] = powf( src0->f[2], src1->f[2] );
1197 dst->f[3] = powf( src0->f[3], src1->f[3] );
1198 #endif
1199 }
1200
1201 static void
1202 micro_sub(union tgsi_exec_channel *dst,
1203 const union tgsi_exec_channel *src0,
1204 const union tgsi_exec_channel *src1)
1205 {
1206 dst->f[0] = src0->f[0] - src1->f[0];
1207 dst->f[1] = src0->f[1] - src1->f[1];
1208 dst->f[2] = src0->f[2] - src1->f[2];
1209 dst->f[3] = src0->f[3] - src1->f[3];
1210 }
1211
1212 static void
1213 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1214 const uint chan_index,
1215 const uint file,
1216 const uint swizzle,
1217 const union tgsi_exec_channel *index,
1218 const union tgsi_exec_channel *index2D,
1219 union tgsi_exec_channel *chan)
1220 {
1221 uint i;
1222
1223 assert(swizzle < 4);
1224
1225 switch (file) {
1226 case TGSI_FILE_CONSTANT:
1227 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1228 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1229 assert(mach->Consts[index2D->i[i]]);
1230
1231 if (index->i[i] < 0) {
1232 chan->u[i] = 0;
1233 } else {
1234 /* NOTE: copying the const value as a uint instead of float */
1235 const uint constbuf = index2D->i[i];
1236 const uint *buf = (const uint *)mach->Consts[constbuf];
1237 const int pos = index->i[i] * 4 + swizzle;
1238 /* const buffer bounds check */
1239 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1240 if (0) {
1241 /* Debug: print warning */
1242 static int count = 0;
1243 if (count++ < 100)
1244 debug_printf("TGSI Exec: const buffer index %d"
1245 " out of bounds\n", pos);
1246 }
1247 chan->u[i] = 0;
1248 }
1249 else
1250 chan->u[i] = buf[pos];
1251 }
1252 }
1253 break;
1254
1255 case TGSI_FILE_INPUT:
1256 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1257 /*
1258 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1259 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1260 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1261 index2D->i[i], index->i[i]);
1262 }*/
1263 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1264 assert(pos >= 0);
1265 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1266 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1267 }
1268 break;
1269
1270 case TGSI_FILE_SYSTEM_VALUE:
1271 /* XXX no swizzling at this point. Will be needed if we put
1272 * gl_FragCoord, for example, in a sys value register.
1273 */
1274 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1275 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1276 }
1277 break;
1278
1279 case TGSI_FILE_TEMPORARY:
1280 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1281 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1282 assert(index2D->i[i] == 0);
1283
1284 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1285 }
1286 break;
1287
1288 case TGSI_FILE_IMMEDIATE:
1289 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1290 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1291 assert(index2D->i[i] == 0);
1292
1293 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1294 }
1295 break;
1296
1297 case TGSI_FILE_ADDRESS:
1298 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1299 assert(index->i[i] >= 0);
1300 assert(index2D->i[i] == 0);
1301
1302 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1303 }
1304 break;
1305
1306 case TGSI_FILE_PREDICATE:
1307 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1308 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1309 assert(index2D->i[i] == 0);
1310
1311 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1312 }
1313 break;
1314
1315 case TGSI_FILE_OUTPUT:
1316 /* vertex/fragment output vars can be read too */
1317 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1318 assert(index->i[i] >= 0);
1319 assert(index2D->i[i] == 0);
1320
1321 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1322 }
1323 break;
1324
1325 default:
1326 assert(0);
1327 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1328 chan->u[i] = 0;
1329 }
1330 }
1331 }
1332
1333 static void
1334 fetch_source_d(const struct tgsi_exec_machine *mach,
1335 union tgsi_exec_channel *chan,
1336 const struct tgsi_full_src_register *reg,
1337 const uint chan_index,
1338 enum tgsi_exec_datatype src_datatype)
1339 {
1340 union tgsi_exec_channel index;
1341 union tgsi_exec_channel index2D;
1342 uint swizzle;
1343
1344 /* We start with a direct index into a register file.
1345 *
1346 * file[1],
1347 * where:
1348 * file = Register.File
1349 * [1] = Register.Index
1350 */
1351 index.i[0] =
1352 index.i[1] =
1353 index.i[2] =
1354 index.i[3] = reg->Register.Index;
1355
1356 /* There is an extra source register that indirectly subscripts
1357 * a register file. The direct index now becomes an offset
1358 * that is being added to the indirect register.
1359 *
1360 * file[ind[2].x+1],
1361 * where:
1362 * ind = Indirect.File
1363 * [2] = Indirect.Index
1364 * .x = Indirect.SwizzleX
1365 */
1366 if (reg->Register.Indirect) {
1367 union tgsi_exec_channel index2;
1368 union tgsi_exec_channel indir_index;
1369 const uint execmask = mach->ExecMask;
1370 uint i;
1371
1372 /* which address register (always zero now) */
1373 index2.i[0] =
1374 index2.i[1] =
1375 index2.i[2] =
1376 index2.i[3] = reg->Indirect.Index;
1377 /* get current value of address register[swizzle] */
1378 swizzle = reg->Indirect.Swizzle;
1379 fetch_src_file_channel(mach,
1380 chan_index,
1381 reg->Indirect.File,
1382 swizzle,
1383 &index2,
1384 &ZeroVec,
1385 &indir_index);
1386
1387 /* add value of address register to the offset */
1388 index.i[0] += indir_index.i[0];
1389 index.i[1] += indir_index.i[1];
1390 index.i[2] += indir_index.i[2];
1391 index.i[3] += indir_index.i[3];
1392
1393 /* for disabled execution channels, zero-out the index to
1394 * avoid using a potential garbage value.
1395 */
1396 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1397 if ((execmask & (1 << i)) == 0)
1398 index.i[i] = 0;
1399 }
1400 }
1401
1402 /* There is an extra source register that is a second
1403 * subscript to a register file. Effectively it means that
1404 * the register file is actually a 2D array of registers.
1405 *
1406 * file[3][1],
1407 * where:
1408 * [3] = Dimension.Index
1409 */
1410 if (reg->Register.Dimension) {
1411 index2D.i[0] =
1412 index2D.i[1] =
1413 index2D.i[2] =
1414 index2D.i[3] = reg->Dimension.Index;
1415
1416 /* Again, the second subscript index can be addressed indirectly
1417 * identically to the first one.
1418 * Nothing stops us from indirectly addressing the indirect register,
1419 * but there is no need for that, so we won't exercise it.
1420 *
1421 * file[ind[4].y+3][1],
1422 * where:
1423 * ind = DimIndirect.File
1424 * [4] = DimIndirect.Index
1425 * .y = DimIndirect.SwizzleX
1426 */
1427 if (reg->Dimension.Indirect) {
1428 union tgsi_exec_channel index2;
1429 union tgsi_exec_channel indir_index;
1430 const uint execmask = mach->ExecMask;
1431 uint i;
1432
1433 index2.i[0] =
1434 index2.i[1] =
1435 index2.i[2] =
1436 index2.i[3] = reg->DimIndirect.Index;
1437
1438 swizzle = reg->DimIndirect.Swizzle;
1439 fetch_src_file_channel(mach,
1440 chan_index,
1441 reg->DimIndirect.File,
1442 swizzle,
1443 &index2,
1444 &ZeroVec,
1445 &indir_index);
1446
1447 index2D.i[0] += indir_index.i[0];
1448 index2D.i[1] += indir_index.i[1];
1449 index2D.i[2] += indir_index.i[2];
1450 index2D.i[3] += indir_index.i[3];
1451
1452 /* for disabled execution channels, zero-out the index to
1453 * avoid using a potential garbage value.
1454 */
1455 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1456 if ((execmask & (1 << i)) == 0) {
1457 index2D.i[i] = 0;
1458 }
1459 }
1460 }
1461
1462 /* If by any chance there was a need for a 3D array of register
1463 * files, we would have to check whether Dimension is followed
1464 * by a dimension register and continue the saga.
1465 */
1466 } else {
1467 index2D.i[0] =
1468 index2D.i[1] =
1469 index2D.i[2] =
1470 index2D.i[3] = 0;
1471 }
1472
1473 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1474 fetch_src_file_channel(mach,
1475 chan_index,
1476 reg->Register.File,
1477 swizzle,
1478 &index,
1479 &index2D,
1480 chan);
1481 }
1482
1483 static void
1484 fetch_source(const struct tgsi_exec_machine *mach,
1485 union tgsi_exec_channel *chan,
1486 const struct tgsi_full_src_register *reg,
1487 const uint chan_index,
1488 enum tgsi_exec_datatype src_datatype)
1489 {
1490 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1491
1492 if (reg->Register.Absolute) {
1493 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1494 micro_abs(chan, chan);
1495 } else {
1496 micro_iabs(chan, chan);
1497 }
1498 }
1499
1500 if (reg->Register.Negate) {
1501 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1502 micro_neg(chan, chan);
1503 } else {
1504 micro_ineg(chan, chan);
1505 }
1506 }
1507 }
1508
1509 static union tgsi_exec_channel *
1510 store_dest_dstret(struct tgsi_exec_machine *mach,
1511 const union tgsi_exec_channel *chan,
1512 const struct tgsi_full_dst_register *reg,
1513 const struct tgsi_full_instruction *inst,
1514 uint chan_index,
1515 enum tgsi_exec_datatype dst_datatype)
1516 {
1517 uint i;
1518 static union tgsi_exec_channel null;
1519 union tgsi_exec_channel *dst;
1520 union tgsi_exec_channel index2D;
1521 uint execmask = mach->ExecMask;
1522 int offset = 0; /* indirection offset */
1523 int index;
1524
1525 /* for debugging */
1526 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1527 check_inf_or_nan(chan);
1528 }
1529
1530 /* There is an extra source register that indirectly subscripts
1531 * a register file. The direct index now becomes an offset
1532 * that is being added to the indirect register.
1533 *
1534 * file[ind[2].x+1],
1535 * where:
1536 * ind = Indirect.File
1537 * [2] = Indirect.Index
1538 * .x = Indirect.SwizzleX
1539 */
1540 if (reg->Register.Indirect) {
1541 union tgsi_exec_channel index;
1542 union tgsi_exec_channel indir_index;
1543 uint swizzle;
1544
1545 /* which address register (always zero for now) */
1546 index.i[0] =
1547 index.i[1] =
1548 index.i[2] =
1549 index.i[3] = reg->Indirect.Index;
1550
1551 /* get current value of address register[swizzle] */
1552 swizzle = reg->Indirect.Swizzle;
1553
1554 /* fetch values from the address/indirection register */
1555 fetch_src_file_channel(mach,
1556 chan_index,
1557 reg->Indirect.File,
1558 swizzle,
1559 &index,
1560 &ZeroVec,
1561 &indir_index);
1562
1563 /* save indirection offset */
1564 offset = indir_index.i[0];
1565 }
1566
1567 /* There is an extra source register that is a second
1568 * subscript to a register file. Effectively it means that
1569 * the register file is actually a 2D array of registers.
1570 *
1571 * file[3][1],
1572 * where:
1573 * [3] = Dimension.Index
1574 */
1575 if (reg->Register.Dimension) {
1576 index2D.i[0] =
1577 index2D.i[1] =
1578 index2D.i[2] =
1579 index2D.i[3] = reg->Dimension.Index;
1580
1581 /* Again, the second subscript index can be addressed indirectly
1582 * identically to the first one.
1583 * Nothing stops us from indirectly addressing the indirect register,
1584 * but there is no need for that, so we won't exercise it.
1585 *
1586 * file[ind[4].y+3][1],
1587 * where:
1588 * ind = DimIndirect.File
1589 * [4] = DimIndirect.Index
1590 * .y = DimIndirect.SwizzleX
1591 */
1592 if (reg->Dimension.Indirect) {
1593 union tgsi_exec_channel index2;
1594 union tgsi_exec_channel indir_index;
1595 const uint execmask = mach->ExecMask;
1596 unsigned swizzle;
1597 uint i;
1598
1599 index2.i[0] =
1600 index2.i[1] =
1601 index2.i[2] =
1602 index2.i[3] = reg->DimIndirect.Index;
1603
1604 swizzle = reg->DimIndirect.Swizzle;
1605 fetch_src_file_channel(mach,
1606 chan_index,
1607 reg->DimIndirect.File,
1608 swizzle,
1609 &index2,
1610 &ZeroVec,
1611 &indir_index);
1612
1613 index2D.i[0] += indir_index.i[0];
1614 index2D.i[1] += indir_index.i[1];
1615 index2D.i[2] += indir_index.i[2];
1616 index2D.i[3] += indir_index.i[3];
1617
1618 /* for disabled execution channels, zero-out the index to
1619 * avoid using a potential garbage value.
1620 */
1621 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1622 if ((execmask & (1 << i)) == 0) {
1623 index2D.i[i] = 0;
1624 }
1625 }
1626 }
1627
1628 /* If by any chance there was a need for a 3D array of register
1629 * files, we would have to check whether Dimension is followed
1630 * by a dimension register and continue the saga.
1631 */
1632 } else {
1633 index2D.i[0] =
1634 index2D.i[1] =
1635 index2D.i[2] =
1636 index2D.i[3] = 0;
1637 }
1638
1639 switch (reg->Register.File) {
1640 case TGSI_FILE_NULL:
1641 dst = &null;
1642 break;
1643
1644 case TGSI_FILE_OUTPUT:
1645 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1646 + reg->Register.Index;
1647 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1648 #if 0
1649 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1650 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1651 reg->Register.Index);
1652 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1653 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1654 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1655 if (execmask & (1 << i))
1656 debug_printf("%f, ", chan->f[i]);
1657 debug_printf(")\n");
1658 }
1659 #endif
1660 break;
1661
1662 case TGSI_FILE_TEMPORARY:
1663 index = reg->Register.Index;
1664 assert( index < TGSI_EXEC_NUM_TEMPS );
1665 dst = &mach->Temps[offset + index].xyzw[chan_index];
1666 break;
1667
1668 case TGSI_FILE_ADDRESS:
1669 index = reg->Register.Index;
1670 dst = &mach->Addrs[index].xyzw[chan_index];
1671 break;
1672
1673 case TGSI_FILE_PREDICATE:
1674 index = reg->Register.Index;
1675 assert(index < TGSI_EXEC_NUM_PREDS);
1676 dst = &mach->Predicates[index].xyzw[chan_index];
1677 break;
1678
1679 default:
1680 assert( 0 );
1681 return NULL;
1682 }
1683
1684 if (inst->Instruction.Predicate) {
1685 uint swizzle;
1686 union tgsi_exec_channel *pred;
1687
1688 switch (chan_index) {
1689 case TGSI_CHAN_X:
1690 swizzle = inst->Predicate.SwizzleX;
1691 break;
1692 case TGSI_CHAN_Y:
1693 swizzle = inst->Predicate.SwizzleY;
1694 break;
1695 case TGSI_CHAN_Z:
1696 swizzle = inst->Predicate.SwizzleZ;
1697 break;
1698 case TGSI_CHAN_W:
1699 swizzle = inst->Predicate.SwizzleW;
1700 break;
1701 default:
1702 assert(0);
1703 return NULL;
1704 }
1705
1706 assert(inst->Predicate.Index == 0);
1707
1708 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1709
1710 if (inst->Predicate.Negate) {
1711 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1712 if (pred->u[i]) {
1713 execmask &= ~(1 << i);
1714 }
1715 }
1716 } else {
1717 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1718 if (!pred->u[i]) {
1719 execmask &= ~(1 << i);
1720 }
1721 }
1722 }
1723 }
1724
1725 return dst;
1726 }
1727
1728 static void
1729 store_dest_double(struct tgsi_exec_machine *mach,
1730 const union tgsi_exec_channel *chan,
1731 const struct tgsi_full_dst_register *reg,
1732 const struct tgsi_full_instruction *inst,
1733 uint chan_index,
1734 enum tgsi_exec_datatype dst_datatype)
1735 {
1736 union tgsi_exec_channel *dst;
1737 const uint execmask = mach->ExecMask;
1738 int i;
1739
1740 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1741 dst_datatype);
1742 if (!dst)
1743 return;
1744
1745 /* doubles path */
1746 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1747 if (execmask & (1 << i))
1748 dst->i[i] = chan->i[i];
1749 }
1750
1751 static void
1752 store_dest(struct tgsi_exec_machine *mach,
1753 const union tgsi_exec_channel *chan,
1754 const struct tgsi_full_dst_register *reg,
1755 const struct tgsi_full_instruction *inst,
1756 uint chan_index,
1757 enum tgsi_exec_datatype dst_datatype)
1758 {
1759 union tgsi_exec_channel *dst;
1760 const uint execmask = mach->ExecMask;
1761 int i;
1762
1763 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1764 dst_datatype);
1765 if (!dst)
1766 return;
1767
1768 if (!inst->Instruction.Saturate) {
1769 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1770 if (execmask & (1 << i))
1771 dst->i[i] = chan->i[i];
1772 }
1773 else {
1774 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1775 if (execmask & (1 << i)) {
1776 if (chan->f[i] < 0.0f)
1777 dst->f[i] = 0.0f;
1778 else if (chan->f[i] > 1.0f)
1779 dst->f[i] = 1.0f;
1780 else
1781 dst->i[i] = chan->i[i];
1782 }
1783 }
1784 }
1785
1786 #define FETCH(VAL,INDEX,CHAN)\
1787 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1788
1789 #define IFETCH(VAL,INDEX,CHAN)\
1790 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1791
1792
1793 /**
1794 * Execute ARB-style KIL which is predicated by a src register.
1795 * Kill fragment if any of the four values is less than zero.
1796 */
1797 static void
1798 exec_kill_if(struct tgsi_exec_machine *mach,
1799 const struct tgsi_full_instruction *inst)
1800 {
1801 uint uniquemask;
1802 uint chan_index;
1803 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1804 union tgsi_exec_channel r[1];
1805
1806 /* This mask stores component bits that were already tested. */
1807 uniquemask = 0;
1808
1809 for (chan_index = 0; chan_index < 4; chan_index++)
1810 {
1811 uint swizzle;
1812 uint i;
1813
1814 /* unswizzle channel */
1815 swizzle = tgsi_util_get_full_src_register_swizzle (
1816 &inst->Src[0],
1817 chan_index);
1818
1819 /* check if the component has not been already tested */
1820 if (uniquemask & (1 << swizzle))
1821 continue;
1822 uniquemask |= 1 << swizzle;
1823
1824 FETCH(&r[0], 0, chan_index);
1825 for (i = 0; i < 4; i++)
1826 if (r[0].f[i] < 0.0f)
1827 kilmask |= 1 << i;
1828 }
1829
1830 /* restrict to fragments currently executing */
1831 kilmask &= mach->ExecMask;
1832
1833 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1834 }
1835
1836 /**
1837 * Unconditional fragment kill/discard.
1838 */
1839 static void
1840 exec_kill(struct tgsi_exec_machine *mach,
1841 const struct tgsi_full_instruction *inst)
1842 {
1843 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1844
1845 /* kill fragment for all fragments currently executing */
1846 kilmask = mach->ExecMask;
1847 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1848 }
1849
1850 static void
1851 emit_vertex(struct tgsi_exec_machine *mach)
1852 {
1853 /* FIXME: check for exec mask correctly
1854 unsigned i;
1855 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1856 if ((mach->ExecMask & (1 << i)))
1857 */
1858 if (mach->ExecMask) {
1859 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1860 return;
1861
1862 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1863 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1864 }
1865 }
1866
1867 static void
1868 emit_primitive(struct tgsi_exec_machine *mach)
1869 {
1870 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1871 /* FIXME: check for exec mask correctly
1872 unsigned i;
1873 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1874 if ((mach->ExecMask & (1 << i)))
1875 */
1876 if (mach->ExecMask) {
1877 ++(*prim_count);
1878 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1879 mach->Primitives[*prim_count] = 0;
1880 }
1881 }
1882
1883 static void
1884 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1885 {
1886 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1887 int emitted_verts =
1888 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1889 if (emitted_verts) {
1890 emit_primitive(mach);
1891 }
1892 }
1893 }
1894
1895
1896 /*
1897 * Fetch four texture samples using STR texture coordinates.
1898 */
1899 static void
1900 fetch_texel( struct tgsi_sampler *sampler,
1901 const unsigned sview_idx,
1902 const unsigned sampler_idx,
1903 const union tgsi_exec_channel *s,
1904 const union tgsi_exec_channel *t,
1905 const union tgsi_exec_channel *p,
1906 const union tgsi_exec_channel *c0,
1907 const union tgsi_exec_channel *c1,
1908 float derivs[3][2][TGSI_QUAD_SIZE],
1909 const int8_t offset[3],
1910 enum tgsi_sampler_control control,
1911 union tgsi_exec_channel *r,
1912 union tgsi_exec_channel *g,
1913 union tgsi_exec_channel *b,
1914 union tgsi_exec_channel *a )
1915 {
1916 uint j;
1917 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1918
1919 /* FIXME: handle explicit derivs, offsets */
1920 sampler->get_samples(sampler, sview_idx, sampler_idx,
1921 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1922
1923 for (j = 0; j < 4; j++) {
1924 r->f[j] = rgba[0][j];
1925 g->f[j] = rgba[1][j];
1926 b->f[j] = rgba[2][j];
1927 a->f[j] = rgba[3][j];
1928 }
1929 }
1930
1931
1932 #define TEX_MODIFIER_NONE 0
1933 #define TEX_MODIFIER_PROJECTED 1
1934 #define TEX_MODIFIER_LOD_BIAS 2
1935 #define TEX_MODIFIER_EXPLICIT_LOD 3
1936 #define TEX_MODIFIER_LEVEL_ZERO 4
1937 #define TEX_MODIFIER_GATHER 5
1938
1939 /*
1940 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1941 */
1942 static void
1943 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1944 const struct tgsi_full_instruction *inst,
1945 int8_t offsets[3])
1946 {
1947 if (inst->Texture.NumOffsets == 1) {
1948 union tgsi_exec_channel index;
1949 union tgsi_exec_channel offset[3];
1950 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1951 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1952 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1953 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1954 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1955 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1956 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1957 offsets[0] = offset[0].i[0];
1958 offsets[1] = offset[1].i[0];
1959 offsets[2] = offset[2].i[0];
1960 } else {
1961 assert(inst->Texture.NumOffsets == 0);
1962 offsets[0] = offsets[1] = offsets[2] = 0;
1963 }
1964 }
1965
1966
1967 /*
1968 * Fetch dx and dy values for one channel (s, t or r).
1969 * Put dx values into one float array, dy values into another.
1970 */
1971 static void
1972 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1973 const struct tgsi_full_instruction *inst,
1974 unsigned regdsrcx,
1975 unsigned chan,
1976 float derivs[2][TGSI_QUAD_SIZE])
1977 {
1978 union tgsi_exec_channel d;
1979 FETCH(&d, regdsrcx, chan);
1980 derivs[0][0] = d.f[0];
1981 derivs[0][1] = d.f[1];
1982 derivs[0][2] = d.f[2];
1983 derivs[0][3] = d.f[3];
1984 FETCH(&d, regdsrcx + 1, chan);
1985 derivs[1][0] = d.f[0];
1986 derivs[1][1] = d.f[1];
1987 derivs[1][2] = d.f[2];
1988 derivs[1][3] = d.f[3];
1989 }
1990
1991 static uint
1992 fetch_sampler_unit(struct tgsi_exec_machine *mach,
1993 const struct tgsi_full_instruction *inst,
1994 uint sampler)
1995 {
1996 uint unit;
1997
1998 if (inst->Src[sampler].Register.Indirect) {
1999 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2000 union tgsi_exec_channel indir_index, index2;
2001
2002 index2.i[0] =
2003 index2.i[1] =
2004 index2.i[2] =
2005 index2.i[3] = reg->Indirect.Index;
2006
2007 fetch_src_file_channel(mach,
2008 0,
2009 reg->Indirect.File,
2010 reg->Indirect.Swizzle,
2011 &index2,
2012 &ZeroVec,
2013 &indir_index);
2014 unit = inst->Src[sampler].Register.Index + indir_index.i[0];
2015 } else {
2016 unit = inst->Src[sampler].Register.Index;
2017 }
2018 return unit;
2019 }
2020
2021 /*
2022 * execute a texture instruction.
2023 *
2024 * modifier is used to control the channel routing for the\
2025 * instruction variants like proj, lod, and texture with lod bias.
2026 * sampler indicates which src register the sampler is contained in.
2027 */
2028 static void
2029 exec_tex(struct tgsi_exec_machine *mach,
2030 const struct tgsi_full_instruction *inst,
2031 uint modifier, uint sampler)
2032 {
2033 const union tgsi_exec_channel *args[5], *proj = NULL;
2034 union tgsi_exec_channel r[5];
2035 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2036 uint chan;
2037 uint unit;
2038 int8_t offsets[3];
2039 int dim, shadow_ref, i;
2040
2041 unit = fetch_sampler_unit(mach, inst, sampler);
2042 /* always fetch all 3 offsets, overkill but keeps code simple */
2043 fetch_texel_offsets(mach, inst, offsets);
2044
2045 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2046 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2047
2048 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
2049
2050 assert(dim <= 4);
2051 if (shadow_ref >= 0)
2052 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2053
2054 /* fetch modifier to the last argument */
2055 if (modifier != TEX_MODIFIER_NONE) {
2056 const int last = Elements(args) - 1;
2057
2058 /* fetch modifier from src0.w or src1.x */
2059 if (sampler == 1) {
2060 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2061 FETCH(&r[last], 0, TGSI_CHAN_W);
2062 }
2063 else {
2064 assert(shadow_ref != 4);
2065 FETCH(&r[last], 1, TGSI_CHAN_X);
2066 }
2067
2068 if (modifier != TEX_MODIFIER_PROJECTED) {
2069 args[last] = &r[last];
2070 }
2071 else {
2072 proj = &r[last];
2073 args[last] = &ZeroVec;
2074 }
2075
2076 /* point unused arguments to zero vector */
2077 for (i = dim; i < last; i++)
2078 args[i] = &ZeroVec;
2079
2080 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2081 control = tgsi_sampler_lod_explicit;
2082 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2083 control = tgsi_sampler_lod_bias;
2084 else if (modifier == TEX_MODIFIER_GATHER)
2085 control = tgsi_sampler_gather;
2086 }
2087 else {
2088 for (i = dim; i < Elements(args); i++)
2089 args[i] = &ZeroVec;
2090 }
2091
2092 /* fetch coordinates */
2093 for (i = 0; i < dim; i++) {
2094 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2095
2096 if (proj)
2097 micro_div(&r[i], &r[i], proj);
2098
2099 args[i] = &r[i];
2100 }
2101
2102 /* fetch reference value */
2103 if (shadow_ref >= 0) {
2104 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2105
2106 if (proj)
2107 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2108
2109 args[shadow_ref] = &r[shadow_ref];
2110 }
2111
2112 fetch_texel(mach->Sampler, unit, unit,
2113 args[0], args[1], args[2], args[3], args[4],
2114 NULL, offsets, control,
2115 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2116
2117 #if 0
2118 debug_printf("fetch r: %g %g %g %g\n",
2119 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2120 debug_printf("fetch g: %g %g %g %g\n",
2121 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2122 debug_printf("fetch b: %g %g %g %g\n",
2123 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2124 debug_printf("fetch a: %g %g %g %g\n",
2125 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2126 #endif
2127
2128 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2129 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2130 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2131 }
2132 }
2133 }
2134
2135
2136 static void
2137 exec_txd(struct tgsi_exec_machine *mach,
2138 const struct tgsi_full_instruction *inst)
2139 {
2140 union tgsi_exec_channel r[4];
2141 float derivs[3][2][TGSI_QUAD_SIZE];
2142 uint chan;
2143 uint unit;
2144 int8_t offsets[3];
2145
2146 unit = fetch_sampler_unit(mach, inst, 3);
2147 /* always fetch all 3 offsets, overkill but keeps code simple */
2148 fetch_texel_offsets(mach, inst, offsets);
2149
2150 switch (inst->Texture.Texture) {
2151 case TGSI_TEXTURE_1D:
2152 FETCH(&r[0], 0, TGSI_CHAN_X);
2153
2154 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2155
2156 fetch_texel(mach->Sampler, unit, unit,
2157 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2158 derivs, offsets, tgsi_sampler_derivs_explicit,
2159 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2160 break;
2161
2162 case TGSI_TEXTURE_SHADOW1D:
2163 case TGSI_TEXTURE_1D_ARRAY:
2164 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2165 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2166 FETCH(&r[0], 0, TGSI_CHAN_X);
2167 FETCH(&r[1], 0, TGSI_CHAN_Y);
2168 FETCH(&r[2], 0, TGSI_CHAN_Z);
2169
2170 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2171
2172 fetch_texel(mach->Sampler, unit, unit,
2173 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2174 derivs, offsets, tgsi_sampler_derivs_explicit,
2175 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2176 break;
2177
2178 case TGSI_TEXTURE_2D:
2179 case TGSI_TEXTURE_RECT:
2180 FETCH(&r[0], 0, TGSI_CHAN_X);
2181 FETCH(&r[1], 0, TGSI_CHAN_Y);
2182
2183 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2184 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2185
2186 fetch_texel(mach->Sampler, unit, unit,
2187 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2188 derivs, offsets, tgsi_sampler_derivs_explicit,
2189 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2190 break;
2191
2192
2193 case TGSI_TEXTURE_SHADOW2D:
2194 case TGSI_TEXTURE_SHADOWRECT:
2195 case TGSI_TEXTURE_2D_ARRAY:
2196 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2197 /* only SHADOW2D_ARRAY actually needs W */
2198 FETCH(&r[0], 0, TGSI_CHAN_X);
2199 FETCH(&r[1], 0, TGSI_CHAN_Y);
2200 FETCH(&r[2], 0, TGSI_CHAN_Z);
2201 FETCH(&r[3], 0, TGSI_CHAN_W);
2202
2203 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2204 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2205
2206 fetch_texel(mach->Sampler, unit, unit,
2207 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2208 derivs, offsets, tgsi_sampler_derivs_explicit,
2209 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2210 break;
2211
2212 case TGSI_TEXTURE_3D:
2213 case TGSI_TEXTURE_CUBE:
2214 case TGSI_TEXTURE_CUBE_ARRAY:
2215 case TGSI_TEXTURE_SHADOWCUBE:
2216 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2217 FETCH(&r[0], 0, TGSI_CHAN_X);
2218 FETCH(&r[1], 0, TGSI_CHAN_Y);
2219 FETCH(&r[2], 0, TGSI_CHAN_Z);
2220 FETCH(&r[3], 0, TGSI_CHAN_W);
2221
2222 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2223 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2224 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2225
2226 fetch_texel(mach->Sampler, unit, unit,
2227 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2228 derivs, offsets, tgsi_sampler_derivs_explicit,
2229 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2230 break;
2231
2232 default:
2233 assert(0);
2234 }
2235
2236 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2237 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2238 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2239 }
2240 }
2241 }
2242
2243
2244 static void
2245 exec_txf(struct tgsi_exec_machine *mach,
2246 const struct tgsi_full_instruction *inst)
2247 {
2248 union tgsi_exec_channel r[4];
2249 uint chan;
2250 uint unit;
2251 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2252 int j;
2253 int8_t offsets[3];
2254 unsigned target;
2255
2256 unit = fetch_sampler_unit(mach, inst, 1);
2257 /* always fetch all 3 offsets, overkill but keeps code simple */
2258 fetch_texel_offsets(mach, inst, offsets);
2259
2260 IFETCH(&r[3], 0, TGSI_CHAN_W);
2261
2262 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2263 target = mach->SamplerViews[unit].Resource;
2264 }
2265 else {
2266 target = inst->Texture.Texture;
2267 }
2268 switch(target) {
2269 case TGSI_TEXTURE_3D:
2270 case TGSI_TEXTURE_2D_ARRAY:
2271 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2272 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2273 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2274 /* fallthrough */
2275 case TGSI_TEXTURE_2D:
2276 case TGSI_TEXTURE_RECT:
2277 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2278 case TGSI_TEXTURE_SHADOW2D:
2279 case TGSI_TEXTURE_SHADOWRECT:
2280 case TGSI_TEXTURE_1D_ARRAY:
2281 case TGSI_TEXTURE_2D_MSAA:
2282 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2283 /* fallthrough */
2284 case TGSI_TEXTURE_BUFFER:
2285 case TGSI_TEXTURE_1D:
2286 case TGSI_TEXTURE_SHADOW1D:
2287 IFETCH(&r[0], 0, TGSI_CHAN_X);
2288 break;
2289 default:
2290 assert(0);
2291 break;
2292 }
2293
2294 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2295 offsets, rgba);
2296
2297 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2298 r[0].f[j] = rgba[0][j];
2299 r[1].f[j] = rgba[1][j];
2300 r[2].f[j] = rgba[2][j];
2301 r[3].f[j] = rgba[3][j];
2302 }
2303
2304 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2305 unsigned char swizzles[4];
2306 swizzles[0] = inst->Src[1].Register.SwizzleX;
2307 swizzles[1] = inst->Src[1].Register.SwizzleY;
2308 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2309 swizzles[3] = inst->Src[1].Register.SwizzleW;
2310
2311 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2312 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2313 store_dest(mach, &r[swizzles[chan]],
2314 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2315 }
2316 }
2317 }
2318 else {
2319 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2320 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2321 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2322 }
2323 }
2324 }
2325 }
2326
2327 static void
2328 exec_txq(struct tgsi_exec_machine *mach,
2329 const struct tgsi_full_instruction *inst)
2330 {
2331 int result[4];
2332 union tgsi_exec_channel r[4], src;
2333 uint chan;
2334 uint unit;
2335 int i,j;
2336
2337 unit = fetch_sampler_unit(mach, inst, 1);
2338
2339 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2340
2341 /* XXX: This interface can't return per-pixel values */
2342 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2343
2344 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2345 for (j = 0; j < 4; j++) {
2346 r[j].i[i] = result[j];
2347 }
2348 }
2349
2350 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2351 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2352 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2353 TGSI_EXEC_DATA_INT);
2354 }
2355 }
2356 }
2357
2358 static void
2359 exec_sample(struct tgsi_exec_machine *mach,
2360 const struct tgsi_full_instruction *inst,
2361 uint modifier, boolean compare)
2362 {
2363 const uint resource_unit = inst->Src[1].Register.Index;
2364 const uint sampler_unit = inst->Src[2].Register.Index;
2365 union tgsi_exec_channel r[5], c1;
2366 const union tgsi_exec_channel *lod = &ZeroVec;
2367 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2368 uint chan;
2369 unsigned char swizzles[4];
2370 int8_t offsets[3];
2371
2372 /* always fetch all 3 offsets, overkill but keeps code simple */
2373 fetch_texel_offsets(mach, inst, offsets);
2374
2375 assert(modifier != TEX_MODIFIER_PROJECTED);
2376
2377 if (modifier != TEX_MODIFIER_NONE) {
2378 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2379 FETCH(&c1, 3, TGSI_CHAN_X);
2380 lod = &c1;
2381 control = tgsi_sampler_lod_bias;
2382 }
2383 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2384 FETCH(&c1, 3, TGSI_CHAN_X);
2385 lod = &c1;
2386 control = tgsi_sampler_lod_explicit;
2387 }
2388 else {
2389 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2390 control = tgsi_sampler_lod_zero;
2391 }
2392 }
2393
2394 FETCH(&r[0], 0, TGSI_CHAN_X);
2395
2396 switch (mach->SamplerViews[resource_unit].Resource) {
2397 case TGSI_TEXTURE_1D:
2398 if (compare) {
2399 FETCH(&r[2], 3, TGSI_CHAN_X);
2400 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2401 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2402 NULL, offsets, control,
2403 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2404 }
2405 else {
2406 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2407 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2408 NULL, offsets, control,
2409 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2410 }
2411 break;
2412
2413 case TGSI_TEXTURE_1D_ARRAY:
2414 case TGSI_TEXTURE_2D:
2415 case TGSI_TEXTURE_RECT:
2416 FETCH(&r[1], 0, TGSI_CHAN_Y);
2417 if (compare) {
2418 FETCH(&r[2], 3, TGSI_CHAN_X);
2419 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2420 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2421 NULL, offsets, control,
2422 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2423 }
2424 else {
2425 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2426 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2427 NULL, offsets, control,
2428 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2429 }
2430 break;
2431
2432 case TGSI_TEXTURE_2D_ARRAY:
2433 case TGSI_TEXTURE_3D:
2434 case TGSI_TEXTURE_CUBE:
2435 FETCH(&r[1], 0, TGSI_CHAN_Y);
2436 FETCH(&r[2], 0, TGSI_CHAN_Z);
2437 if(compare) {
2438 FETCH(&r[3], 3, TGSI_CHAN_X);
2439 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2440 &r[0], &r[1], &r[2], &r[3], lod,
2441 NULL, offsets, control,
2442 &r[0], &r[1], &r[2], &r[3]);
2443 }
2444 else {
2445 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2446 &r[0], &r[1], &r[2], &ZeroVec, lod,
2447 NULL, offsets, control,
2448 &r[0], &r[1], &r[2], &r[3]);
2449 }
2450 break;
2451
2452 case TGSI_TEXTURE_CUBE_ARRAY:
2453 FETCH(&r[1], 0, TGSI_CHAN_Y);
2454 FETCH(&r[2], 0, TGSI_CHAN_Z);
2455 FETCH(&r[3], 0, TGSI_CHAN_W);
2456 if(compare) {
2457 FETCH(&r[4], 3, TGSI_CHAN_X);
2458 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2459 &r[0], &r[1], &r[2], &r[3], &r[4],
2460 NULL, offsets, control,
2461 &r[0], &r[1], &r[2], &r[3]);
2462 }
2463 else {
2464 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2465 &r[0], &r[1], &r[2], &r[3], lod,
2466 NULL, offsets, control,
2467 &r[0], &r[1], &r[2], &r[3]);
2468 }
2469 break;
2470
2471
2472 default:
2473 assert(0);
2474 }
2475
2476 swizzles[0] = inst->Src[1].Register.SwizzleX;
2477 swizzles[1] = inst->Src[1].Register.SwizzleY;
2478 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2479 swizzles[3] = inst->Src[1].Register.SwizzleW;
2480
2481 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2482 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2483 store_dest(mach, &r[swizzles[chan]],
2484 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2485 }
2486 }
2487 }
2488
2489 static void
2490 exec_sample_d(struct tgsi_exec_machine *mach,
2491 const struct tgsi_full_instruction *inst)
2492 {
2493 const uint resource_unit = inst->Src[1].Register.Index;
2494 const uint sampler_unit = inst->Src[2].Register.Index;
2495 union tgsi_exec_channel r[4];
2496 float derivs[3][2][TGSI_QUAD_SIZE];
2497 uint chan;
2498 unsigned char swizzles[4];
2499 int8_t offsets[3];
2500
2501 /* always fetch all 3 offsets, overkill but keeps code simple */
2502 fetch_texel_offsets(mach, inst, offsets);
2503
2504 FETCH(&r[0], 0, TGSI_CHAN_X);
2505
2506 switch (mach->SamplerViews[resource_unit].Resource) {
2507 case TGSI_TEXTURE_1D:
2508 case TGSI_TEXTURE_1D_ARRAY:
2509 /* only 1D array actually needs Y */
2510 FETCH(&r[1], 0, TGSI_CHAN_Y);
2511
2512 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2513
2514 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2515 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2516 derivs, offsets, tgsi_sampler_derivs_explicit,
2517 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2518 break;
2519
2520 case TGSI_TEXTURE_2D:
2521 case TGSI_TEXTURE_RECT:
2522 case TGSI_TEXTURE_2D_ARRAY:
2523 /* only 2D array actually needs Z */
2524 FETCH(&r[1], 0, TGSI_CHAN_Y);
2525 FETCH(&r[2], 0, TGSI_CHAN_Z);
2526
2527 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2528 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2529
2530 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2531 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2532 derivs, offsets, tgsi_sampler_derivs_explicit,
2533 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2534 break;
2535
2536 case TGSI_TEXTURE_3D:
2537 case TGSI_TEXTURE_CUBE:
2538 case TGSI_TEXTURE_CUBE_ARRAY:
2539 /* only cube array actually needs W */
2540 FETCH(&r[1], 0, TGSI_CHAN_Y);
2541 FETCH(&r[2], 0, TGSI_CHAN_Z);
2542 FETCH(&r[3], 0, TGSI_CHAN_W);
2543
2544 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2545 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2546 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2547
2548 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2549 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2550 derivs, offsets, tgsi_sampler_derivs_explicit,
2551 &r[0], &r[1], &r[2], &r[3]);
2552 break;
2553
2554 default:
2555 assert(0);
2556 }
2557
2558 swizzles[0] = inst->Src[1].Register.SwizzleX;
2559 swizzles[1] = inst->Src[1].Register.SwizzleY;
2560 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2561 swizzles[3] = inst->Src[1].Register.SwizzleW;
2562
2563 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2564 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2565 store_dest(mach, &r[swizzles[chan]],
2566 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2567 }
2568 }
2569 }
2570
2571
2572 /**
2573 * Evaluate a constant-valued coefficient at the position of the
2574 * current quad.
2575 */
2576 static void
2577 eval_constant_coef(
2578 struct tgsi_exec_machine *mach,
2579 unsigned attrib,
2580 unsigned chan )
2581 {
2582 unsigned i;
2583
2584 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2585 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2586 }
2587 }
2588
2589 /**
2590 * Evaluate a linear-valued coefficient at the position of the
2591 * current quad.
2592 */
2593 static void
2594 eval_linear_coef(
2595 struct tgsi_exec_machine *mach,
2596 unsigned attrib,
2597 unsigned chan )
2598 {
2599 const float x = mach->QuadPos.xyzw[0].f[0];
2600 const float y = mach->QuadPos.xyzw[1].f[0];
2601 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2602 const float dady = mach->InterpCoefs[attrib].dady[chan];
2603 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2604 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2605 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2606 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2607 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2608 }
2609
2610 /**
2611 * Evaluate a perspective-valued coefficient at the position of the
2612 * current quad.
2613 */
2614 static void
2615 eval_perspective_coef(
2616 struct tgsi_exec_machine *mach,
2617 unsigned attrib,
2618 unsigned chan )
2619 {
2620 const float x = mach->QuadPos.xyzw[0].f[0];
2621 const float y = mach->QuadPos.xyzw[1].f[0];
2622 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2623 const float dady = mach->InterpCoefs[attrib].dady[chan];
2624 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2625 const float *w = mach->QuadPos.xyzw[3].f;
2626 /* divide by W here */
2627 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2628 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2629 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2630 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2631 }
2632
2633
2634 typedef void (* eval_coef_func)(
2635 struct tgsi_exec_machine *mach,
2636 unsigned attrib,
2637 unsigned chan );
2638
2639 static void
2640 exec_declaration(struct tgsi_exec_machine *mach,
2641 const struct tgsi_full_declaration *decl)
2642 {
2643 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2644 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2645 return;
2646 }
2647
2648 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2649 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2650 uint first, last, mask;
2651
2652 first = decl->Range.First;
2653 last = decl->Range.Last;
2654 mask = decl->Declaration.UsageMask;
2655
2656 /* XXX we could remove this special-case code since
2657 * mach->InterpCoefs[first].a0 should already have the
2658 * front/back-face value. But we should first update the
2659 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2660 * Then, we could remove the tgsi_exec_machine::Face field.
2661 */
2662 /* XXX make FACE a system value */
2663 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2664 uint i;
2665
2666 assert(decl->Semantic.Index == 0);
2667 assert(first == last);
2668
2669 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2670 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2671 }
2672 } else {
2673 eval_coef_func eval;
2674 uint i, j;
2675
2676 switch (decl->Interp.Interpolate) {
2677 case TGSI_INTERPOLATE_CONSTANT:
2678 eval = eval_constant_coef;
2679 break;
2680
2681 case TGSI_INTERPOLATE_LINEAR:
2682 eval = eval_linear_coef;
2683 break;
2684
2685 case TGSI_INTERPOLATE_PERSPECTIVE:
2686 eval = eval_perspective_coef;
2687 break;
2688
2689 case TGSI_INTERPOLATE_COLOR:
2690 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2691 break;
2692
2693 default:
2694 assert(0);
2695 return;
2696 }
2697
2698 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2699 if (mask & (1 << j)) {
2700 for (i = first; i <= last; i++) {
2701 eval(mach, i, j);
2702 }
2703 }
2704 }
2705 }
2706
2707 if (DEBUG_EXECUTION) {
2708 uint i, j;
2709 for (i = first; i <= last; ++i) {
2710 debug_printf("IN[%2u] = ", i);
2711 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2712 if (j > 0) {
2713 debug_printf(" ");
2714 }
2715 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2716 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2717 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2718 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2719 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2720 }
2721 }
2722 }
2723 }
2724 }
2725
2726 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2727 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2728 }
2729 }
2730
2731 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2732 const union tgsi_exec_channel *src);
2733
2734 static void
2735 exec_scalar_unary(struct tgsi_exec_machine *mach,
2736 const struct tgsi_full_instruction *inst,
2737 micro_unary_op op,
2738 enum tgsi_exec_datatype dst_datatype,
2739 enum tgsi_exec_datatype src_datatype)
2740 {
2741 unsigned int chan;
2742 union tgsi_exec_channel src;
2743 union tgsi_exec_channel dst;
2744
2745 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2746 op(&dst, &src);
2747 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2748 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2749 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2750 }
2751 }
2752 }
2753
2754 static void
2755 exec_vector_unary(struct tgsi_exec_machine *mach,
2756 const struct tgsi_full_instruction *inst,
2757 micro_unary_op op,
2758 enum tgsi_exec_datatype dst_datatype,
2759 enum tgsi_exec_datatype src_datatype)
2760 {
2761 unsigned int chan;
2762 struct tgsi_exec_vector dst;
2763
2764 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2765 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2766 union tgsi_exec_channel src;
2767
2768 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2769 op(&dst.xyzw[chan], &src);
2770 }
2771 }
2772 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2773 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2774 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2775 }
2776 }
2777 }
2778
2779 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2780 const union tgsi_exec_channel *src0,
2781 const union tgsi_exec_channel *src1);
2782
2783 static void
2784 exec_scalar_binary(struct tgsi_exec_machine *mach,
2785 const struct tgsi_full_instruction *inst,
2786 micro_binary_op op,
2787 enum tgsi_exec_datatype dst_datatype,
2788 enum tgsi_exec_datatype src_datatype)
2789 {
2790 unsigned int chan;
2791 union tgsi_exec_channel src[2];
2792 union tgsi_exec_channel dst;
2793
2794 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2795 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2796 op(&dst, &src[0], &src[1]);
2797 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2798 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2799 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2800 }
2801 }
2802 }
2803
2804 static void
2805 exec_vector_binary(struct tgsi_exec_machine *mach,
2806 const struct tgsi_full_instruction *inst,
2807 micro_binary_op op,
2808 enum tgsi_exec_datatype dst_datatype,
2809 enum tgsi_exec_datatype src_datatype)
2810 {
2811 unsigned int chan;
2812 struct tgsi_exec_vector dst;
2813
2814 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2815 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2816 union tgsi_exec_channel src[2];
2817
2818 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2819 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2820 op(&dst.xyzw[chan], &src[0], &src[1]);
2821 }
2822 }
2823 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2824 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2825 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2826 }
2827 }
2828 }
2829
2830 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2831 const union tgsi_exec_channel *src0,
2832 const union tgsi_exec_channel *src1,
2833 const union tgsi_exec_channel *src2);
2834
2835 static void
2836 exec_vector_trinary(struct tgsi_exec_machine *mach,
2837 const struct tgsi_full_instruction *inst,
2838 micro_trinary_op op,
2839 enum tgsi_exec_datatype dst_datatype,
2840 enum tgsi_exec_datatype src_datatype)
2841 {
2842 unsigned int chan;
2843 struct tgsi_exec_vector dst;
2844
2845 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2846 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2847 union tgsi_exec_channel src[3];
2848
2849 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2850 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2851 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2852 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2853 }
2854 }
2855 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2856 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2857 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2858 }
2859 }
2860 }
2861
2862 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2863 const union tgsi_exec_channel *src0,
2864 const union tgsi_exec_channel *src1,
2865 const union tgsi_exec_channel *src2,
2866 const union tgsi_exec_channel *src3);
2867
2868 static void
2869 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2870 const struct tgsi_full_instruction *inst,
2871 micro_quaternary_op op,
2872 enum tgsi_exec_datatype dst_datatype,
2873 enum tgsi_exec_datatype src_datatype)
2874 {
2875 unsigned int chan;
2876 struct tgsi_exec_vector dst;
2877
2878 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2879 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2880 union tgsi_exec_channel src[4];
2881
2882 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2883 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2884 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2885 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2886 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2887 }
2888 }
2889 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2890 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2891 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2892 }
2893 }
2894 }
2895
2896 static void
2897 exec_dp3(struct tgsi_exec_machine *mach,
2898 const struct tgsi_full_instruction *inst)
2899 {
2900 unsigned int chan;
2901 union tgsi_exec_channel arg[3];
2902
2903 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2904 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2905 micro_mul(&arg[2], &arg[0], &arg[1]);
2906
2907 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2908 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2909 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2910 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2911 }
2912
2913 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2914 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2915 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2916 }
2917 }
2918 }
2919
2920 static void
2921 exec_dp4(struct tgsi_exec_machine *mach,
2922 const struct tgsi_full_instruction *inst)
2923 {
2924 unsigned int chan;
2925 union tgsi_exec_channel arg[3];
2926
2927 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2928 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2929 micro_mul(&arg[2], &arg[0], &arg[1]);
2930
2931 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2932 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2933 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2934 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2935 }
2936
2937 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2938 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2939 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2940 }
2941 }
2942 }
2943
2944 static void
2945 exec_dp2a(struct tgsi_exec_machine *mach,
2946 const struct tgsi_full_instruction *inst)
2947 {
2948 unsigned int chan;
2949 union tgsi_exec_channel arg[3];
2950
2951 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2952 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2953 micro_mul(&arg[2], &arg[0], &arg[1]);
2954
2955 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2956 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2957 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2958
2959 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2960 micro_add(&arg[0], &arg[0], &arg[1]);
2961
2962 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2963 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2964 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2965 }
2966 }
2967 }
2968
2969 static void
2970 exec_dph(struct tgsi_exec_machine *mach,
2971 const struct tgsi_full_instruction *inst)
2972 {
2973 unsigned int chan;
2974 union tgsi_exec_channel arg[3];
2975
2976 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2977 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2978 micro_mul(&arg[2], &arg[0], &arg[1]);
2979
2980 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2981 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2982 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2983
2984 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2985 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2986 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2987
2988 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2989 micro_add(&arg[0], &arg[0], &arg[1]);
2990
2991 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2992 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2993 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2994 }
2995 }
2996 }
2997
2998 static void
2999 exec_dp2(struct tgsi_exec_machine *mach,
3000 const struct tgsi_full_instruction *inst)
3001 {
3002 unsigned int chan;
3003 union tgsi_exec_channel arg[3];
3004
3005 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3006 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3007 micro_mul(&arg[2], &arg[0], &arg[1]);
3008
3009 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3010 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3011 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3012
3013 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3014 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3015 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3016 }
3017 }
3018 }
3019
3020 static void
3021 exec_scs(struct tgsi_exec_machine *mach,
3022 const struct tgsi_full_instruction *inst)
3023 {
3024 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3025 union tgsi_exec_channel arg;
3026 union tgsi_exec_channel result;
3027
3028 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3029
3030 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3031 micro_cos(&result, &arg);
3032 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3033 }
3034 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3035 micro_sin(&result, &arg);
3036 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3037 }
3038 }
3039 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3040 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3041 }
3042 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3043 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3044 }
3045 }
3046
3047 static void
3048 exec_xpd(struct tgsi_exec_machine *mach,
3049 const struct tgsi_full_instruction *inst)
3050 {
3051 union tgsi_exec_channel r[6];
3052 union tgsi_exec_channel d[3];
3053
3054 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3055 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3056
3057 micro_mul(&r[2], &r[0], &r[1]);
3058
3059 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3060 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3061
3062 micro_mul(&r[5], &r[3], &r[4] );
3063 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3064
3065 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3066
3067 micro_mul(&r[3], &r[3], &r[2]);
3068
3069 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3070
3071 micro_mul(&r[1], &r[1], &r[5]);
3072 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3073
3074 micro_mul(&r[5], &r[5], &r[4]);
3075 micro_mul(&r[0], &r[0], &r[2]);
3076 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3077
3078 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3079 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3080 }
3081 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3082 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3083 }
3084 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3085 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3086 }
3087 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3088 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3089 }
3090 }
3091
3092 static void
3093 exec_dst(struct tgsi_exec_machine *mach,
3094 const struct tgsi_full_instruction *inst)
3095 {
3096 union tgsi_exec_channel r[2];
3097 union tgsi_exec_channel d[4];
3098
3099 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3100 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3101 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3102 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3103 }
3104 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3105 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3106 }
3107 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3108 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3109 }
3110
3111 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3112 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3113 }
3114 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3115 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3116 }
3117 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3118 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3119 }
3120 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3121 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3122 }
3123 }
3124
3125 static void
3126 exec_log(struct tgsi_exec_machine *mach,
3127 const struct tgsi_full_instruction *inst)
3128 {
3129 union tgsi_exec_channel r[3];
3130
3131 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3132 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3133 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3134 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3135 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3136 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3137 }
3138 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3139 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3140 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3141 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3142 }
3143 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3144 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3145 }
3146 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3147 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3148 }
3149 }
3150
3151 static void
3152 exec_exp(struct tgsi_exec_machine *mach,
3153 const struct tgsi_full_instruction *inst)
3154 {
3155 union tgsi_exec_channel r[3];
3156
3157 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3158 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3159 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3160 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3161 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3162 }
3163 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3164 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3165 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3166 }
3167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3168 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3169 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3170 }
3171 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3172 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3173 }
3174 }
3175
3176 static void
3177 exec_lit(struct tgsi_exec_machine *mach,
3178 const struct tgsi_full_instruction *inst)
3179 {
3180 union tgsi_exec_channel r[3];
3181 union tgsi_exec_channel d[3];
3182
3183 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3184 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3185 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3186 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3187 micro_max(&r[1], &r[1], &ZeroVec);
3188
3189 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3190 micro_min(&r[2], &r[2], &P128Vec);
3191 micro_max(&r[2], &r[2], &M128Vec);
3192 micro_pow(&r[1], &r[1], &r[2]);
3193 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3194 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3195 }
3196 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3197 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3198 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3199 }
3200 }
3201 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3202 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3203 }
3204
3205 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3206 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3207 }
3208 }
3209
3210 static void
3211 exec_break(struct tgsi_exec_machine *mach)
3212 {
3213 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3214 /* turn off loop channels for each enabled exec channel */
3215 mach->LoopMask &= ~mach->ExecMask;
3216 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3217 UPDATE_EXEC_MASK(mach);
3218 } else {
3219 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3220
3221 mach->Switch.mask = 0x0;
3222
3223 UPDATE_EXEC_MASK(mach);
3224 }
3225 }
3226
3227 static void
3228 exec_switch(struct tgsi_exec_machine *mach,
3229 const struct tgsi_full_instruction *inst)
3230 {
3231 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3232 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3233
3234 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3235 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3236 mach->Switch.mask = 0x0;
3237 mach->Switch.defaultMask = 0x0;
3238
3239 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3240 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3241
3242 UPDATE_EXEC_MASK(mach);
3243 }
3244
3245 static void
3246 exec_case(struct tgsi_exec_machine *mach,
3247 const struct tgsi_full_instruction *inst)
3248 {
3249 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3250 union tgsi_exec_channel src;
3251 uint mask = 0;
3252
3253 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3254
3255 if (mach->Switch.selector.u[0] == src.u[0]) {
3256 mask |= 0x1;
3257 }
3258 if (mach->Switch.selector.u[1] == src.u[1]) {
3259 mask |= 0x2;
3260 }
3261 if (mach->Switch.selector.u[2] == src.u[2]) {
3262 mask |= 0x4;
3263 }
3264 if (mach->Switch.selector.u[3] == src.u[3]) {
3265 mask |= 0x8;
3266 }
3267
3268 mach->Switch.defaultMask |= mask;
3269
3270 mach->Switch.mask |= mask & prevMask;
3271
3272 UPDATE_EXEC_MASK(mach);
3273 }
3274
3275 /* FIXME: this will only work if default is last */
3276 static void
3277 exec_default(struct tgsi_exec_machine *mach)
3278 {
3279 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3280
3281 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3282
3283 UPDATE_EXEC_MASK(mach);
3284 }
3285
3286 static void
3287 exec_endswitch(struct tgsi_exec_machine *mach)
3288 {
3289 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3290 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3291
3292 UPDATE_EXEC_MASK(mach);
3293 }
3294
3295 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3296 const union tgsi_double_channel *src);
3297
3298 static void
3299 fetch_double_channel(struct tgsi_exec_machine *mach,
3300 union tgsi_double_channel *chan,
3301 const struct tgsi_full_src_register *reg,
3302 uint chan_0,
3303 uint chan_1)
3304 {
3305 union tgsi_exec_channel src[2];
3306 uint i;
3307
3308 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3309 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3310
3311 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3312 chan->u[i][0] = src[0].u[i];
3313 chan->u[i][1] = src[1].u[i];
3314 }
3315 if (reg->Register.Absolute) {
3316 micro_dabs(chan, chan);
3317 }
3318 if (reg->Register.Negate) {
3319 micro_dneg(chan, chan);
3320 }
3321 }
3322
3323 static void
3324 store_double_channel(struct tgsi_exec_machine *mach,
3325 const union tgsi_double_channel *chan,
3326 const struct tgsi_full_dst_register *reg,
3327 const struct tgsi_full_instruction *inst,
3328 uint chan_0,
3329 uint chan_1)
3330 {
3331 union tgsi_exec_channel dst[2];
3332 uint i;
3333 union tgsi_double_channel temp;
3334 const uint execmask = mach->ExecMask;
3335
3336 if (!inst->Instruction.Saturate) {
3337 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3338 if (execmask & (1 << i)) {
3339 dst[0].u[i] = chan->u[i][0];
3340 dst[1].u[i] = chan->u[i][1];
3341 }
3342 }
3343 else {
3344 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3345 if (execmask & (1 << i)) {
3346 if (chan->d[i] < 0.0)
3347 temp.d[i] = 0.0;
3348 else if (chan->d[i] > 1.0)
3349 temp.d[i] = 1.0;
3350 else
3351 temp.d[i] = chan->d[i];
3352
3353 dst[0].u[i] = temp.u[i][0];
3354 dst[1].u[i] = temp.u[i][1];
3355 }
3356 }
3357
3358 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3359 if (chan_1 != -1)
3360 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3361 }
3362
3363 static void
3364 exec_double_unary(struct tgsi_exec_machine *mach,
3365 const struct tgsi_full_instruction *inst,
3366 micro_dop op)
3367 {
3368 union tgsi_double_channel src;
3369 union tgsi_double_channel dst;
3370
3371 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3372 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3373 op(&dst, &src);
3374 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3375 }
3376 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3377 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3378 op(&dst, &src);
3379 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3380 }
3381 }
3382
3383 static void
3384 exec_double_binary(struct tgsi_exec_machine *mach,
3385 const struct tgsi_full_instruction *inst,
3386 micro_dop op,
3387 enum tgsi_exec_datatype dst_datatype)
3388 {
3389 union tgsi_double_channel src[2];
3390 union tgsi_double_channel dst;
3391 int first_dest_chan, second_dest_chan;
3392 int wmask;
3393
3394 wmask = inst->Dst[0].Register.WriteMask;
3395 /* these are & because of the way DSLT etc store their destinations */
3396 if (wmask & TGSI_WRITEMASK_XY) {
3397 first_dest_chan = TGSI_CHAN_X;
3398 second_dest_chan = TGSI_CHAN_Y;
3399 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3400 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3401 second_dest_chan = -1;
3402 }
3403
3404 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3405 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3406 op(&dst, src);
3407 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3408 }
3409
3410 if (wmask & TGSI_WRITEMASK_ZW) {
3411 first_dest_chan = TGSI_CHAN_Z;
3412 second_dest_chan = TGSI_CHAN_W;
3413 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3414 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3415 second_dest_chan = -1;
3416 }
3417
3418 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3419 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3420 op(&dst, src);
3421 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3422 }
3423 }
3424
3425 static void
3426 exec_double_trinary(struct tgsi_exec_machine *mach,
3427 const struct tgsi_full_instruction *inst,
3428 micro_dop op)
3429 {
3430 union tgsi_double_channel src[3];
3431 union tgsi_double_channel dst;
3432
3433 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3434 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3435 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3436 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3437 op(&dst, src);
3438 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3439 }
3440 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3441 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3442 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3443 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3444 op(&dst, src);
3445 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3446 }
3447 }
3448
3449 static void
3450 exec_f2d(struct tgsi_exec_machine *mach,
3451 const struct tgsi_full_instruction *inst)
3452 {
3453 union tgsi_exec_channel src;
3454 union tgsi_double_channel dst;
3455
3456 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3457 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3458 micro_f2d(&dst, &src);
3459 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3460 }
3461 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3462 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3463 micro_f2d(&dst, &src);
3464 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3465 }
3466 }
3467
3468 static void
3469 exec_d2f(struct tgsi_exec_machine *mach,
3470 const struct tgsi_full_instruction *inst)
3471 {
3472 union tgsi_double_channel src;
3473 union tgsi_exec_channel dst;
3474 int wm = inst->Dst[0].Register.WriteMask;
3475 int i;
3476 int bit;
3477 for (i = 0; i < 2; i++) {
3478 bit = ffs(wm);
3479 if (bit) {
3480 wm &= ~(1 << (bit - 1));
3481 if (i == 0)
3482 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3483 else
3484 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3485 micro_d2f(&dst, &src);
3486 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3487 }
3488 }
3489 }
3490
3491 static void
3492 exec_i2d(struct tgsi_exec_machine *mach,
3493 const struct tgsi_full_instruction *inst)
3494 {
3495 union tgsi_exec_channel src;
3496 union tgsi_double_channel dst;
3497
3498 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3499 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3500 micro_i2d(&dst, &src);
3501 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3502 }
3503 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3504 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3505 micro_i2d(&dst, &src);
3506 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3507 }
3508 }
3509
3510 static void
3511 exec_d2i(struct tgsi_exec_machine *mach,
3512 const struct tgsi_full_instruction *inst)
3513 {
3514 union tgsi_double_channel src;
3515 union tgsi_exec_channel dst;
3516 int wm = inst->Dst[0].Register.WriteMask;
3517 int i;
3518 int bit;
3519 for (i = 0; i < 2; i++) {
3520 bit = ffs(wm);
3521 if (bit) {
3522 wm &= ~(1 << (bit - 1));
3523 if (i == 0)
3524 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3525 else
3526 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3527 micro_d2i(&dst, &src);
3528 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3529 }
3530 }
3531 }
3532 static void
3533 exec_u2d(struct tgsi_exec_machine *mach,
3534 const struct tgsi_full_instruction *inst)
3535 {
3536 union tgsi_exec_channel src;
3537 union tgsi_double_channel dst;
3538
3539 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3540 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3541 micro_u2d(&dst, &src);
3542 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3543 }
3544 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3545 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3546 micro_u2d(&dst, &src);
3547 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3548 }
3549 }
3550
3551 static void
3552 exec_d2u(struct tgsi_exec_machine *mach,
3553 const struct tgsi_full_instruction *inst)
3554 {
3555 union tgsi_double_channel src;
3556 union tgsi_exec_channel dst;
3557 int wm = inst->Dst[0].Register.WriteMask;
3558 int i;
3559 int bit;
3560 for (i = 0; i < 2; i++) {
3561 bit = ffs(wm);
3562 if (bit) {
3563 wm &= ~(1 << (bit - 1));
3564 if (i == 0)
3565 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3566 else
3567 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3568 micro_d2u(&dst, &src);
3569 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3570 }
3571 }
3572 }
3573
3574 static void
3575 exec_dldexp(struct tgsi_exec_machine *mach,
3576 const struct tgsi_full_instruction *inst)
3577 {
3578 union tgsi_double_channel src0;
3579 union tgsi_exec_channel src1;
3580 union tgsi_double_channel dst;
3581 int wmask;
3582
3583 wmask = inst->Dst[0].Register.WriteMask;
3584 if (wmask & TGSI_WRITEMASK_XY) {
3585 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3586 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3587 micro_dldexp(&dst, &src0, &src1);
3588 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3589 }
3590
3591 if (wmask & TGSI_WRITEMASK_ZW) {
3592 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3593 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3594 micro_dldexp(&dst, &src0, &src1);
3595 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3596 }
3597 }
3598
3599 static void
3600 exec_dfracexp(struct tgsi_exec_machine *mach,
3601 const struct tgsi_full_instruction *inst)
3602 {
3603 union tgsi_double_channel src;
3604 union tgsi_double_channel dst;
3605 union tgsi_exec_channel dst_exp;
3606
3607 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3608 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3609 micro_dfracexp(&dst, &dst_exp, &src);
3610 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3611 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3612 }
3613 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3614 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3615 micro_dfracexp(&dst, &dst_exp, &src);
3616 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3617 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3618 }
3619 }
3620
3621
3622 static void
3623 micro_i2f(union tgsi_exec_channel *dst,
3624 const union tgsi_exec_channel *src)
3625 {
3626 dst->f[0] = (float)src->i[0];
3627 dst->f[1] = (float)src->i[1];
3628 dst->f[2] = (float)src->i[2];
3629 dst->f[3] = (float)src->i[3];
3630 }
3631
3632 static void
3633 micro_not(union tgsi_exec_channel *dst,
3634 const union tgsi_exec_channel *src)
3635 {
3636 dst->u[0] = ~src->u[0];
3637 dst->u[1] = ~src->u[1];
3638 dst->u[2] = ~src->u[2];
3639 dst->u[3] = ~src->u[3];
3640 }
3641
3642 static void
3643 micro_shl(union tgsi_exec_channel *dst,
3644 const union tgsi_exec_channel *src0,
3645 const union tgsi_exec_channel *src1)
3646 {
3647 unsigned masked_count;
3648 masked_count = src1->u[0] & 0x1f;
3649 dst->u[0] = src0->u[0] << masked_count;
3650 masked_count = src1->u[1] & 0x1f;
3651 dst->u[1] = src0->u[1] << masked_count;
3652 masked_count = src1->u[2] & 0x1f;
3653 dst->u[2] = src0->u[2] << masked_count;
3654 masked_count = src1->u[3] & 0x1f;
3655 dst->u[3] = src0->u[3] << masked_count;
3656 }
3657
3658 static void
3659 micro_and(union tgsi_exec_channel *dst,
3660 const union tgsi_exec_channel *src0,
3661 const union tgsi_exec_channel *src1)
3662 {
3663 dst->u[0] = src0->u[0] & src1->u[0];
3664 dst->u[1] = src0->u[1] & src1->u[1];
3665 dst->u[2] = src0->u[2] & src1->u[2];
3666 dst->u[3] = src0->u[3] & src1->u[3];
3667 }
3668
3669 static void
3670 micro_or(union tgsi_exec_channel *dst,
3671 const union tgsi_exec_channel *src0,
3672 const union tgsi_exec_channel *src1)
3673 {
3674 dst->u[0] = src0->u[0] | src1->u[0];
3675 dst->u[1] = src0->u[1] | src1->u[1];
3676 dst->u[2] = src0->u[2] | src1->u[2];
3677 dst->u[3] = src0->u[3] | src1->u[3];
3678 }
3679
3680 static void
3681 micro_xor(union tgsi_exec_channel *dst,
3682 const union tgsi_exec_channel *src0,
3683 const union tgsi_exec_channel *src1)
3684 {
3685 dst->u[0] = src0->u[0] ^ src1->u[0];
3686 dst->u[1] = src0->u[1] ^ src1->u[1];
3687 dst->u[2] = src0->u[2] ^ src1->u[2];
3688 dst->u[3] = src0->u[3] ^ src1->u[3];
3689 }
3690
3691 static void
3692 micro_mod(union tgsi_exec_channel *dst,
3693 const union tgsi_exec_channel *src0,
3694 const union tgsi_exec_channel *src1)
3695 {
3696 dst->i[0] = src0->i[0] % src1->i[0];
3697 dst->i[1] = src0->i[1] % src1->i[1];
3698 dst->i[2] = src0->i[2] % src1->i[2];
3699 dst->i[3] = src0->i[3] % src1->i[3];
3700 }
3701
3702 static void
3703 micro_f2i(union tgsi_exec_channel *dst,
3704 const union tgsi_exec_channel *src)
3705 {
3706 dst->i[0] = (int)src->f[0];
3707 dst->i[1] = (int)src->f[1];
3708 dst->i[2] = (int)src->f[2];
3709 dst->i[3] = (int)src->f[3];
3710 }
3711
3712 static void
3713 micro_fseq(union tgsi_exec_channel *dst,
3714 const union tgsi_exec_channel *src0,
3715 const union tgsi_exec_channel *src1)
3716 {
3717 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3718 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3719 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3720 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3721 }
3722
3723 static void
3724 micro_fsge(union tgsi_exec_channel *dst,
3725 const union tgsi_exec_channel *src0,
3726 const union tgsi_exec_channel *src1)
3727 {
3728 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3729 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3730 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3731 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3732 }
3733
3734 static void
3735 micro_fslt(union tgsi_exec_channel *dst,
3736 const union tgsi_exec_channel *src0,
3737 const union tgsi_exec_channel *src1)
3738 {
3739 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3740 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3741 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3742 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3743 }
3744
3745 static void
3746 micro_fsne(union tgsi_exec_channel *dst,
3747 const union tgsi_exec_channel *src0,
3748 const union tgsi_exec_channel *src1)
3749 {
3750 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3751 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3752 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3753 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3754 }
3755
3756 static void
3757 micro_idiv(union tgsi_exec_channel *dst,
3758 const union tgsi_exec_channel *src0,
3759 const union tgsi_exec_channel *src1)
3760 {
3761 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
3762 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
3763 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
3764 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
3765 }
3766
3767 static void
3768 micro_imax(union tgsi_exec_channel *dst,
3769 const union tgsi_exec_channel *src0,
3770 const union tgsi_exec_channel *src1)
3771 {
3772 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3773 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3774 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3775 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3776 }
3777
3778 static void
3779 micro_imin(union tgsi_exec_channel *dst,
3780 const union tgsi_exec_channel *src0,
3781 const union tgsi_exec_channel *src1)
3782 {
3783 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3784 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3785 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3786 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3787 }
3788
3789 static void
3790 micro_isge(union tgsi_exec_channel *dst,
3791 const union tgsi_exec_channel *src0,
3792 const union tgsi_exec_channel *src1)
3793 {
3794 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3795 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3796 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3797 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3798 }
3799
3800 static void
3801 micro_ishr(union tgsi_exec_channel *dst,
3802 const union tgsi_exec_channel *src0,
3803 const union tgsi_exec_channel *src1)
3804 {
3805 unsigned masked_count;
3806 masked_count = src1->i[0] & 0x1f;
3807 dst->i[0] = src0->i[0] >> masked_count;
3808 masked_count = src1->i[1] & 0x1f;
3809 dst->i[1] = src0->i[1] >> masked_count;
3810 masked_count = src1->i[2] & 0x1f;
3811 dst->i[2] = src0->i[2] >> masked_count;
3812 masked_count = src1->i[3] & 0x1f;
3813 dst->i[3] = src0->i[3] >> masked_count;
3814 }
3815
3816 static void
3817 micro_islt(union tgsi_exec_channel *dst,
3818 const union tgsi_exec_channel *src0,
3819 const union tgsi_exec_channel *src1)
3820 {
3821 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3822 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3823 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3824 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3825 }
3826
3827 static void
3828 micro_f2u(union tgsi_exec_channel *dst,
3829 const union tgsi_exec_channel *src)
3830 {
3831 dst->u[0] = (uint)src->f[0];
3832 dst->u[1] = (uint)src->f[1];
3833 dst->u[2] = (uint)src->f[2];
3834 dst->u[3] = (uint)src->f[3];
3835 }
3836
3837 static void
3838 micro_u2f(union tgsi_exec_channel *dst,
3839 const union tgsi_exec_channel *src)
3840 {
3841 dst->f[0] = (float)src->u[0];
3842 dst->f[1] = (float)src->u[1];
3843 dst->f[2] = (float)src->u[2];
3844 dst->f[3] = (float)src->u[3];
3845 }
3846
3847 static void
3848 micro_uadd(union tgsi_exec_channel *dst,
3849 const union tgsi_exec_channel *src0,
3850 const union tgsi_exec_channel *src1)
3851 {
3852 dst->u[0] = src0->u[0] + src1->u[0];
3853 dst->u[1] = src0->u[1] + src1->u[1];
3854 dst->u[2] = src0->u[2] + src1->u[2];
3855 dst->u[3] = src0->u[3] + src1->u[3];
3856 }
3857
3858 static void
3859 micro_udiv(union tgsi_exec_channel *dst,
3860 const union tgsi_exec_channel *src0,
3861 const union tgsi_exec_channel *src1)
3862 {
3863 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3864 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3865 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3866 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3867 }
3868
3869 static void
3870 micro_umad(union tgsi_exec_channel *dst,
3871 const union tgsi_exec_channel *src0,
3872 const union tgsi_exec_channel *src1,
3873 const union tgsi_exec_channel *src2)
3874 {
3875 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3876 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3877 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3878 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3879 }
3880
3881 static void
3882 micro_umax(union tgsi_exec_channel *dst,
3883 const union tgsi_exec_channel *src0,
3884 const union tgsi_exec_channel *src1)
3885 {
3886 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3887 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3888 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3889 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3890 }
3891
3892 static void
3893 micro_umin(union tgsi_exec_channel *dst,
3894 const union tgsi_exec_channel *src0,
3895 const union tgsi_exec_channel *src1)
3896 {
3897 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3898 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3899 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3900 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3901 }
3902
3903 static void
3904 micro_umod(union tgsi_exec_channel *dst,
3905 const union tgsi_exec_channel *src0,
3906 const union tgsi_exec_channel *src1)
3907 {
3908 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3909 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3910 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3911 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3912 }
3913
3914 static void
3915 micro_umul(union tgsi_exec_channel *dst,
3916 const union tgsi_exec_channel *src0,
3917 const union tgsi_exec_channel *src1)
3918 {
3919 dst->u[0] = src0->u[0] * src1->u[0];
3920 dst->u[1] = src0->u[1] * src1->u[1];
3921 dst->u[2] = src0->u[2] * src1->u[2];
3922 dst->u[3] = src0->u[3] * src1->u[3];
3923 }
3924
3925 static void
3926 micro_imul_hi(union tgsi_exec_channel *dst,
3927 const union tgsi_exec_channel *src0,
3928 const union tgsi_exec_channel *src1)
3929 {
3930 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3931 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3932 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3933 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3934 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3935 #undef I64M
3936 }
3937
3938 static void
3939 micro_umul_hi(union tgsi_exec_channel *dst,
3940 const union tgsi_exec_channel *src0,
3941 const union tgsi_exec_channel *src1)
3942 {
3943 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3944 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3945 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3946 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3947 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3948 #undef U64M
3949 }
3950
3951 static void
3952 micro_useq(union tgsi_exec_channel *dst,
3953 const union tgsi_exec_channel *src0,
3954 const union tgsi_exec_channel *src1)
3955 {
3956 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3957 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3958 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3959 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3960 }
3961
3962 static void
3963 micro_usge(union tgsi_exec_channel *dst,
3964 const union tgsi_exec_channel *src0,
3965 const union tgsi_exec_channel *src1)
3966 {
3967 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3968 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3969 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3970 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3971 }
3972
3973 static void
3974 micro_ushr(union tgsi_exec_channel *dst,
3975 const union tgsi_exec_channel *src0,
3976 const union tgsi_exec_channel *src1)
3977 {
3978 unsigned masked_count;
3979 masked_count = src1->u[0] & 0x1f;
3980 dst->u[0] = src0->u[0] >> masked_count;
3981 masked_count = src1->u[1] & 0x1f;
3982 dst->u[1] = src0->u[1] >> masked_count;
3983 masked_count = src1->u[2] & 0x1f;
3984 dst->u[2] = src0->u[2] >> masked_count;
3985 masked_count = src1->u[3] & 0x1f;
3986 dst->u[3] = src0->u[3] >> masked_count;
3987 }
3988
3989 static void
3990 micro_uslt(union tgsi_exec_channel *dst,
3991 const union tgsi_exec_channel *src0,
3992 const union tgsi_exec_channel *src1)
3993 {
3994 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3995 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3996 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3997 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3998 }
3999
4000 static void
4001 micro_usne(union tgsi_exec_channel *dst,
4002 const union tgsi_exec_channel *src0,
4003 const union tgsi_exec_channel *src1)
4004 {
4005 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4006 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4007 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4008 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4009 }
4010
4011 static void
4012 micro_uarl(union tgsi_exec_channel *dst,
4013 const union tgsi_exec_channel *src)
4014 {
4015 dst->i[0] = src->u[0];
4016 dst->i[1] = src->u[1];
4017 dst->i[2] = src->u[2];
4018 dst->i[3] = src->u[3];
4019 }
4020
4021 static void
4022 micro_ucmp(union tgsi_exec_channel *dst,
4023 const union tgsi_exec_channel *src0,
4024 const union tgsi_exec_channel *src1,
4025 const union tgsi_exec_channel *src2)
4026 {
4027 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4028 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4029 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4030 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4031 }
4032
4033 /**
4034 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4035 */
4036 static void
4037 micro_ibfe(union tgsi_exec_channel *dst,
4038 const union tgsi_exec_channel *src0,
4039 const union tgsi_exec_channel *src1,
4040 const union tgsi_exec_channel *src2)
4041 {
4042 int i;
4043 for (i = 0; i < 4; i++) {
4044 int width = src2->i[i] & 0x1f;
4045 int offset = src1->i[i] & 0x1f;
4046 if (width == 0)
4047 dst->i[i] = 0;
4048 else if (width + offset < 32)
4049 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4050 else
4051 dst->i[i] = src0->i[i] >> offset;
4052 }
4053 }
4054
4055 /**
4056 * Unsigned bitfield extract
4057 */
4058 static void
4059 micro_ubfe(union tgsi_exec_channel *dst,
4060 const union tgsi_exec_channel *src0,
4061 const union tgsi_exec_channel *src1,
4062 const union tgsi_exec_channel *src2)
4063 {
4064 int i;
4065 for (i = 0; i < 4; i++) {
4066 int width = src2->u[i] & 0x1f;
4067 int offset = src1->u[i] & 0x1f;
4068 if (width == 0)
4069 dst->u[i] = 0;
4070 else if (width + offset < 32)
4071 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4072 else
4073 dst->u[i] = src0->u[i] >> offset;
4074 }
4075 }
4076
4077 /**
4078 * Bitfield insert: copy low bits from src1 into a region of src0.
4079 */
4080 static void
4081 micro_bfi(union tgsi_exec_channel *dst,
4082 const union tgsi_exec_channel *src0,
4083 const union tgsi_exec_channel *src1,
4084 const union tgsi_exec_channel *src2,
4085 const union tgsi_exec_channel *src3)
4086 {
4087 int i;
4088 for (i = 0; i < 4; i++) {
4089 int width = src3->u[i] & 0x1f;
4090 int offset = src2->u[i] & 0x1f;
4091 int bitmask = ((1 << width) - 1) << offset;
4092 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4093 }
4094 }
4095
4096 static void
4097 micro_brev(union tgsi_exec_channel *dst,
4098 const union tgsi_exec_channel *src)
4099 {
4100 dst->u[0] = util_bitreverse(src->u[0]);
4101 dst->u[1] = util_bitreverse(src->u[1]);
4102 dst->u[2] = util_bitreverse(src->u[2]);
4103 dst->u[3] = util_bitreverse(src->u[3]);
4104 }
4105
4106 static void
4107 micro_popc(union tgsi_exec_channel *dst,
4108 const union tgsi_exec_channel *src)
4109 {
4110 dst->u[0] = util_bitcount(src->u[0]);
4111 dst->u[1] = util_bitcount(src->u[1]);
4112 dst->u[2] = util_bitcount(src->u[2]);
4113 dst->u[3] = util_bitcount(src->u[3]);
4114 }
4115
4116 static void
4117 micro_lsb(union tgsi_exec_channel *dst,
4118 const union tgsi_exec_channel *src)
4119 {
4120 dst->i[0] = ffs(src->u[0]) - 1;
4121 dst->i[1] = ffs(src->u[1]) - 1;
4122 dst->i[2] = ffs(src->u[2]) - 1;
4123 dst->i[3] = ffs(src->u[3]) - 1;
4124 }
4125
4126 static void
4127 micro_imsb(union tgsi_exec_channel *dst,
4128 const union tgsi_exec_channel *src)
4129 {
4130 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4131 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4132 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4133 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4134 }
4135
4136 static void
4137 micro_umsb(union tgsi_exec_channel *dst,
4138 const union tgsi_exec_channel *src)
4139 {
4140 dst->i[0] = util_last_bit(src->u[0]) - 1;
4141 dst->i[1] = util_last_bit(src->u[1]) - 1;
4142 dst->i[2] = util_last_bit(src->u[2]) - 1;
4143 dst->i[3] = util_last_bit(src->u[3]) - 1;
4144 }
4145
4146 static void
4147 exec_instruction(
4148 struct tgsi_exec_machine *mach,
4149 const struct tgsi_full_instruction *inst,
4150 int *pc )
4151 {
4152 union tgsi_exec_channel r[10];
4153
4154 (*pc)++;
4155
4156 switch (inst->Instruction.Opcode) {
4157 case TGSI_OPCODE_ARL:
4158 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4159 break;
4160
4161 case TGSI_OPCODE_MOV:
4162 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4163 break;
4164
4165 case TGSI_OPCODE_LIT:
4166 exec_lit(mach, inst);
4167 break;
4168
4169 case TGSI_OPCODE_RCP:
4170 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4171 break;
4172
4173 case TGSI_OPCODE_RSQ:
4174 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4175 break;
4176
4177 case TGSI_OPCODE_EXP:
4178 exec_exp(mach, inst);
4179 break;
4180
4181 case TGSI_OPCODE_LOG:
4182 exec_log(mach, inst);
4183 break;
4184
4185 case TGSI_OPCODE_MUL:
4186 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4187 break;
4188
4189 case TGSI_OPCODE_ADD:
4190 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4191 break;
4192
4193 case TGSI_OPCODE_DP3:
4194 exec_dp3(mach, inst);
4195 break;
4196
4197 case TGSI_OPCODE_DP4:
4198 exec_dp4(mach, inst);
4199 break;
4200
4201 case TGSI_OPCODE_DST:
4202 exec_dst(mach, inst);
4203 break;
4204
4205 case TGSI_OPCODE_MIN:
4206 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4207 break;
4208
4209 case TGSI_OPCODE_MAX:
4210 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4211 break;
4212
4213 case TGSI_OPCODE_SLT:
4214 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4215 break;
4216
4217 case TGSI_OPCODE_SGE:
4218 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4219 break;
4220
4221 case TGSI_OPCODE_MAD:
4222 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4223 break;
4224
4225 case TGSI_OPCODE_SUB:
4226 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4227 break;
4228
4229 case TGSI_OPCODE_LRP:
4230 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4231 break;
4232
4233 case TGSI_OPCODE_SQRT:
4234 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4235 break;
4236
4237 case TGSI_OPCODE_DP2A:
4238 exec_dp2a(mach, inst);
4239 break;
4240
4241 case TGSI_OPCODE_FRC:
4242 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4243 break;
4244
4245 case TGSI_OPCODE_CLAMP:
4246 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4247 break;
4248
4249 case TGSI_OPCODE_FLR:
4250 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4251 break;
4252
4253 case TGSI_OPCODE_ROUND:
4254 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4255 break;
4256
4257 case TGSI_OPCODE_EX2:
4258 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4259 break;
4260
4261 case TGSI_OPCODE_LG2:
4262 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4263 break;
4264
4265 case TGSI_OPCODE_POW:
4266 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4267 break;
4268
4269 case TGSI_OPCODE_XPD:
4270 exec_xpd(mach, inst);
4271 break;
4272
4273 case TGSI_OPCODE_ABS:
4274 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4275 break;
4276
4277 case TGSI_OPCODE_DPH:
4278 exec_dph(mach, inst);
4279 break;
4280
4281 case TGSI_OPCODE_COS:
4282 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4283 break;
4284
4285 case TGSI_OPCODE_DDX:
4286 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4287 break;
4288
4289 case TGSI_OPCODE_DDY:
4290 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4291 break;
4292
4293 case TGSI_OPCODE_KILL:
4294 exec_kill (mach, inst);
4295 break;
4296
4297 case TGSI_OPCODE_KILL_IF:
4298 exec_kill_if (mach, inst);
4299 break;
4300
4301 case TGSI_OPCODE_PK2H:
4302 assert (0);
4303 break;
4304
4305 case TGSI_OPCODE_PK2US:
4306 assert (0);
4307 break;
4308
4309 case TGSI_OPCODE_PK4B:
4310 assert (0);
4311 break;
4312
4313 case TGSI_OPCODE_PK4UB:
4314 assert (0);
4315 break;
4316
4317 case TGSI_OPCODE_SEQ:
4318 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4319 break;
4320
4321 case TGSI_OPCODE_SGT:
4322 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4323 break;
4324
4325 case TGSI_OPCODE_SIN:
4326 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4327 break;
4328
4329 case TGSI_OPCODE_SLE:
4330 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4331 break;
4332
4333 case TGSI_OPCODE_SNE:
4334 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4335 break;
4336
4337 case TGSI_OPCODE_TEX:
4338 /* simple texture lookup */
4339 /* src[0] = texcoord */
4340 /* src[1] = sampler unit */
4341 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
4342 break;
4343
4344 case TGSI_OPCODE_TXB:
4345 /* Texture lookup with lod bias */
4346 /* src[0] = texcoord (src[0].w = LOD bias) */
4347 /* src[1] = sampler unit */
4348 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
4349 break;
4350
4351 case TGSI_OPCODE_TXD:
4352 /* Texture lookup with explict partial derivatives */
4353 /* src[0] = texcoord */
4354 /* src[1] = d[strq]/dx */
4355 /* src[2] = d[strq]/dy */
4356 /* src[3] = sampler unit */
4357 exec_txd(mach, inst);
4358 break;
4359
4360 case TGSI_OPCODE_TXL:
4361 /* Texture lookup with explit LOD */
4362 /* src[0] = texcoord (src[0].w = LOD) */
4363 /* src[1] = sampler unit */
4364 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
4365 break;
4366
4367 case TGSI_OPCODE_TXP:
4368 /* Texture lookup with projection */
4369 /* src[0] = texcoord (src[0].w = projection) */
4370 /* src[1] = sampler unit */
4371 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
4372 break;
4373
4374 case TGSI_OPCODE_TG4:
4375 /* src[0] = texcoord */
4376 /* src[1] = component */
4377 /* src[2] = sampler unit */
4378 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
4379 break;
4380
4381 case TGSI_OPCODE_UP2H:
4382 assert (0);
4383 break;
4384
4385 case TGSI_OPCODE_UP2US:
4386 assert (0);
4387 break;
4388
4389 case TGSI_OPCODE_UP4B:
4390 assert (0);
4391 break;
4392
4393 case TGSI_OPCODE_UP4UB:
4394 assert (0);
4395 break;
4396
4397 case TGSI_OPCODE_ARR:
4398 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4399 break;
4400
4401 case TGSI_OPCODE_CAL:
4402 /* skip the call if no execution channels are enabled */
4403 if (mach->ExecMask) {
4404 /* do the call */
4405
4406 /* First, record the depths of the execution stacks.
4407 * This is important for deeply nested/looped return statements.
4408 * We have to unwind the stacks by the correct amount. For a
4409 * real code generator, we could determine the number of entries
4410 * to pop off each stack with simple static analysis and avoid
4411 * implementing this data structure at run time.
4412 */
4413 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4414 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4415 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4416 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4417 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4418 /* note that PC was already incremented above */
4419 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4420
4421 mach->CallStackTop++;
4422
4423 /* Second, push the Cond, Loop, Cont, Func stacks */
4424 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4425 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4426 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4427 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4428 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4429 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4430
4431 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4432 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4433 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4434 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4435 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4436 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4437
4438 /* Finally, jump to the subroutine. The label is a pointer
4439 * (an instruction number) to the BGNSUB instruction.
4440 */
4441 *pc = inst->Label.Label;
4442 assert(mach->Instructions[*pc].Instruction.Opcode
4443 == TGSI_OPCODE_BGNSUB);
4444 }
4445 break;
4446
4447 case TGSI_OPCODE_RET:
4448 mach->FuncMask &= ~mach->ExecMask;
4449 UPDATE_EXEC_MASK(mach);
4450
4451 if (mach->FuncMask == 0x0) {
4452 /* really return now (otherwise, keep executing */
4453
4454 if (mach->CallStackTop == 0) {
4455 /* returning from main() */
4456 mach->CondStackTop = 0;
4457 mach->LoopStackTop = 0;
4458 *pc = -1;
4459 return;
4460 }
4461
4462 assert(mach->CallStackTop > 0);
4463 mach->CallStackTop--;
4464
4465 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4466 mach->CondMask = mach->CondStack[mach->CondStackTop];
4467
4468 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4469 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4470
4471 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4472 mach->ContMask = mach->ContStack[mach->ContStackTop];
4473
4474 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4475 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4476
4477 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4478 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4479
4480 assert(mach->FuncStackTop > 0);
4481 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4482
4483 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4484
4485 UPDATE_EXEC_MASK(mach);
4486 }
4487 break;
4488
4489 case TGSI_OPCODE_SSG:
4490 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4491 break;
4492
4493 case TGSI_OPCODE_CMP:
4494 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4495 break;
4496
4497 case TGSI_OPCODE_SCS:
4498 exec_scs(mach, inst);
4499 break;
4500
4501 case TGSI_OPCODE_DIV:
4502 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4503 break;
4504
4505 case TGSI_OPCODE_DP2:
4506 exec_dp2(mach, inst);
4507 break;
4508
4509 case TGSI_OPCODE_IF:
4510 /* push CondMask */
4511 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4512 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4513 FETCH( &r[0], 0, TGSI_CHAN_X );
4514 /* update CondMask */
4515 if( ! r[0].f[0] ) {
4516 mach->CondMask &= ~0x1;
4517 }
4518 if( ! r[0].f[1] ) {
4519 mach->CondMask &= ~0x2;
4520 }
4521 if( ! r[0].f[2] ) {
4522 mach->CondMask &= ~0x4;
4523 }
4524 if( ! r[0].f[3] ) {
4525 mach->CondMask &= ~0x8;
4526 }
4527 UPDATE_EXEC_MASK(mach);
4528 /* Todo: If CondMask==0, jump to ELSE */
4529 break;
4530
4531 case TGSI_OPCODE_UIF:
4532 /* push CondMask */
4533 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4534 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4535 IFETCH( &r[0], 0, TGSI_CHAN_X );
4536 /* update CondMask */
4537 if( ! r[0].u[0] ) {
4538 mach->CondMask &= ~0x1;
4539 }
4540 if( ! r[0].u[1] ) {
4541 mach->CondMask &= ~0x2;
4542 }
4543 if( ! r[0].u[2] ) {
4544 mach->CondMask &= ~0x4;
4545 }
4546 if( ! r[0].u[3] ) {
4547 mach->CondMask &= ~0x8;
4548 }
4549 UPDATE_EXEC_MASK(mach);
4550 /* Todo: If CondMask==0, jump to ELSE */
4551 break;
4552
4553 case TGSI_OPCODE_ELSE:
4554 /* invert CondMask wrt previous mask */
4555 {
4556 uint prevMask;
4557 assert(mach->CondStackTop > 0);
4558 prevMask = mach->CondStack[mach->CondStackTop - 1];
4559 mach->CondMask = ~mach->CondMask & prevMask;
4560 UPDATE_EXEC_MASK(mach);
4561 /* Todo: If CondMask==0, jump to ENDIF */
4562 }
4563 break;
4564
4565 case TGSI_OPCODE_ENDIF:
4566 /* pop CondMask */
4567 assert(mach->CondStackTop > 0);
4568 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4569 UPDATE_EXEC_MASK(mach);
4570 break;
4571
4572 case TGSI_OPCODE_END:
4573 /* make sure we end primitives which haven't
4574 * been explicitly emitted */
4575 conditional_emit_primitive(mach);
4576 /* halt execution */
4577 *pc = -1;
4578 break;
4579
4580 case TGSI_OPCODE_PUSHA:
4581 assert (0);
4582 break;
4583
4584 case TGSI_OPCODE_POPA:
4585 assert (0);
4586 break;
4587
4588 case TGSI_OPCODE_CEIL:
4589 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4590 break;
4591
4592 case TGSI_OPCODE_I2F:
4593 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4594 break;
4595
4596 case TGSI_OPCODE_NOT:
4597 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4598 break;
4599
4600 case TGSI_OPCODE_TRUNC:
4601 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4602 break;
4603
4604 case TGSI_OPCODE_SHL:
4605 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4606 break;
4607
4608 case TGSI_OPCODE_AND:
4609 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4610 break;
4611
4612 case TGSI_OPCODE_OR:
4613 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4614 break;
4615
4616 case TGSI_OPCODE_MOD:
4617 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4618 break;
4619
4620 case TGSI_OPCODE_XOR:
4621 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4622 break;
4623
4624 case TGSI_OPCODE_SAD:
4625 assert (0);
4626 break;
4627
4628 case TGSI_OPCODE_TXF:
4629 exec_txf(mach, inst);
4630 break;
4631
4632 case TGSI_OPCODE_TXQ:
4633 exec_txq(mach, inst);
4634 break;
4635
4636 case TGSI_OPCODE_EMIT:
4637 emit_vertex(mach);
4638 break;
4639
4640 case TGSI_OPCODE_ENDPRIM:
4641 emit_primitive(mach);
4642 break;
4643
4644 case TGSI_OPCODE_BGNLOOP:
4645 /* push LoopMask and ContMasks */
4646 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4647 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4648 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4649 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4650
4651 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4652 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4653 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4654 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4655 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4656 break;
4657
4658 case TGSI_OPCODE_ENDLOOP:
4659 /* Restore ContMask, but don't pop */
4660 assert(mach->ContStackTop > 0);
4661 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4662 UPDATE_EXEC_MASK(mach);
4663 if (mach->ExecMask) {
4664 /* repeat loop: jump to instruction just past BGNLOOP */
4665 assert(mach->LoopLabelStackTop > 0);
4666 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4667 }
4668 else {
4669 /* exit loop: pop LoopMask */
4670 assert(mach->LoopStackTop > 0);
4671 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4672 /* pop ContMask */
4673 assert(mach->ContStackTop > 0);
4674 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4675 assert(mach->LoopLabelStackTop > 0);
4676 --mach->LoopLabelStackTop;
4677
4678 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4679 }
4680 UPDATE_EXEC_MASK(mach);
4681 break;
4682
4683 case TGSI_OPCODE_BRK:
4684 exec_break(mach);
4685 break;
4686
4687 case TGSI_OPCODE_CONT:
4688 /* turn off cont channels for each enabled exec channel */
4689 mach->ContMask &= ~mach->ExecMask;
4690 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4691 UPDATE_EXEC_MASK(mach);
4692 break;
4693
4694 case TGSI_OPCODE_BGNSUB:
4695 /* no-op */
4696 break;
4697
4698 case TGSI_OPCODE_ENDSUB:
4699 /*
4700 * XXX: This really should be a no-op. We should never reach this opcode.
4701 */
4702
4703 assert(mach->CallStackTop > 0);
4704 mach->CallStackTop--;
4705
4706 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4707 mach->CondMask = mach->CondStack[mach->CondStackTop];
4708
4709 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4710 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4711
4712 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4713 mach->ContMask = mach->ContStack[mach->ContStackTop];
4714
4715 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4716 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4717
4718 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4719 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4720
4721 assert(mach->FuncStackTop > 0);
4722 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4723
4724 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4725
4726 UPDATE_EXEC_MASK(mach);
4727 break;
4728
4729 case TGSI_OPCODE_NOP:
4730 break;
4731
4732 case TGSI_OPCODE_BREAKC:
4733 IFETCH(&r[0], 0, TGSI_CHAN_X);
4734 /* update CondMask */
4735 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4736 mach->LoopMask &= ~0x1;
4737 }
4738 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4739 mach->LoopMask &= ~0x2;
4740 }
4741 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4742 mach->LoopMask &= ~0x4;
4743 }
4744 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4745 mach->LoopMask &= ~0x8;
4746 }
4747 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4748 UPDATE_EXEC_MASK(mach);
4749 break;
4750
4751 case TGSI_OPCODE_F2I:
4752 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4753 break;
4754
4755 case TGSI_OPCODE_FSEQ:
4756 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4757 break;
4758
4759 case TGSI_OPCODE_FSGE:
4760 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4761 break;
4762
4763 case TGSI_OPCODE_FSLT:
4764 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4765 break;
4766
4767 case TGSI_OPCODE_FSNE:
4768 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4769 break;
4770
4771 case TGSI_OPCODE_IDIV:
4772 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4773 break;
4774
4775 case TGSI_OPCODE_IMAX:
4776 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4777 break;
4778
4779 case TGSI_OPCODE_IMIN:
4780 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4781 break;
4782
4783 case TGSI_OPCODE_INEG:
4784 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4785 break;
4786
4787 case TGSI_OPCODE_ISGE:
4788 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4789 break;
4790
4791 case TGSI_OPCODE_ISHR:
4792 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4793 break;
4794
4795 case TGSI_OPCODE_ISLT:
4796 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4797 break;
4798
4799 case TGSI_OPCODE_F2U:
4800 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4801 break;
4802
4803 case TGSI_OPCODE_U2F:
4804 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4805 break;
4806
4807 case TGSI_OPCODE_UADD:
4808 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4809 break;
4810
4811 case TGSI_OPCODE_UDIV:
4812 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4813 break;
4814
4815 case TGSI_OPCODE_UMAD:
4816 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4817 break;
4818
4819 case TGSI_OPCODE_UMAX:
4820 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4821 break;
4822
4823 case TGSI_OPCODE_UMIN:
4824 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4825 break;
4826
4827 case TGSI_OPCODE_UMOD:
4828 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4829 break;
4830
4831 case TGSI_OPCODE_UMUL:
4832 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4833 break;
4834
4835 case TGSI_OPCODE_IMUL_HI:
4836 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4837 break;
4838
4839 case TGSI_OPCODE_UMUL_HI:
4840 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4841 break;
4842
4843 case TGSI_OPCODE_USEQ:
4844 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4845 break;
4846
4847 case TGSI_OPCODE_USGE:
4848 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4849 break;
4850
4851 case TGSI_OPCODE_USHR:
4852 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4853 break;
4854
4855 case TGSI_OPCODE_USLT:
4856 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4857 break;
4858
4859 case TGSI_OPCODE_USNE:
4860 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4861 break;
4862
4863 case TGSI_OPCODE_SWITCH:
4864 exec_switch(mach, inst);
4865 break;
4866
4867 case TGSI_OPCODE_CASE:
4868 exec_case(mach, inst);
4869 break;
4870
4871 case TGSI_OPCODE_DEFAULT:
4872 exec_default(mach);
4873 break;
4874
4875 case TGSI_OPCODE_ENDSWITCH:
4876 exec_endswitch(mach);
4877 break;
4878
4879 case TGSI_OPCODE_SAMPLE_I:
4880 exec_txf(mach, inst);
4881 break;
4882
4883 case TGSI_OPCODE_SAMPLE_I_MS:
4884 assert(0);
4885 break;
4886
4887 case TGSI_OPCODE_SAMPLE:
4888 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4889 break;
4890
4891 case TGSI_OPCODE_SAMPLE_B:
4892 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4893 break;
4894
4895 case TGSI_OPCODE_SAMPLE_C:
4896 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4897 break;
4898
4899 case TGSI_OPCODE_SAMPLE_C_LZ:
4900 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4901 break;
4902
4903 case TGSI_OPCODE_SAMPLE_D:
4904 exec_sample_d(mach, inst);
4905 break;
4906
4907 case TGSI_OPCODE_SAMPLE_L:
4908 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4909 break;
4910
4911 case TGSI_OPCODE_GATHER4:
4912 assert(0);
4913 break;
4914
4915 case TGSI_OPCODE_SVIEWINFO:
4916 exec_txq(mach, inst);
4917 break;
4918
4919 case TGSI_OPCODE_SAMPLE_POS:
4920 assert(0);
4921 break;
4922
4923 case TGSI_OPCODE_SAMPLE_INFO:
4924 assert(0);
4925 break;
4926
4927 case TGSI_OPCODE_UARL:
4928 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4929 break;
4930
4931 case TGSI_OPCODE_UCMP:
4932 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4933 break;
4934
4935 case TGSI_OPCODE_IABS:
4936 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4937 break;
4938
4939 case TGSI_OPCODE_ISSG:
4940 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4941 break;
4942
4943 case TGSI_OPCODE_TEX2:
4944 /* simple texture lookup */
4945 /* src[0] = texcoord */
4946 /* src[1] = compare */
4947 /* src[2] = sampler unit */
4948 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4949 break;
4950 case TGSI_OPCODE_TXB2:
4951 /* simple texture lookup */
4952 /* src[0] = texcoord */
4953 /* src[1] = bias */
4954 /* src[2] = sampler unit */
4955 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4956 break;
4957 case TGSI_OPCODE_TXL2:
4958 /* simple texture lookup */
4959 /* src[0] = texcoord */
4960 /* src[1] = lod */
4961 /* src[2] = sampler unit */
4962 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4963 break;
4964
4965 case TGSI_OPCODE_IBFE:
4966 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4967 break;
4968 case TGSI_OPCODE_UBFE:
4969 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4970 break;
4971 case TGSI_OPCODE_BFI:
4972 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4973 break;
4974 case TGSI_OPCODE_BREV:
4975 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4976 break;
4977 case TGSI_OPCODE_POPC:
4978 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4979 break;
4980 case TGSI_OPCODE_LSB:
4981 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4982 break;
4983 case TGSI_OPCODE_IMSB:
4984 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4985 break;
4986 case TGSI_OPCODE_UMSB:
4987 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4988 break;
4989
4990 case TGSI_OPCODE_F2D:
4991 exec_f2d(mach, inst);
4992 break;
4993
4994 case TGSI_OPCODE_D2F:
4995 exec_d2f(mach, inst);
4996 break;
4997
4998 case TGSI_OPCODE_DABS:
4999 exec_double_unary(mach, inst, micro_dabs);
5000 break;
5001
5002 case TGSI_OPCODE_DNEG:
5003 exec_double_unary(mach, inst, micro_dneg);
5004 break;
5005
5006 case TGSI_OPCODE_DADD:
5007 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5008 break;
5009
5010 case TGSI_OPCODE_DMUL:
5011 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5012 break;
5013
5014 case TGSI_OPCODE_DMAX:
5015 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5016 break;
5017
5018 case TGSI_OPCODE_DMIN:
5019 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5020 break;
5021
5022 case TGSI_OPCODE_DSLT:
5023 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5024 break;
5025
5026 case TGSI_OPCODE_DSGE:
5027 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5028 break;
5029
5030 case TGSI_OPCODE_DSEQ:
5031 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5032 break;
5033
5034 case TGSI_OPCODE_DSNE:
5035 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5036 break;
5037
5038 case TGSI_OPCODE_DRCP:
5039 exec_double_unary(mach, inst, micro_drcp);
5040 break;
5041
5042 case TGSI_OPCODE_DSQRT:
5043 exec_double_unary(mach, inst, micro_dsqrt);
5044 break;
5045
5046 case TGSI_OPCODE_DRSQ:
5047 exec_double_unary(mach, inst, micro_drsq);
5048 break;
5049
5050 case TGSI_OPCODE_DMAD:
5051 exec_double_trinary(mach, inst, micro_dmad);
5052 break;
5053
5054 case TGSI_OPCODE_DFRAC:
5055 exec_double_unary(mach, inst, micro_dfrac);
5056 break;
5057
5058 case TGSI_OPCODE_DLDEXP:
5059 exec_dldexp(mach, inst);
5060 break;
5061
5062 case TGSI_OPCODE_DFRACEXP:
5063 exec_dfracexp(mach, inst);
5064 break;
5065
5066 case TGSI_OPCODE_I2D:
5067 exec_i2d(mach, inst);
5068 break;
5069
5070 case TGSI_OPCODE_D2I:
5071 exec_d2i(mach, inst);
5072 break;
5073
5074 case TGSI_OPCODE_U2D:
5075 exec_u2d(mach, inst);
5076 break;
5077
5078 case TGSI_OPCODE_D2U:
5079 exec_d2u(mach, inst);
5080 break;
5081 default:
5082 assert( 0 );
5083 }
5084 }
5085
5086
5087 /**
5088 * Run TGSI interpreter.
5089 * \return bitmask of "alive" quad components
5090 */
5091 uint
5092 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
5093 {
5094 uint i;
5095 int pc = 0;
5096 uint default_mask = 0xf;
5097
5098 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5099 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5100
5101 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
5102 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5103 mach->Primitives[0] = 0;
5104 /* GS runs on a single primitive for now */
5105 default_mask = 0x1;
5106 }
5107
5108 mach->CondMask = default_mask;
5109 mach->LoopMask = default_mask;
5110 mach->ContMask = default_mask;
5111 mach->FuncMask = default_mask;
5112 mach->ExecMask = default_mask;
5113
5114 mach->Switch.mask = default_mask;
5115
5116 assert(mach->CondStackTop == 0);
5117 assert(mach->LoopStackTop == 0);
5118 assert(mach->ContStackTop == 0);
5119 assert(mach->SwitchStackTop == 0);
5120 assert(mach->BreakStackTop == 0);
5121 assert(mach->CallStackTop == 0);
5122
5123
5124 /* execute declarations (interpolants) */
5125 for (i = 0; i < mach->NumDeclarations; i++) {
5126 exec_declaration( mach, mach->Declarations+i );
5127 }
5128
5129 {
5130 #if DEBUG_EXECUTION
5131 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5132 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5133 uint inst = 1;
5134
5135 memset(mach->Temps, 0, sizeof(temps));
5136 memset(mach->Outputs, 0, sizeof(outputs));
5137 memset(temps, 0, sizeof(temps));
5138 memset(outputs, 0, sizeof(outputs));
5139 #endif
5140
5141 /* execute instructions, until pc is set to -1 */
5142 while (pc != -1) {
5143
5144 #if DEBUG_EXECUTION
5145 uint i;
5146
5147 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5148 #endif
5149
5150 assert(pc < (int) mach->NumInstructions);
5151 exec_instruction(mach, mach->Instructions + pc, &pc);
5152
5153 #if DEBUG_EXECUTION
5154 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5155 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5156 uint j;
5157
5158 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5159 debug_printf("TEMP[%2u] = ", i);
5160 for (j = 0; j < 4; j++) {
5161 if (j > 0) {
5162 debug_printf(" ");
5163 }
5164 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5165 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5166 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5167 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5168 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5169 }
5170 }
5171 }
5172 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5173 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5174 uint j;
5175
5176 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5177 debug_printf("OUT[%2u] = ", i);
5178 for (j = 0; j < 4; j++) {
5179 if (j > 0) {
5180 debug_printf(" ");
5181 }
5182 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5183 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5184 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5185 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5186 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5187 }
5188 }
5189 }
5190 #endif
5191 }
5192 }
5193
5194 #if 0
5195 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5196 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
5197 /*
5198 * Scale back depth component.
5199 */
5200 for (i = 0; i < 4; i++)
5201 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5202 }
5203 #endif
5204
5205 /* Strictly speaking, these assertions aren't really needed but they
5206 * can potentially catch some bugs in the control flow code.
5207 */
5208 assert(mach->CondStackTop == 0);
5209 assert(mach->LoopStackTop == 0);
5210 assert(mach->ContStackTop == 0);
5211 assert(mach->SwitchStackTop == 0);
5212 assert(mach->BreakStackTop == 0);
5213 assert(mach->CallStackTop == 0);
5214
5215 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5216 }