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gallium: add LDEXP TGSI instruction and corresponding cap
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
65
66
67 #define DEBUG_EXECUTION 0
68
69
70 #define FAST_MATH 0
71
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
76
77 union tgsi_double_channel {
78 double d[TGSI_QUAD_SIZE];
79 unsigned u[TGSI_QUAD_SIZE][2];
80 uint64_t u64[TGSI_QUAD_SIZE];
81 int64_t i64[TGSI_QUAD_SIZE];
82 };
83
84 struct tgsi_double_vector {
85 union tgsi_double_channel xy;
86 union tgsi_double_channel zw;
87 };
88
89 static void
90 micro_abs(union tgsi_exec_channel *dst,
91 const union tgsi_exec_channel *src)
92 {
93 dst->f[0] = fabsf(src->f[0]);
94 dst->f[1] = fabsf(src->f[1]);
95 dst->f[2] = fabsf(src->f[2]);
96 dst->f[3] = fabsf(src->f[3]);
97 }
98
99 static void
100 micro_arl(union tgsi_exec_channel *dst,
101 const union tgsi_exec_channel *src)
102 {
103 dst->i[0] = (int)floorf(src->f[0]);
104 dst->i[1] = (int)floorf(src->f[1]);
105 dst->i[2] = (int)floorf(src->f[2]);
106 dst->i[3] = (int)floorf(src->f[3]);
107 }
108
109 static void
110 micro_arr(union tgsi_exec_channel *dst,
111 const union tgsi_exec_channel *src)
112 {
113 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
114 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
115 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
116 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
117 }
118
119 static void
120 micro_ceil(union tgsi_exec_channel *dst,
121 const union tgsi_exec_channel *src)
122 {
123 dst->f[0] = ceilf(src->f[0]);
124 dst->f[1] = ceilf(src->f[1]);
125 dst->f[2] = ceilf(src->f[2]);
126 dst->f[3] = ceilf(src->f[3]);
127 }
128
129 static void
130 micro_cmp(union tgsi_exec_channel *dst,
131 const union tgsi_exec_channel *src0,
132 const union tgsi_exec_channel *src1,
133 const union tgsi_exec_channel *src2)
134 {
135 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
136 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
137 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
138 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
139 }
140
141 static void
142 micro_cos(union tgsi_exec_channel *dst,
143 const union tgsi_exec_channel *src)
144 {
145 dst->f[0] = cosf(src->f[0]);
146 dst->f[1] = cosf(src->f[1]);
147 dst->f[2] = cosf(src->f[2]);
148 dst->f[3] = cosf(src->f[3]);
149 }
150
151 static void
152 micro_d2f(union tgsi_exec_channel *dst,
153 const union tgsi_double_channel *src)
154 {
155 dst->f[0] = (float)src->d[0];
156 dst->f[1] = (float)src->d[1];
157 dst->f[2] = (float)src->d[2];
158 dst->f[3] = (float)src->d[3];
159 }
160
161 static void
162 micro_d2i(union tgsi_exec_channel *dst,
163 const union tgsi_double_channel *src)
164 {
165 dst->i[0] = (int)src->d[0];
166 dst->i[1] = (int)src->d[1];
167 dst->i[2] = (int)src->d[2];
168 dst->i[3] = (int)src->d[3];
169 }
170
171 static void
172 micro_d2u(union tgsi_exec_channel *dst,
173 const union tgsi_double_channel *src)
174 {
175 dst->u[0] = (unsigned)src->d[0];
176 dst->u[1] = (unsigned)src->d[1];
177 dst->u[2] = (unsigned)src->d[2];
178 dst->u[3] = (unsigned)src->d[3];
179 }
180 static void
181 micro_dabs(union tgsi_double_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
185 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
186 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
187 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
188 }
189
190 static void
191 micro_dadd(union tgsi_double_channel *dst,
192 const union tgsi_double_channel *src)
193 {
194 dst->d[0] = src[0].d[0] + src[1].d[0];
195 dst->d[1] = src[0].d[1] + src[1].d[1];
196 dst->d[2] = src[0].d[2] + src[1].d[2];
197 dst->d[3] = src[0].d[3] + src[1].d[3];
198 }
199
200 static void
201 micro_ddiv(union tgsi_double_channel *dst,
202 const union tgsi_double_channel *src)
203 {
204 dst->d[0] = src[0].d[0] / src[1].d[0];
205 dst->d[1] = src[0].d[1] / src[1].d[1];
206 dst->d[2] = src[0].d[2] / src[1].d[2];
207 dst->d[3] = src[0].d[3] / src[1].d[3];
208 }
209
210 static void
211 micro_ddx(union tgsi_exec_channel *dst,
212 const union tgsi_exec_channel *src)
213 {
214 dst->f[0] =
215 dst->f[1] =
216 dst->f[2] =
217 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
218 }
219
220 static void
221 micro_ddy(union tgsi_exec_channel *dst,
222 const union tgsi_exec_channel *src)
223 {
224 dst->f[0] =
225 dst->f[1] =
226 dst->f[2] =
227 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
228 }
229
230 static void
231 micro_dmul(union tgsi_double_channel *dst,
232 const union tgsi_double_channel *src)
233 {
234 dst->d[0] = src[0].d[0] * src[1].d[0];
235 dst->d[1] = src[0].d[1] * src[1].d[1];
236 dst->d[2] = src[0].d[2] * src[1].d[2];
237 dst->d[3] = src[0].d[3] * src[1].d[3];
238 }
239
240 static void
241 micro_dmax(union tgsi_double_channel *dst,
242 const union tgsi_double_channel *src)
243 {
244 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
245 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
246 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
247 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
248 }
249
250 static void
251 micro_dmin(union tgsi_double_channel *dst,
252 const union tgsi_double_channel *src)
253 {
254 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
255 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
256 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
257 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
258 }
259
260 static void
261 micro_dneg(union tgsi_double_channel *dst,
262 const union tgsi_double_channel *src)
263 {
264 dst->d[0] = -src->d[0];
265 dst->d[1] = -src->d[1];
266 dst->d[2] = -src->d[2];
267 dst->d[3] = -src->d[3];
268 }
269
270 static void
271 micro_dslt(union tgsi_double_channel *dst,
272 const union tgsi_double_channel *src)
273 {
274 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
275 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
276 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
277 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
278 }
279
280 static void
281 micro_dsne(union tgsi_double_channel *dst,
282 const union tgsi_double_channel *src)
283 {
284 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
285 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
286 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
287 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
288 }
289
290 static void
291 micro_dsge(union tgsi_double_channel *dst,
292 const union tgsi_double_channel *src)
293 {
294 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
295 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
296 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
297 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
298 }
299
300 static void
301 micro_dseq(union tgsi_double_channel *dst,
302 const union tgsi_double_channel *src)
303 {
304 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
305 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
306 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
307 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
308 }
309
310 static void
311 micro_drcp(union tgsi_double_channel *dst,
312 const union tgsi_double_channel *src)
313 {
314 dst->d[0] = 1.0 / src->d[0];
315 dst->d[1] = 1.0 / src->d[1];
316 dst->d[2] = 1.0 / src->d[2];
317 dst->d[3] = 1.0 / src->d[3];
318 }
319
320 static void
321 micro_dsqrt(union tgsi_double_channel *dst,
322 const union tgsi_double_channel *src)
323 {
324 dst->d[0] = sqrt(src->d[0]);
325 dst->d[1] = sqrt(src->d[1]);
326 dst->d[2] = sqrt(src->d[2]);
327 dst->d[3] = sqrt(src->d[3]);
328 }
329
330 static void
331 micro_drsq(union tgsi_double_channel *dst,
332 const union tgsi_double_channel *src)
333 {
334 dst->d[0] = 1.0 / sqrt(src->d[0]);
335 dst->d[1] = 1.0 / sqrt(src->d[1]);
336 dst->d[2] = 1.0 / sqrt(src->d[2]);
337 dst->d[3] = 1.0 / sqrt(src->d[3]);
338 }
339
340 static void
341 micro_dmad(union tgsi_double_channel *dst,
342 const union tgsi_double_channel *src)
343 {
344 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
345 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
346 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
347 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
348 }
349
350 static void
351 micro_dfrac(union tgsi_double_channel *dst,
352 const union tgsi_double_channel *src)
353 {
354 dst->d[0] = src->d[0] - floor(src->d[0]);
355 dst->d[1] = src->d[1] - floor(src->d[1]);
356 dst->d[2] = src->d[2] - floor(src->d[2]);
357 dst->d[3] = src->d[3] - floor(src->d[3]);
358 }
359
360 static void
361 micro_dldexp(union tgsi_double_channel *dst,
362 const union tgsi_double_channel *src0,
363 union tgsi_exec_channel *src1)
364 {
365 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
366 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
367 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
368 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
369 }
370
371 static void
372 micro_dfracexp(union tgsi_double_channel *dst,
373 union tgsi_exec_channel *dst_exp,
374 const union tgsi_double_channel *src)
375 {
376 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
377 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
378 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
379 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
380 }
381
382 static void
383 micro_exp2(union tgsi_exec_channel *dst,
384 const union tgsi_exec_channel *src)
385 {
386 #if FAST_MATH
387 dst->f[0] = util_fast_exp2(src->f[0]);
388 dst->f[1] = util_fast_exp2(src->f[1]);
389 dst->f[2] = util_fast_exp2(src->f[2]);
390 dst->f[3] = util_fast_exp2(src->f[3]);
391 #else
392 #if DEBUG
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 uint i;
395 union tgsi_exec_channel clamped;
396
397 for (i = 0; i < 4; i++) {
398 if (src->f[i] > 127.99999f) {
399 clamped.f[i] = 127.99999f;
400 } else if (src->f[i] < -126.99999f) {
401 clamped.f[i] = -126.99999f;
402 } else {
403 clamped.f[i] = src->f[i];
404 }
405 }
406 src = &clamped;
407 #endif /* DEBUG */
408
409 dst->f[0] = powf(2.0f, src->f[0]);
410 dst->f[1] = powf(2.0f, src->f[1]);
411 dst->f[2] = powf(2.0f, src->f[2]);
412 dst->f[3] = powf(2.0f, src->f[3]);
413 #endif /* FAST_MATH */
414 }
415
416 static void
417 micro_f2d(union tgsi_double_channel *dst,
418 const union tgsi_exec_channel *src)
419 {
420 dst->d[0] = (double)src->f[0];
421 dst->d[1] = (double)src->f[1];
422 dst->d[2] = (double)src->f[2];
423 dst->d[3] = (double)src->f[3];
424 }
425
426 static void
427 micro_flr(union tgsi_exec_channel *dst,
428 const union tgsi_exec_channel *src)
429 {
430 dst->f[0] = floorf(src->f[0]);
431 dst->f[1] = floorf(src->f[1]);
432 dst->f[2] = floorf(src->f[2]);
433 dst->f[3] = floorf(src->f[3]);
434 }
435
436 static void
437 micro_frc(union tgsi_exec_channel *dst,
438 const union tgsi_exec_channel *src)
439 {
440 dst->f[0] = src->f[0] - floorf(src->f[0]);
441 dst->f[1] = src->f[1] - floorf(src->f[1]);
442 dst->f[2] = src->f[2] - floorf(src->f[2]);
443 dst->f[3] = src->f[3] - floorf(src->f[3]);
444 }
445
446 static void
447 micro_i2d(union tgsi_double_channel *dst,
448 const union tgsi_exec_channel *src)
449 {
450 dst->d[0] = (double)src->i[0];
451 dst->d[1] = (double)src->i[1];
452 dst->d[2] = (double)src->i[2];
453 dst->d[3] = (double)src->i[3];
454 }
455
456 static void
457 micro_iabs(union tgsi_exec_channel *dst,
458 const union tgsi_exec_channel *src)
459 {
460 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
461 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
462 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
463 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
464 }
465
466 static void
467 micro_ineg(union tgsi_exec_channel *dst,
468 const union tgsi_exec_channel *src)
469 {
470 dst->i[0] = -src->i[0];
471 dst->i[1] = -src->i[1];
472 dst->i[2] = -src->i[2];
473 dst->i[3] = -src->i[3];
474 }
475
476 static void
477 micro_lg2(union tgsi_exec_channel *dst,
478 const union tgsi_exec_channel *src)
479 {
480 #if FAST_MATH
481 dst->f[0] = util_fast_log2(src->f[0]);
482 dst->f[1] = util_fast_log2(src->f[1]);
483 dst->f[2] = util_fast_log2(src->f[2]);
484 dst->f[3] = util_fast_log2(src->f[3]);
485 #else
486 dst->f[0] = logf(src->f[0]) * 1.442695f;
487 dst->f[1] = logf(src->f[1]) * 1.442695f;
488 dst->f[2] = logf(src->f[2]) * 1.442695f;
489 dst->f[3] = logf(src->f[3]) * 1.442695f;
490 #endif
491 }
492
493 static void
494 micro_lrp(union tgsi_exec_channel *dst,
495 const union tgsi_exec_channel *src0,
496 const union tgsi_exec_channel *src1,
497 const union tgsi_exec_channel *src2)
498 {
499 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
500 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
501 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
502 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
503 }
504
505 static void
506 micro_mad(union tgsi_exec_channel *dst,
507 const union tgsi_exec_channel *src0,
508 const union tgsi_exec_channel *src1,
509 const union tgsi_exec_channel *src2)
510 {
511 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
512 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
513 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
514 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
515 }
516
517 static void
518 micro_mov(union tgsi_exec_channel *dst,
519 const union tgsi_exec_channel *src)
520 {
521 dst->u[0] = src->u[0];
522 dst->u[1] = src->u[1];
523 dst->u[2] = src->u[2];
524 dst->u[3] = src->u[3];
525 }
526
527 static void
528 micro_rcp(union tgsi_exec_channel *dst,
529 const union tgsi_exec_channel *src)
530 {
531 #if 0 /* for debugging */
532 assert(src->f[0] != 0.0f);
533 assert(src->f[1] != 0.0f);
534 assert(src->f[2] != 0.0f);
535 assert(src->f[3] != 0.0f);
536 #endif
537 dst->f[0] = 1.0f / src->f[0];
538 dst->f[1] = 1.0f / src->f[1];
539 dst->f[2] = 1.0f / src->f[2];
540 dst->f[3] = 1.0f / src->f[3];
541 }
542
543 static void
544 micro_rnd(union tgsi_exec_channel *dst,
545 const union tgsi_exec_channel *src)
546 {
547 dst->f[0] = _mesa_roundevenf(src->f[0]);
548 dst->f[1] = _mesa_roundevenf(src->f[1]);
549 dst->f[2] = _mesa_roundevenf(src->f[2]);
550 dst->f[3] = _mesa_roundevenf(src->f[3]);
551 }
552
553 static void
554 micro_rsq(union tgsi_exec_channel *dst,
555 const union tgsi_exec_channel *src)
556 {
557 #if 0 /* for debugging */
558 assert(src->f[0] != 0.0f);
559 assert(src->f[1] != 0.0f);
560 assert(src->f[2] != 0.0f);
561 assert(src->f[3] != 0.0f);
562 #endif
563 dst->f[0] = 1.0f / sqrtf(src->f[0]);
564 dst->f[1] = 1.0f / sqrtf(src->f[1]);
565 dst->f[2] = 1.0f / sqrtf(src->f[2]);
566 dst->f[3] = 1.0f / sqrtf(src->f[3]);
567 }
568
569 static void
570 micro_sqrt(union tgsi_exec_channel *dst,
571 const union tgsi_exec_channel *src)
572 {
573 dst->f[0] = sqrtf(src->f[0]);
574 dst->f[1] = sqrtf(src->f[1]);
575 dst->f[2] = sqrtf(src->f[2]);
576 dst->f[3] = sqrtf(src->f[3]);
577 }
578
579 static void
580 micro_seq(union tgsi_exec_channel *dst,
581 const union tgsi_exec_channel *src0,
582 const union tgsi_exec_channel *src1)
583 {
584 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
585 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
586 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
587 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
588 }
589
590 static void
591 micro_sge(union tgsi_exec_channel *dst,
592 const union tgsi_exec_channel *src0,
593 const union tgsi_exec_channel *src1)
594 {
595 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
596 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
597 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
598 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
599 }
600
601 static void
602 micro_sgn(union tgsi_exec_channel *dst,
603 const union tgsi_exec_channel *src)
604 {
605 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
606 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
607 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
608 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
609 }
610
611 static void
612 micro_isgn(union tgsi_exec_channel *dst,
613 const union tgsi_exec_channel *src)
614 {
615 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
616 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
617 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
618 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
619 }
620
621 static void
622 micro_sgt(union tgsi_exec_channel *dst,
623 const union tgsi_exec_channel *src0,
624 const union tgsi_exec_channel *src1)
625 {
626 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
627 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
628 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
629 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
630 }
631
632 static void
633 micro_sin(union tgsi_exec_channel *dst,
634 const union tgsi_exec_channel *src)
635 {
636 dst->f[0] = sinf(src->f[0]);
637 dst->f[1] = sinf(src->f[1]);
638 dst->f[2] = sinf(src->f[2]);
639 dst->f[3] = sinf(src->f[3]);
640 }
641
642 static void
643 micro_sle(union tgsi_exec_channel *dst,
644 const union tgsi_exec_channel *src0,
645 const union tgsi_exec_channel *src1)
646 {
647 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
648 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
649 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
650 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
651 }
652
653 static void
654 micro_slt(union tgsi_exec_channel *dst,
655 const union tgsi_exec_channel *src0,
656 const union tgsi_exec_channel *src1)
657 {
658 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
659 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
660 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
661 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
662 }
663
664 static void
665 micro_sne(union tgsi_exec_channel *dst,
666 const union tgsi_exec_channel *src0,
667 const union tgsi_exec_channel *src1)
668 {
669 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
670 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
671 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
672 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
673 }
674
675 static void
676 micro_trunc(union tgsi_exec_channel *dst,
677 const union tgsi_exec_channel *src)
678 {
679 dst->f[0] = truncf(src->f[0]);
680 dst->f[1] = truncf(src->f[1]);
681 dst->f[2] = truncf(src->f[2]);
682 dst->f[3] = truncf(src->f[3]);
683 }
684
685 static void
686 micro_u2d(union tgsi_double_channel *dst,
687 const union tgsi_exec_channel *src)
688 {
689 dst->d[0] = (double)src->u[0];
690 dst->d[1] = (double)src->u[1];
691 dst->d[2] = (double)src->u[2];
692 dst->d[3] = (double)src->u[3];
693 }
694
695 static void
696 micro_i64abs(union tgsi_double_channel *dst,
697 const union tgsi_double_channel *src)
698 {
699 dst->i64[0] = src->i64[0] >= 0.0 ? src->i64[0] : -src->i64[0];
700 dst->i64[1] = src->i64[1] >= 0.0 ? src->i64[1] : -src->i64[1];
701 dst->i64[2] = src->i64[2] >= 0.0 ? src->i64[2] : -src->i64[2];
702 dst->i64[3] = src->i64[3] >= 0.0 ? src->i64[3] : -src->i64[3];
703 }
704
705 static void
706 micro_i64sgn(union tgsi_double_channel *dst,
707 const union tgsi_double_channel *src)
708 {
709 dst->i64[0] = src->i64[0] < 0 ? -1 : src->i64[0] > 0 ? 1 : 0;
710 dst->i64[1] = src->i64[1] < 0 ? -1 : src->i64[1] > 0 ? 1 : 0;
711 dst->i64[2] = src->i64[2] < 0 ? -1 : src->i64[2] > 0 ? 1 : 0;
712 dst->i64[3] = src->i64[3] < 0 ? -1 : src->i64[3] > 0 ? 1 : 0;
713 }
714
715 static void
716 micro_i64neg(union tgsi_double_channel *dst,
717 const union tgsi_double_channel *src)
718 {
719 dst->i64[0] = -src->i64[0];
720 dst->i64[1] = -src->i64[1];
721 dst->i64[2] = -src->i64[2];
722 dst->i64[3] = -src->i64[3];
723 }
724
725 static void
726 micro_u64seq(union tgsi_double_channel *dst,
727 const union tgsi_double_channel *src)
728 {
729 dst->u[0][0] = src[0].u64[0] == src[1].u64[0] ? ~0U : 0U;
730 dst->u[1][0] = src[0].u64[1] == src[1].u64[1] ? ~0U : 0U;
731 dst->u[2][0] = src[0].u64[2] == src[1].u64[2] ? ~0U : 0U;
732 dst->u[3][0] = src[0].u64[3] == src[1].u64[3] ? ~0U : 0U;
733 }
734
735 static void
736 micro_u64sne(union tgsi_double_channel *dst,
737 const union tgsi_double_channel *src)
738 {
739 dst->u[0][0] = src[0].u64[0] != src[1].u64[0] ? ~0U : 0U;
740 dst->u[1][0] = src[0].u64[1] != src[1].u64[1] ? ~0U : 0U;
741 dst->u[2][0] = src[0].u64[2] != src[1].u64[2] ? ~0U : 0U;
742 dst->u[3][0] = src[0].u64[3] != src[1].u64[3] ? ~0U : 0U;
743 }
744
745 static void
746 micro_i64slt(union tgsi_double_channel *dst,
747 const union tgsi_double_channel *src)
748 {
749 dst->u[0][0] = src[0].i64[0] < src[1].i64[0] ? ~0U : 0U;
750 dst->u[1][0] = src[0].i64[1] < src[1].i64[1] ? ~0U : 0U;
751 dst->u[2][0] = src[0].i64[2] < src[1].i64[2] ? ~0U : 0U;
752 dst->u[3][0] = src[0].i64[3] < src[1].i64[3] ? ~0U : 0U;
753 }
754
755 static void
756 micro_u64slt(union tgsi_double_channel *dst,
757 const union tgsi_double_channel *src)
758 {
759 dst->u[0][0] = src[0].u64[0] < src[1].u64[0] ? ~0U : 0U;
760 dst->u[1][0] = src[0].u64[1] < src[1].u64[1] ? ~0U : 0U;
761 dst->u[2][0] = src[0].u64[2] < src[1].u64[2] ? ~0U : 0U;
762 dst->u[3][0] = src[0].u64[3] < src[1].u64[3] ? ~0U : 0U;
763 }
764
765 static void
766 micro_i64sge(union tgsi_double_channel *dst,
767 const union tgsi_double_channel *src)
768 {
769 dst->u[0][0] = src[0].i64[0] >= src[1].i64[0] ? ~0U : 0U;
770 dst->u[1][0] = src[0].i64[1] >= src[1].i64[1] ? ~0U : 0U;
771 dst->u[2][0] = src[0].i64[2] >= src[1].i64[2] ? ~0U : 0U;
772 dst->u[3][0] = src[0].i64[3] >= src[1].i64[3] ? ~0U : 0U;
773 }
774
775 static void
776 micro_u64sge(union tgsi_double_channel *dst,
777 const union tgsi_double_channel *src)
778 {
779 dst->u[0][0] = src[0].u64[0] >= src[1].u64[0] ? ~0U : 0U;
780 dst->u[1][0] = src[0].u64[1] >= src[1].u64[1] ? ~0U : 0U;
781 dst->u[2][0] = src[0].u64[2] >= src[1].u64[2] ? ~0U : 0U;
782 dst->u[3][0] = src[0].u64[3] >= src[1].u64[3] ? ~0U : 0U;
783 }
784
785 static void
786 micro_u64max(union tgsi_double_channel *dst,
787 const union tgsi_double_channel *src)
788 {
789 dst->u64[0] = src[0].u64[0] > src[1].u64[0] ? src[0].u64[0] : src[1].u64[0];
790 dst->u64[1] = src[0].u64[1] > src[1].u64[1] ? src[0].u64[1] : src[1].u64[1];
791 dst->u64[2] = src[0].u64[2] > src[1].u64[2] ? src[0].u64[2] : src[1].u64[2];
792 dst->u64[3] = src[0].u64[3] > src[1].u64[3] ? src[0].u64[3] : src[1].u64[3];
793 }
794
795 static void
796 micro_i64max(union tgsi_double_channel *dst,
797 const union tgsi_double_channel *src)
798 {
799 dst->i64[0] = src[0].i64[0] > src[1].i64[0] ? src[0].i64[0] : src[1].i64[0];
800 dst->i64[1] = src[0].i64[1] > src[1].i64[1] ? src[0].i64[1] : src[1].i64[1];
801 dst->i64[2] = src[0].i64[2] > src[1].i64[2] ? src[0].i64[2] : src[1].i64[2];
802 dst->i64[3] = src[0].i64[3] > src[1].i64[3] ? src[0].i64[3] : src[1].i64[3];
803 }
804
805 static void
806 micro_u64min(union tgsi_double_channel *dst,
807 const union tgsi_double_channel *src)
808 {
809 dst->u64[0] = src[0].u64[0] < src[1].u64[0] ? src[0].u64[0] : src[1].u64[0];
810 dst->u64[1] = src[0].u64[1] < src[1].u64[1] ? src[0].u64[1] : src[1].u64[1];
811 dst->u64[2] = src[0].u64[2] < src[1].u64[2] ? src[0].u64[2] : src[1].u64[2];
812 dst->u64[3] = src[0].u64[3] < src[1].u64[3] ? src[0].u64[3] : src[1].u64[3];
813 }
814
815 static void
816 micro_i64min(union tgsi_double_channel *dst,
817 const union tgsi_double_channel *src)
818 {
819 dst->i64[0] = src[0].i64[0] < src[1].i64[0] ? src[0].i64[0] : src[1].i64[0];
820 dst->i64[1] = src[0].i64[1] < src[1].i64[1] ? src[0].i64[1] : src[1].i64[1];
821 dst->i64[2] = src[0].i64[2] < src[1].i64[2] ? src[0].i64[2] : src[1].i64[2];
822 dst->i64[3] = src[0].i64[3] < src[1].i64[3] ? src[0].i64[3] : src[1].i64[3];
823 }
824
825 static void
826 micro_u64add(union tgsi_double_channel *dst,
827 const union tgsi_double_channel *src)
828 {
829 dst->u64[0] = src[0].u64[0] + src[1].u64[0];
830 dst->u64[1] = src[0].u64[1] + src[1].u64[1];
831 dst->u64[2] = src[0].u64[2] + src[1].u64[2];
832 dst->u64[3] = src[0].u64[3] + src[1].u64[3];
833 }
834
835 static void
836 micro_u64mul(union tgsi_double_channel *dst,
837 const union tgsi_double_channel *src)
838 {
839 dst->u64[0] = src[0].u64[0] * src[1].u64[0];
840 dst->u64[1] = src[0].u64[1] * src[1].u64[1];
841 dst->u64[2] = src[0].u64[2] * src[1].u64[2];
842 dst->u64[3] = src[0].u64[3] * src[1].u64[3];
843 }
844
845 static void
846 micro_u64div(union tgsi_double_channel *dst,
847 const union tgsi_double_channel *src)
848 {
849 dst->u64[0] = src[1].u64[0] ? src[0].u64[0] / src[1].u64[0] : ~0ull;
850 dst->u64[1] = src[1].u64[1] ? src[0].u64[1] / src[1].u64[1] : ~0ull;
851 dst->u64[2] = src[1].u64[2] ? src[0].u64[2] / src[1].u64[2] : ~0ull;
852 dst->u64[3] = src[1].u64[3] ? src[0].u64[3] / src[1].u64[3] : ~0ull;
853 }
854
855 static void
856 micro_i64div(union tgsi_double_channel *dst,
857 const union tgsi_double_channel *src)
858 {
859 dst->i64[0] = src[1].i64[0] ? src[0].i64[0] / src[1].i64[0] : 0;
860 dst->i64[1] = src[1].i64[1] ? src[0].i64[1] / src[1].i64[1] : 0;
861 dst->i64[2] = src[1].i64[2] ? src[0].i64[2] / src[1].i64[2] : 0;
862 dst->i64[3] = src[1].i64[3] ? src[0].i64[3] / src[1].i64[3] : 0;
863 }
864
865 static void
866 micro_u64mod(union tgsi_double_channel *dst,
867 const union tgsi_double_channel *src)
868 {
869 dst->u64[0] = src[1].u64[0] ? src[0].u64[0] % src[1].u64[0] : ~0ull;
870 dst->u64[1] = src[1].u64[1] ? src[0].u64[1] % src[1].u64[1] : ~0ull;
871 dst->u64[2] = src[1].u64[2] ? src[0].u64[2] % src[1].u64[2] : ~0ull;
872 dst->u64[3] = src[1].u64[3] ? src[0].u64[3] % src[1].u64[3] : ~0ull;
873 }
874
875 static void
876 micro_i64mod(union tgsi_double_channel *dst,
877 const union tgsi_double_channel *src)
878 {
879 dst->i64[0] = src[1].i64[0] ? src[0].i64[0] % src[1].i64[0] : ~0ll;
880 dst->i64[1] = src[1].i64[1] ? src[0].i64[1] % src[1].i64[1] : ~0ll;
881 dst->i64[2] = src[1].i64[2] ? src[0].i64[2] % src[1].i64[2] : ~0ll;
882 dst->i64[3] = src[1].i64[3] ? src[0].i64[3] % src[1].i64[3] : ~0ll;
883 }
884
885 static void
886 micro_u64shl(union tgsi_double_channel *dst,
887 const union tgsi_double_channel *src0,
888 union tgsi_exec_channel *src1)
889 {
890 unsigned masked_count;
891 masked_count = src1->u[0] & 0x3f;
892 dst->u64[0] = src0->u64[0] << masked_count;
893 masked_count = src1->u[1] & 0x3f;
894 dst->u64[1] = src0->u64[1] << masked_count;
895 masked_count = src1->u[2] & 0x3f;
896 dst->u64[2] = src0->u64[2] << masked_count;
897 masked_count = src1->u[3] & 0x3f;
898 dst->u64[3] = src0->u64[3] << masked_count;
899 }
900
901 static void
902 micro_i64shr(union tgsi_double_channel *dst,
903 const union tgsi_double_channel *src0,
904 union tgsi_exec_channel *src1)
905 {
906 unsigned masked_count;
907 masked_count = src1->u[0] & 0x3f;
908 dst->i64[0] = src0->i64[0] >> masked_count;
909 masked_count = src1->u[1] & 0x3f;
910 dst->i64[1] = src0->i64[1] >> masked_count;
911 masked_count = src1->u[2] & 0x3f;
912 dst->i64[2] = src0->i64[2] >> masked_count;
913 masked_count = src1->u[3] & 0x3f;
914 dst->i64[3] = src0->i64[3] >> masked_count;
915 }
916
917 static void
918 micro_u64shr(union tgsi_double_channel *dst,
919 const union tgsi_double_channel *src0,
920 union tgsi_exec_channel *src1)
921 {
922 unsigned masked_count;
923 masked_count = src1->u[0] & 0x3f;
924 dst->u64[0] = src0->u64[0] >> masked_count;
925 masked_count = src1->u[1] & 0x3f;
926 dst->u64[1] = src0->u64[1] >> masked_count;
927 masked_count = src1->u[2] & 0x3f;
928 dst->u64[2] = src0->u64[2] >> masked_count;
929 masked_count = src1->u[3] & 0x3f;
930 dst->u64[3] = src0->u64[3] >> masked_count;
931 }
932
933 enum tgsi_exec_datatype {
934 TGSI_EXEC_DATA_FLOAT,
935 TGSI_EXEC_DATA_INT,
936 TGSI_EXEC_DATA_UINT,
937 TGSI_EXEC_DATA_DOUBLE,
938 TGSI_EXEC_DATA_INT64,
939 TGSI_EXEC_DATA_UINT64,
940 };
941
942 /*
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
944 */
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
951
952
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
956
957
958 static const union tgsi_exec_channel ZeroVec =
959 { { 0.0, 0.0, 0.0, 0.0 } };
960
961 static const union tgsi_exec_channel OneVec = {
962 {1.0f, 1.0f, 1.0f, 1.0f}
963 };
964
965 static const union tgsi_exec_channel P128Vec = {
966 {128.0f, 128.0f, 128.0f, 128.0f}
967 };
968
969 static const union tgsi_exec_channel M128Vec = {
970 {-128.0f, -128.0f, -128.0f, -128.0f}
971 };
972
973
974 /**
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
978 * them.
979 */
980 static inline void
981 check_inf_or_nan(const union tgsi_exec_channel *chan)
982 {
983 assert(!util_is_inf_or_nan((chan)->f[0]));
984 assert(!util_is_inf_or_nan((chan)->f[1]));
985 assert(!util_is_inf_or_nan((chan)->f[2]));
986 assert(!util_is_inf_or_nan((chan)->f[3]));
987 }
988
989
990 #ifdef DEBUG
991 static void
992 print_chan(const char *msg, const union tgsi_exec_channel *chan)
993 {
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
996 }
997 #endif
998
999
1000 #ifdef DEBUG
1001 static void
1002 print_temp(const struct tgsi_exec_machine *mach, uint index)
1003 {
1004 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
1005 int i;
1006 debug_printf("Temp[%u] =\n", index);
1007 for (i = 0; i < 4; i++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1009 "XYZW"[i],
1010 tmp->xyzw[i].f[0],
1011 tmp->xyzw[i].f[1],
1012 tmp->xyzw[i].f[2],
1013 tmp->xyzw[i].f[3]);
1014 }
1015 }
1016 #endif
1017
1018
1019 void
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
1021 unsigned num_bufs,
1022 const void **bufs,
1023 const unsigned *buf_sizes)
1024 {
1025 unsigned i;
1026
1027 for (i = 0; i < num_bufs; i++) {
1028 mach->Consts[i] = bufs[i];
1029 mach->ConstsSize[i] = buf_sizes[i];
1030 }
1031 }
1032
1033
1034 /**
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1037 * Example:
1038 * MOV T, T.yxwz;
1039 * This would expand into:
1040 * MOV t0, t1;
1041 * MOV t1, t0;
1042 * MOV t2, t3;
1043 * MOV t3, t2;
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1045 */
1046 boolean
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
1048 {
1049 uint i, chan;
1050
1051 uint writemask = inst->Dst[0].Register.WriteMask;
1052 if (writemask == TGSI_WRITEMASK_X ||
1053 writemask == TGSI_WRITEMASK_Y ||
1054 writemask == TGSI_WRITEMASK_Z ||
1055 writemask == TGSI_WRITEMASK_W ||
1056 writemask == TGSI_WRITEMASK_NONE) {
1057 /* no chance of data dependency */
1058 return FALSE;
1059 }
1060
1061 /* loop over src regs */
1062 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1063 if ((inst->Src[i].Register.File ==
1064 inst->Dst[0].Register.File) &&
1065 ((inst->Src[i].Register.Index ==
1066 inst->Dst[0].Register.Index) ||
1067 inst->Src[i].Register.Indirect ||
1068 inst->Dst[0].Register.Indirect)) {
1069 /* loop over dest channels */
1070 uint channelsWritten = 0x0;
1071 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1072 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
1075 if (channelsWritten & (1 << swizzle)) {
1076 return TRUE;
1077 }
1078
1079 channelsWritten |= (1 << chan);
1080 }
1081 }
1082 }
1083 }
1084 return FALSE;
1085 }
1086
1087
1088 /**
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1092 */
1093 void
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine *mach,
1096 const struct tgsi_token *tokens,
1097 struct tgsi_sampler *sampler,
1098 struct tgsi_image *image,
1099 struct tgsi_buffer *buffer)
1100 {
1101 uint k;
1102 struct tgsi_parse_context parse;
1103 struct tgsi_full_instruction *instructions;
1104 struct tgsi_full_declaration *declarations;
1105 uint maxInstructions = 10, numInstructions = 0;
1106 uint maxDeclarations = 10, numDeclarations = 0;
1107
1108 #if 0
1109 tgsi_dump(tokens, 0);
1110 #endif
1111
1112 util_init_math();
1113
1114
1115 mach->Tokens = tokens;
1116 mach->Sampler = sampler;
1117 mach->Image = image;
1118 mach->Buffer = buffer;
1119
1120 if (!tokens) {
1121 /* unbind and free all */
1122 FREE(mach->Declarations);
1123 mach->Declarations = NULL;
1124 mach->NumDeclarations = 0;
1125
1126 FREE(mach->Instructions);
1127 mach->Instructions = NULL;
1128 mach->NumInstructions = 0;
1129
1130 return;
1131 }
1132
1133 k = tgsi_parse_init (&parse, mach->Tokens);
1134 if (k != TGSI_PARSE_OK) {
1135 debug_printf( "Problem parsing!\n" );
1136 return;
1137 }
1138
1139 mach->ImmLimit = 0;
1140 mach->NumOutputs = 0;
1141
1142 for (k = 0; k < TGSI_SEMANTIC_COUNT; k++)
1143 mach->SysSemanticToIndex[k] = -1;
1144
1145 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
1146 !mach->UsedGeometryShader) {
1147 struct tgsi_exec_vector *inputs;
1148 struct tgsi_exec_vector *outputs;
1149
1150 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
1151 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
1152 16);
1153
1154 if (!inputs)
1155 return;
1156
1157 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
1158 TGSI_MAX_TOTAL_VERTICES, 16);
1159
1160 if (!outputs) {
1161 align_free(inputs);
1162 return;
1163 }
1164
1165 align_free(mach->Inputs);
1166 align_free(mach->Outputs);
1167
1168 mach->Inputs = inputs;
1169 mach->Outputs = outputs;
1170 mach->UsedGeometryShader = TRUE;
1171 }
1172
1173 declarations = (struct tgsi_full_declaration *)
1174 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
1175
1176 if (!declarations) {
1177 return;
1178 }
1179
1180 instructions = (struct tgsi_full_instruction *)
1181 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
1182
1183 if (!instructions) {
1184 FREE( declarations );
1185 return;
1186 }
1187
1188 while( !tgsi_parse_end_of_tokens( &parse ) ) {
1189 uint i;
1190
1191 tgsi_parse_token( &parse );
1192 switch( parse.FullToken.Token.Type ) {
1193 case TGSI_TOKEN_TYPE_DECLARATION:
1194 /* save expanded declaration */
1195 if (numDeclarations == maxDeclarations) {
1196 declarations = REALLOC(declarations,
1197 maxDeclarations
1198 * sizeof(struct tgsi_full_declaration),
1199 (maxDeclarations + 10)
1200 * sizeof(struct tgsi_full_declaration));
1201 maxDeclarations += 10;
1202 }
1203 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
1204 unsigned reg;
1205 for (reg = parse.FullToken.FullDeclaration.Range.First;
1206 reg <= parse.FullToken.FullDeclaration.Range.Last;
1207 ++reg) {
1208 ++mach->NumOutputs;
1209 }
1210 }
1211 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1212 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
1213 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
1214 }
1215
1216 memcpy(declarations + numDeclarations,
1217 &parse.FullToken.FullDeclaration,
1218 sizeof(declarations[0]));
1219 numDeclarations++;
1220 break;
1221
1222 case TGSI_TOKEN_TYPE_IMMEDIATE:
1223 {
1224 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
1225 assert( size <= 4 );
1226 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
1227
1228 for( i = 0; i < size; i++ ) {
1229 mach->Imms[mach->ImmLimit][i] =
1230 parse.FullToken.FullImmediate.u[i].Float;
1231 }
1232 mach->ImmLimit += 1;
1233 }
1234 break;
1235
1236 case TGSI_TOKEN_TYPE_INSTRUCTION:
1237
1238 /* save expanded instruction */
1239 if (numInstructions == maxInstructions) {
1240 instructions = REALLOC(instructions,
1241 maxInstructions
1242 * sizeof(struct tgsi_full_instruction),
1243 (maxInstructions + 10)
1244 * sizeof(struct tgsi_full_instruction));
1245 maxInstructions += 10;
1246 }
1247
1248 memcpy(instructions + numInstructions,
1249 &parse.FullToken.FullInstruction,
1250 sizeof(instructions[0]));
1251
1252 numInstructions++;
1253 break;
1254
1255 case TGSI_TOKEN_TYPE_PROPERTY:
1256 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1257 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1258 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1259 }
1260 }
1261 break;
1262
1263 default:
1264 assert( 0 );
1265 }
1266 }
1267 tgsi_parse_free (&parse);
1268
1269 FREE(mach->Declarations);
1270 mach->Declarations = declarations;
1271 mach->NumDeclarations = numDeclarations;
1272
1273 FREE(mach->Instructions);
1274 mach->Instructions = instructions;
1275 mach->NumInstructions = numInstructions;
1276 }
1277
1278
1279 struct tgsi_exec_machine *
1280 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1281 {
1282 struct tgsi_exec_machine *mach;
1283 uint i;
1284
1285 mach = align_malloc( sizeof *mach, 16 );
1286 if (!mach)
1287 goto fail;
1288
1289 memset(mach, 0, sizeof(*mach));
1290
1291 mach->ShaderType = shader_type;
1292 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1293 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1294
1295 if (shader_type != PIPE_SHADER_COMPUTE) {
1296 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1297 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1298 if (!mach->Inputs || !mach->Outputs)
1299 goto fail;
1300 }
1301
1302 /* Setup constants needed by the SSE2 executor. */
1303 for( i = 0; i < 4; i++ ) {
1304 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1305 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1306 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1307 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1308 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1309 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1310 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1311 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1312 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1313 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1314 }
1315
1316 #ifdef DEBUG
1317 /* silence warnings */
1318 (void) print_chan;
1319 (void) print_temp;
1320 #endif
1321
1322 return mach;
1323
1324 fail:
1325 if (mach) {
1326 align_free(mach->Inputs);
1327 align_free(mach->Outputs);
1328 align_free(mach);
1329 }
1330 return NULL;
1331 }
1332
1333
1334 void
1335 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1336 {
1337 if (mach) {
1338 FREE(mach->Instructions);
1339 FREE(mach->Declarations);
1340
1341 align_free(mach->Inputs);
1342 align_free(mach->Outputs);
1343
1344 align_free(mach);
1345 }
1346 }
1347
1348 static void
1349 micro_add(union tgsi_exec_channel *dst,
1350 const union tgsi_exec_channel *src0,
1351 const union tgsi_exec_channel *src1)
1352 {
1353 dst->f[0] = src0->f[0] + src1->f[0];
1354 dst->f[1] = src0->f[1] + src1->f[1];
1355 dst->f[2] = src0->f[2] + src1->f[2];
1356 dst->f[3] = src0->f[3] + src1->f[3];
1357 }
1358
1359 static void
1360 micro_div(
1361 union tgsi_exec_channel *dst,
1362 const union tgsi_exec_channel *src0,
1363 const union tgsi_exec_channel *src1 )
1364 {
1365 if (src1->f[0] != 0) {
1366 dst->f[0] = src0->f[0] / src1->f[0];
1367 }
1368 if (src1->f[1] != 0) {
1369 dst->f[1] = src0->f[1] / src1->f[1];
1370 }
1371 if (src1->f[2] != 0) {
1372 dst->f[2] = src0->f[2] / src1->f[2];
1373 }
1374 if (src1->f[3] != 0) {
1375 dst->f[3] = src0->f[3] / src1->f[3];
1376 }
1377 }
1378
1379 static void
1380 micro_lt(
1381 union tgsi_exec_channel *dst,
1382 const union tgsi_exec_channel *src0,
1383 const union tgsi_exec_channel *src1,
1384 const union tgsi_exec_channel *src2,
1385 const union tgsi_exec_channel *src3 )
1386 {
1387 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1388 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1389 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1390 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1391 }
1392
1393 static void
1394 micro_max(union tgsi_exec_channel *dst,
1395 const union tgsi_exec_channel *src0,
1396 const union tgsi_exec_channel *src1)
1397 {
1398 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1399 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1400 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1401 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1402 }
1403
1404 static void
1405 micro_min(union tgsi_exec_channel *dst,
1406 const union tgsi_exec_channel *src0,
1407 const union tgsi_exec_channel *src1)
1408 {
1409 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1410 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1411 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1412 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1413 }
1414
1415 static void
1416 micro_mul(union tgsi_exec_channel *dst,
1417 const union tgsi_exec_channel *src0,
1418 const union tgsi_exec_channel *src1)
1419 {
1420 dst->f[0] = src0->f[0] * src1->f[0];
1421 dst->f[1] = src0->f[1] * src1->f[1];
1422 dst->f[2] = src0->f[2] * src1->f[2];
1423 dst->f[3] = src0->f[3] * src1->f[3];
1424 }
1425
1426 static void
1427 micro_neg(
1428 union tgsi_exec_channel *dst,
1429 const union tgsi_exec_channel *src )
1430 {
1431 dst->f[0] = -src->f[0];
1432 dst->f[1] = -src->f[1];
1433 dst->f[2] = -src->f[2];
1434 dst->f[3] = -src->f[3];
1435 }
1436
1437 static void
1438 micro_pow(
1439 union tgsi_exec_channel *dst,
1440 const union tgsi_exec_channel *src0,
1441 const union tgsi_exec_channel *src1 )
1442 {
1443 #if FAST_MATH
1444 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1445 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1446 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1447 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1448 #else
1449 dst->f[0] = powf( src0->f[0], src1->f[0] );
1450 dst->f[1] = powf( src0->f[1], src1->f[1] );
1451 dst->f[2] = powf( src0->f[2], src1->f[2] );
1452 dst->f[3] = powf( src0->f[3], src1->f[3] );
1453 #endif
1454 }
1455
1456 static void
1457 micro_ldexp(union tgsi_exec_channel *dst,
1458 const union tgsi_exec_channel *src0,
1459 const union tgsi_exec_channel *src1)
1460 {
1461 dst->f[0] = ldexpf(src0->f[0], src1->i[0]);
1462 dst->f[1] = ldexpf(src0->f[1], src1->i[1]);
1463 dst->f[2] = ldexpf(src0->f[2], src1->i[2]);
1464 dst->f[3] = ldexpf(src0->f[3], src1->i[3]);
1465 }
1466
1467 static void
1468 micro_sub(union tgsi_exec_channel *dst,
1469 const union tgsi_exec_channel *src0,
1470 const union tgsi_exec_channel *src1)
1471 {
1472 dst->f[0] = src0->f[0] - src1->f[0];
1473 dst->f[1] = src0->f[1] - src1->f[1];
1474 dst->f[2] = src0->f[2] - src1->f[2];
1475 dst->f[3] = src0->f[3] - src1->f[3];
1476 }
1477
1478 static void
1479 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1480 const uint chan_index,
1481 const uint file,
1482 const uint swizzle,
1483 const union tgsi_exec_channel *index,
1484 const union tgsi_exec_channel *index2D,
1485 union tgsi_exec_channel *chan)
1486 {
1487 uint i;
1488
1489 assert(swizzle < 4);
1490
1491 switch (file) {
1492 case TGSI_FILE_CONSTANT:
1493 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1494 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1495 assert(mach->Consts[index2D->i[i]]);
1496
1497 if (index->i[i] < 0) {
1498 chan->u[i] = 0;
1499 } else {
1500 /* NOTE: copying the const value as a uint instead of float */
1501 const uint constbuf = index2D->i[i];
1502 const uint *buf = (const uint *)mach->Consts[constbuf];
1503 const int pos = index->i[i] * 4 + swizzle;
1504 /* const buffer bounds check */
1505 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1506 if (0) {
1507 /* Debug: print warning */
1508 static int count = 0;
1509 if (count++ < 100)
1510 debug_printf("TGSI Exec: const buffer index %d"
1511 " out of bounds\n", pos);
1512 }
1513 chan->u[i] = 0;
1514 }
1515 else
1516 chan->u[i] = buf[pos];
1517 }
1518 }
1519 break;
1520
1521 case TGSI_FILE_INPUT:
1522 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1523 /*
1524 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1525 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1526 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1527 index2D->i[i], index->i[i]);
1528 }*/
1529 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1530 assert(pos >= 0);
1531 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1532 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1533 }
1534 break;
1535
1536 case TGSI_FILE_SYSTEM_VALUE:
1537 /* XXX no swizzling at this point. Will be needed if we put
1538 * gl_FragCoord, for example, in a sys value register.
1539 */
1540 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1541 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1542 }
1543 break;
1544
1545 case TGSI_FILE_TEMPORARY:
1546 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1547 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1548 assert(index2D->i[i] == 0);
1549
1550 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1551 }
1552 break;
1553
1554 case TGSI_FILE_IMMEDIATE:
1555 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1556 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1557 assert(index2D->i[i] == 0);
1558
1559 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1560 }
1561 break;
1562
1563 case TGSI_FILE_ADDRESS:
1564 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1565 assert(index->i[i] >= 0);
1566 assert(index2D->i[i] == 0);
1567
1568 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1569 }
1570 break;
1571
1572 case TGSI_FILE_OUTPUT:
1573 /* vertex/fragment output vars can be read too */
1574 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1575 assert(index->i[i] >= 0);
1576 assert(index2D->i[i] == 0);
1577
1578 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1579 }
1580 break;
1581
1582 default:
1583 assert(0);
1584 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1585 chan->u[i] = 0;
1586 }
1587 }
1588 }
1589
1590 static void
1591 fetch_source_d(const struct tgsi_exec_machine *mach,
1592 union tgsi_exec_channel *chan,
1593 const struct tgsi_full_src_register *reg,
1594 const uint chan_index,
1595 enum tgsi_exec_datatype src_datatype)
1596 {
1597 union tgsi_exec_channel index;
1598 union tgsi_exec_channel index2D;
1599 uint swizzle;
1600
1601 /* We start with a direct index into a register file.
1602 *
1603 * file[1],
1604 * where:
1605 * file = Register.File
1606 * [1] = Register.Index
1607 */
1608 index.i[0] =
1609 index.i[1] =
1610 index.i[2] =
1611 index.i[3] = reg->Register.Index;
1612
1613 /* There is an extra source register that indirectly subscripts
1614 * a register file. The direct index now becomes an offset
1615 * that is being added to the indirect register.
1616 *
1617 * file[ind[2].x+1],
1618 * where:
1619 * ind = Indirect.File
1620 * [2] = Indirect.Index
1621 * .x = Indirect.SwizzleX
1622 */
1623 if (reg->Register.Indirect) {
1624 union tgsi_exec_channel index2;
1625 union tgsi_exec_channel indir_index;
1626 const uint execmask = mach->ExecMask;
1627 uint i;
1628
1629 /* which address register (always zero now) */
1630 index2.i[0] =
1631 index2.i[1] =
1632 index2.i[2] =
1633 index2.i[3] = reg->Indirect.Index;
1634 /* get current value of address register[swizzle] */
1635 swizzle = reg->Indirect.Swizzle;
1636 fetch_src_file_channel(mach,
1637 chan_index,
1638 reg->Indirect.File,
1639 swizzle,
1640 &index2,
1641 &ZeroVec,
1642 &indir_index);
1643
1644 /* add value of address register to the offset */
1645 index.i[0] += indir_index.i[0];
1646 index.i[1] += indir_index.i[1];
1647 index.i[2] += indir_index.i[2];
1648 index.i[3] += indir_index.i[3];
1649
1650 /* for disabled execution channels, zero-out the index to
1651 * avoid using a potential garbage value.
1652 */
1653 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1654 if ((execmask & (1 << i)) == 0)
1655 index.i[i] = 0;
1656 }
1657 }
1658
1659 /* There is an extra source register that is a second
1660 * subscript to a register file. Effectively it means that
1661 * the register file is actually a 2D array of registers.
1662 *
1663 * file[3][1],
1664 * where:
1665 * [3] = Dimension.Index
1666 */
1667 if (reg->Register.Dimension) {
1668 index2D.i[0] =
1669 index2D.i[1] =
1670 index2D.i[2] =
1671 index2D.i[3] = reg->Dimension.Index;
1672
1673 /* Again, the second subscript index can be addressed indirectly
1674 * identically to the first one.
1675 * Nothing stops us from indirectly addressing the indirect register,
1676 * but there is no need for that, so we won't exercise it.
1677 *
1678 * file[ind[4].y+3][1],
1679 * where:
1680 * ind = DimIndirect.File
1681 * [4] = DimIndirect.Index
1682 * .y = DimIndirect.SwizzleX
1683 */
1684 if (reg->Dimension.Indirect) {
1685 union tgsi_exec_channel index2;
1686 union tgsi_exec_channel indir_index;
1687 const uint execmask = mach->ExecMask;
1688 uint i;
1689
1690 index2.i[0] =
1691 index2.i[1] =
1692 index2.i[2] =
1693 index2.i[3] = reg->DimIndirect.Index;
1694
1695 swizzle = reg->DimIndirect.Swizzle;
1696 fetch_src_file_channel(mach,
1697 chan_index,
1698 reg->DimIndirect.File,
1699 swizzle,
1700 &index2,
1701 &ZeroVec,
1702 &indir_index);
1703
1704 index2D.i[0] += indir_index.i[0];
1705 index2D.i[1] += indir_index.i[1];
1706 index2D.i[2] += indir_index.i[2];
1707 index2D.i[3] += indir_index.i[3];
1708
1709 /* for disabled execution channels, zero-out the index to
1710 * avoid using a potential garbage value.
1711 */
1712 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1713 if ((execmask & (1 << i)) == 0) {
1714 index2D.i[i] = 0;
1715 }
1716 }
1717 }
1718
1719 /* If by any chance there was a need for a 3D array of register
1720 * files, we would have to check whether Dimension is followed
1721 * by a dimension register and continue the saga.
1722 */
1723 } else {
1724 index2D.i[0] =
1725 index2D.i[1] =
1726 index2D.i[2] =
1727 index2D.i[3] = 0;
1728 }
1729
1730 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1731 fetch_src_file_channel(mach,
1732 chan_index,
1733 reg->Register.File,
1734 swizzle,
1735 &index,
1736 &index2D,
1737 chan);
1738 }
1739
1740 static void
1741 fetch_source(const struct tgsi_exec_machine *mach,
1742 union tgsi_exec_channel *chan,
1743 const struct tgsi_full_src_register *reg,
1744 const uint chan_index,
1745 enum tgsi_exec_datatype src_datatype)
1746 {
1747 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1748
1749 if (reg->Register.Absolute) {
1750 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1751 micro_abs(chan, chan);
1752 } else {
1753 micro_iabs(chan, chan);
1754 }
1755 }
1756
1757 if (reg->Register.Negate) {
1758 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1759 micro_neg(chan, chan);
1760 } else {
1761 micro_ineg(chan, chan);
1762 }
1763 }
1764 }
1765
1766 static union tgsi_exec_channel *
1767 store_dest_dstret(struct tgsi_exec_machine *mach,
1768 const union tgsi_exec_channel *chan,
1769 const struct tgsi_full_dst_register *reg,
1770 const struct tgsi_full_instruction *inst,
1771 uint chan_index,
1772 enum tgsi_exec_datatype dst_datatype)
1773 {
1774 static union tgsi_exec_channel null;
1775 union tgsi_exec_channel *dst;
1776 union tgsi_exec_channel index2D;
1777 int offset = 0; /* indirection offset */
1778 int index;
1779
1780 /* for debugging */
1781 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1782 check_inf_or_nan(chan);
1783 }
1784
1785 /* There is an extra source register that indirectly subscripts
1786 * a register file. The direct index now becomes an offset
1787 * that is being added to the indirect register.
1788 *
1789 * file[ind[2].x+1],
1790 * where:
1791 * ind = Indirect.File
1792 * [2] = Indirect.Index
1793 * .x = Indirect.SwizzleX
1794 */
1795 if (reg->Register.Indirect) {
1796 union tgsi_exec_channel index;
1797 union tgsi_exec_channel indir_index;
1798 uint swizzle;
1799
1800 /* which address register (always zero for now) */
1801 index.i[0] =
1802 index.i[1] =
1803 index.i[2] =
1804 index.i[3] = reg->Indirect.Index;
1805
1806 /* get current value of address register[swizzle] */
1807 swizzle = reg->Indirect.Swizzle;
1808
1809 /* fetch values from the address/indirection register */
1810 fetch_src_file_channel(mach,
1811 chan_index,
1812 reg->Indirect.File,
1813 swizzle,
1814 &index,
1815 &ZeroVec,
1816 &indir_index);
1817
1818 /* save indirection offset */
1819 offset = indir_index.i[0];
1820 }
1821
1822 /* There is an extra source register that is a second
1823 * subscript to a register file. Effectively it means that
1824 * the register file is actually a 2D array of registers.
1825 *
1826 * file[3][1],
1827 * where:
1828 * [3] = Dimension.Index
1829 */
1830 if (reg->Register.Dimension) {
1831 index2D.i[0] =
1832 index2D.i[1] =
1833 index2D.i[2] =
1834 index2D.i[3] = reg->Dimension.Index;
1835
1836 /* Again, the second subscript index can be addressed indirectly
1837 * identically to the first one.
1838 * Nothing stops us from indirectly addressing the indirect register,
1839 * but there is no need for that, so we won't exercise it.
1840 *
1841 * file[ind[4].y+3][1],
1842 * where:
1843 * ind = DimIndirect.File
1844 * [4] = DimIndirect.Index
1845 * .y = DimIndirect.SwizzleX
1846 */
1847 if (reg->Dimension.Indirect) {
1848 union tgsi_exec_channel index2;
1849 union tgsi_exec_channel indir_index;
1850 const uint execmask = mach->ExecMask;
1851 unsigned swizzle;
1852 uint i;
1853
1854 index2.i[0] =
1855 index2.i[1] =
1856 index2.i[2] =
1857 index2.i[3] = reg->DimIndirect.Index;
1858
1859 swizzle = reg->DimIndirect.Swizzle;
1860 fetch_src_file_channel(mach,
1861 chan_index,
1862 reg->DimIndirect.File,
1863 swizzle,
1864 &index2,
1865 &ZeroVec,
1866 &indir_index);
1867
1868 index2D.i[0] += indir_index.i[0];
1869 index2D.i[1] += indir_index.i[1];
1870 index2D.i[2] += indir_index.i[2];
1871 index2D.i[3] += indir_index.i[3];
1872
1873 /* for disabled execution channels, zero-out the index to
1874 * avoid using a potential garbage value.
1875 */
1876 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1877 if ((execmask & (1 << i)) == 0) {
1878 index2D.i[i] = 0;
1879 }
1880 }
1881 }
1882
1883 /* If by any chance there was a need for a 3D array of register
1884 * files, we would have to check whether Dimension is followed
1885 * by a dimension register and continue the saga.
1886 */
1887 } else {
1888 index2D.i[0] =
1889 index2D.i[1] =
1890 index2D.i[2] =
1891 index2D.i[3] = 0;
1892 }
1893
1894 switch (reg->Register.File) {
1895 case TGSI_FILE_NULL:
1896 dst = &null;
1897 break;
1898
1899 case TGSI_FILE_OUTPUT:
1900 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1901 + reg->Register.Index;
1902 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1903 #if 0
1904 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1905 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1906 reg->Register.Index);
1907 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1908 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1909 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1910 if (execmask & (1 << i))
1911 debug_printf("%f, ", chan->f[i]);
1912 debug_printf(")\n");
1913 }
1914 #endif
1915 break;
1916
1917 case TGSI_FILE_TEMPORARY:
1918 index = reg->Register.Index;
1919 assert( index < TGSI_EXEC_NUM_TEMPS );
1920 dst = &mach->Temps[offset + index].xyzw[chan_index];
1921 break;
1922
1923 case TGSI_FILE_ADDRESS:
1924 index = reg->Register.Index;
1925 dst = &mach->Addrs[index].xyzw[chan_index];
1926 break;
1927
1928 default:
1929 assert( 0 );
1930 return NULL;
1931 }
1932
1933 return dst;
1934 }
1935
1936 static void
1937 store_dest_double(struct tgsi_exec_machine *mach,
1938 const union tgsi_exec_channel *chan,
1939 const struct tgsi_full_dst_register *reg,
1940 const struct tgsi_full_instruction *inst,
1941 uint chan_index,
1942 enum tgsi_exec_datatype dst_datatype)
1943 {
1944 union tgsi_exec_channel *dst;
1945 const uint execmask = mach->ExecMask;
1946 int i;
1947
1948 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1949 dst_datatype);
1950 if (!dst)
1951 return;
1952
1953 /* doubles path */
1954 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1955 if (execmask & (1 << i))
1956 dst->i[i] = chan->i[i];
1957 }
1958
1959 static void
1960 store_dest(struct tgsi_exec_machine *mach,
1961 const union tgsi_exec_channel *chan,
1962 const struct tgsi_full_dst_register *reg,
1963 const struct tgsi_full_instruction *inst,
1964 uint chan_index,
1965 enum tgsi_exec_datatype dst_datatype)
1966 {
1967 union tgsi_exec_channel *dst;
1968 const uint execmask = mach->ExecMask;
1969 int i;
1970
1971 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1972 dst_datatype);
1973 if (!dst)
1974 return;
1975
1976 if (!inst->Instruction.Saturate) {
1977 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1978 if (execmask & (1 << i))
1979 dst->i[i] = chan->i[i];
1980 }
1981 else {
1982 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1983 if (execmask & (1 << i)) {
1984 if (chan->f[i] < 0.0f)
1985 dst->f[i] = 0.0f;
1986 else if (chan->f[i] > 1.0f)
1987 dst->f[i] = 1.0f;
1988 else
1989 dst->i[i] = chan->i[i];
1990 }
1991 }
1992 }
1993
1994 #define FETCH(VAL,INDEX,CHAN)\
1995 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1996
1997 #define IFETCH(VAL,INDEX,CHAN)\
1998 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1999
2000
2001 /**
2002 * Execute ARB-style KIL which is predicated by a src register.
2003 * Kill fragment if any of the four values is less than zero.
2004 */
2005 static void
2006 exec_kill_if(struct tgsi_exec_machine *mach,
2007 const struct tgsi_full_instruction *inst)
2008 {
2009 uint uniquemask;
2010 uint chan_index;
2011 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2012 union tgsi_exec_channel r[1];
2013
2014 /* This mask stores component bits that were already tested. */
2015 uniquemask = 0;
2016
2017 for (chan_index = 0; chan_index < 4; chan_index++)
2018 {
2019 uint swizzle;
2020 uint i;
2021
2022 /* unswizzle channel */
2023 swizzle = tgsi_util_get_full_src_register_swizzle (
2024 &inst->Src[0],
2025 chan_index);
2026
2027 /* check if the component has not been already tested */
2028 if (uniquemask & (1 << swizzle))
2029 continue;
2030 uniquemask |= 1 << swizzle;
2031
2032 FETCH(&r[0], 0, chan_index);
2033 for (i = 0; i < 4; i++)
2034 if (r[0].f[i] < 0.0f)
2035 kilmask |= 1 << i;
2036 }
2037
2038 /* restrict to fragments currently executing */
2039 kilmask &= mach->ExecMask;
2040
2041 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
2042 }
2043
2044 /**
2045 * Unconditional fragment kill/discard.
2046 */
2047 static void
2048 exec_kill(struct tgsi_exec_machine *mach,
2049 const struct tgsi_full_instruction *inst)
2050 {
2051 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2052
2053 /* kill fragment for all fragments currently executing */
2054 kilmask = mach->ExecMask;
2055 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
2056 }
2057
2058 static void
2059 emit_vertex(struct tgsi_exec_machine *mach)
2060 {
2061 /* FIXME: check for exec mask correctly
2062 unsigned i;
2063 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2064 if ((mach->ExecMask & (1 << i)))
2065 */
2066 if (mach->ExecMask) {
2067 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
2068 return;
2069
2070 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
2071 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
2072 }
2073 }
2074
2075 static void
2076 emit_primitive(struct tgsi_exec_machine *mach)
2077 {
2078 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
2079 /* FIXME: check for exec mask correctly
2080 unsigned i;
2081 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2082 if ((mach->ExecMask & (1 << i)))
2083 */
2084 if (mach->ExecMask) {
2085 ++(*prim_count);
2086 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
2087 mach->Primitives[*prim_count] = 0;
2088 }
2089 }
2090
2091 static void
2092 conditional_emit_primitive(struct tgsi_exec_machine *mach)
2093 {
2094 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
2095 int emitted_verts =
2096 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
2097 if (emitted_verts) {
2098 emit_primitive(mach);
2099 }
2100 }
2101 }
2102
2103
2104 /*
2105 * Fetch four texture samples using STR texture coordinates.
2106 */
2107 static void
2108 fetch_texel( struct tgsi_sampler *sampler,
2109 const unsigned sview_idx,
2110 const unsigned sampler_idx,
2111 const union tgsi_exec_channel *s,
2112 const union tgsi_exec_channel *t,
2113 const union tgsi_exec_channel *p,
2114 const union tgsi_exec_channel *c0,
2115 const union tgsi_exec_channel *c1,
2116 float derivs[3][2][TGSI_QUAD_SIZE],
2117 const int8_t offset[3],
2118 enum tgsi_sampler_control control,
2119 union tgsi_exec_channel *r,
2120 union tgsi_exec_channel *g,
2121 union tgsi_exec_channel *b,
2122 union tgsi_exec_channel *a )
2123 {
2124 uint j;
2125 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2126
2127 /* FIXME: handle explicit derivs, offsets */
2128 sampler->get_samples(sampler, sview_idx, sampler_idx,
2129 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
2130
2131 for (j = 0; j < 4; j++) {
2132 r->f[j] = rgba[0][j];
2133 g->f[j] = rgba[1][j];
2134 b->f[j] = rgba[2][j];
2135 a->f[j] = rgba[3][j];
2136 }
2137 }
2138
2139
2140 #define TEX_MODIFIER_NONE 0
2141 #define TEX_MODIFIER_PROJECTED 1
2142 #define TEX_MODIFIER_LOD_BIAS 2
2143 #define TEX_MODIFIER_EXPLICIT_LOD 3
2144 #define TEX_MODIFIER_LEVEL_ZERO 4
2145 #define TEX_MODIFIER_GATHER 5
2146
2147 /*
2148 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2149 */
2150 static void
2151 fetch_texel_offsets(struct tgsi_exec_machine *mach,
2152 const struct tgsi_full_instruction *inst,
2153 int8_t offsets[3])
2154 {
2155 if (inst->Texture.NumOffsets == 1) {
2156 union tgsi_exec_channel index;
2157 union tgsi_exec_channel offset[3];
2158 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2159 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2160 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2161 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2162 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2163 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
2164 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2165 offsets[0] = offset[0].i[0];
2166 offsets[1] = offset[1].i[0];
2167 offsets[2] = offset[2].i[0];
2168 } else {
2169 assert(inst->Texture.NumOffsets == 0);
2170 offsets[0] = offsets[1] = offsets[2] = 0;
2171 }
2172 }
2173
2174
2175 /*
2176 * Fetch dx and dy values for one channel (s, t or r).
2177 * Put dx values into one float array, dy values into another.
2178 */
2179 static void
2180 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
2181 const struct tgsi_full_instruction *inst,
2182 unsigned regdsrcx,
2183 unsigned chan,
2184 float derivs[2][TGSI_QUAD_SIZE])
2185 {
2186 union tgsi_exec_channel d;
2187 FETCH(&d, regdsrcx, chan);
2188 derivs[0][0] = d.f[0];
2189 derivs[0][1] = d.f[1];
2190 derivs[0][2] = d.f[2];
2191 derivs[0][3] = d.f[3];
2192 FETCH(&d, regdsrcx + 1, chan);
2193 derivs[1][0] = d.f[0];
2194 derivs[1][1] = d.f[1];
2195 derivs[1][2] = d.f[2];
2196 derivs[1][3] = d.f[3];
2197 }
2198
2199 static uint
2200 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2201 const struct tgsi_full_instruction *inst,
2202 uint sampler)
2203 {
2204 uint unit = 0;
2205 int i;
2206 if (inst->Src[sampler].Register.Indirect) {
2207 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2208 union tgsi_exec_channel indir_index, index2;
2209 const uint execmask = mach->ExecMask;
2210 index2.i[0] =
2211 index2.i[1] =
2212 index2.i[2] =
2213 index2.i[3] = reg->Indirect.Index;
2214
2215 fetch_src_file_channel(mach,
2216 0,
2217 reg->Indirect.File,
2218 reg->Indirect.Swizzle,
2219 &index2,
2220 &ZeroVec,
2221 &indir_index);
2222 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2223 if (execmask & (1 << i)) {
2224 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2225 break;
2226 }
2227 }
2228
2229 } else {
2230 unit = inst->Src[sampler].Register.Index;
2231 }
2232 return unit;
2233 }
2234
2235 /*
2236 * execute a texture instruction.
2237 *
2238 * modifier is used to control the channel routing for the
2239 * instruction variants like proj, lod, and texture with lod bias.
2240 * sampler indicates which src register the sampler is contained in.
2241 */
2242 static void
2243 exec_tex(struct tgsi_exec_machine *mach,
2244 const struct tgsi_full_instruction *inst,
2245 uint modifier, uint sampler)
2246 {
2247 const union tgsi_exec_channel *args[5], *proj = NULL;
2248 union tgsi_exec_channel r[5];
2249 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2250 uint chan;
2251 uint unit;
2252 int8_t offsets[3];
2253 int dim, shadow_ref, i;
2254
2255 unit = fetch_sampler_unit(mach, inst, sampler);
2256 /* always fetch all 3 offsets, overkill but keeps code simple */
2257 fetch_texel_offsets(mach, inst, offsets);
2258
2259 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2260 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2261
2262 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2263 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2264
2265 assert(dim <= 4);
2266 if (shadow_ref >= 0)
2267 assert(shadow_ref >= dim && shadow_ref < ARRAY_SIZE(args));
2268
2269 /* fetch modifier to the last argument */
2270 if (modifier != TEX_MODIFIER_NONE) {
2271 const int last = ARRAY_SIZE(args) - 1;
2272
2273 /* fetch modifier from src0.w or src1.x */
2274 if (sampler == 1) {
2275 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2276 FETCH(&r[last], 0, TGSI_CHAN_W);
2277 }
2278 else {
2279 assert(shadow_ref != 4);
2280 FETCH(&r[last], 1, TGSI_CHAN_X);
2281 }
2282
2283 if (modifier != TEX_MODIFIER_PROJECTED) {
2284 args[last] = &r[last];
2285 }
2286 else {
2287 proj = &r[last];
2288 args[last] = &ZeroVec;
2289 }
2290
2291 /* point unused arguments to zero vector */
2292 for (i = dim; i < last; i++)
2293 args[i] = &ZeroVec;
2294
2295 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2296 control = TGSI_SAMPLER_LOD_EXPLICIT;
2297 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2298 control = TGSI_SAMPLER_LOD_BIAS;
2299 else if (modifier == TEX_MODIFIER_GATHER)
2300 control = TGSI_SAMPLER_GATHER;
2301 }
2302 else {
2303 for (i = dim; i < ARRAY_SIZE(args); i++)
2304 args[i] = &ZeroVec;
2305 }
2306
2307 /* fetch coordinates */
2308 for (i = 0; i < dim; i++) {
2309 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2310
2311 if (proj)
2312 micro_div(&r[i], &r[i], proj);
2313
2314 args[i] = &r[i];
2315 }
2316
2317 /* fetch reference value */
2318 if (shadow_ref >= 0) {
2319 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2320
2321 if (proj)
2322 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2323
2324 args[shadow_ref] = &r[shadow_ref];
2325 }
2326
2327 fetch_texel(mach->Sampler, unit, unit,
2328 args[0], args[1], args[2], args[3], args[4],
2329 NULL, offsets, control,
2330 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2331
2332 #if 0
2333 debug_printf("fetch r: %g %g %g %g\n",
2334 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2335 debug_printf("fetch g: %g %g %g %g\n",
2336 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2337 debug_printf("fetch b: %g %g %g %g\n",
2338 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2339 debug_printf("fetch a: %g %g %g %g\n",
2340 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2341 #endif
2342
2343 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2344 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2345 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2346 }
2347 }
2348 }
2349
2350 static void
2351 exec_lodq(struct tgsi_exec_machine *mach,
2352 const struct tgsi_full_instruction *inst)
2353 {
2354 uint unit;
2355 int dim;
2356 int i;
2357 union tgsi_exec_channel coords[4];
2358 const union tgsi_exec_channel *args[ARRAY_SIZE(coords)];
2359 union tgsi_exec_channel r[2];
2360
2361 unit = fetch_sampler_unit(mach, inst, 1);
2362 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2363 assert(dim <= ARRAY_SIZE(coords));
2364 /* fetch coordinates */
2365 for (i = 0; i < dim; i++) {
2366 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2367 args[i] = &coords[i];
2368 }
2369 for (i = dim; i < ARRAY_SIZE(coords); i++) {
2370 args[i] = &ZeroVec;
2371 }
2372 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2373 args[0]->f,
2374 args[1]->f,
2375 args[2]->f,
2376 args[3]->f,
2377 TGSI_SAMPLER_LOD_NONE,
2378 r[0].f,
2379 r[1].f);
2380
2381 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2382 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2383 TGSI_EXEC_DATA_FLOAT);
2384 }
2385 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2386 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2387 TGSI_EXEC_DATA_FLOAT);
2388 }
2389 }
2390
2391 static void
2392 exec_txd(struct tgsi_exec_machine *mach,
2393 const struct tgsi_full_instruction *inst)
2394 {
2395 union tgsi_exec_channel r[4];
2396 float derivs[3][2][TGSI_QUAD_SIZE];
2397 uint chan;
2398 uint unit;
2399 int8_t offsets[3];
2400
2401 unit = fetch_sampler_unit(mach, inst, 3);
2402 /* always fetch all 3 offsets, overkill but keeps code simple */
2403 fetch_texel_offsets(mach, inst, offsets);
2404
2405 switch (inst->Texture.Texture) {
2406 case TGSI_TEXTURE_1D:
2407 FETCH(&r[0], 0, TGSI_CHAN_X);
2408
2409 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2410
2411 fetch_texel(mach->Sampler, unit, unit,
2412 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2413 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2414 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2415 break;
2416
2417 case TGSI_TEXTURE_SHADOW1D:
2418 case TGSI_TEXTURE_1D_ARRAY:
2419 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2420 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2421 FETCH(&r[0], 0, TGSI_CHAN_X);
2422 FETCH(&r[1], 0, TGSI_CHAN_Y);
2423 FETCH(&r[2], 0, TGSI_CHAN_Z);
2424
2425 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2426
2427 fetch_texel(mach->Sampler, unit, unit,
2428 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2429 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2430 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2431 break;
2432
2433 case TGSI_TEXTURE_2D:
2434 case TGSI_TEXTURE_RECT:
2435 FETCH(&r[0], 0, TGSI_CHAN_X);
2436 FETCH(&r[1], 0, TGSI_CHAN_Y);
2437
2438 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2439 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2440
2441 fetch_texel(mach->Sampler, unit, unit,
2442 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2443 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2444 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2445 break;
2446
2447
2448 case TGSI_TEXTURE_SHADOW2D:
2449 case TGSI_TEXTURE_SHADOWRECT:
2450 case TGSI_TEXTURE_2D_ARRAY:
2451 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2452 /* only SHADOW2D_ARRAY actually needs W */
2453 FETCH(&r[0], 0, TGSI_CHAN_X);
2454 FETCH(&r[1], 0, TGSI_CHAN_Y);
2455 FETCH(&r[2], 0, TGSI_CHAN_Z);
2456 FETCH(&r[3], 0, TGSI_CHAN_W);
2457
2458 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2459 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2460
2461 fetch_texel(mach->Sampler, unit, unit,
2462 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2463 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2464 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2465 break;
2466
2467 case TGSI_TEXTURE_3D:
2468 case TGSI_TEXTURE_CUBE:
2469 case TGSI_TEXTURE_CUBE_ARRAY:
2470 case TGSI_TEXTURE_SHADOWCUBE:
2471 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2472 FETCH(&r[0], 0, TGSI_CHAN_X);
2473 FETCH(&r[1], 0, TGSI_CHAN_Y);
2474 FETCH(&r[2], 0, TGSI_CHAN_Z);
2475 FETCH(&r[3], 0, TGSI_CHAN_W);
2476
2477 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2478 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2479 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2480
2481 fetch_texel(mach->Sampler, unit, unit,
2482 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2483 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2484 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2485 break;
2486
2487 default:
2488 assert(0);
2489 }
2490
2491 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2492 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2493 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2494 }
2495 }
2496 }
2497
2498
2499 static void
2500 exec_txf(struct tgsi_exec_machine *mach,
2501 const struct tgsi_full_instruction *inst)
2502 {
2503 union tgsi_exec_channel r[4];
2504 uint chan;
2505 uint unit;
2506 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2507 int j;
2508 int8_t offsets[3];
2509 unsigned target;
2510
2511 unit = fetch_sampler_unit(mach, inst, 1);
2512 /* always fetch all 3 offsets, overkill but keeps code simple */
2513 fetch_texel_offsets(mach, inst, offsets);
2514
2515 IFETCH(&r[3], 0, TGSI_CHAN_W);
2516
2517 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2518 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2519 target = mach->SamplerViews[unit].Resource;
2520 }
2521 else {
2522 target = inst->Texture.Texture;
2523 }
2524 switch(target) {
2525 case TGSI_TEXTURE_3D:
2526 case TGSI_TEXTURE_2D_ARRAY:
2527 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2528 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2529 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2530 /* fallthrough */
2531 case TGSI_TEXTURE_2D:
2532 case TGSI_TEXTURE_RECT:
2533 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2534 case TGSI_TEXTURE_SHADOW2D:
2535 case TGSI_TEXTURE_SHADOWRECT:
2536 case TGSI_TEXTURE_1D_ARRAY:
2537 case TGSI_TEXTURE_2D_MSAA:
2538 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2539 /* fallthrough */
2540 case TGSI_TEXTURE_BUFFER:
2541 case TGSI_TEXTURE_1D:
2542 case TGSI_TEXTURE_SHADOW1D:
2543 IFETCH(&r[0], 0, TGSI_CHAN_X);
2544 break;
2545 default:
2546 assert(0);
2547 break;
2548 }
2549
2550 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2551 offsets, rgba);
2552
2553 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2554 r[0].f[j] = rgba[0][j];
2555 r[1].f[j] = rgba[1][j];
2556 r[2].f[j] = rgba[2][j];
2557 r[3].f[j] = rgba[3][j];
2558 }
2559
2560 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2561 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2562 unsigned char swizzles[4];
2563 swizzles[0] = inst->Src[1].Register.SwizzleX;
2564 swizzles[1] = inst->Src[1].Register.SwizzleY;
2565 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2566 swizzles[3] = inst->Src[1].Register.SwizzleW;
2567
2568 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2569 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2570 store_dest(mach, &r[swizzles[chan]],
2571 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2572 }
2573 }
2574 }
2575 else {
2576 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2577 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2578 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2579 }
2580 }
2581 }
2582 }
2583
2584 static void
2585 exec_txq(struct tgsi_exec_machine *mach,
2586 const struct tgsi_full_instruction *inst)
2587 {
2588 int result[4];
2589 union tgsi_exec_channel r[4], src;
2590 uint chan;
2591 uint unit;
2592 int i,j;
2593
2594 unit = fetch_sampler_unit(mach, inst, 1);
2595
2596 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2597
2598 /* XXX: This interface can't return per-pixel values */
2599 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2600
2601 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2602 for (j = 0; j < 4; j++) {
2603 r[j].i[i] = result[j];
2604 }
2605 }
2606
2607 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2608 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2609 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2610 TGSI_EXEC_DATA_INT);
2611 }
2612 }
2613 }
2614
2615 static void
2616 exec_sample(struct tgsi_exec_machine *mach,
2617 const struct tgsi_full_instruction *inst,
2618 uint modifier, boolean compare)
2619 {
2620 const uint resource_unit = inst->Src[1].Register.Index;
2621 const uint sampler_unit = inst->Src[2].Register.Index;
2622 union tgsi_exec_channel r[5], c1;
2623 const union tgsi_exec_channel *lod = &ZeroVec;
2624 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2625 uint chan;
2626 unsigned char swizzles[4];
2627 int8_t offsets[3];
2628
2629 /* always fetch all 3 offsets, overkill but keeps code simple */
2630 fetch_texel_offsets(mach, inst, offsets);
2631
2632 assert(modifier != TEX_MODIFIER_PROJECTED);
2633
2634 if (modifier != TEX_MODIFIER_NONE) {
2635 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2636 FETCH(&c1, 3, TGSI_CHAN_X);
2637 lod = &c1;
2638 control = TGSI_SAMPLER_LOD_BIAS;
2639 }
2640 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2641 FETCH(&c1, 3, TGSI_CHAN_X);
2642 lod = &c1;
2643 control = TGSI_SAMPLER_LOD_EXPLICIT;
2644 }
2645 else if (modifier == TEX_MODIFIER_GATHER) {
2646 control = TGSI_SAMPLER_GATHER;
2647 }
2648 else {
2649 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2650 control = TGSI_SAMPLER_LOD_ZERO;
2651 }
2652 }
2653
2654 FETCH(&r[0], 0, TGSI_CHAN_X);
2655
2656 switch (mach->SamplerViews[resource_unit].Resource) {
2657 case TGSI_TEXTURE_1D:
2658 if (compare) {
2659 FETCH(&r[2], 3, TGSI_CHAN_X);
2660 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2661 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2662 NULL, offsets, control,
2663 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2664 }
2665 else {
2666 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2667 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2668 NULL, offsets, control,
2669 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2670 }
2671 break;
2672
2673 case TGSI_TEXTURE_1D_ARRAY:
2674 case TGSI_TEXTURE_2D:
2675 case TGSI_TEXTURE_RECT:
2676 FETCH(&r[1], 0, TGSI_CHAN_Y);
2677 if (compare) {
2678 FETCH(&r[2], 3, TGSI_CHAN_X);
2679 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2680 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2681 NULL, offsets, control,
2682 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2683 }
2684 else {
2685 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2686 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2687 NULL, offsets, control,
2688 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2689 }
2690 break;
2691
2692 case TGSI_TEXTURE_2D_ARRAY:
2693 case TGSI_TEXTURE_3D:
2694 case TGSI_TEXTURE_CUBE:
2695 FETCH(&r[1], 0, TGSI_CHAN_Y);
2696 FETCH(&r[2], 0, TGSI_CHAN_Z);
2697 if(compare) {
2698 FETCH(&r[3], 3, TGSI_CHAN_X);
2699 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2700 &r[0], &r[1], &r[2], &r[3], lod,
2701 NULL, offsets, control,
2702 &r[0], &r[1], &r[2], &r[3]);
2703 }
2704 else {
2705 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2706 &r[0], &r[1], &r[2], &ZeroVec, lod,
2707 NULL, offsets, control,
2708 &r[0], &r[1], &r[2], &r[3]);
2709 }
2710 break;
2711
2712 case TGSI_TEXTURE_CUBE_ARRAY:
2713 FETCH(&r[1], 0, TGSI_CHAN_Y);
2714 FETCH(&r[2], 0, TGSI_CHAN_Z);
2715 FETCH(&r[3], 0, TGSI_CHAN_W);
2716 if(compare) {
2717 FETCH(&r[4], 3, TGSI_CHAN_X);
2718 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2719 &r[0], &r[1], &r[2], &r[3], &r[4],
2720 NULL, offsets, control,
2721 &r[0], &r[1], &r[2], &r[3]);
2722 }
2723 else {
2724 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2725 &r[0], &r[1], &r[2], &r[3], lod,
2726 NULL, offsets, control,
2727 &r[0], &r[1], &r[2], &r[3]);
2728 }
2729 break;
2730
2731
2732 default:
2733 assert(0);
2734 }
2735
2736 swizzles[0] = inst->Src[1].Register.SwizzleX;
2737 swizzles[1] = inst->Src[1].Register.SwizzleY;
2738 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2739 swizzles[3] = inst->Src[1].Register.SwizzleW;
2740
2741 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2742 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2743 store_dest(mach, &r[swizzles[chan]],
2744 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2745 }
2746 }
2747 }
2748
2749 static void
2750 exec_sample_d(struct tgsi_exec_machine *mach,
2751 const struct tgsi_full_instruction *inst)
2752 {
2753 const uint resource_unit = inst->Src[1].Register.Index;
2754 const uint sampler_unit = inst->Src[2].Register.Index;
2755 union tgsi_exec_channel r[4];
2756 float derivs[3][2][TGSI_QUAD_SIZE];
2757 uint chan;
2758 unsigned char swizzles[4];
2759 int8_t offsets[3];
2760
2761 /* always fetch all 3 offsets, overkill but keeps code simple */
2762 fetch_texel_offsets(mach, inst, offsets);
2763
2764 FETCH(&r[0], 0, TGSI_CHAN_X);
2765
2766 switch (mach->SamplerViews[resource_unit].Resource) {
2767 case TGSI_TEXTURE_1D:
2768 case TGSI_TEXTURE_1D_ARRAY:
2769 /* only 1D array actually needs Y */
2770 FETCH(&r[1], 0, TGSI_CHAN_Y);
2771
2772 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2773
2774 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2775 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2776 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2777 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2778 break;
2779
2780 case TGSI_TEXTURE_2D:
2781 case TGSI_TEXTURE_RECT:
2782 case TGSI_TEXTURE_2D_ARRAY:
2783 /* only 2D array actually needs Z */
2784 FETCH(&r[1], 0, TGSI_CHAN_Y);
2785 FETCH(&r[2], 0, TGSI_CHAN_Z);
2786
2787 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2788 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2789
2790 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2791 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2792 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2793 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2794 break;
2795
2796 case TGSI_TEXTURE_3D:
2797 case TGSI_TEXTURE_CUBE:
2798 case TGSI_TEXTURE_CUBE_ARRAY:
2799 /* only cube array actually needs W */
2800 FETCH(&r[1], 0, TGSI_CHAN_Y);
2801 FETCH(&r[2], 0, TGSI_CHAN_Z);
2802 FETCH(&r[3], 0, TGSI_CHAN_W);
2803
2804 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2805 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2806 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2807
2808 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2809 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2810 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2811 &r[0], &r[1], &r[2], &r[3]);
2812 break;
2813
2814 default:
2815 assert(0);
2816 }
2817
2818 swizzles[0] = inst->Src[1].Register.SwizzleX;
2819 swizzles[1] = inst->Src[1].Register.SwizzleY;
2820 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2821 swizzles[3] = inst->Src[1].Register.SwizzleW;
2822
2823 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2824 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2825 store_dest(mach, &r[swizzles[chan]],
2826 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2827 }
2828 }
2829 }
2830
2831
2832 /**
2833 * Evaluate a constant-valued coefficient at the position of the
2834 * current quad.
2835 */
2836 static void
2837 eval_constant_coef(
2838 struct tgsi_exec_machine *mach,
2839 unsigned attrib,
2840 unsigned chan )
2841 {
2842 unsigned i;
2843
2844 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2845 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2846 }
2847 }
2848
2849 /**
2850 * Evaluate a linear-valued coefficient at the position of the
2851 * current quad.
2852 */
2853 static void
2854 eval_linear_coef(
2855 struct tgsi_exec_machine *mach,
2856 unsigned attrib,
2857 unsigned chan )
2858 {
2859 const float x = mach->QuadPos.xyzw[0].f[0];
2860 const float y = mach->QuadPos.xyzw[1].f[0];
2861 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2862 const float dady = mach->InterpCoefs[attrib].dady[chan];
2863 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2864 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2865 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2866 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2867 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2868 }
2869
2870 /**
2871 * Evaluate a perspective-valued coefficient at the position of the
2872 * current quad.
2873 */
2874 static void
2875 eval_perspective_coef(
2876 struct tgsi_exec_machine *mach,
2877 unsigned attrib,
2878 unsigned chan )
2879 {
2880 const float x = mach->QuadPos.xyzw[0].f[0];
2881 const float y = mach->QuadPos.xyzw[1].f[0];
2882 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2883 const float dady = mach->InterpCoefs[attrib].dady[chan];
2884 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2885 const float *w = mach->QuadPos.xyzw[3].f;
2886 /* divide by W here */
2887 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2888 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2889 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2890 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2891 }
2892
2893
2894 typedef void (* eval_coef_func)(
2895 struct tgsi_exec_machine *mach,
2896 unsigned attrib,
2897 unsigned chan );
2898
2899 static void
2900 exec_declaration(struct tgsi_exec_machine *mach,
2901 const struct tgsi_full_declaration *decl)
2902 {
2903 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2904 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2905 return;
2906 }
2907
2908 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2909 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2910 uint first, last, mask;
2911
2912 first = decl->Range.First;
2913 last = decl->Range.Last;
2914 mask = decl->Declaration.UsageMask;
2915
2916 /* XXX we could remove this special-case code since
2917 * mach->InterpCoefs[first].a0 should already have the
2918 * front/back-face value. But we should first update the
2919 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2920 * Then, we could remove the tgsi_exec_machine::Face field.
2921 */
2922 /* XXX make FACE a system value */
2923 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2924 uint i;
2925
2926 assert(decl->Semantic.Index == 0);
2927 assert(first == last);
2928
2929 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2930 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2931 }
2932 } else {
2933 eval_coef_func eval;
2934 uint i, j;
2935
2936 switch (decl->Interp.Interpolate) {
2937 case TGSI_INTERPOLATE_CONSTANT:
2938 eval = eval_constant_coef;
2939 break;
2940
2941 case TGSI_INTERPOLATE_LINEAR:
2942 eval = eval_linear_coef;
2943 break;
2944
2945 case TGSI_INTERPOLATE_PERSPECTIVE:
2946 eval = eval_perspective_coef;
2947 break;
2948
2949 case TGSI_INTERPOLATE_COLOR:
2950 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2951 break;
2952
2953 default:
2954 assert(0);
2955 return;
2956 }
2957
2958 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2959 if (mask & (1 << j)) {
2960 for (i = first; i <= last; i++) {
2961 eval(mach, i, j);
2962 }
2963 }
2964 }
2965 }
2966
2967 if (DEBUG_EXECUTION) {
2968 uint i, j;
2969 for (i = first; i <= last; ++i) {
2970 debug_printf("IN[%2u] = ", i);
2971 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2972 if (j > 0) {
2973 debug_printf(" ");
2974 }
2975 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2976 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2977 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2978 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2979 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2980 }
2981 }
2982 }
2983 }
2984 }
2985
2986 }
2987
2988 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2989 const union tgsi_exec_channel *src);
2990
2991 static void
2992 exec_scalar_unary(struct tgsi_exec_machine *mach,
2993 const struct tgsi_full_instruction *inst,
2994 micro_unary_op op,
2995 enum tgsi_exec_datatype dst_datatype,
2996 enum tgsi_exec_datatype src_datatype)
2997 {
2998 unsigned int chan;
2999 union tgsi_exec_channel src;
3000 union tgsi_exec_channel dst;
3001
3002 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
3003 op(&dst, &src);
3004 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3005 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3006 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
3007 }
3008 }
3009 }
3010
3011 static void
3012 exec_vector_unary(struct tgsi_exec_machine *mach,
3013 const struct tgsi_full_instruction *inst,
3014 micro_unary_op op,
3015 enum tgsi_exec_datatype dst_datatype,
3016 enum tgsi_exec_datatype src_datatype)
3017 {
3018 unsigned int chan;
3019 struct tgsi_exec_vector dst;
3020
3021 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3022 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3023 union tgsi_exec_channel src;
3024
3025 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
3026 op(&dst.xyzw[chan], &src);
3027 }
3028 }
3029 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3030 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3031 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3032 }
3033 }
3034 }
3035
3036 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
3037 const union tgsi_exec_channel *src0,
3038 const union tgsi_exec_channel *src1);
3039
3040 static void
3041 exec_scalar_binary(struct tgsi_exec_machine *mach,
3042 const struct tgsi_full_instruction *inst,
3043 micro_binary_op op,
3044 enum tgsi_exec_datatype dst_datatype,
3045 enum tgsi_exec_datatype src_datatype)
3046 {
3047 unsigned int chan;
3048 union tgsi_exec_channel src[2];
3049 union tgsi_exec_channel dst;
3050
3051 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
3052 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
3053 op(&dst, &src[0], &src[1]);
3054 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3055 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3056 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
3057 }
3058 }
3059 }
3060
3061 static void
3062 exec_vector_binary(struct tgsi_exec_machine *mach,
3063 const struct tgsi_full_instruction *inst,
3064 micro_binary_op op,
3065 enum tgsi_exec_datatype dst_datatype,
3066 enum tgsi_exec_datatype src_datatype)
3067 {
3068 unsigned int chan;
3069 struct tgsi_exec_vector dst;
3070
3071 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3072 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3073 union tgsi_exec_channel src[2];
3074
3075 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3076 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3077 op(&dst.xyzw[chan], &src[0], &src[1]);
3078 }
3079 }
3080 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3081 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3082 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3083 }
3084 }
3085 }
3086
3087 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
3088 const union tgsi_exec_channel *src0,
3089 const union tgsi_exec_channel *src1,
3090 const union tgsi_exec_channel *src2);
3091
3092 static void
3093 exec_vector_trinary(struct tgsi_exec_machine *mach,
3094 const struct tgsi_full_instruction *inst,
3095 micro_trinary_op op,
3096 enum tgsi_exec_datatype dst_datatype,
3097 enum tgsi_exec_datatype src_datatype)
3098 {
3099 unsigned int chan;
3100 struct tgsi_exec_vector dst;
3101
3102 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3103 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3104 union tgsi_exec_channel src[3];
3105
3106 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3107 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3108 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3109 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
3110 }
3111 }
3112 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3113 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3114 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3115 }
3116 }
3117 }
3118
3119 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
3120 const union tgsi_exec_channel *src0,
3121 const union tgsi_exec_channel *src1,
3122 const union tgsi_exec_channel *src2,
3123 const union tgsi_exec_channel *src3);
3124
3125 static void
3126 exec_vector_quaternary(struct tgsi_exec_machine *mach,
3127 const struct tgsi_full_instruction *inst,
3128 micro_quaternary_op op,
3129 enum tgsi_exec_datatype dst_datatype,
3130 enum tgsi_exec_datatype src_datatype)
3131 {
3132 unsigned int chan;
3133 struct tgsi_exec_vector dst;
3134
3135 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3136 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3137 union tgsi_exec_channel src[4];
3138
3139 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3140 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3141 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3142 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
3143 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
3144 }
3145 }
3146 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3147 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3148 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
3149 }
3150 }
3151 }
3152
3153 static void
3154 exec_dp3(struct tgsi_exec_machine *mach,
3155 const struct tgsi_full_instruction *inst)
3156 {
3157 unsigned int chan;
3158 union tgsi_exec_channel arg[3];
3159
3160 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3161 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3162 micro_mul(&arg[2], &arg[0], &arg[1]);
3163
3164 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
3165 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3166 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3167 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3168 }
3169
3170 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3171 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3172 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3173 }
3174 }
3175 }
3176
3177 static void
3178 exec_dp4(struct tgsi_exec_machine *mach,
3179 const struct tgsi_full_instruction *inst)
3180 {
3181 unsigned int chan;
3182 union tgsi_exec_channel arg[3];
3183
3184 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3185 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3186 micro_mul(&arg[2], &arg[0], &arg[1]);
3187
3188 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
3189 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3190 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3191 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3192 }
3193
3194 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3195 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3196 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3197 }
3198 }
3199 }
3200
3201 static void
3202 exec_dp2(struct tgsi_exec_machine *mach,
3203 const struct tgsi_full_instruction *inst)
3204 {
3205 unsigned int chan;
3206 union tgsi_exec_channel arg[3];
3207
3208 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3209 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3210 micro_mul(&arg[2], &arg[0], &arg[1]);
3211
3212 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3213 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3214 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3215
3216 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3217 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3218 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3219 }
3220 }
3221 }
3222
3223 static void
3224 exec_pk2h(struct tgsi_exec_machine *mach,
3225 const struct tgsi_full_instruction *inst)
3226 {
3227 unsigned chan;
3228 union tgsi_exec_channel arg[2], dst;
3229
3230 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3231 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3232 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3233 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3234 (util_float_to_half(arg[1].f[chan]) << 16);
3235 }
3236 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3237 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3238 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3239 }
3240 }
3241 }
3242
3243 static void
3244 exec_up2h(struct tgsi_exec_machine *mach,
3245 const struct tgsi_full_instruction *inst)
3246 {
3247 unsigned chan;
3248 union tgsi_exec_channel arg, dst[2];
3249
3250 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3251 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3252 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3253 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3254 }
3255 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3256 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3257 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3258 }
3259 }
3260 }
3261
3262 static void
3263 micro_ucmp(union tgsi_exec_channel *dst,
3264 const union tgsi_exec_channel *src0,
3265 const union tgsi_exec_channel *src1,
3266 const union tgsi_exec_channel *src2)
3267 {
3268 dst->f[0] = src0->u[0] ? src1->f[0] : src2->f[0];
3269 dst->f[1] = src0->u[1] ? src1->f[1] : src2->f[1];
3270 dst->f[2] = src0->u[2] ? src1->f[2] : src2->f[2];
3271 dst->f[3] = src0->u[3] ? src1->f[3] : src2->f[3];
3272 }
3273
3274 static void
3275 exec_ucmp(struct tgsi_exec_machine *mach,
3276 const struct tgsi_full_instruction *inst)
3277 {
3278 unsigned int chan;
3279 struct tgsi_exec_vector dst;
3280
3281 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3282 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3283 union tgsi_exec_channel src[3];
3284
3285 fetch_source(mach, &src[0], &inst->Src[0], chan,
3286 TGSI_EXEC_DATA_UINT);
3287 fetch_source(mach, &src[1], &inst->Src[1], chan,
3288 TGSI_EXEC_DATA_FLOAT);
3289 fetch_source(mach, &src[2], &inst->Src[2], chan,
3290 TGSI_EXEC_DATA_FLOAT);
3291 micro_ucmp(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
3292 }
3293 }
3294 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3295 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3296 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan,
3297 TGSI_EXEC_DATA_FLOAT);
3298 }
3299 }
3300 }
3301
3302 static void
3303 exec_dst(struct tgsi_exec_machine *mach,
3304 const struct tgsi_full_instruction *inst)
3305 {
3306 union tgsi_exec_channel r[2];
3307 union tgsi_exec_channel d[4];
3308
3309 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3310 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3311 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3312 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3313 }
3314 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3315 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3316 }
3317 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3318 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3319 }
3320
3321 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3322 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3323 }
3324 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3325 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3326 }
3327 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3328 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3329 }
3330 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3331 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3332 }
3333 }
3334
3335 static void
3336 exec_log(struct tgsi_exec_machine *mach,
3337 const struct tgsi_full_instruction *inst)
3338 {
3339 union tgsi_exec_channel r[3];
3340
3341 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3342 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3343 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3344 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3345 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3346 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3347 }
3348 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3349 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3350 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3351 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3352 }
3353 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3354 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3355 }
3356 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3357 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3358 }
3359 }
3360
3361 static void
3362 exec_exp(struct tgsi_exec_machine *mach,
3363 const struct tgsi_full_instruction *inst)
3364 {
3365 union tgsi_exec_channel r[3];
3366
3367 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3368 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3369 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3370 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3371 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3372 }
3373 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3374 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3375 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3376 }
3377 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3378 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3379 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3380 }
3381 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3382 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3383 }
3384 }
3385
3386 static void
3387 exec_lit(struct tgsi_exec_machine *mach,
3388 const struct tgsi_full_instruction *inst)
3389 {
3390 union tgsi_exec_channel r[3];
3391 union tgsi_exec_channel d[3];
3392
3393 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3394 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3395 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3396 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3397 micro_max(&r[1], &r[1], &ZeroVec);
3398
3399 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3400 micro_min(&r[2], &r[2], &P128Vec);
3401 micro_max(&r[2], &r[2], &M128Vec);
3402 micro_pow(&r[1], &r[1], &r[2]);
3403 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3404 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3405 }
3406 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3407 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3408 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3409 }
3410 }
3411 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3412 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3413 }
3414
3415 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3416 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3417 }
3418 }
3419
3420 static void
3421 exec_break(struct tgsi_exec_machine *mach)
3422 {
3423 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3424 /* turn off loop channels for each enabled exec channel */
3425 mach->LoopMask &= ~mach->ExecMask;
3426 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3427 UPDATE_EXEC_MASK(mach);
3428 } else {
3429 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3430
3431 mach->Switch.mask = 0x0;
3432
3433 UPDATE_EXEC_MASK(mach);
3434 }
3435 }
3436
3437 static void
3438 exec_switch(struct tgsi_exec_machine *mach,
3439 const struct tgsi_full_instruction *inst)
3440 {
3441 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3442 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3443
3444 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3445 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3446 mach->Switch.mask = 0x0;
3447 mach->Switch.defaultMask = 0x0;
3448
3449 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3450 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3451
3452 UPDATE_EXEC_MASK(mach);
3453 }
3454
3455 static void
3456 exec_case(struct tgsi_exec_machine *mach,
3457 const struct tgsi_full_instruction *inst)
3458 {
3459 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3460 union tgsi_exec_channel src;
3461 uint mask = 0;
3462
3463 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3464
3465 if (mach->Switch.selector.u[0] == src.u[0]) {
3466 mask |= 0x1;
3467 }
3468 if (mach->Switch.selector.u[1] == src.u[1]) {
3469 mask |= 0x2;
3470 }
3471 if (mach->Switch.selector.u[2] == src.u[2]) {
3472 mask |= 0x4;
3473 }
3474 if (mach->Switch.selector.u[3] == src.u[3]) {
3475 mask |= 0x8;
3476 }
3477
3478 mach->Switch.defaultMask |= mask;
3479
3480 mach->Switch.mask |= mask & prevMask;
3481
3482 UPDATE_EXEC_MASK(mach);
3483 }
3484
3485 /* FIXME: this will only work if default is last */
3486 static void
3487 exec_default(struct tgsi_exec_machine *mach)
3488 {
3489 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3490
3491 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3492
3493 UPDATE_EXEC_MASK(mach);
3494 }
3495
3496 static void
3497 exec_endswitch(struct tgsi_exec_machine *mach)
3498 {
3499 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3500 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3501
3502 UPDATE_EXEC_MASK(mach);
3503 }
3504
3505 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3506 const union tgsi_double_channel *src);
3507
3508 typedef void (* micro_dop_sop)(union tgsi_double_channel *dst,
3509 const union tgsi_double_channel *src0,
3510 union tgsi_exec_channel *src1);
3511
3512 typedef void (* micro_dop_s)(union tgsi_double_channel *dst,
3513 const union tgsi_exec_channel *src);
3514
3515 typedef void (* micro_sop_d)(union tgsi_exec_channel *dst,
3516 const union tgsi_double_channel *src);
3517
3518 static void
3519 fetch_double_channel(struct tgsi_exec_machine *mach,
3520 union tgsi_double_channel *chan,
3521 const struct tgsi_full_src_register *reg,
3522 uint chan_0,
3523 uint chan_1)
3524 {
3525 union tgsi_exec_channel src[2];
3526 uint i;
3527
3528 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3529 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3530
3531 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3532 chan->u[i][0] = src[0].u[i];
3533 chan->u[i][1] = src[1].u[i];
3534 }
3535 if (reg->Register.Absolute) {
3536 micro_dabs(chan, chan);
3537 }
3538 if (reg->Register.Negate) {
3539 micro_dneg(chan, chan);
3540 }
3541 }
3542
3543 static void
3544 store_double_channel(struct tgsi_exec_machine *mach,
3545 const union tgsi_double_channel *chan,
3546 const struct tgsi_full_dst_register *reg,
3547 const struct tgsi_full_instruction *inst,
3548 uint chan_0,
3549 uint chan_1)
3550 {
3551 union tgsi_exec_channel dst[2];
3552 uint i;
3553 union tgsi_double_channel temp;
3554 const uint execmask = mach->ExecMask;
3555
3556 if (!inst->Instruction.Saturate) {
3557 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3558 if (execmask & (1 << i)) {
3559 dst[0].u[i] = chan->u[i][0];
3560 dst[1].u[i] = chan->u[i][1];
3561 }
3562 }
3563 else {
3564 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3565 if (execmask & (1 << i)) {
3566 if (chan->d[i] < 0.0)
3567 temp.d[i] = 0.0;
3568 else if (chan->d[i] > 1.0)
3569 temp.d[i] = 1.0;
3570 else
3571 temp.d[i] = chan->d[i];
3572
3573 dst[0].u[i] = temp.u[i][0];
3574 dst[1].u[i] = temp.u[i][1];
3575 }
3576 }
3577
3578 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3579 if (chan_1 != -1)
3580 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3581 }
3582
3583 static void
3584 exec_double_unary(struct tgsi_exec_machine *mach,
3585 const struct tgsi_full_instruction *inst,
3586 micro_dop op)
3587 {
3588 union tgsi_double_channel src;
3589 union tgsi_double_channel dst;
3590
3591 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3592 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3593 op(&dst, &src);
3594 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3595 }
3596 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3597 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3598 op(&dst, &src);
3599 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3600 }
3601 }
3602
3603 static void
3604 exec_double_binary(struct tgsi_exec_machine *mach,
3605 const struct tgsi_full_instruction *inst,
3606 micro_dop op,
3607 enum tgsi_exec_datatype dst_datatype)
3608 {
3609 union tgsi_double_channel src[2];
3610 union tgsi_double_channel dst;
3611 int first_dest_chan, second_dest_chan;
3612 int wmask;
3613
3614 wmask = inst->Dst[0].Register.WriteMask;
3615 /* these are & because of the way DSLT etc store their destinations */
3616 if (wmask & TGSI_WRITEMASK_XY) {
3617 first_dest_chan = TGSI_CHAN_X;
3618 second_dest_chan = TGSI_CHAN_Y;
3619 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3620 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3621 second_dest_chan = -1;
3622 }
3623
3624 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3625 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3626 op(&dst, src);
3627 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3628 }
3629
3630 if (wmask & TGSI_WRITEMASK_ZW) {
3631 first_dest_chan = TGSI_CHAN_Z;
3632 second_dest_chan = TGSI_CHAN_W;
3633 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3634 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3635 second_dest_chan = -1;
3636 }
3637
3638 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3639 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3640 op(&dst, src);
3641 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3642 }
3643 }
3644
3645 static void
3646 exec_double_trinary(struct tgsi_exec_machine *mach,
3647 const struct tgsi_full_instruction *inst,
3648 micro_dop op)
3649 {
3650 union tgsi_double_channel src[3];
3651 union tgsi_double_channel dst;
3652
3653 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3654 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3655 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3656 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3657 op(&dst, src);
3658 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3659 }
3660 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3661 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3662 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3663 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3664 op(&dst, src);
3665 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3666 }
3667 }
3668
3669 static void
3670 exec_dldexp(struct tgsi_exec_machine *mach,
3671 const struct tgsi_full_instruction *inst)
3672 {
3673 union tgsi_double_channel src0;
3674 union tgsi_exec_channel src1;
3675 union tgsi_double_channel dst;
3676 int wmask;
3677
3678 wmask = inst->Dst[0].Register.WriteMask;
3679 if (wmask & TGSI_WRITEMASK_XY) {
3680 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3681 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3682 micro_dldexp(&dst, &src0, &src1);
3683 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3684 }
3685
3686 if (wmask & TGSI_WRITEMASK_ZW) {
3687 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3688 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3689 micro_dldexp(&dst, &src0, &src1);
3690 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3691 }
3692 }
3693
3694 static void
3695 exec_dfracexp(struct tgsi_exec_machine *mach,
3696 const struct tgsi_full_instruction *inst)
3697 {
3698 union tgsi_double_channel src;
3699 union tgsi_double_channel dst;
3700 union tgsi_exec_channel dst_exp;
3701
3702 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3703 micro_dfracexp(&dst, &dst_exp, &src);
3704 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)
3705 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3706 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)
3707 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3708 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3709 if (inst->Dst[1].Register.WriteMask & (1 << chan))
3710 store_dest(mach, &dst_exp, &inst->Dst[1], inst, chan, TGSI_EXEC_DATA_INT);
3711 }
3712 }
3713
3714 static void
3715 exec_arg0_64_arg1_32(struct tgsi_exec_machine *mach,
3716 const struct tgsi_full_instruction *inst,
3717 micro_dop_sop op)
3718 {
3719 union tgsi_double_channel src0;
3720 union tgsi_exec_channel src1;
3721 union tgsi_double_channel dst;
3722 int wmask;
3723
3724 wmask = inst->Dst[0].Register.WriteMask;
3725 if (wmask & TGSI_WRITEMASK_XY) {
3726 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3727 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3728 op(&dst, &src0, &src1);
3729 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3730 }
3731
3732 if (wmask & TGSI_WRITEMASK_ZW) {
3733 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3734 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3735 op(&dst, &src0, &src1);
3736 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3737 }
3738 }
3739
3740 static int
3741 get_image_coord_dim(unsigned tgsi_tex)
3742 {
3743 int dim;
3744 switch (tgsi_tex) {
3745 case TGSI_TEXTURE_BUFFER:
3746 case TGSI_TEXTURE_1D:
3747 dim = 1;
3748 break;
3749 case TGSI_TEXTURE_2D:
3750 case TGSI_TEXTURE_RECT:
3751 case TGSI_TEXTURE_1D_ARRAY:
3752 case TGSI_TEXTURE_2D_MSAA:
3753 dim = 2;
3754 break;
3755 case TGSI_TEXTURE_3D:
3756 case TGSI_TEXTURE_CUBE:
3757 case TGSI_TEXTURE_2D_ARRAY:
3758 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3759 case TGSI_TEXTURE_CUBE_ARRAY:
3760 dim = 3;
3761 break;
3762 default:
3763 assert(!"unknown texture target");
3764 dim = 0;
3765 break;
3766 }
3767
3768 return dim;
3769 }
3770
3771 static int
3772 get_image_coord_sample(unsigned tgsi_tex)
3773 {
3774 int sample = 0;
3775 switch (tgsi_tex) {
3776 case TGSI_TEXTURE_2D_MSAA:
3777 sample = 3;
3778 break;
3779 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3780 sample = 4;
3781 break;
3782 default:
3783 break;
3784 }
3785 return sample;
3786 }
3787
3788 static void
3789 exec_load_img(struct tgsi_exec_machine *mach,
3790 const struct tgsi_full_instruction *inst)
3791 {
3792 union tgsi_exec_channel r[4], sample_r;
3793 uint unit;
3794 int sample;
3795 int i, j;
3796 int dim;
3797 uint chan;
3798 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3799 struct tgsi_image_params params;
3800 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3801
3802 unit = fetch_sampler_unit(mach, inst, 0);
3803 dim = get_image_coord_dim(inst->Memory.Texture);
3804 sample = get_image_coord_sample(inst->Memory.Texture);
3805 assert(dim <= 3);
3806
3807 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3808 params.unit = unit;
3809 params.tgsi_tex_instr = inst->Memory.Texture;
3810 params.format = inst->Memory.Format;
3811
3812 for (i = 0; i < dim; i++) {
3813 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3814 }
3815
3816 if (sample)
3817 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3818
3819 mach->Image->load(mach->Image, &params,
3820 r[0].i, r[1].i, r[2].i, sample_r.i,
3821 rgba);
3822 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3823 r[0].f[j] = rgba[0][j];
3824 r[1].f[j] = rgba[1][j];
3825 r[2].f[j] = rgba[2][j];
3826 r[3].f[j] = rgba[3][j];
3827 }
3828 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3829 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3830 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3831 }
3832 }
3833 }
3834
3835 static void
3836 exec_load_buf(struct tgsi_exec_machine *mach,
3837 const struct tgsi_full_instruction *inst)
3838 {
3839 union tgsi_exec_channel r[4];
3840 uint unit;
3841 int j;
3842 uint chan;
3843 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3844 struct tgsi_buffer_params params;
3845 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3846
3847 unit = fetch_sampler_unit(mach, inst, 0);
3848
3849 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3850 params.unit = unit;
3851 IFETCH(&r[0], 1, TGSI_CHAN_X);
3852
3853 mach->Buffer->load(mach->Buffer, &params,
3854 r[0].i, rgba);
3855 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3856 r[0].f[j] = rgba[0][j];
3857 r[1].f[j] = rgba[1][j];
3858 r[2].f[j] = rgba[2][j];
3859 r[3].f[j] = rgba[3][j];
3860 }
3861 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3862 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3863 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3864 }
3865 }
3866 }
3867
3868 static void
3869 exec_load_mem(struct tgsi_exec_machine *mach,
3870 const struct tgsi_full_instruction *inst)
3871 {
3872 union tgsi_exec_channel r[4];
3873 uint chan;
3874 char *ptr = mach->LocalMem;
3875 uint32_t offset;
3876 int j;
3877
3878 IFETCH(&r[0], 1, TGSI_CHAN_X);
3879 if (r[0].u[0] >= mach->LocalMemSize)
3880 return;
3881
3882 offset = r[0].u[0];
3883 ptr += offset;
3884
3885 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3886 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3887 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3888 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
3889 }
3890 }
3891 }
3892
3893 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3894 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3895 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3896 }
3897 }
3898 }
3899
3900 static void
3901 exec_load(struct tgsi_exec_machine *mach,
3902 const struct tgsi_full_instruction *inst)
3903 {
3904 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3905 exec_load_img(mach, inst);
3906 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
3907 exec_load_buf(mach, inst);
3908 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
3909 exec_load_mem(mach, inst);
3910 }
3911
3912 static void
3913 exec_store_img(struct tgsi_exec_machine *mach,
3914 const struct tgsi_full_instruction *inst)
3915 {
3916 union tgsi_exec_channel r[3], sample_r;
3917 union tgsi_exec_channel value[4];
3918 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3919 struct tgsi_image_params params;
3920 int dim;
3921 int sample;
3922 int i, j;
3923 uint unit;
3924 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3925 unit = inst->Dst[0].Register.Index;
3926 dim = get_image_coord_dim(inst->Memory.Texture);
3927 sample = get_image_coord_sample(inst->Memory.Texture);
3928 assert(dim <= 3);
3929
3930 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3931 params.unit = unit;
3932 params.tgsi_tex_instr = inst->Memory.Texture;
3933 params.format = inst->Memory.Format;
3934
3935 for (i = 0; i < dim; i++) {
3936 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3937 }
3938
3939 for (i = 0; i < 4; i++) {
3940 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3941 }
3942 if (sample)
3943 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3944
3945 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3946 rgba[0][j] = value[0].f[j];
3947 rgba[1][j] = value[1].f[j];
3948 rgba[2][j] = value[2].f[j];
3949 rgba[3][j] = value[3].f[j];
3950 }
3951
3952 mach->Image->store(mach->Image, &params,
3953 r[0].i, r[1].i, r[2].i, sample_r.i,
3954 rgba);
3955 }
3956
3957 static void
3958 exec_store_buf(struct tgsi_exec_machine *mach,
3959 const struct tgsi_full_instruction *inst)
3960 {
3961 union tgsi_exec_channel r[3];
3962 union tgsi_exec_channel value[4];
3963 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3964 struct tgsi_buffer_params params;
3965 int i, j;
3966 uint unit;
3967 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3968
3969 unit = inst->Dst[0].Register.Index;
3970
3971 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3972 params.unit = unit;
3973 params.writemask = inst->Dst[0].Register.WriteMask;
3974
3975 IFETCH(&r[0], 0, TGSI_CHAN_X);
3976 for (i = 0; i < 4; i++) {
3977 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3978 }
3979
3980 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3981 rgba[0][j] = value[0].f[j];
3982 rgba[1][j] = value[1].f[j];
3983 rgba[2][j] = value[2].f[j];
3984 rgba[3][j] = value[3].f[j];
3985 }
3986
3987 mach->Buffer->store(mach->Buffer, &params,
3988 r[0].i,
3989 rgba);
3990 }
3991
3992 static void
3993 exec_store_mem(struct tgsi_exec_machine *mach,
3994 const struct tgsi_full_instruction *inst)
3995 {
3996 union tgsi_exec_channel r[3];
3997 union tgsi_exec_channel value[4];
3998 uint i, chan;
3999 char *ptr = mach->LocalMem;
4000 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4001 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4002
4003 IFETCH(&r[0], 0, TGSI_CHAN_X);
4004
4005 for (i = 0; i < 4; i++) {
4006 FETCH(&value[i], 1, TGSI_CHAN_X + i);
4007 }
4008
4009 if (r[0].u[0] >= mach->LocalMemSize)
4010 return;
4011 ptr += r[0].u[0];
4012
4013 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4014 if (execmask & (1 << i)) {
4015 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4016 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4017 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
4018 }
4019 }
4020 }
4021 }
4022 }
4023
4024 static void
4025 exec_store(struct tgsi_exec_machine *mach,
4026 const struct tgsi_full_instruction *inst)
4027 {
4028 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4029 exec_store_img(mach, inst);
4030 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4031 exec_store_buf(mach, inst);
4032 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4033 exec_store_mem(mach, inst);
4034 }
4035
4036 static void
4037 exec_atomop_img(struct tgsi_exec_machine *mach,
4038 const struct tgsi_full_instruction *inst)
4039 {
4040 union tgsi_exec_channel r[4], sample_r;
4041 union tgsi_exec_channel value[4], value2[4];
4042 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4043 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4044 struct tgsi_image_params params;
4045 int dim;
4046 int sample;
4047 int i, j;
4048 uint unit, chan;
4049 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4050 unit = fetch_sampler_unit(mach, inst, 0);
4051 dim = get_image_coord_dim(inst->Memory.Texture);
4052 sample = get_image_coord_sample(inst->Memory.Texture);
4053 assert(dim <= 3);
4054
4055 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4056 params.unit = unit;
4057 params.tgsi_tex_instr = inst->Memory.Texture;
4058 params.format = inst->Memory.Format;
4059
4060 for (i = 0; i < dim; i++) {
4061 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4062 }
4063
4064 for (i = 0; i < 4; i++) {
4065 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4066 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4067 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4068 }
4069 if (sample)
4070 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4071
4072 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4073 rgba[0][j] = value[0].f[j];
4074 rgba[1][j] = value[1].f[j];
4075 rgba[2][j] = value[2].f[j];
4076 rgba[3][j] = value[3].f[j];
4077 }
4078 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4079 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4080 rgba2[0][j] = value2[0].f[j];
4081 rgba2[1][j] = value2[1].f[j];
4082 rgba2[2][j] = value2[2].f[j];
4083 rgba2[3][j] = value2[3].f[j];
4084 }
4085 }
4086
4087 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4088 r[0].i, r[1].i, r[2].i, sample_r.i,
4089 rgba, rgba2);
4090
4091 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4092 r[0].f[j] = rgba[0][j];
4093 r[1].f[j] = rgba[1][j];
4094 r[2].f[j] = rgba[2][j];
4095 r[3].f[j] = rgba[3][j];
4096 }
4097 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4098 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4099 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4100 }
4101 }
4102 }
4103
4104 static void
4105 exec_atomop_buf(struct tgsi_exec_machine *mach,
4106 const struct tgsi_full_instruction *inst)
4107 {
4108 union tgsi_exec_channel r[4];
4109 union tgsi_exec_channel value[4], value2[4];
4110 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4111 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4112 struct tgsi_buffer_params params;
4113 int i, j;
4114 uint unit, chan;
4115 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4116
4117 unit = fetch_sampler_unit(mach, inst, 0);
4118
4119 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4120 params.unit = unit;
4121 params.writemask = inst->Dst[0].Register.WriteMask;
4122
4123 IFETCH(&r[0], 1, TGSI_CHAN_X);
4124
4125 for (i = 0; i < 4; i++) {
4126 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4127 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4128 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4129 }
4130
4131 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4132 rgba[0][j] = value[0].f[j];
4133 rgba[1][j] = value[1].f[j];
4134 rgba[2][j] = value[2].f[j];
4135 rgba[3][j] = value[3].f[j];
4136 }
4137 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4138 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4139 rgba2[0][j] = value2[0].f[j];
4140 rgba2[1][j] = value2[1].f[j];
4141 rgba2[2][j] = value2[2].f[j];
4142 rgba2[3][j] = value2[3].f[j];
4143 }
4144 }
4145
4146 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4147 r[0].i,
4148 rgba, rgba2);
4149
4150 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4151 r[0].f[j] = rgba[0][j];
4152 r[1].f[j] = rgba[1][j];
4153 r[2].f[j] = rgba[2][j];
4154 r[3].f[j] = rgba[3][j];
4155 }
4156 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4157 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4158 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4159 }
4160 }
4161 }
4162
4163 static void
4164 exec_atomop_mem(struct tgsi_exec_machine *mach,
4165 const struct tgsi_full_instruction *inst)
4166 {
4167 union tgsi_exec_channel r[4];
4168 union tgsi_exec_channel value[4], value2[4];
4169 char *ptr = mach->LocalMem;
4170 uint32_t val;
4171 uint chan, i;
4172 uint32_t offset;
4173 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4174 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4175 IFETCH(&r[0], 1, TGSI_CHAN_X);
4176
4177 if (r[0].u[0] >= mach->LocalMemSize)
4178 return;
4179
4180 offset = r[0].u[0];
4181 ptr += offset;
4182 for (i = 0; i < 4; i++) {
4183 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4184 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4185 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4186 }
4187
4188 memcpy(&r[0].u[0], ptr, 4);
4189 val = r[0].u[0];
4190 switch (inst->Instruction.Opcode) {
4191 case TGSI_OPCODE_ATOMUADD:
4192 val += value[0].u[0];
4193 break;
4194 case TGSI_OPCODE_ATOMXOR:
4195 val ^= value[0].u[0];
4196 break;
4197 case TGSI_OPCODE_ATOMOR:
4198 val |= value[0].u[0];
4199 break;
4200 case TGSI_OPCODE_ATOMAND:
4201 val &= value[0].u[0];
4202 break;
4203 case TGSI_OPCODE_ATOMUMIN:
4204 val = MIN2(val, value[0].u[0]);
4205 break;
4206 case TGSI_OPCODE_ATOMUMAX:
4207 val = MAX2(val, value[0].u[0]);
4208 break;
4209 case TGSI_OPCODE_ATOMIMIN:
4210 val = MIN2(r[0].i[0], value[0].i[0]);
4211 break;
4212 case TGSI_OPCODE_ATOMIMAX:
4213 val = MAX2(r[0].i[0], value[0].i[0]);
4214 break;
4215 case TGSI_OPCODE_ATOMXCHG:
4216 val = value[0].i[0];
4217 break;
4218 case TGSI_OPCODE_ATOMCAS:
4219 if (val == value[0].u[0])
4220 val = value2[0].u[0];
4221 break;
4222 default:
4223 break;
4224 }
4225 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4226 if (execmask & (1 << i))
4227 memcpy(ptr, &val, 4);
4228
4229 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4230 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4231 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4232 }
4233 }
4234 }
4235
4236 static void
4237 exec_atomop(struct tgsi_exec_machine *mach,
4238 const struct tgsi_full_instruction *inst)
4239 {
4240 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4241 exec_atomop_img(mach, inst);
4242 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4243 exec_atomop_buf(mach, inst);
4244 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4245 exec_atomop_mem(mach, inst);
4246 }
4247
4248 static void
4249 exec_resq_img(struct tgsi_exec_machine *mach,
4250 const struct tgsi_full_instruction *inst)
4251 {
4252 int result[4];
4253 union tgsi_exec_channel r[4];
4254 uint unit;
4255 int i, chan, j;
4256 struct tgsi_image_params params;
4257 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4258
4259 unit = fetch_sampler_unit(mach, inst, 0);
4260
4261 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4262 params.unit = unit;
4263 params.tgsi_tex_instr = inst->Memory.Texture;
4264 params.format = inst->Memory.Format;
4265
4266 mach->Image->get_dims(mach->Image, &params, result);
4267
4268 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4269 for (j = 0; j < 4; j++) {
4270 r[j].i[i] = result[j];
4271 }
4272 }
4273
4274 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4275 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4276 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4277 TGSI_EXEC_DATA_INT);
4278 }
4279 }
4280 }
4281
4282 static void
4283 exec_resq_buf(struct tgsi_exec_machine *mach,
4284 const struct tgsi_full_instruction *inst)
4285 {
4286 int result;
4287 union tgsi_exec_channel r[4];
4288 uint unit;
4289 int i, chan;
4290 struct tgsi_buffer_params params;
4291 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4292
4293 unit = fetch_sampler_unit(mach, inst, 0);
4294
4295 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4296 params.unit = unit;
4297
4298 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4299
4300 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4301 r[0].i[i] = result;
4302 }
4303
4304 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4305 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4306 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4307 TGSI_EXEC_DATA_INT);
4308 }
4309 }
4310 }
4311
4312 static void
4313 exec_resq(struct tgsi_exec_machine *mach,
4314 const struct tgsi_full_instruction *inst)
4315 {
4316 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4317 exec_resq_img(mach, inst);
4318 else
4319 exec_resq_buf(mach, inst);
4320 }
4321
4322 static void
4323 micro_f2u64(union tgsi_double_channel *dst,
4324 const union tgsi_exec_channel *src)
4325 {
4326 dst->u64[0] = (uint64_t)src->f[0];
4327 dst->u64[1] = (uint64_t)src->f[1];
4328 dst->u64[2] = (uint64_t)src->f[2];
4329 dst->u64[3] = (uint64_t)src->f[3];
4330 }
4331
4332 static void
4333 micro_f2i64(union tgsi_double_channel *dst,
4334 const union tgsi_exec_channel *src)
4335 {
4336 dst->i64[0] = (int64_t)src->f[0];
4337 dst->i64[1] = (int64_t)src->f[1];
4338 dst->i64[2] = (int64_t)src->f[2];
4339 dst->i64[3] = (int64_t)src->f[3];
4340 }
4341
4342 static void
4343 micro_u2i64(union tgsi_double_channel *dst,
4344 const union tgsi_exec_channel *src)
4345 {
4346 dst->u64[0] = (uint64_t)src->u[0];
4347 dst->u64[1] = (uint64_t)src->u[1];
4348 dst->u64[2] = (uint64_t)src->u[2];
4349 dst->u64[3] = (uint64_t)src->u[3];
4350 }
4351
4352 static void
4353 micro_i2i64(union tgsi_double_channel *dst,
4354 const union tgsi_exec_channel *src)
4355 {
4356 dst->i64[0] = (int64_t)src->i[0];
4357 dst->i64[1] = (int64_t)src->i[1];
4358 dst->i64[2] = (int64_t)src->i[2];
4359 dst->i64[3] = (int64_t)src->i[3];
4360 }
4361
4362 static void
4363 micro_d2u64(union tgsi_double_channel *dst,
4364 const union tgsi_double_channel *src)
4365 {
4366 dst->u64[0] = (uint64_t)src->d[0];
4367 dst->u64[1] = (uint64_t)src->d[1];
4368 dst->u64[2] = (uint64_t)src->d[2];
4369 dst->u64[3] = (uint64_t)src->d[3];
4370 }
4371
4372 static void
4373 micro_d2i64(union tgsi_double_channel *dst,
4374 const union tgsi_double_channel *src)
4375 {
4376 dst->i64[0] = (int64_t)src->d[0];
4377 dst->i64[1] = (int64_t)src->d[1];
4378 dst->i64[2] = (int64_t)src->d[2];
4379 dst->i64[3] = (int64_t)src->d[3];
4380 }
4381
4382 static void
4383 micro_u642d(union tgsi_double_channel *dst,
4384 const union tgsi_double_channel *src)
4385 {
4386 dst->d[0] = (double)src->u64[0];
4387 dst->d[1] = (double)src->u64[1];
4388 dst->d[2] = (double)src->u64[2];
4389 dst->d[3] = (double)src->u64[3];
4390 }
4391
4392 static void
4393 micro_i642d(union tgsi_double_channel *dst,
4394 const union tgsi_double_channel *src)
4395 {
4396 dst->d[0] = (double)src->i64[0];
4397 dst->d[1] = (double)src->i64[1];
4398 dst->d[2] = (double)src->i64[2];
4399 dst->d[3] = (double)src->i64[3];
4400 }
4401
4402 static void
4403 micro_u642f(union tgsi_exec_channel *dst,
4404 const union tgsi_double_channel *src)
4405 {
4406 dst->f[0] = (float)src->u64[0];
4407 dst->f[1] = (float)src->u64[1];
4408 dst->f[2] = (float)src->u64[2];
4409 dst->f[3] = (float)src->u64[3];
4410 }
4411
4412 static void
4413 micro_i642f(union tgsi_exec_channel *dst,
4414 const union tgsi_double_channel *src)
4415 {
4416 dst->f[0] = (float)src->i64[0];
4417 dst->f[1] = (float)src->i64[1];
4418 dst->f[2] = (float)src->i64[2];
4419 dst->f[3] = (float)src->i64[3];
4420 }
4421
4422 static void
4423 exec_t_2_64(struct tgsi_exec_machine *mach,
4424 const struct tgsi_full_instruction *inst,
4425 micro_dop_s op,
4426 enum tgsi_exec_datatype src_datatype)
4427 {
4428 union tgsi_exec_channel src;
4429 union tgsi_double_channel dst;
4430
4431 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
4432 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
4433 op(&dst, &src);
4434 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
4435 }
4436 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
4437 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, src_datatype);
4438 op(&dst, &src);
4439 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
4440 }
4441 }
4442
4443 static void
4444 exec_64_2_t(struct tgsi_exec_machine *mach,
4445 const struct tgsi_full_instruction *inst,
4446 micro_sop_d op,
4447 enum tgsi_exec_datatype dst_datatype)
4448 {
4449 union tgsi_double_channel src;
4450 union tgsi_exec_channel dst;
4451 int wm = inst->Dst[0].Register.WriteMask;
4452 int i;
4453 int bit;
4454 for (i = 0; i < 2; i++) {
4455 bit = ffs(wm);
4456 if (bit) {
4457 wm &= ~(1 << (bit - 1));
4458 if (i == 0)
4459 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
4460 else
4461 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
4462 op(&dst, &src);
4463 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, dst_datatype);
4464 }
4465 }
4466 }
4467
4468 static void
4469 micro_i2f(union tgsi_exec_channel *dst,
4470 const union tgsi_exec_channel *src)
4471 {
4472 dst->f[0] = (float)src->i[0];
4473 dst->f[1] = (float)src->i[1];
4474 dst->f[2] = (float)src->i[2];
4475 dst->f[3] = (float)src->i[3];
4476 }
4477
4478 static void
4479 micro_not(union tgsi_exec_channel *dst,
4480 const union tgsi_exec_channel *src)
4481 {
4482 dst->u[0] = ~src->u[0];
4483 dst->u[1] = ~src->u[1];
4484 dst->u[2] = ~src->u[2];
4485 dst->u[3] = ~src->u[3];
4486 }
4487
4488 static void
4489 micro_shl(union tgsi_exec_channel *dst,
4490 const union tgsi_exec_channel *src0,
4491 const union tgsi_exec_channel *src1)
4492 {
4493 unsigned masked_count;
4494 masked_count = src1->u[0] & 0x1f;
4495 dst->u[0] = src0->u[0] << masked_count;
4496 masked_count = src1->u[1] & 0x1f;
4497 dst->u[1] = src0->u[1] << masked_count;
4498 masked_count = src1->u[2] & 0x1f;
4499 dst->u[2] = src0->u[2] << masked_count;
4500 masked_count = src1->u[3] & 0x1f;
4501 dst->u[3] = src0->u[3] << masked_count;
4502 }
4503
4504 static void
4505 micro_and(union tgsi_exec_channel *dst,
4506 const union tgsi_exec_channel *src0,
4507 const union tgsi_exec_channel *src1)
4508 {
4509 dst->u[0] = src0->u[0] & src1->u[0];
4510 dst->u[1] = src0->u[1] & src1->u[1];
4511 dst->u[2] = src0->u[2] & src1->u[2];
4512 dst->u[3] = src0->u[3] & src1->u[3];
4513 }
4514
4515 static void
4516 micro_or(union tgsi_exec_channel *dst,
4517 const union tgsi_exec_channel *src0,
4518 const union tgsi_exec_channel *src1)
4519 {
4520 dst->u[0] = src0->u[0] | src1->u[0];
4521 dst->u[1] = src0->u[1] | src1->u[1];
4522 dst->u[2] = src0->u[2] | src1->u[2];
4523 dst->u[3] = src0->u[3] | src1->u[3];
4524 }
4525
4526 static void
4527 micro_xor(union tgsi_exec_channel *dst,
4528 const union tgsi_exec_channel *src0,
4529 const union tgsi_exec_channel *src1)
4530 {
4531 dst->u[0] = src0->u[0] ^ src1->u[0];
4532 dst->u[1] = src0->u[1] ^ src1->u[1];
4533 dst->u[2] = src0->u[2] ^ src1->u[2];
4534 dst->u[3] = src0->u[3] ^ src1->u[3];
4535 }
4536
4537 static void
4538 micro_mod(union tgsi_exec_channel *dst,
4539 const union tgsi_exec_channel *src0,
4540 const union tgsi_exec_channel *src1)
4541 {
4542 dst->i[0] = src1->i[0] ? src0->i[0] % src1->i[0] : ~0;
4543 dst->i[1] = src1->i[1] ? src0->i[1] % src1->i[1] : ~0;
4544 dst->i[2] = src1->i[2] ? src0->i[2] % src1->i[2] : ~0;
4545 dst->i[3] = src1->i[3] ? src0->i[3] % src1->i[3] : ~0;
4546 }
4547
4548 static void
4549 micro_f2i(union tgsi_exec_channel *dst,
4550 const union tgsi_exec_channel *src)
4551 {
4552 dst->i[0] = (int)src->f[0];
4553 dst->i[1] = (int)src->f[1];
4554 dst->i[2] = (int)src->f[2];
4555 dst->i[3] = (int)src->f[3];
4556 }
4557
4558 static void
4559 micro_fseq(union tgsi_exec_channel *dst,
4560 const union tgsi_exec_channel *src0,
4561 const union tgsi_exec_channel *src1)
4562 {
4563 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4564 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4565 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4566 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4567 }
4568
4569 static void
4570 micro_fsge(union tgsi_exec_channel *dst,
4571 const union tgsi_exec_channel *src0,
4572 const union tgsi_exec_channel *src1)
4573 {
4574 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4575 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4576 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4577 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4578 }
4579
4580 static void
4581 micro_fslt(union tgsi_exec_channel *dst,
4582 const union tgsi_exec_channel *src0,
4583 const union tgsi_exec_channel *src1)
4584 {
4585 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4586 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4587 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4588 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4589 }
4590
4591 static void
4592 micro_fsne(union tgsi_exec_channel *dst,
4593 const union tgsi_exec_channel *src0,
4594 const union tgsi_exec_channel *src1)
4595 {
4596 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4597 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4598 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4599 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4600 }
4601
4602 static void
4603 micro_idiv(union tgsi_exec_channel *dst,
4604 const union tgsi_exec_channel *src0,
4605 const union tgsi_exec_channel *src1)
4606 {
4607 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4608 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4609 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4610 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4611 }
4612
4613 static void
4614 micro_imax(union tgsi_exec_channel *dst,
4615 const union tgsi_exec_channel *src0,
4616 const union tgsi_exec_channel *src1)
4617 {
4618 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4619 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4620 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4621 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4622 }
4623
4624 static void
4625 micro_imin(union tgsi_exec_channel *dst,
4626 const union tgsi_exec_channel *src0,
4627 const union tgsi_exec_channel *src1)
4628 {
4629 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4630 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4631 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4632 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4633 }
4634
4635 static void
4636 micro_isge(union tgsi_exec_channel *dst,
4637 const union tgsi_exec_channel *src0,
4638 const union tgsi_exec_channel *src1)
4639 {
4640 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4641 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4642 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4643 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4644 }
4645
4646 static void
4647 micro_ishr(union tgsi_exec_channel *dst,
4648 const union tgsi_exec_channel *src0,
4649 const union tgsi_exec_channel *src1)
4650 {
4651 unsigned masked_count;
4652 masked_count = src1->i[0] & 0x1f;
4653 dst->i[0] = src0->i[0] >> masked_count;
4654 masked_count = src1->i[1] & 0x1f;
4655 dst->i[1] = src0->i[1] >> masked_count;
4656 masked_count = src1->i[2] & 0x1f;
4657 dst->i[2] = src0->i[2] >> masked_count;
4658 masked_count = src1->i[3] & 0x1f;
4659 dst->i[3] = src0->i[3] >> masked_count;
4660 }
4661
4662 static void
4663 micro_islt(union tgsi_exec_channel *dst,
4664 const union tgsi_exec_channel *src0,
4665 const union tgsi_exec_channel *src1)
4666 {
4667 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4668 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4669 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4670 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4671 }
4672
4673 static void
4674 micro_f2u(union tgsi_exec_channel *dst,
4675 const union tgsi_exec_channel *src)
4676 {
4677 dst->u[0] = (uint)src->f[0];
4678 dst->u[1] = (uint)src->f[1];
4679 dst->u[2] = (uint)src->f[2];
4680 dst->u[3] = (uint)src->f[3];
4681 }
4682
4683 static void
4684 micro_u2f(union tgsi_exec_channel *dst,
4685 const union tgsi_exec_channel *src)
4686 {
4687 dst->f[0] = (float)src->u[0];
4688 dst->f[1] = (float)src->u[1];
4689 dst->f[2] = (float)src->u[2];
4690 dst->f[3] = (float)src->u[3];
4691 }
4692
4693 static void
4694 micro_uadd(union tgsi_exec_channel *dst,
4695 const union tgsi_exec_channel *src0,
4696 const union tgsi_exec_channel *src1)
4697 {
4698 dst->u[0] = src0->u[0] + src1->u[0];
4699 dst->u[1] = src0->u[1] + src1->u[1];
4700 dst->u[2] = src0->u[2] + src1->u[2];
4701 dst->u[3] = src0->u[3] + src1->u[3];
4702 }
4703
4704 static void
4705 micro_udiv(union tgsi_exec_channel *dst,
4706 const union tgsi_exec_channel *src0,
4707 const union tgsi_exec_channel *src1)
4708 {
4709 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4710 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4711 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4712 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4713 }
4714
4715 static void
4716 micro_umad(union tgsi_exec_channel *dst,
4717 const union tgsi_exec_channel *src0,
4718 const union tgsi_exec_channel *src1,
4719 const union tgsi_exec_channel *src2)
4720 {
4721 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4722 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4723 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4724 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4725 }
4726
4727 static void
4728 micro_umax(union tgsi_exec_channel *dst,
4729 const union tgsi_exec_channel *src0,
4730 const union tgsi_exec_channel *src1)
4731 {
4732 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4733 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4734 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4735 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4736 }
4737
4738 static void
4739 micro_umin(union tgsi_exec_channel *dst,
4740 const union tgsi_exec_channel *src0,
4741 const union tgsi_exec_channel *src1)
4742 {
4743 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4744 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4745 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4746 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4747 }
4748
4749 static void
4750 micro_umod(union tgsi_exec_channel *dst,
4751 const union tgsi_exec_channel *src0,
4752 const union tgsi_exec_channel *src1)
4753 {
4754 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4755 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4756 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4757 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4758 }
4759
4760 static void
4761 micro_umul(union tgsi_exec_channel *dst,
4762 const union tgsi_exec_channel *src0,
4763 const union tgsi_exec_channel *src1)
4764 {
4765 dst->u[0] = src0->u[0] * src1->u[0];
4766 dst->u[1] = src0->u[1] * src1->u[1];
4767 dst->u[2] = src0->u[2] * src1->u[2];
4768 dst->u[3] = src0->u[3] * src1->u[3];
4769 }
4770
4771 static void
4772 micro_imul_hi(union tgsi_exec_channel *dst,
4773 const union tgsi_exec_channel *src0,
4774 const union tgsi_exec_channel *src1)
4775 {
4776 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4777 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4778 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4779 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4780 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4781 #undef I64M
4782 }
4783
4784 static void
4785 micro_umul_hi(union tgsi_exec_channel *dst,
4786 const union tgsi_exec_channel *src0,
4787 const union tgsi_exec_channel *src1)
4788 {
4789 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4790 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4791 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4792 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4793 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4794 #undef U64M
4795 }
4796
4797 static void
4798 micro_useq(union tgsi_exec_channel *dst,
4799 const union tgsi_exec_channel *src0,
4800 const union tgsi_exec_channel *src1)
4801 {
4802 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4803 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4804 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4805 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4806 }
4807
4808 static void
4809 micro_usge(union tgsi_exec_channel *dst,
4810 const union tgsi_exec_channel *src0,
4811 const union tgsi_exec_channel *src1)
4812 {
4813 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4814 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4815 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4816 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4817 }
4818
4819 static void
4820 micro_ushr(union tgsi_exec_channel *dst,
4821 const union tgsi_exec_channel *src0,
4822 const union tgsi_exec_channel *src1)
4823 {
4824 unsigned masked_count;
4825 masked_count = src1->u[0] & 0x1f;
4826 dst->u[0] = src0->u[0] >> masked_count;
4827 masked_count = src1->u[1] & 0x1f;
4828 dst->u[1] = src0->u[1] >> masked_count;
4829 masked_count = src1->u[2] & 0x1f;
4830 dst->u[2] = src0->u[2] >> masked_count;
4831 masked_count = src1->u[3] & 0x1f;
4832 dst->u[3] = src0->u[3] >> masked_count;
4833 }
4834
4835 static void
4836 micro_uslt(union tgsi_exec_channel *dst,
4837 const union tgsi_exec_channel *src0,
4838 const union tgsi_exec_channel *src1)
4839 {
4840 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4841 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4842 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4843 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4844 }
4845
4846 static void
4847 micro_usne(union tgsi_exec_channel *dst,
4848 const union tgsi_exec_channel *src0,
4849 const union tgsi_exec_channel *src1)
4850 {
4851 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4852 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4853 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4854 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4855 }
4856
4857 static void
4858 micro_uarl(union tgsi_exec_channel *dst,
4859 const union tgsi_exec_channel *src)
4860 {
4861 dst->i[0] = src->u[0];
4862 dst->i[1] = src->u[1];
4863 dst->i[2] = src->u[2];
4864 dst->i[3] = src->u[3];
4865 }
4866
4867 /**
4868 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4869 */
4870 static void
4871 micro_ibfe(union tgsi_exec_channel *dst,
4872 const union tgsi_exec_channel *src0,
4873 const union tgsi_exec_channel *src1,
4874 const union tgsi_exec_channel *src2)
4875 {
4876 int i;
4877 for (i = 0; i < 4; i++) {
4878 int width = src2->i[i] & 0x1f;
4879 int offset = src1->i[i] & 0x1f;
4880 if (width == 0)
4881 dst->i[i] = 0;
4882 else if (width + offset < 32)
4883 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4884 else
4885 dst->i[i] = src0->i[i] >> offset;
4886 }
4887 }
4888
4889 /**
4890 * Unsigned bitfield extract
4891 */
4892 static void
4893 micro_ubfe(union tgsi_exec_channel *dst,
4894 const union tgsi_exec_channel *src0,
4895 const union tgsi_exec_channel *src1,
4896 const union tgsi_exec_channel *src2)
4897 {
4898 int i;
4899 for (i = 0; i < 4; i++) {
4900 int width = src2->u[i] & 0x1f;
4901 int offset = src1->u[i] & 0x1f;
4902 if (width == 0)
4903 dst->u[i] = 0;
4904 else if (width + offset < 32)
4905 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4906 else
4907 dst->u[i] = src0->u[i] >> offset;
4908 }
4909 }
4910
4911 /**
4912 * Bitfield insert: copy low bits from src1 into a region of src0.
4913 */
4914 static void
4915 micro_bfi(union tgsi_exec_channel *dst,
4916 const union tgsi_exec_channel *src0,
4917 const union tgsi_exec_channel *src1,
4918 const union tgsi_exec_channel *src2,
4919 const union tgsi_exec_channel *src3)
4920 {
4921 int i;
4922 for (i = 0; i < 4; i++) {
4923 int width = src3->u[i] & 0x1f;
4924 int offset = src2->u[i] & 0x1f;
4925 int bitmask = ((1 << width) - 1) << offset;
4926 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4927 }
4928 }
4929
4930 static void
4931 micro_brev(union tgsi_exec_channel *dst,
4932 const union tgsi_exec_channel *src)
4933 {
4934 dst->u[0] = util_bitreverse(src->u[0]);
4935 dst->u[1] = util_bitreverse(src->u[1]);
4936 dst->u[2] = util_bitreverse(src->u[2]);
4937 dst->u[3] = util_bitreverse(src->u[3]);
4938 }
4939
4940 static void
4941 micro_popc(union tgsi_exec_channel *dst,
4942 const union tgsi_exec_channel *src)
4943 {
4944 dst->u[0] = util_bitcount(src->u[0]);
4945 dst->u[1] = util_bitcount(src->u[1]);
4946 dst->u[2] = util_bitcount(src->u[2]);
4947 dst->u[3] = util_bitcount(src->u[3]);
4948 }
4949
4950 static void
4951 micro_lsb(union tgsi_exec_channel *dst,
4952 const union tgsi_exec_channel *src)
4953 {
4954 dst->i[0] = ffs(src->u[0]) - 1;
4955 dst->i[1] = ffs(src->u[1]) - 1;
4956 dst->i[2] = ffs(src->u[2]) - 1;
4957 dst->i[3] = ffs(src->u[3]) - 1;
4958 }
4959
4960 static void
4961 micro_imsb(union tgsi_exec_channel *dst,
4962 const union tgsi_exec_channel *src)
4963 {
4964 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4965 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4966 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4967 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4968 }
4969
4970 static void
4971 micro_umsb(union tgsi_exec_channel *dst,
4972 const union tgsi_exec_channel *src)
4973 {
4974 dst->i[0] = util_last_bit(src->u[0]) - 1;
4975 dst->i[1] = util_last_bit(src->u[1]) - 1;
4976 dst->i[2] = util_last_bit(src->u[2]) - 1;
4977 dst->i[3] = util_last_bit(src->u[3]) - 1;
4978 }
4979
4980 /**
4981 * Execute a TGSI instruction.
4982 * Returns TRUE if a barrier instruction is hit,
4983 * otherwise FALSE.
4984 */
4985 static boolean
4986 exec_instruction(
4987 struct tgsi_exec_machine *mach,
4988 const struct tgsi_full_instruction *inst,
4989 int *pc )
4990 {
4991 union tgsi_exec_channel r[10];
4992
4993 (*pc)++;
4994
4995 switch (inst->Instruction.Opcode) {
4996 case TGSI_OPCODE_ARL:
4997 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4998 break;
4999
5000 case TGSI_OPCODE_MOV:
5001 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5002 break;
5003
5004 case TGSI_OPCODE_LIT:
5005 exec_lit(mach, inst);
5006 break;
5007
5008 case TGSI_OPCODE_RCP:
5009 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5010 break;
5011
5012 case TGSI_OPCODE_RSQ:
5013 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5014 break;
5015
5016 case TGSI_OPCODE_EXP:
5017 exec_exp(mach, inst);
5018 break;
5019
5020 case TGSI_OPCODE_LOG:
5021 exec_log(mach, inst);
5022 break;
5023
5024 case TGSI_OPCODE_MUL:
5025 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5026 break;
5027
5028 case TGSI_OPCODE_ADD:
5029 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5030 break;
5031
5032 case TGSI_OPCODE_DP3:
5033 exec_dp3(mach, inst);
5034 break;
5035
5036 case TGSI_OPCODE_DP4:
5037 exec_dp4(mach, inst);
5038 break;
5039
5040 case TGSI_OPCODE_DST:
5041 exec_dst(mach, inst);
5042 break;
5043
5044 case TGSI_OPCODE_MIN:
5045 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5046 break;
5047
5048 case TGSI_OPCODE_MAX:
5049 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5050 break;
5051
5052 case TGSI_OPCODE_SLT:
5053 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5054 break;
5055
5056 case TGSI_OPCODE_SGE:
5057 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5058 break;
5059
5060 case TGSI_OPCODE_MAD:
5061 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5062 break;
5063
5064 case TGSI_OPCODE_LRP:
5065 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5066 break;
5067
5068 case TGSI_OPCODE_SQRT:
5069 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5070 break;
5071
5072 case TGSI_OPCODE_FRC:
5073 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5074 break;
5075
5076 case TGSI_OPCODE_FLR:
5077 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5078 break;
5079
5080 case TGSI_OPCODE_ROUND:
5081 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5082 break;
5083
5084 case TGSI_OPCODE_EX2:
5085 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5086 break;
5087
5088 case TGSI_OPCODE_LG2:
5089 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5090 break;
5091
5092 case TGSI_OPCODE_POW:
5093 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5094 break;
5095
5096 case TGSI_OPCODE_LDEXP:
5097 exec_scalar_binary(mach, inst, micro_ldexp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5098 break;
5099
5100 case TGSI_OPCODE_COS:
5101 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5102 break;
5103
5104 case TGSI_OPCODE_DDX:
5105 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5106 break;
5107
5108 case TGSI_OPCODE_DDY:
5109 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5110 break;
5111
5112 case TGSI_OPCODE_KILL:
5113 exec_kill (mach, inst);
5114 break;
5115
5116 case TGSI_OPCODE_KILL_IF:
5117 exec_kill_if (mach, inst);
5118 break;
5119
5120 case TGSI_OPCODE_PK2H:
5121 exec_pk2h(mach, inst);
5122 break;
5123
5124 case TGSI_OPCODE_PK2US:
5125 assert (0);
5126 break;
5127
5128 case TGSI_OPCODE_PK4B:
5129 assert (0);
5130 break;
5131
5132 case TGSI_OPCODE_PK4UB:
5133 assert (0);
5134 break;
5135
5136 case TGSI_OPCODE_SEQ:
5137 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5138 break;
5139
5140 case TGSI_OPCODE_SGT:
5141 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5142 break;
5143
5144 case TGSI_OPCODE_SIN:
5145 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5146 break;
5147
5148 case TGSI_OPCODE_SLE:
5149 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5150 break;
5151
5152 case TGSI_OPCODE_SNE:
5153 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5154 break;
5155
5156 case TGSI_OPCODE_TEX:
5157 /* simple texture lookup */
5158 /* src[0] = texcoord */
5159 /* src[1] = sampler unit */
5160 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5161 break;
5162
5163 case TGSI_OPCODE_TXB:
5164 /* Texture lookup with lod bias */
5165 /* src[0] = texcoord (src[0].w = LOD bias) */
5166 /* src[1] = sampler unit */
5167 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5168 break;
5169
5170 case TGSI_OPCODE_TXD:
5171 /* Texture lookup with explict partial derivatives */
5172 /* src[0] = texcoord */
5173 /* src[1] = d[strq]/dx */
5174 /* src[2] = d[strq]/dy */
5175 /* src[3] = sampler unit */
5176 exec_txd(mach, inst);
5177 break;
5178
5179 case TGSI_OPCODE_TXL:
5180 /* Texture lookup with explit LOD */
5181 /* src[0] = texcoord (src[0].w = LOD) */
5182 /* src[1] = sampler unit */
5183 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5184 break;
5185
5186 case TGSI_OPCODE_TXP:
5187 /* Texture lookup with projection */
5188 /* src[0] = texcoord (src[0].w = projection) */
5189 /* src[1] = sampler unit */
5190 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5191 break;
5192
5193 case TGSI_OPCODE_TG4:
5194 /* src[0] = texcoord */
5195 /* src[1] = component */
5196 /* src[2] = sampler unit */
5197 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5198 break;
5199
5200 case TGSI_OPCODE_LODQ:
5201 /* src[0] = texcoord */
5202 /* src[1] = sampler unit */
5203 exec_lodq(mach, inst);
5204 break;
5205
5206 case TGSI_OPCODE_UP2H:
5207 exec_up2h(mach, inst);
5208 break;
5209
5210 case TGSI_OPCODE_UP2US:
5211 assert (0);
5212 break;
5213
5214 case TGSI_OPCODE_UP4B:
5215 assert (0);
5216 break;
5217
5218 case TGSI_OPCODE_UP4UB:
5219 assert (0);
5220 break;
5221
5222 case TGSI_OPCODE_ARR:
5223 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5224 break;
5225
5226 case TGSI_OPCODE_CAL:
5227 /* skip the call if no execution channels are enabled */
5228 if (mach->ExecMask) {
5229 /* do the call */
5230
5231 /* First, record the depths of the execution stacks.
5232 * This is important for deeply nested/looped return statements.
5233 * We have to unwind the stacks by the correct amount. For a
5234 * real code generator, we could determine the number of entries
5235 * to pop off each stack with simple static analysis and avoid
5236 * implementing this data structure at run time.
5237 */
5238 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5239 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5240 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5241 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5242 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5243 /* note that PC was already incremented above */
5244 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5245
5246 mach->CallStackTop++;
5247
5248 /* Second, push the Cond, Loop, Cont, Func stacks */
5249 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5250 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5251 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5252 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5253 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5254 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5255
5256 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5257 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5258 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5259 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5260 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5261 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5262
5263 /* Finally, jump to the subroutine. The label is a pointer
5264 * (an instruction number) to the BGNSUB instruction.
5265 */
5266 *pc = inst->Label.Label;
5267 assert(mach->Instructions[*pc].Instruction.Opcode
5268 == TGSI_OPCODE_BGNSUB);
5269 }
5270 break;
5271
5272 case TGSI_OPCODE_RET:
5273 mach->FuncMask &= ~mach->ExecMask;
5274 UPDATE_EXEC_MASK(mach);
5275
5276 if (mach->FuncMask == 0x0) {
5277 /* really return now (otherwise, keep executing */
5278
5279 if (mach->CallStackTop == 0) {
5280 /* returning from main() */
5281 mach->CondStackTop = 0;
5282 mach->LoopStackTop = 0;
5283 mach->ContStackTop = 0;
5284 mach->LoopLabelStackTop = 0;
5285 mach->SwitchStackTop = 0;
5286 mach->BreakStackTop = 0;
5287 *pc = -1;
5288 return FALSE;
5289 }
5290
5291 assert(mach->CallStackTop > 0);
5292 mach->CallStackTop--;
5293
5294 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5295 mach->CondMask = mach->CondStack[mach->CondStackTop];
5296
5297 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5298 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5299
5300 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5301 mach->ContMask = mach->ContStack[mach->ContStackTop];
5302
5303 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5304 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5305
5306 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5307 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5308
5309 assert(mach->FuncStackTop > 0);
5310 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5311
5312 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5313
5314 UPDATE_EXEC_MASK(mach);
5315 }
5316 break;
5317
5318 case TGSI_OPCODE_SSG:
5319 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5320 break;
5321
5322 case TGSI_OPCODE_CMP:
5323 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5324 break;
5325
5326 case TGSI_OPCODE_DIV:
5327 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5328 break;
5329
5330 case TGSI_OPCODE_DP2:
5331 exec_dp2(mach, inst);
5332 break;
5333
5334 case TGSI_OPCODE_IF:
5335 /* push CondMask */
5336 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5337 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5338 FETCH( &r[0], 0, TGSI_CHAN_X );
5339 /* update CondMask */
5340 if( ! r[0].f[0] ) {
5341 mach->CondMask &= ~0x1;
5342 }
5343 if( ! r[0].f[1] ) {
5344 mach->CondMask &= ~0x2;
5345 }
5346 if( ! r[0].f[2] ) {
5347 mach->CondMask &= ~0x4;
5348 }
5349 if( ! r[0].f[3] ) {
5350 mach->CondMask &= ~0x8;
5351 }
5352 UPDATE_EXEC_MASK(mach);
5353 /* Todo: If CondMask==0, jump to ELSE */
5354 break;
5355
5356 case TGSI_OPCODE_UIF:
5357 /* push CondMask */
5358 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5359 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5360 IFETCH( &r[0], 0, TGSI_CHAN_X );
5361 /* update CondMask */
5362 if( ! r[0].u[0] ) {
5363 mach->CondMask &= ~0x1;
5364 }
5365 if( ! r[0].u[1] ) {
5366 mach->CondMask &= ~0x2;
5367 }
5368 if( ! r[0].u[2] ) {
5369 mach->CondMask &= ~0x4;
5370 }
5371 if( ! r[0].u[3] ) {
5372 mach->CondMask &= ~0x8;
5373 }
5374 UPDATE_EXEC_MASK(mach);
5375 /* Todo: If CondMask==0, jump to ELSE */
5376 break;
5377
5378 case TGSI_OPCODE_ELSE:
5379 /* invert CondMask wrt previous mask */
5380 {
5381 uint prevMask;
5382 assert(mach->CondStackTop > 0);
5383 prevMask = mach->CondStack[mach->CondStackTop - 1];
5384 mach->CondMask = ~mach->CondMask & prevMask;
5385 UPDATE_EXEC_MASK(mach);
5386 /* Todo: If CondMask==0, jump to ENDIF */
5387 }
5388 break;
5389
5390 case TGSI_OPCODE_ENDIF:
5391 /* pop CondMask */
5392 assert(mach->CondStackTop > 0);
5393 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5394 UPDATE_EXEC_MASK(mach);
5395 break;
5396
5397 case TGSI_OPCODE_END:
5398 /* make sure we end primitives which haven't
5399 * been explicitly emitted */
5400 conditional_emit_primitive(mach);
5401 /* halt execution */
5402 *pc = -1;
5403 break;
5404
5405 case TGSI_OPCODE_CEIL:
5406 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5407 break;
5408
5409 case TGSI_OPCODE_I2F:
5410 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5411 break;
5412
5413 case TGSI_OPCODE_NOT:
5414 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5415 break;
5416
5417 case TGSI_OPCODE_TRUNC:
5418 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5419 break;
5420
5421 case TGSI_OPCODE_SHL:
5422 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5423 break;
5424
5425 case TGSI_OPCODE_AND:
5426 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5427 break;
5428
5429 case TGSI_OPCODE_OR:
5430 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5431 break;
5432
5433 case TGSI_OPCODE_MOD:
5434 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5435 break;
5436
5437 case TGSI_OPCODE_XOR:
5438 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5439 break;
5440
5441 case TGSI_OPCODE_TXF:
5442 exec_txf(mach, inst);
5443 break;
5444
5445 case TGSI_OPCODE_TXQ:
5446 exec_txq(mach, inst);
5447 break;
5448
5449 case TGSI_OPCODE_EMIT:
5450 emit_vertex(mach);
5451 break;
5452
5453 case TGSI_OPCODE_ENDPRIM:
5454 emit_primitive(mach);
5455 break;
5456
5457 case TGSI_OPCODE_BGNLOOP:
5458 /* push LoopMask and ContMasks */
5459 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5460 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5461 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5462 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5463
5464 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5465 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5466 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5467 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5468 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5469 break;
5470
5471 case TGSI_OPCODE_ENDLOOP:
5472 /* Restore ContMask, but don't pop */
5473 assert(mach->ContStackTop > 0);
5474 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5475 UPDATE_EXEC_MASK(mach);
5476 if (mach->ExecMask) {
5477 /* repeat loop: jump to instruction just past BGNLOOP */
5478 assert(mach->LoopLabelStackTop > 0);
5479 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5480 }
5481 else {
5482 /* exit loop: pop LoopMask */
5483 assert(mach->LoopStackTop > 0);
5484 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5485 /* pop ContMask */
5486 assert(mach->ContStackTop > 0);
5487 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5488 assert(mach->LoopLabelStackTop > 0);
5489 --mach->LoopLabelStackTop;
5490
5491 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5492 }
5493 UPDATE_EXEC_MASK(mach);
5494 break;
5495
5496 case TGSI_OPCODE_BRK:
5497 exec_break(mach);
5498 break;
5499
5500 case TGSI_OPCODE_CONT:
5501 /* turn off cont channels for each enabled exec channel */
5502 mach->ContMask &= ~mach->ExecMask;
5503 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5504 UPDATE_EXEC_MASK(mach);
5505 break;
5506
5507 case TGSI_OPCODE_BGNSUB:
5508 /* no-op */
5509 break;
5510
5511 case TGSI_OPCODE_ENDSUB:
5512 /*
5513 * XXX: This really should be a no-op. We should never reach this opcode.
5514 */
5515
5516 assert(mach->CallStackTop > 0);
5517 mach->CallStackTop--;
5518
5519 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5520 mach->CondMask = mach->CondStack[mach->CondStackTop];
5521
5522 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5523 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5524
5525 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5526 mach->ContMask = mach->ContStack[mach->ContStackTop];
5527
5528 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5529 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5530
5531 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5532 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5533
5534 assert(mach->FuncStackTop > 0);
5535 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5536
5537 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5538
5539 UPDATE_EXEC_MASK(mach);
5540 break;
5541
5542 case TGSI_OPCODE_NOP:
5543 break;
5544
5545 case TGSI_OPCODE_F2I:
5546 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5547 break;
5548
5549 case TGSI_OPCODE_FSEQ:
5550 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5551 break;
5552
5553 case TGSI_OPCODE_FSGE:
5554 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5555 break;
5556
5557 case TGSI_OPCODE_FSLT:
5558 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5559 break;
5560
5561 case TGSI_OPCODE_FSNE:
5562 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5563 break;
5564
5565 case TGSI_OPCODE_IDIV:
5566 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5567 break;
5568
5569 case TGSI_OPCODE_IMAX:
5570 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5571 break;
5572
5573 case TGSI_OPCODE_IMIN:
5574 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5575 break;
5576
5577 case TGSI_OPCODE_INEG:
5578 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5579 break;
5580
5581 case TGSI_OPCODE_ISGE:
5582 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5583 break;
5584
5585 case TGSI_OPCODE_ISHR:
5586 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5587 break;
5588
5589 case TGSI_OPCODE_ISLT:
5590 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5591 break;
5592
5593 case TGSI_OPCODE_F2U:
5594 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5595 break;
5596
5597 case TGSI_OPCODE_U2F:
5598 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5599 break;
5600
5601 case TGSI_OPCODE_UADD:
5602 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5603 break;
5604
5605 case TGSI_OPCODE_UDIV:
5606 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5607 break;
5608
5609 case TGSI_OPCODE_UMAD:
5610 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5611 break;
5612
5613 case TGSI_OPCODE_UMAX:
5614 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5615 break;
5616
5617 case TGSI_OPCODE_UMIN:
5618 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5619 break;
5620
5621 case TGSI_OPCODE_UMOD:
5622 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5623 break;
5624
5625 case TGSI_OPCODE_UMUL:
5626 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5627 break;
5628
5629 case TGSI_OPCODE_IMUL_HI:
5630 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5631 break;
5632
5633 case TGSI_OPCODE_UMUL_HI:
5634 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5635 break;
5636
5637 case TGSI_OPCODE_USEQ:
5638 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5639 break;
5640
5641 case TGSI_OPCODE_USGE:
5642 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5643 break;
5644
5645 case TGSI_OPCODE_USHR:
5646 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5647 break;
5648
5649 case TGSI_OPCODE_USLT:
5650 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5651 break;
5652
5653 case TGSI_OPCODE_USNE:
5654 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5655 break;
5656
5657 case TGSI_OPCODE_SWITCH:
5658 exec_switch(mach, inst);
5659 break;
5660
5661 case TGSI_OPCODE_CASE:
5662 exec_case(mach, inst);
5663 break;
5664
5665 case TGSI_OPCODE_DEFAULT:
5666 exec_default(mach);
5667 break;
5668
5669 case TGSI_OPCODE_ENDSWITCH:
5670 exec_endswitch(mach);
5671 break;
5672
5673 case TGSI_OPCODE_SAMPLE_I:
5674 exec_txf(mach, inst);
5675 break;
5676
5677 case TGSI_OPCODE_SAMPLE_I_MS:
5678 exec_txf(mach, inst);
5679 break;
5680
5681 case TGSI_OPCODE_SAMPLE:
5682 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5683 break;
5684
5685 case TGSI_OPCODE_SAMPLE_B:
5686 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5687 break;
5688
5689 case TGSI_OPCODE_SAMPLE_C:
5690 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5691 break;
5692
5693 case TGSI_OPCODE_SAMPLE_C_LZ:
5694 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5695 break;
5696
5697 case TGSI_OPCODE_SAMPLE_D:
5698 exec_sample_d(mach, inst);
5699 break;
5700
5701 case TGSI_OPCODE_SAMPLE_L:
5702 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5703 break;
5704
5705 case TGSI_OPCODE_GATHER4:
5706 exec_sample(mach, inst, TEX_MODIFIER_GATHER, FALSE);
5707 break;
5708
5709 case TGSI_OPCODE_SVIEWINFO:
5710 exec_txq(mach, inst);
5711 break;
5712
5713 case TGSI_OPCODE_SAMPLE_POS:
5714 assert(0);
5715 break;
5716
5717 case TGSI_OPCODE_SAMPLE_INFO:
5718 assert(0);
5719 break;
5720
5721 case TGSI_OPCODE_UARL:
5722 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5723 break;
5724
5725 case TGSI_OPCODE_UCMP:
5726 exec_ucmp(mach, inst);
5727 break;
5728
5729 case TGSI_OPCODE_IABS:
5730 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5731 break;
5732
5733 case TGSI_OPCODE_ISSG:
5734 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5735 break;
5736
5737 case TGSI_OPCODE_TEX2:
5738 /* simple texture lookup */
5739 /* src[0] = texcoord */
5740 /* src[1] = compare */
5741 /* src[2] = sampler unit */
5742 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5743 break;
5744 case TGSI_OPCODE_TXB2:
5745 /* simple texture lookup */
5746 /* src[0] = texcoord */
5747 /* src[1] = bias */
5748 /* src[2] = sampler unit */
5749 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5750 break;
5751 case TGSI_OPCODE_TXL2:
5752 /* simple texture lookup */
5753 /* src[0] = texcoord */
5754 /* src[1] = lod */
5755 /* src[2] = sampler unit */
5756 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5757 break;
5758
5759 case TGSI_OPCODE_IBFE:
5760 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5761 break;
5762 case TGSI_OPCODE_UBFE:
5763 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5764 break;
5765 case TGSI_OPCODE_BFI:
5766 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5767 break;
5768 case TGSI_OPCODE_BREV:
5769 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5770 break;
5771 case TGSI_OPCODE_POPC:
5772 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5773 break;
5774 case TGSI_OPCODE_LSB:
5775 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5776 break;
5777 case TGSI_OPCODE_IMSB:
5778 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5779 break;
5780 case TGSI_OPCODE_UMSB:
5781 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5782 break;
5783
5784 case TGSI_OPCODE_F2D:
5785 exec_t_2_64(mach, inst, micro_f2d, TGSI_EXEC_DATA_FLOAT);
5786 break;
5787
5788 case TGSI_OPCODE_D2F:
5789 exec_64_2_t(mach, inst, micro_d2f, TGSI_EXEC_DATA_FLOAT);
5790 break;
5791
5792 case TGSI_OPCODE_DABS:
5793 exec_double_unary(mach, inst, micro_dabs);
5794 break;
5795
5796 case TGSI_OPCODE_DNEG:
5797 exec_double_unary(mach, inst, micro_dneg);
5798 break;
5799
5800 case TGSI_OPCODE_DADD:
5801 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5802 break;
5803
5804 case TGSI_OPCODE_DDIV:
5805 exec_double_binary(mach, inst, micro_ddiv, TGSI_EXEC_DATA_DOUBLE);
5806 break;
5807
5808 case TGSI_OPCODE_DMUL:
5809 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5810 break;
5811
5812 case TGSI_OPCODE_DMAX:
5813 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5814 break;
5815
5816 case TGSI_OPCODE_DMIN:
5817 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5818 break;
5819
5820 case TGSI_OPCODE_DSLT:
5821 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5822 break;
5823
5824 case TGSI_OPCODE_DSGE:
5825 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5826 break;
5827
5828 case TGSI_OPCODE_DSEQ:
5829 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5830 break;
5831
5832 case TGSI_OPCODE_DSNE:
5833 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5834 break;
5835
5836 case TGSI_OPCODE_DRCP:
5837 exec_double_unary(mach, inst, micro_drcp);
5838 break;
5839
5840 case TGSI_OPCODE_DSQRT:
5841 exec_double_unary(mach, inst, micro_dsqrt);
5842 break;
5843
5844 case TGSI_OPCODE_DRSQ:
5845 exec_double_unary(mach, inst, micro_drsq);
5846 break;
5847
5848 case TGSI_OPCODE_DMAD:
5849 exec_double_trinary(mach, inst, micro_dmad);
5850 break;
5851
5852 case TGSI_OPCODE_DFRAC:
5853 exec_double_unary(mach, inst, micro_dfrac);
5854 break;
5855
5856 case TGSI_OPCODE_DLDEXP:
5857 exec_dldexp(mach, inst);
5858 break;
5859
5860 case TGSI_OPCODE_DFRACEXP:
5861 exec_dfracexp(mach, inst);
5862 break;
5863
5864 case TGSI_OPCODE_I2D:
5865 exec_t_2_64(mach, inst, micro_i2d, TGSI_EXEC_DATA_INT);
5866 break;
5867
5868 case TGSI_OPCODE_D2I:
5869 exec_64_2_t(mach, inst, micro_d2i, TGSI_EXEC_DATA_INT);
5870 break;
5871
5872 case TGSI_OPCODE_U2D:
5873 exec_t_2_64(mach, inst, micro_u2d, TGSI_EXEC_DATA_UINT);
5874 break;
5875
5876 case TGSI_OPCODE_D2U:
5877 exec_64_2_t(mach, inst, micro_d2u, TGSI_EXEC_DATA_INT);
5878 break;
5879
5880 case TGSI_OPCODE_LOAD:
5881 exec_load(mach, inst);
5882 break;
5883
5884 case TGSI_OPCODE_STORE:
5885 exec_store(mach, inst);
5886 break;
5887
5888 case TGSI_OPCODE_ATOMUADD:
5889 case TGSI_OPCODE_ATOMXCHG:
5890 case TGSI_OPCODE_ATOMCAS:
5891 case TGSI_OPCODE_ATOMAND:
5892 case TGSI_OPCODE_ATOMOR:
5893 case TGSI_OPCODE_ATOMXOR:
5894 case TGSI_OPCODE_ATOMUMIN:
5895 case TGSI_OPCODE_ATOMUMAX:
5896 case TGSI_OPCODE_ATOMIMIN:
5897 case TGSI_OPCODE_ATOMIMAX:
5898 exec_atomop(mach, inst);
5899 break;
5900
5901 case TGSI_OPCODE_RESQ:
5902 exec_resq(mach, inst);
5903 break;
5904 case TGSI_OPCODE_BARRIER:
5905 case TGSI_OPCODE_MEMBAR:
5906 return TRUE;
5907 break;
5908
5909 case TGSI_OPCODE_I64ABS:
5910 exec_double_unary(mach, inst, micro_i64abs);
5911 break;
5912
5913 case TGSI_OPCODE_I64SSG:
5914 exec_double_unary(mach, inst, micro_i64sgn);
5915 break;
5916
5917 case TGSI_OPCODE_I64NEG:
5918 exec_double_unary(mach, inst, micro_i64neg);
5919 break;
5920
5921 case TGSI_OPCODE_U64SEQ:
5922 exec_double_binary(mach, inst, micro_u64seq, TGSI_EXEC_DATA_UINT);
5923 break;
5924
5925 case TGSI_OPCODE_U64SNE:
5926 exec_double_binary(mach, inst, micro_u64sne, TGSI_EXEC_DATA_UINT);
5927 break;
5928
5929 case TGSI_OPCODE_I64SLT:
5930 exec_double_binary(mach, inst, micro_i64slt, TGSI_EXEC_DATA_UINT);
5931 break;
5932 case TGSI_OPCODE_U64SLT:
5933 exec_double_binary(mach, inst, micro_u64slt, TGSI_EXEC_DATA_UINT);
5934 break;
5935
5936 case TGSI_OPCODE_I64SGE:
5937 exec_double_binary(mach, inst, micro_i64sge, TGSI_EXEC_DATA_UINT);
5938 break;
5939 case TGSI_OPCODE_U64SGE:
5940 exec_double_binary(mach, inst, micro_u64sge, TGSI_EXEC_DATA_UINT);
5941 break;
5942
5943 case TGSI_OPCODE_I64MIN:
5944 exec_double_binary(mach, inst, micro_i64min, TGSI_EXEC_DATA_INT64);
5945 break;
5946 case TGSI_OPCODE_U64MIN:
5947 exec_double_binary(mach, inst, micro_u64min, TGSI_EXEC_DATA_UINT64);
5948 break;
5949 case TGSI_OPCODE_I64MAX:
5950 exec_double_binary(mach, inst, micro_i64max, TGSI_EXEC_DATA_INT64);
5951 break;
5952 case TGSI_OPCODE_U64MAX:
5953 exec_double_binary(mach, inst, micro_u64max, TGSI_EXEC_DATA_UINT64);
5954 break;
5955 case TGSI_OPCODE_U64ADD:
5956 exec_double_binary(mach, inst, micro_u64add, TGSI_EXEC_DATA_UINT64);
5957 break;
5958 case TGSI_OPCODE_U64MUL:
5959 exec_double_binary(mach, inst, micro_u64mul, TGSI_EXEC_DATA_UINT64);
5960 break;
5961 case TGSI_OPCODE_U64SHL:
5962 exec_arg0_64_arg1_32(mach, inst, micro_u64shl);
5963 break;
5964 case TGSI_OPCODE_I64SHR:
5965 exec_arg0_64_arg1_32(mach, inst, micro_i64shr);
5966 break;
5967 case TGSI_OPCODE_U64SHR:
5968 exec_arg0_64_arg1_32(mach, inst, micro_u64shr);
5969 break;
5970 case TGSI_OPCODE_U64DIV:
5971 exec_double_binary(mach, inst, micro_u64div, TGSI_EXEC_DATA_UINT64);
5972 break;
5973 case TGSI_OPCODE_I64DIV:
5974 exec_double_binary(mach, inst, micro_i64div, TGSI_EXEC_DATA_INT64);
5975 break;
5976 case TGSI_OPCODE_U64MOD:
5977 exec_double_binary(mach, inst, micro_u64mod, TGSI_EXEC_DATA_UINT64);
5978 break;
5979 case TGSI_OPCODE_I64MOD:
5980 exec_double_binary(mach, inst, micro_i64mod, TGSI_EXEC_DATA_INT64);
5981 break;
5982
5983 case TGSI_OPCODE_F2U64:
5984 exec_t_2_64(mach, inst, micro_f2u64, TGSI_EXEC_DATA_FLOAT);
5985 break;
5986
5987 case TGSI_OPCODE_F2I64:
5988 exec_t_2_64(mach, inst, micro_f2i64, TGSI_EXEC_DATA_FLOAT);
5989 break;
5990
5991 case TGSI_OPCODE_U2I64:
5992 exec_t_2_64(mach, inst, micro_u2i64, TGSI_EXEC_DATA_INT);
5993 break;
5994 case TGSI_OPCODE_I2I64:
5995 exec_t_2_64(mach, inst, micro_i2i64, TGSI_EXEC_DATA_INT);
5996 break;
5997
5998 case TGSI_OPCODE_D2U64:
5999 exec_double_unary(mach, inst, micro_d2u64);
6000 break;
6001
6002 case TGSI_OPCODE_D2I64:
6003 exec_double_unary(mach, inst, micro_d2i64);
6004 break;
6005
6006 case TGSI_OPCODE_U642F:
6007 exec_64_2_t(mach, inst, micro_u642f, TGSI_EXEC_DATA_FLOAT);
6008 break;
6009 case TGSI_OPCODE_I642F:
6010 exec_64_2_t(mach, inst, micro_i642f, TGSI_EXEC_DATA_FLOAT);
6011 break;
6012
6013 case TGSI_OPCODE_U642D:
6014 exec_double_unary(mach, inst, micro_u642d);
6015 break;
6016 case TGSI_OPCODE_I642D:
6017 exec_double_unary(mach, inst, micro_i642d);
6018 break;
6019
6020 default:
6021 assert( 0 );
6022 }
6023 return FALSE;
6024 }
6025
6026 static void
6027 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
6028 {
6029 uint default_mask = 0xf;
6030
6031 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
6032 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
6033
6034 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
6035 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
6036 mach->Primitives[0] = 0;
6037 /* GS runs on a single primitive for now */
6038 default_mask = 0x1;
6039 }
6040
6041 if (mach->NonHelperMask == 0)
6042 mach->NonHelperMask = default_mask;
6043 mach->CondMask = default_mask;
6044 mach->LoopMask = default_mask;
6045 mach->ContMask = default_mask;
6046 mach->FuncMask = default_mask;
6047 mach->ExecMask = default_mask;
6048
6049 mach->Switch.mask = default_mask;
6050
6051 assert(mach->CondStackTop == 0);
6052 assert(mach->LoopStackTop == 0);
6053 assert(mach->ContStackTop == 0);
6054 assert(mach->SwitchStackTop == 0);
6055 assert(mach->BreakStackTop == 0);
6056 assert(mach->CallStackTop == 0);
6057 }
6058
6059 /**
6060 * Run TGSI interpreter.
6061 * \return bitmask of "alive" quad components
6062 */
6063 uint
6064 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
6065 {
6066 uint i;
6067
6068 mach->pc = start_pc;
6069
6070 if (!start_pc) {
6071 tgsi_exec_machine_setup_masks(mach);
6072
6073 /* execute declarations (interpolants) */
6074 for (i = 0; i < mach->NumDeclarations; i++) {
6075 exec_declaration( mach, mach->Declarations+i );
6076 }
6077 }
6078
6079 {
6080 #if DEBUG_EXECUTION
6081 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
6082 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
6083 uint inst = 1;
6084
6085 if (!start_pc) {
6086 memset(mach->Temps, 0, sizeof(temps));
6087 if (mach->Outputs)
6088 memset(mach->Outputs, 0, sizeof(outputs));
6089 memset(temps, 0, sizeof(temps));
6090 memset(outputs, 0, sizeof(outputs));
6091 }
6092 #endif
6093
6094 /* execute instructions, until pc is set to -1 */
6095 while (mach->pc != -1) {
6096 boolean barrier_hit;
6097 #if DEBUG_EXECUTION
6098 uint i;
6099
6100 tgsi_dump_instruction(&mach->Instructions[mach->pc], inst++);
6101 #endif
6102
6103 assert(mach->pc < (int) mach->NumInstructions);
6104 barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
6105
6106 /* for compute shaders if we hit a barrier return now for later rescheduling */
6107 if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
6108 return 0;
6109
6110 #if DEBUG_EXECUTION
6111 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
6112 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
6113 uint j;
6114
6115 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
6116 debug_printf("TEMP[%2u] = ", i);
6117 for (j = 0; j < 4; j++) {
6118 if (j > 0) {
6119 debug_printf(" ");
6120 }
6121 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6122 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
6123 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
6124 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
6125 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
6126 }
6127 }
6128 }
6129 if (mach->Outputs) {
6130 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
6131 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
6132 uint j;
6133
6134 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
6135 debug_printf("OUT[%2u] = ", i);
6136 for (j = 0; j < 4; j++) {
6137 if (j > 0) {
6138 debug_printf(" ");
6139 }
6140 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6141 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
6142 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
6143 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
6144 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
6145 }
6146 }
6147 }
6148 }
6149 #endif
6150 }
6151 }
6152
6153 #if 0
6154 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6155 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
6156 /*
6157 * Scale back depth component.
6158 */
6159 for (i = 0; i < 4; i++)
6160 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
6161 }
6162 #endif
6163
6164 /* Strictly speaking, these assertions aren't really needed but they
6165 * can potentially catch some bugs in the control flow code.
6166 */
6167 assert(mach->CondStackTop == 0);
6168 assert(mach->LoopStackTop == 0);
6169 assert(mach->ContStackTop == 0);
6170 assert(mach->SwitchStackTop == 0);
6171 assert(mach->BreakStackTop == 0);
6172 assert(mach->CallStackTop == 0);
6173
6174 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
6175 }