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tgsi: Enable returns from within loops
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
65
66
67 #define DEBUG_EXECUTION 0
68
69
70 #define FAST_MATH 0
71
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
76
77 union tgsi_double_channel {
78 double d[TGSI_QUAD_SIZE];
79 unsigned u[TGSI_QUAD_SIZE][2];
80 };
81
82 struct tgsi_double_vector {
83 union tgsi_double_channel xy;
84 union tgsi_double_channel zw;
85 };
86
87 static void
88 micro_abs(union tgsi_exec_channel *dst,
89 const union tgsi_exec_channel *src)
90 {
91 dst->f[0] = fabsf(src->f[0]);
92 dst->f[1] = fabsf(src->f[1]);
93 dst->f[2] = fabsf(src->f[2]);
94 dst->f[3] = fabsf(src->f[3]);
95 }
96
97 static void
98 micro_arl(union tgsi_exec_channel *dst,
99 const union tgsi_exec_channel *src)
100 {
101 dst->i[0] = (int)floorf(src->f[0]);
102 dst->i[1] = (int)floorf(src->f[1]);
103 dst->i[2] = (int)floorf(src->f[2]);
104 dst->i[3] = (int)floorf(src->f[3]);
105 }
106
107 static void
108 micro_arr(union tgsi_exec_channel *dst,
109 const union tgsi_exec_channel *src)
110 {
111 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
112 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
113 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
114 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
115 }
116
117 static void
118 micro_ceil(union tgsi_exec_channel *dst,
119 const union tgsi_exec_channel *src)
120 {
121 dst->f[0] = ceilf(src->f[0]);
122 dst->f[1] = ceilf(src->f[1]);
123 dst->f[2] = ceilf(src->f[2]);
124 dst->f[3] = ceilf(src->f[3]);
125 }
126
127 static void
128 micro_clamp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
132 {
133 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
134 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
135 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
136 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
137 }
138
139 static void
140 micro_cmp(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
144 {
145 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
146 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
147 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
148 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
149 }
150
151 static void
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
154 {
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
159 }
160
161 static void
162 micro_d2f(union tgsi_exec_channel *dst,
163 const union tgsi_double_channel *src)
164 {
165 dst->f[0] = (float)src->d[0];
166 dst->f[1] = (float)src->d[1];
167 dst->f[2] = (float)src->d[2];
168 dst->f[3] = (float)src->d[3];
169 }
170
171 static void
172 micro_d2i(union tgsi_exec_channel *dst,
173 const union tgsi_double_channel *src)
174 {
175 dst->i[0] = (int)src->d[0];
176 dst->i[1] = (int)src->d[1];
177 dst->i[2] = (int)src->d[2];
178 dst->i[3] = (int)src->d[3];
179 }
180
181 static void
182 micro_d2u(union tgsi_exec_channel *dst,
183 const union tgsi_double_channel *src)
184 {
185 dst->u[0] = (unsigned)src->d[0];
186 dst->u[1] = (unsigned)src->d[1];
187 dst->u[2] = (unsigned)src->d[2];
188 dst->u[3] = (unsigned)src->d[3];
189 }
190 static void
191 micro_dabs(union tgsi_double_channel *dst,
192 const union tgsi_double_channel *src)
193 {
194 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
195 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
196 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
197 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
198 }
199
200 static void
201 micro_dadd(union tgsi_double_channel *dst,
202 const union tgsi_double_channel *src)
203 {
204 dst->d[0] = src[0].d[0] + src[1].d[0];
205 dst->d[1] = src[0].d[1] + src[1].d[1];
206 dst->d[2] = src[0].d[2] + src[1].d[2];
207 dst->d[3] = src[0].d[3] + src[1].d[3];
208 }
209
210 static void
211 micro_ddx(union tgsi_exec_channel *dst,
212 const union tgsi_exec_channel *src)
213 {
214 dst->f[0] =
215 dst->f[1] =
216 dst->f[2] =
217 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
218 }
219
220 static void
221 micro_ddy(union tgsi_exec_channel *dst,
222 const union tgsi_exec_channel *src)
223 {
224 dst->f[0] =
225 dst->f[1] =
226 dst->f[2] =
227 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
228 }
229
230 static void
231 micro_dmul(union tgsi_double_channel *dst,
232 const union tgsi_double_channel *src)
233 {
234 dst->d[0] = src[0].d[0] * src[1].d[0];
235 dst->d[1] = src[0].d[1] * src[1].d[1];
236 dst->d[2] = src[0].d[2] * src[1].d[2];
237 dst->d[3] = src[0].d[3] * src[1].d[3];
238 }
239
240 static void
241 micro_dmax(union tgsi_double_channel *dst,
242 const union tgsi_double_channel *src)
243 {
244 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
245 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
246 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
247 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
248 }
249
250 static void
251 micro_dmin(union tgsi_double_channel *dst,
252 const union tgsi_double_channel *src)
253 {
254 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
255 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
256 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
257 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
258 }
259
260 static void
261 micro_dneg(union tgsi_double_channel *dst,
262 const union tgsi_double_channel *src)
263 {
264 dst->d[0] = -src->d[0];
265 dst->d[1] = -src->d[1];
266 dst->d[2] = -src->d[2];
267 dst->d[3] = -src->d[3];
268 }
269
270 static void
271 micro_dslt(union tgsi_double_channel *dst,
272 const union tgsi_double_channel *src)
273 {
274 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
275 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
276 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
277 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
278 }
279
280 static void
281 micro_dsne(union tgsi_double_channel *dst,
282 const union tgsi_double_channel *src)
283 {
284 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
285 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
286 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
287 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
288 }
289
290 static void
291 micro_dsge(union tgsi_double_channel *dst,
292 const union tgsi_double_channel *src)
293 {
294 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
295 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
296 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
297 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
298 }
299
300 static void
301 micro_dseq(union tgsi_double_channel *dst,
302 const union tgsi_double_channel *src)
303 {
304 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
305 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
306 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
307 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
308 }
309
310 static void
311 micro_drcp(union tgsi_double_channel *dst,
312 const union tgsi_double_channel *src)
313 {
314 dst->d[0] = 1.0 / src->d[0];
315 dst->d[1] = 1.0 / src->d[1];
316 dst->d[2] = 1.0 / src->d[2];
317 dst->d[3] = 1.0 / src->d[3];
318 }
319
320 static void
321 micro_dsqrt(union tgsi_double_channel *dst,
322 const union tgsi_double_channel *src)
323 {
324 dst->d[0] = sqrt(src->d[0]);
325 dst->d[1] = sqrt(src->d[1]);
326 dst->d[2] = sqrt(src->d[2]);
327 dst->d[3] = sqrt(src->d[3]);
328 }
329
330 static void
331 micro_drsq(union tgsi_double_channel *dst,
332 const union tgsi_double_channel *src)
333 {
334 dst->d[0] = 1.0 / sqrt(src->d[0]);
335 dst->d[1] = 1.0 / sqrt(src->d[1]);
336 dst->d[2] = 1.0 / sqrt(src->d[2]);
337 dst->d[3] = 1.0 / sqrt(src->d[3]);
338 }
339
340 static void
341 micro_dmad(union tgsi_double_channel *dst,
342 const union tgsi_double_channel *src)
343 {
344 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
345 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
346 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
347 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
348 }
349
350 static void
351 micro_dfrac(union tgsi_double_channel *dst,
352 const union tgsi_double_channel *src)
353 {
354 dst->d[0] = src->d[0] - floor(src->d[0]);
355 dst->d[1] = src->d[1] - floor(src->d[1]);
356 dst->d[2] = src->d[2] - floor(src->d[2]);
357 dst->d[3] = src->d[3] - floor(src->d[3]);
358 }
359
360 static void
361 micro_dldexp(union tgsi_double_channel *dst,
362 const union tgsi_double_channel *src0,
363 union tgsi_exec_channel *src1)
364 {
365 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
366 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
367 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
368 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
369 }
370
371 static void
372 micro_dfracexp(union tgsi_double_channel *dst,
373 union tgsi_exec_channel *dst_exp,
374 const union tgsi_double_channel *src)
375 {
376 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
377 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
378 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
379 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
380 }
381
382 static void
383 micro_exp2(union tgsi_exec_channel *dst,
384 const union tgsi_exec_channel *src)
385 {
386 #if FAST_MATH
387 dst->f[0] = util_fast_exp2(src->f[0]);
388 dst->f[1] = util_fast_exp2(src->f[1]);
389 dst->f[2] = util_fast_exp2(src->f[2]);
390 dst->f[3] = util_fast_exp2(src->f[3]);
391 #else
392 #if DEBUG
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
394 uint i;
395 union tgsi_exec_channel clamped;
396
397 for (i = 0; i < 4; i++) {
398 if (src->f[i] > 127.99999f) {
399 clamped.f[i] = 127.99999f;
400 } else if (src->f[i] < -126.99999f) {
401 clamped.f[i] = -126.99999f;
402 } else {
403 clamped.f[i] = src->f[i];
404 }
405 }
406 src = &clamped;
407 #endif /* DEBUG */
408
409 dst->f[0] = powf(2.0f, src->f[0]);
410 dst->f[1] = powf(2.0f, src->f[1]);
411 dst->f[2] = powf(2.0f, src->f[2]);
412 dst->f[3] = powf(2.0f, src->f[3]);
413 #endif /* FAST_MATH */
414 }
415
416 static void
417 micro_f2d(union tgsi_double_channel *dst,
418 const union tgsi_exec_channel *src)
419 {
420 dst->d[0] = (double)src->f[0];
421 dst->d[1] = (double)src->f[1];
422 dst->d[2] = (double)src->f[2];
423 dst->d[3] = (double)src->f[3];
424 }
425
426 static void
427 micro_flr(union tgsi_exec_channel *dst,
428 const union tgsi_exec_channel *src)
429 {
430 dst->f[0] = floorf(src->f[0]);
431 dst->f[1] = floorf(src->f[1]);
432 dst->f[2] = floorf(src->f[2]);
433 dst->f[3] = floorf(src->f[3]);
434 }
435
436 static void
437 micro_frc(union tgsi_exec_channel *dst,
438 const union tgsi_exec_channel *src)
439 {
440 dst->f[0] = src->f[0] - floorf(src->f[0]);
441 dst->f[1] = src->f[1] - floorf(src->f[1]);
442 dst->f[2] = src->f[2] - floorf(src->f[2]);
443 dst->f[3] = src->f[3] - floorf(src->f[3]);
444 }
445
446 static void
447 micro_i2d(union tgsi_double_channel *dst,
448 const union tgsi_exec_channel *src)
449 {
450 dst->d[0] = (double)src->i[0];
451 dst->d[1] = (double)src->i[1];
452 dst->d[2] = (double)src->i[2];
453 dst->d[3] = (double)src->i[3];
454 }
455
456 static void
457 micro_iabs(union tgsi_exec_channel *dst,
458 const union tgsi_exec_channel *src)
459 {
460 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
461 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
462 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
463 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
464 }
465
466 static void
467 micro_ineg(union tgsi_exec_channel *dst,
468 const union tgsi_exec_channel *src)
469 {
470 dst->i[0] = -src->i[0];
471 dst->i[1] = -src->i[1];
472 dst->i[2] = -src->i[2];
473 dst->i[3] = -src->i[3];
474 }
475
476 static void
477 micro_lg2(union tgsi_exec_channel *dst,
478 const union tgsi_exec_channel *src)
479 {
480 #if FAST_MATH
481 dst->f[0] = util_fast_log2(src->f[0]);
482 dst->f[1] = util_fast_log2(src->f[1]);
483 dst->f[2] = util_fast_log2(src->f[2]);
484 dst->f[3] = util_fast_log2(src->f[3]);
485 #else
486 dst->f[0] = logf(src->f[0]) * 1.442695f;
487 dst->f[1] = logf(src->f[1]) * 1.442695f;
488 dst->f[2] = logf(src->f[2]) * 1.442695f;
489 dst->f[3] = logf(src->f[3]) * 1.442695f;
490 #endif
491 }
492
493 static void
494 micro_lrp(union tgsi_exec_channel *dst,
495 const union tgsi_exec_channel *src0,
496 const union tgsi_exec_channel *src1,
497 const union tgsi_exec_channel *src2)
498 {
499 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
500 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
501 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
502 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
503 }
504
505 static void
506 micro_mad(union tgsi_exec_channel *dst,
507 const union tgsi_exec_channel *src0,
508 const union tgsi_exec_channel *src1,
509 const union tgsi_exec_channel *src2)
510 {
511 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
512 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
513 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
514 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
515 }
516
517 static void
518 micro_mov(union tgsi_exec_channel *dst,
519 const union tgsi_exec_channel *src)
520 {
521 dst->u[0] = src->u[0];
522 dst->u[1] = src->u[1];
523 dst->u[2] = src->u[2];
524 dst->u[3] = src->u[3];
525 }
526
527 static void
528 micro_rcp(union tgsi_exec_channel *dst,
529 const union tgsi_exec_channel *src)
530 {
531 #if 0 /* for debugging */
532 assert(src->f[0] != 0.0f);
533 assert(src->f[1] != 0.0f);
534 assert(src->f[2] != 0.0f);
535 assert(src->f[3] != 0.0f);
536 #endif
537 dst->f[0] = 1.0f / src->f[0];
538 dst->f[1] = 1.0f / src->f[1];
539 dst->f[2] = 1.0f / src->f[2];
540 dst->f[3] = 1.0f / src->f[3];
541 }
542
543 static void
544 micro_rnd(union tgsi_exec_channel *dst,
545 const union tgsi_exec_channel *src)
546 {
547 dst->f[0] = _mesa_roundevenf(src->f[0]);
548 dst->f[1] = _mesa_roundevenf(src->f[1]);
549 dst->f[2] = _mesa_roundevenf(src->f[2]);
550 dst->f[3] = _mesa_roundevenf(src->f[3]);
551 }
552
553 static void
554 micro_rsq(union tgsi_exec_channel *dst,
555 const union tgsi_exec_channel *src)
556 {
557 #if 0 /* for debugging */
558 assert(src->f[0] != 0.0f);
559 assert(src->f[1] != 0.0f);
560 assert(src->f[2] != 0.0f);
561 assert(src->f[3] != 0.0f);
562 #endif
563 dst->f[0] = 1.0f / sqrtf(src->f[0]);
564 dst->f[1] = 1.0f / sqrtf(src->f[1]);
565 dst->f[2] = 1.0f / sqrtf(src->f[2]);
566 dst->f[3] = 1.0f / sqrtf(src->f[3]);
567 }
568
569 static void
570 micro_sqrt(union tgsi_exec_channel *dst,
571 const union tgsi_exec_channel *src)
572 {
573 dst->f[0] = sqrtf(src->f[0]);
574 dst->f[1] = sqrtf(src->f[1]);
575 dst->f[2] = sqrtf(src->f[2]);
576 dst->f[3] = sqrtf(src->f[3]);
577 }
578
579 static void
580 micro_seq(union tgsi_exec_channel *dst,
581 const union tgsi_exec_channel *src0,
582 const union tgsi_exec_channel *src1)
583 {
584 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
585 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
586 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
587 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
588 }
589
590 static void
591 micro_sge(union tgsi_exec_channel *dst,
592 const union tgsi_exec_channel *src0,
593 const union tgsi_exec_channel *src1)
594 {
595 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
596 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
597 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
598 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
599 }
600
601 static void
602 micro_sgn(union tgsi_exec_channel *dst,
603 const union tgsi_exec_channel *src)
604 {
605 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
606 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
607 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
608 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
609 }
610
611 static void
612 micro_isgn(union tgsi_exec_channel *dst,
613 const union tgsi_exec_channel *src)
614 {
615 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
616 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
617 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
618 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
619 }
620
621 static void
622 micro_sgt(union tgsi_exec_channel *dst,
623 const union tgsi_exec_channel *src0,
624 const union tgsi_exec_channel *src1)
625 {
626 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
627 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
628 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
629 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
630 }
631
632 static void
633 micro_sin(union tgsi_exec_channel *dst,
634 const union tgsi_exec_channel *src)
635 {
636 dst->f[0] = sinf(src->f[0]);
637 dst->f[1] = sinf(src->f[1]);
638 dst->f[2] = sinf(src->f[2]);
639 dst->f[3] = sinf(src->f[3]);
640 }
641
642 static void
643 micro_sle(union tgsi_exec_channel *dst,
644 const union tgsi_exec_channel *src0,
645 const union tgsi_exec_channel *src1)
646 {
647 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
648 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
649 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
650 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
651 }
652
653 static void
654 micro_slt(union tgsi_exec_channel *dst,
655 const union tgsi_exec_channel *src0,
656 const union tgsi_exec_channel *src1)
657 {
658 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
659 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
660 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
661 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
662 }
663
664 static void
665 micro_sne(union tgsi_exec_channel *dst,
666 const union tgsi_exec_channel *src0,
667 const union tgsi_exec_channel *src1)
668 {
669 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
670 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
671 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
672 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
673 }
674
675 static void
676 micro_trunc(union tgsi_exec_channel *dst,
677 const union tgsi_exec_channel *src)
678 {
679 dst->f[0] = truncf(src->f[0]);
680 dst->f[1] = truncf(src->f[1]);
681 dst->f[2] = truncf(src->f[2]);
682 dst->f[3] = truncf(src->f[3]);
683 }
684
685 static void
686 micro_u2d(union tgsi_double_channel *dst,
687 const union tgsi_exec_channel *src)
688 {
689 dst->d[0] = (double)src->u[0];
690 dst->d[1] = (double)src->u[1];
691 dst->d[2] = (double)src->u[2];
692 dst->d[3] = (double)src->u[3];
693 }
694
695 enum tgsi_exec_datatype {
696 TGSI_EXEC_DATA_FLOAT,
697 TGSI_EXEC_DATA_INT,
698 TGSI_EXEC_DATA_UINT,
699 TGSI_EXEC_DATA_DOUBLE
700 };
701
702 /*
703 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
704 */
705 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
706 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
707 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
708 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
709 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
710 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
711
712
713 /** The execution mask depends on the conditional mask and the loop mask */
714 #define UPDATE_EXEC_MASK(MACH) \
715 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
716
717
718 static const union tgsi_exec_channel ZeroVec =
719 { { 0.0, 0.0, 0.0, 0.0 } };
720
721 static const union tgsi_exec_channel OneVec = {
722 {1.0f, 1.0f, 1.0f, 1.0f}
723 };
724
725 static const union tgsi_exec_channel P128Vec = {
726 {128.0f, 128.0f, 128.0f, 128.0f}
727 };
728
729 static const union tgsi_exec_channel M128Vec = {
730 {-128.0f, -128.0f, -128.0f, -128.0f}
731 };
732
733
734 /**
735 * Assert that none of the float values in 'chan' are infinite or NaN.
736 * NaN and Inf may occur normally during program execution and should
737 * not lead to crashes, etc. But when debugging, it's helpful to catch
738 * them.
739 */
740 static inline void
741 check_inf_or_nan(const union tgsi_exec_channel *chan)
742 {
743 assert(!util_is_inf_or_nan((chan)->f[0]));
744 assert(!util_is_inf_or_nan((chan)->f[1]));
745 assert(!util_is_inf_or_nan((chan)->f[2]));
746 assert(!util_is_inf_or_nan((chan)->f[3]));
747 }
748
749
750 #ifdef DEBUG
751 static void
752 print_chan(const char *msg, const union tgsi_exec_channel *chan)
753 {
754 debug_printf("%s = {%f, %f, %f, %f}\n",
755 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
756 }
757 #endif
758
759
760 #ifdef DEBUG
761 static void
762 print_temp(const struct tgsi_exec_machine *mach, uint index)
763 {
764 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
765 int i;
766 debug_printf("Temp[%u] =\n", index);
767 for (i = 0; i < 4; i++) {
768 debug_printf(" %c: { %f, %f, %f, %f }\n",
769 "XYZW"[i],
770 tmp->xyzw[i].f[0],
771 tmp->xyzw[i].f[1],
772 tmp->xyzw[i].f[2],
773 tmp->xyzw[i].f[3]);
774 }
775 }
776 #endif
777
778
779 void
780 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
781 unsigned num_bufs,
782 const void **bufs,
783 const unsigned *buf_sizes)
784 {
785 unsigned i;
786
787 for (i = 0; i < num_bufs; i++) {
788 mach->Consts[i] = bufs[i];
789 mach->ConstsSize[i] = buf_sizes[i];
790 }
791 }
792
793
794 /**
795 * Check if there's a potential src/dst register data dependency when
796 * using SOA execution.
797 * Example:
798 * MOV T, T.yxwz;
799 * This would expand into:
800 * MOV t0, t1;
801 * MOV t1, t0;
802 * MOV t2, t3;
803 * MOV t3, t2;
804 * The second instruction will have the wrong value for t0 if executed as-is.
805 */
806 boolean
807 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
808 {
809 uint i, chan;
810
811 uint writemask = inst->Dst[0].Register.WriteMask;
812 if (writemask == TGSI_WRITEMASK_X ||
813 writemask == TGSI_WRITEMASK_Y ||
814 writemask == TGSI_WRITEMASK_Z ||
815 writemask == TGSI_WRITEMASK_W ||
816 writemask == TGSI_WRITEMASK_NONE) {
817 /* no chance of data dependency */
818 return FALSE;
819 }
820
821 /* loop over src regs */
822 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
823 if ((inst->Src[i].Register.File ==
824 inst->Dst[0].Register.File) &&
825 ((inst->Src[i].Register.Index ==
826 inst->Dst[0].Register.Index) ||
827 inst->Src[i].Register.Indirect ||
828 inst->Dst[0].Register.Indirect)) {
829 /* loop over dest channels */
830 uint channelsWritten = 0x0;
831 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
832 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
833 /* check if we're reading a channel that's been written */
834 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
835 if (channelsWritten & (1 << swizzle)) {
836 return TRUE;
837 }
838
839 channelsWritten |= (1 << chan);
840 }
841 }
842 }
843 }
844 return FALSE;
845 }
846
847
848 /**
849 * Initialize machine state by expanding tokens to full instructions,
850 * allocating temporary storage, setting up constants, etc.
851 * After this, we can call tgsi_exec_machine_run() many times.
852 */
853 void
854 tgsi_exec_machine_bind_shader(
855 struct tgsi_exec_machine *mach,
856 const struct tgsi_token *tokens,
857 struct tgsi_sampler *sampler,
858 struct tgsi_image *image,
859 struct tgsi_buffer *buffer)
860 {
861 uint k;
862 struct tgsi_parse_context parse;
863 struct tgsi_full_instruction *instructions;
864 struct tgsi_full_declaration *declarations;
865 uint maxInstructions = 10, numInstructions = 0;
866 uint maxDeclarations = 10, numDeclarations = 0;
867
868 #if 0
869 tgsi_dump(tokens, 0);
870 #endif
871
872 util_init_math();
873
874
875 mach->Tokens = tokens;
876 mach->Sampler = sampler;
877 mach->Image = image;
878 mach->Buffer = buffer;
879
880 if (!tokens) {
881 /* unbind and free all */
882 FREE(mach->Declarations);
883 mach->Declarations = NULL;
884 mach->NumDeclarations = 0;
885
886 FREE(mach->Instructions);
887 mach->Instructions = NULL;
888 mach->NumInstructions = 0;
889
890 return;
891 }
892
893 k = tgsi_parse_init (&parse, mach->Tokens);
894 if (k != TGSI_PARSE_OK) {
895 debug_printf( "Problem parsing!\n" );
896 return;
897 }
898
899 mach->ImmLimit = 0;
900 mach->NumOutputs = 0;
901
902 for (k = 0; k < TGSI_SEMANTIC_COUNT; k++)
903 mach->SysSemanticToIndex[k] = -1;
904
905 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
906 !mach->UsedGeometryShader) {
907 struct tgsi_exec_vector *inputs;
908 struct tgsi_exec_vector *outputs;
909
910 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
911 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
912 16);
913
914 if (!inputs)
915 return;
916
917 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
918 TGSI_MAX_TOTAL_VERTICES, 16);
919
920 if (!outputs) {
921 align_free(inputs);
922 return;
923 }
924
925 align_free(mach->Inputs);
926 align_free(mach->Outputs);
927
928 mach->Inputs = inputs;
929 mach->Outputs = outputs;
930 mach->UsedGeometryShader = TRUE;
931 }
932
933 declarations = (struct tgsi_full_declaration *)
934 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
935
936 if (!declarations) {
937 return;
938 }
939
940 instructions = (struct tgsi_full_instruction *)
941 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
942
943 if (!instructions) {
944 FREE( declarations );
945 return;
946 }
947
948 while( !tgsi_parse_end_of_tokens( &parse ) ) {
949 uint i;
950
951 tgsi_parse_token( &parse );
952 switch( parse.FullToken.Token.Type ) {
953 case TGSI_TOKEN_TYPE_DECLARATION:
954 /* save expanded declaration */
955 if (numDeclarations == maxDeclarations) {
956 declarations = REALLOC(declarations,
957 maxDeclarations
958 * sizeof(struct tgsi_full_declaration),
959 (maxDeclarations + 10)
960 * sizeof(struct tgsi_full_declaration));
961 maxDeclarations += 10;
962 }
963 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
964 unsigned reg;
965 for (reg = parse.FullToken.FullDeclaration.Range.First;
966 reg <= parse.FullToken.FullDeclaration.Range.Last;
967 ++reg) {
968 ++mach->NumOutputs;
969 }
970 }
971 else if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
972 const struct tgsi_full_declaration *decl = &parse.FullToken.FullDeclaration;
973 mach->SysSemanticToIndex[decl->Semantic.Name] = decl->Range.First;
974 }
975
976 memcpy(declarations + numDeclarations,
977 &parse.FullToken.FullDeclaration,
978 sizeof(declarations[0]));
979 numDeclarations++;
980 break;
981
982 case TGSI_TOKEN_TYPE_IMMEDIATE:
983 {
984 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
985 assert( size <= 4 );
986 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
987
988 for( i = 0; i < size; i++ ) {
989 mach->Imms[mach->ImmLimit][i] =
990 parse.FullToken.FullImmediate.u[i].Float;
991 }
992 mach->ImmLimit += 1;
993 }
994 break;
995
996 case TGSI_TOKEN_TYPE_INSTRUCTION:
997
998 /* save expanded instruction */
999 if (numInstructions == maxInstructions) {
1000 instructions = REALLOC(instructions,
1001 maxInstructions
1002 * sizeof(struct tgsi_full_instruction),
1003 (maxInstructions + 10)
1004 * sizeof(struct tgsi_full_instruction));
1005 maxInstructions += 10;
1006 }
1007
1008 memcpy(instructions + numInstructions,
1009 &parse.FullToken.FullInstruction,
1010 sizeof(instructions[0]));
1011
1012 numInstructions++;
1013 break;
1014
1015 case TGSI_TOKEN_TYPE_PROPERTY:
1016 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1017 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1018 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1019 }
1020 }
1021 break;
1022
1023 default:
1024 assert( 0 );
1025 }
1026 }
1027 tgsi_parse_free (&parse);
1028
1029 FREE(mach->Declarations);
1030 mach->Declarations = declarations;
1031 mach->NumDeclarations = numDeclarations;
1032
1033 FREE(mach->Instructions);
1034 mach->Instructions = instructions;
1035 mach->NumInstructions = numInstructions;
1036 }
1037
1038
1039 struct tgsi_exec_machine *
1040 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1041 {
1042 struct tgsi_exec_machine *mach;
1043 uint i;
1044
1045 mach = align_malloc( sizeof *mach, 16 );
1046 if (!mach)
1047 goto fail;
1048
1049 memset(mach, 0, sizeof(*mach));
1050
1051 mach->ShaderType = shader_type;
1052 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1053 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1054 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1055
1056 if (shader_type != PIPE_SHADER_COMPUTE) {
1057 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1058 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1059 if (!mach->Inputs || !mach->Outputs)
1060 goto fail;
1061 }
1062
1063 /* Setup constants needed by the SSE2 executor. */
1064 for( i = 0; i < 4; i++ ) {
1065 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1066 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1067 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1068 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1069 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1070 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1071 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1072 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1073 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1074 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1075 }
1076
1077 #ifdef DEBUG
1078 /* silence warnings */
1079 (void) print_chan;
1080 (void) print_temp;
1081 #endif
1082
1083 return mach;
1084
1085 fail:
1086 if (mach) {
1087 align_free(mach->Inputs);
1088 align_free(mach->Outputs);
1089 align_free(mach);
1090 }
1091 return NULL;
1092 }
1093
1094
1095 void
1096 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1097 {
1098 if (mach) {
1099 FREE(mach->Instructions);
1100 FREE(mach->Declarations);
1101
1102 align_free(mach->Inputs);
1103 align_free(mach->Outputs);
1104
1105 align_free(mach);
1106 }
1107 }
1108
1109 static void
1110 micro_add(union tgsi_exec_channel *dst,
1111 const union tgsi_exec_channel *src0,
1112 const union tgsi_exec_channel *src1)
1113 {
1114 dst->f[0] = src0->f[0] + src1->f[0];
1115 dst->f[1] = src0->f[1] + src1->f[1];
1116 dst->f[2] = src0->f[2] + src1->f[2];
1117 dst->f[3] = src0->f[3] + src1->f[3];
1118 }
1119
1120 static void
1121 micro_div(
1122 union tgsi_exec_channel *dst,
1123 const union tgsi_exec_channel *src0,
1124 const union tgsi_exec_channel *src1 )
1125 {
1126 if (src1->f[0] != 0) {
1127 dst->f[0] = src0->f[0] / src1->f[0];
1128 }
1129 if (src1->f[1] != 0) {
1130 dst->f[1] = src0->f[1] / src1->f[1];
1131 }
1132 if (src1->f[2] != 0) {
1133 dst->f[2] = src0->f[2] / src1->f[2];
1134 }
1135 if (src1->f[3] != 0) {
1136 dst->f[3] = src0->f[3] / src1->f[3];
1137 }
1138 }
1139
1140 static void
1141 micro_lt(
1142 union tgsi_exec_channel *dst,
1143 const union tgsi_exec_channel *src0,
1144 const union tgsi_exec_channel *src1,
1145 const union tgsi_exec_channel *src2,
1146 const union tgsi_exec_channel *src3 )
1147 {
1148 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1149 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1150 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1151 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1152 }
1153
1154 static void
1155 micro_max(union tgsi_exec_channel *dst,
1156 const union tgsi_exec_channel *src0,
1157 const union tgsi_exec_channel *src1)
1158 {
1159 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1160 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1161 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1162 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1163 }
1164
1165 static void
1166 micro_min(union tgsi_exec_channel *dst,
1167 const union tgsi_exec_channel *src0,
1168 const union tgsi_exec_channel *src1)
1169 {
1170 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1171 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1172 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1173 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1174 }
1175
1176 static void
1177 micro_mul(union tgsi_exec_channel *dst,
1178 const union tgsi_exec_channel *src0,
1179 const union tgsi_exec_channel *src1)
1180 {
1181 dst->f[0] = src0->f[0] * src1->f[0];
1182 dst->f[1] = src0->f[1] * src1->f[1];
1183 dst->f[2] = src0->f[2] * src1->f[2];
1184 dst->f[3] = src0->f[3] * src1->f[3];
1185 }
1186
1187 static void
1188 micro_neg(
1189 union tgsi_exec_channel *dst,
1190 const union tgsi_exec_channel *src )
1191 {
1192 dst->f[0] = -src->f[0];
1193 dst->f[1] = -src->f[1];
1194 dst->f[2] = -src->f[2];
1195 dst->f[3] = -src->f[3];
1196 }
1197
1198 static void
1199 micro_pow(
1200 union tgsi_exec_channel *dst,
1201 const union tgsi_exec_channel *src0,
1202 const union tgsi_exec_channel *src1 )
1203 {
1204 #if FAST_MATH
1205 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1206 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1207 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1208 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1209 #else
1210 dst->f[0] = powf( src0->f[0], src1->f[0] );
1211 dst->f[1] = powf( src0->f[1], src1->f[1] );
1212 dst->f[2] = powf( src0->f[2], src1->f[2] );
1213 dst->f[3] = powf( src0->f[3], src1->f[3] );
1214 #endif
1215 }
1216
1217 static void
1218 micro_sub(union tgsi_exec_channel *dst,
1219 const union tgsi_exec_channel *src0,
1220 const union tgsi_exec_channel *src1)
1221 {
1222 dst->f[0] = src0->f[0] - src1->f[0];
1223 dst->f[1] = src0->f[1] - src1->f[1];
1224 dst->f[2] = src0->f[2] - src1->f[2];
1225 dst->f[3] = src0->f[3] - src1->f[3];
1226 }
1227
1228 static void
1229 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1230 const uint chan_index,
1231 const uint file,
1232 const uint swizzle,
1233 const union tgsi_exec_channel *index,
1234 const union tgsi_exec_channel *index2D,
1235 union tgsi_exec_channel *chan)
1236 {
1237 uint i;
1238
1239 assert(swizzle < 4);
1240
1241 switch (file) {
1242 case TGSI_FILE_CONSTANT:
1243 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1244 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1245 assert(mach->Consts[index2D->i[i]]);
1246
1247 if (index->i[i] < 0) {
1248 chan->u[i] = 0;
1249 } else {
1250 /* NOTE: copying the const value as a uint instead of float */
1251 const uint constbuf = index2D->i[i];
1252 const uint *buf = (const uint *)mach->Consts[constbuf];
1253 const int pos = index->i[i] * 4 + swizzle;
1254 /* const buffer bounds check */
1255 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1256 if (0) {
1257 /* Debug: print warning */
1258 static int count = 0;
1259 if (count++ < 100)
1260 debug_printf("TGSI Exec: const buffer index %d"
1261 " out of bounds\n", pos);
1262 }
1263 chan->u[i] = 0;
1264 }
1265 else
1266 chan->u[i] = buf[pos];
1267 }
1268 }
1269 break;
1270
1271 case TGSI_FILE_INPUT:
1272 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1273 /*
1274 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1275 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1276 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1277 index2D->i[i], index->i[i]);
1278 }*/
1279 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1280 assert(pos >= 0);
1281 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1282 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1283 }
1284 break;
1285
1286 case TGSI_FILE_SYSTEM_VALUE:
1287 /* XXX no swizzling at this point. Will be needed if we put
1288 * gl_FragCoord, for example, in a sys value register.
1289 */
1290 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1291 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1292 }
1293 break;
1294
1295 case TGSI_FILE_TEMPORARY:
1296 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1297 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1298 assert(index2D->i[i] == 0);
1299
1300 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1301 }
1302 break;
1303
1304 case TGSI_FILE_IMMEDIATE:
1305 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1306 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1307 assert(index2D->i[i] == 0);
1308
1309 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1310 }
1311 break;
1312
1313 case TGSI_FILE_ADDRESS:
1314 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1315 assert(index->i[i] >= 0);
1316 assert(index2D->i[i] == 0);
1317
1318 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1319 }
1320 break;
1321
1322 case TGSI_FILE_PREDICATE:
1323 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1324 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1325 assert(index2D->i[i] == 0);
1326
1327 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1328 }
1329 break;
1330
1331 case TGSI_FILE_OUTPUT:
1332 /* vertex/fragment output vars can be read too */
1333 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1334 assert(index->i[i] >= 0);
1335 assert(index2D->i[i] == 0);
1336
1337 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1338 }
1339 break;
1340
1341 default:
1342 assert(0);
1343 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1344 chan->u[i] = 0;
1345 }
1346 }
1347 }
1348
1349 static void
1350 fetch_source_d(const struct tgsi_exec_machine *mach,
1351 union tgsi_exec_channel *chan,
1352 const struct tgsi_full_src_register *reg,
1353 const uint chan_index,
1354 enum tgsi_exec_datatype src_datatype)
1355 {
1356 union tgsi_exec_channel index;
1357 union tgsi_exec_channel index2D;
1358 uint swizzle;
1359
1360 /* We start with a direct index into a register file.
1361 *
1362 * file[1],
1363 * where:
1364 * file = Register.File
1365 * [1] = Register.Index
1366 */
1367 index.i[0] =
1368 index.i[1] =
1369 index.i[2] =
1370 index.i[3] = reg->Register.Index;
1371
1372 /* There is an extra source register that indirectly subscripts
1373 * a register file. The direct index now becomes an offset
1374 * that is being added to the indirect register.
1375 *
1376 * file[ind[2].x+1],
1377 * where:
1378 * ind = Indirect.File
1379 * [2] = Indirect.Index
1380 * .x = Indirect.SwizzleX
1381 */
1382 if (reg->Register.Indirect) {
1383 union tgsi_exec_channel index2;
1384 union tgsi_exec_channel indir_index;
1385 const uint execmask = mach->ExecMask;
1386 uint i;
1387
1388 /* which address register (always zero now) */
1389 index2.i[0] =
1390 index2.i[1] =
1391 index2.i[2] =
1392 index2.i[3] = reg->Indirect.Index;
1393 /* get current value of address register[swizzle] */
1394 swizzle = reg->Indirect.Swizzle;
1395 fetch_src_file_channel(mach,
1396 chan_index,
1397 reg->Indirect.File,
1398 swizzle,
1399 &index2,
1400 &ZeroVec,
1401 &indir_index);
1402
1403 /* add value of address register to the offset */
1404 index.i[0] += indir_index.i[0];
1405 index.i[1] += indir_index.i[1];
1406 index.i[2] += indir_index.i[2];
1407 index.i[3] += indir_index.i[3];
1408
1409 /* for disabled execution channels, zero-out the index to
1410 * avoid using a potential garbage value.
1411 */
1412 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1413 if ((execmask & (1 << i)) == 0)
1414 index.i[i] = 0;
1415 }
1416 }
1417
1418 /* There is an extra source register that is a second
1419 * subscript to a register file. Effectively it means that
1420 * the register file is actually a 2D array of registers.
1421 *
1422 * file[3][1],
1423 * where:
1424 * [3] = Dimension.Index
1425 */
1426 if (reg->Register.Dimension) {
1427 index2D.i[0] =
1428 index2D.i[1] =
1429 index2D.i[2] =
1430 index2D.i[3] = reg->Dimension.Index;
1431
1432 /* Again, the second subscript index can be addressed indirectly
1433 * identically to the first one.
1434 * Nothing stops us from indirectly addressing the indirect register,
1435 * but there is no need for that, so we won't exercise it.
1436 *
1437 * file[ind[4].y+3][1],
1438 * where:
1439 * ind = DimIndirect.File
1440 * [4] = DimIndirect.Index
1441 * .y = DimIndirect.SwizzleX
1442 */
1443 if (reg->Dimension.Indirect) {
1444 union tgsi_exec_channel index2;
1445 union tgsi_exec_channel indir_index;
1446 const uint execmask = mach->ExecMask;
1447 uint i;
1448
1449 index2.i[0] =
1450 index2.i[1] =
1451 index2.i[2] =
1452 index2.i[3] = reg->DimIndirect.Index;
1453
1454 swizzle = reg->DimIndirect.Swizzle;
1455 fetch_src_file_channel(mach,
1456 chan_index,
1457 reg->DimIndirect.File,
1458 swizzle,
1459 &index2,
1460 &ZeroVec,
1461 &indir_index);
1462
1463 index2D.i[0] += indir_index.i[0];
1464 index2D.i[1] += indir_index.i[1];
1465 index2D.i[2] += indir_index.i[2];
1466 index2D.i[3] += indir_index.i[3];
1467
1468 /* for disabled execution channels, zero-out the index to
1469 * avoid using a potential garbage value.
1470 */
1471 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1472 if ((execmask & (1 << i)) == 0) {
1473 index2D.i[i] = 0;
1474 }
1475 }
1476 }
1477
1478 /* If by any chance there was a need for a 3D array of register
1479 * files, we would have to check whether Dimension is followed
1480 * by a dimension register and continue the saga.
1481 */
1482 } else {
1483 index2D.i[0] =
1484 index2D.i[1] =
1485 index2D.i[2] =
1486 index2D.i[3] = 0;
1487 }
1488
1489 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1490 fetch_src_file_channel(mach,
1491 chan_index,
1492 reg->Register.File,
1493 swizzle,
1494 &index,
1495 &index2D,
1496 chan);
1497 }
1498
1499 static void
1500 fetch_source(const struct tgsi_exec_machine *mach,
1501 union tgsi_exec_channel *chan,
1502 const struct tgsi_full_src_register *reg,
1503 const uint chan_index,
1504 enum tgsi_exec_datatype src_datatype)
1505 {
1506 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1507
1508 if (reg->Register.Absolute) {
1509 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1510 micro_abs(chan, chan);
1511 } else {
1512 micro_iabs(chan, chan);
1513 }
1514 }
1515
1516 if (reg->Register.Negate) {
1517 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1518 micro_neg(chan, chan);
1519 } else {
1520 micro_ineg(chan, chan);
1521 }
1522 }
1523 }
1524
1525 static union tgsi_exec_channel *
1526 store_dest_dstret(struct tgsi_exec_machine *mach,
1527 const union tgsi_exec_channel *chan,
1528 const struct tgsi_full_dst_register *reg,
1529 const struct tgsi_full_instruction *inst,
1530 uint chan_index,
1531 enum tgsi_exec_datatype dst_datatype)
1532 {
1533 uint i;
1534 static union tgsi_exec_channel null;
1535 union tgsi_exec_channel *dst;
1536 union tgsi_exec_channel index2D;
1537 uint execmask = mach->ExecMask;
1538 int offset = 0; /* indirection offset */
1539 int index;
1540
1541 /* for debugging */
1542 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1543 check_inf_or_nan(chan);
1544 }
1545
1546 /* There is an extra source register that indirectly subscripts
1547 * a register file. The direct index now becomes an offset
1548 * that is being added to the indirect register.
1549 *
1550 * file[ind[2].x+1],
1551 * where:
1552 * ind = Indirect.File
1553 * [2] = Indirect.Index
1554 * .x = Indirect.SwizzleX
1555 */
1556 if (reg->Register.Indirect) {
1557 union tgsi_exec_channel index;
1558 union tgsi_exec_channel indir_index;
1559 uint swizzle;
1560
1561 /* which address register (always zero for now) */
1562 index.i[0] =
1563 index.i[1] =
1564 index.i[2] =
1565 index.i[3] = reg->Indirect.Index;
1566
1567 /* get current value of address register[swizzle] */
1568 swizzle = reg->Indirect.Swizzle;
1569
1570 /* fetch values from the address/indirection register */
1571 fetch_src_file_channel(mach,
1572 chan_index,
1573 reg->Indirect.File,
1574 swizzle,
1575 &index,
1576 &ZeroVec,
1577 &indir_index);
1578
1579 /* save indirection offset */
1580 offset = indir_index.i[0];
1581 }
1582
1583 /* There is an extra source register that is a second
1584 * subscript to a register file. Effectively it means that
1585 * the register file is actually a 2D array of registers.
1586 *
1587 * file[3][1],
1588 * where:
1589 * [3] = Dimension.Index
1590 */
1591 if (reg->Register.Dimension) {
1592 index2D.i[0] =
1593 index2D.i[1] =
1594 index2D.i[2] =
1595 index2D.i[3] = reg->Dimension.Index;
1596
1597 /* Again, the second subscript index can be addressed indirectly
1598 * identically to the first one.
1599 * Nothing stops us from indirectly addressing the indirect register,
1600 * but there is no need for that, so we won't exercise it.
1601 *
1602 * file[ind[4].y+3][1],
1603 * where:
1604 * ind = DimIndirect.File
1605 * [4] = DimIndirect.Index
1606 * .y = DimIndirect.SwizzleX
1607 */
1608 if (reg->Dimension.Indirect) {
1609 union tgsi_exec_channel index2;
1610 union tgsi_exec_channel indir_index;
1611 const uint execmask = mach->ExecMask;
1612 unsigned swizzle;
1613 uint i;
1614
1615 index2.i[0] =
1616 index2.i[1] =
1617 index2.i[2] =
1618 index2.i[3] = reg->DimIndirect.Index;
1619
1620 swizzle = reg->DimIndirect.Swizzle;
1621 fetch_src_file_channel(mach,
1622 chan_index,
1623 reg->DimIndirect.File,
1624 swizzle,
1625 &index2,
1626 &ZeroVec,
1627 &indir_index);
1628
1629 index2D.i[0] += indir_index.i[0];
1630 index2D.i[1] += indir_index.i[1];
1631 index2D.i[2] += indir_index.i[2];
1632 index2D.i[3] += indir_index.i[3];
1633
1634 /* for disabled execution channels, zero-out the index to
1635 * avoid using a potential garbage value.
1636 */
1637 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1638 if ((execmask & (1 << i)) == 0) {
1639 index2D.i[i] = 0;
1640 }
1641 }
1642 }
1643
1644 /* If by any chance there was a need for a 3D array of register
1645 * files, we would have to check whether Dimension is followed
1646 * by a dimension register and continue the saga.
1647 */
1648 } else {
1649 index2D.i[0] =
1650 index2D.i[1] =
1651 index2D.i[2] =
1652 index2D.i[3] = 0;
1653 }
1654
1655 switch (reg->Register.File) {
1656 case TGSI_FILE_NULL:
1657 dst = &null;
1658 break;
1659
1660 case TGSI_FILE_OUTPUT:
1661 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1662 + reg->Register.Index;
1663 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1664 #if 0
1665 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1666 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1667 reg->Register.Index);
1668 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1669 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1670 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1671 if (execmask & (1 << i))
1672 debug_printf("%f, ", chan->f[i]);
1673 debug_printf(")\n");
1674 }
1675 #endif
1676 break;
1677
1678 case TGSI_FILE_TEMPORARY:
1679 index = reg->Register.Index;
1680 assert( index < TGSI_EXEC_NUM_TEMPS );
1681 dst = &mach->Temps[offset + index].xyzw[chan_index];
1682 break;
1683
1684 case TGSI_FILE_ADDRESS:
1685 index = reg->Register.Index;
1686 dst = &mach->Addrs[index].xyzw[chan_index];
1687 break;
1688
1689 case TGSI_FILE_PREDICATE:
1690 index = reg->Register.Index;
1691 assert(index < TGSI_EXEC_NUM_PREDS);
1692 dst = &mach->Predicates[index].xyzw[chan_index];
1693 break;
1694
1695 default:
1696 assert( 0 );
1697 return NULL;
1698 }
1699
1700 if (inst->Instruction.Predicate) {
1701 uint swizzle;
1702 union tgsi_exec_channel *pred;
1703
1704 switch (chan_index) {
1705 case TGSI_CHAN_X:
1706 swizzle = inst->Predicate.SwizzleX;
1707 break;
1708 case TGSI_CHAN_Y:
1709 swizzle = inst->Predicate.SwizzleY;
1710 break;
1711 case TGSI_CHAN_Z:
1712 swizzle = inst->Predicate.SwizzleZ;
1713 break;
1714 case TGSI_CHAN_W:
1715 swizzle = inst->Predicate.SwizzleW;
1716 break;
1717 default:
1718 assert(0);
1719 return NULL;
1720 }
1721
1722 assert(inst->Predicate.Index == 0);
1723
1724 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1725
1726 if (inst->Predicate.Negate) {
1727 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1728 if (pred->u[i]) {
1729 execmask &= ~(1 << i);
1730 }
1731 }
1732 } else {
1733 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1734 if (!pred->u[i]) {
1735 execmask &= ~(1 << i);
1736 }
1737 }
1738 }
1739 }
1740
1741 return dst;
1742 }
1743
1744 static void
1745 store_dest_double(struct tgsi_exec_machine *mach,
1746 const union tgsi_exec_channel *chan,
1747 const struct tgsi_full_dst_register *reg,
1748 const struct tgsi_full_instruction *inst,
1749 uint chan_index,
1750 enum tgsi_exec_datatype dst_datatype)
1751 {
1752 union tgsi_exec_channel *dst;
1753 const uint execmask = mach->ExecMask;
1754 int i;
1755
1756 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1757 dst_datatype);
1758 if (!dst)
1759 return;
1760
1761 /* doubles path */
1762 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1763 if (execmask & (1 << i))
1764 dst->i[i] = chan->i[i];
1765 }
1766
1767 static void
1768 store_dest(struct tgsi_exec_machine *mach,
1769 const union tgsi_exec_channel *chan,
1770 const struct tgsi_full_dst_register *reg,
1771 const struct tgsi_full_instruction *inst,
1772 uint chan_index,
1773 enum tgsi_exec_datatype dst_datatype)
1774 {
1775 union tgsi_exec_channel *dst;
1776 const uint execmask = mach->ExecMask;
1777 int i;
1778
1779 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1780 dst_datatype);
1781 if (!dst)
1782 return;
1783
1784 if (!inst->Instruction.Saturate) {
1785 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1786 if (execmask & (1 << i))
1787 dst->i[i] = chan->i[i];
1788 }
1789 else {
1790 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1791 if (execmask & (1 << i)) {
1792 if (chan->f[i] < 0.0f)
1793 dst->f[i] = 0.0f;
1794 else if (chan->f[i] > 1.0f)
1795 dst->f[i] = 1.0f;
1796 else
1797 dst->i[i] = chan->i[i];
1798 }
1799 }
1800 }
1801
1802 #define FETCH(VAL,INDEX,CHAN)\
1803 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1804
1805 #define IFETCH(VAL,INDEX,CHAN)\
1806 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1807
1808
1809 /**
1810 * Execute ARB-style KIL which is predicated by a src register.
1811 * Kill fragment if any of the four values is less than zero.
1812 */
1813 static void
1814 exec_kill_if(struct tgsi_exec_machine *mach,
1815 const struct tgsi_full_instruction *inst)
1816 {
1817 uint uniquemask;
1818 uint chan_index;
1819 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1820 union tgsi_exec_channel r[1];
1821
1822 /* This mask stores component bits that were already tested. */
1823 uniquemask = 0;
1824
1825 for (chan_index = 0; chan_index < 4; chan_index++)
1826 {
1827 uint swizzle;
1828 uint i;
1829
1830 /* unswizzle channel */
1831 swizzle = tgsi_util_get_full_src_register_swizzle (
1832 &inst->Src[0],
1833 chan_index);
1834
1835 /* check if the component has not been already tested */
1836 if (uniquemask & (1 << swizzle))
1837 continue;
1838 uniquemask |= 1 << swizzle;
1839
1840 FETCH(&r[0], 0, chan_index);
1841 for (i = 0; i < 4; i++)
1842 if (r[0].f[i] < 0.0f)
1843 kilmask |= 1 << i;
1844 }
1845
1846 /* restrict to fragments currently executing */
1847 kilmask &= mach->ExecMask;
1848
1849 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1850 }
1851
1852 /**
1853 * Unconditional fragment kill/discard.
1854 */
1855 static void
1856 exec_kill(struct tgsi_exec_machine *mach,
1857 const struct tgsi_full_instruction *inst)
1858 {
1859 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1860
1861 /* kill fragment for all fragments currently executing */
1862 kilmask = mach->ExecMask;
1863 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1864 }
1865
1866 static void
1867 emit_vertex(struct tgsi_exec_machine *mach)
1868 {
1869 /* FIXME: check for exec mask correctly
1870 unsigned i;
1871 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1872 if ((mach->ExecMask & (1 << i)))
1873 */
1874 if (mach->ExecMask) {
1875 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1876 return;
1877
1878 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1879 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1880 }
1881 }
1882
1883 static void
1884 emit_primitive(struct tgsi_exec_machine *mach)
1885 {
1886 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1887 /* FIXME: check for exec mask correctly
1888 unsigned i;
1889 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1890 if ((mach->ExecMask & (1 << i)))
1891 */
1892 if (mach->ExecMask) {
1893 ++(*prim_count);
1894 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1895 mach->Primitives[*prim_count] = 0;
1896 }
1897 }
1898
1899 static void
1900 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1901 {
1902 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1903 int emitted_verts =
1904 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1905 if (emitted_verts) {
1906 emit_primitive(mach);
1907 }
1908 }
1909 }
1910
1911
1912 /*
1913 * Fetch four texture samples using STR texture coordinates.
1914 */
1915 static void
1916 fetch_texel( struct tgsi_sampler *sampler,
1917 const unsigned sview_idx,
1918 const unsigned sampler_idx,
1919 const union tgsi_exec_channel *s,
1920 const union tgsi_exec_channel *t,
1921 const union tgsi_exec_channel *p,
1922 const union tgsi_exec_channel *c0,
1923 const union tgsi_exec_channel *c1,
1924 float derivs[3][2][TGSI_QUAD_SIZE],
1925 const int8_t offset[3],
1926 enum tgsi_sampler_control control,
1927 union tgsi_exec_channel *r,
1928 union tgsi_exec_channel *g,
1929 union tgsi_exec_channel *b,
1930 union tgsi_exec_channel *a )
1931 {
1932 uint j;
1933 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1934
1935 /* FIXME: handle explicit derivs, offsets */
1936 sampler->get_samples(sampler, sview_idx, sampler_idx,
1937 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1938
1939 for (j = 0; j < 4; j++) {
1940 r->f[j] = rgba[0][j];
1941 g->f[j] = rgba[1][j];
1942 b->f[j] = rgba[2][j];
1943 a->f[j] = rgba[3][j];
1944 }
1945 }
1946
1947
1948 #define TEX_MODIFIER_NONE 0
1949 #define TEX_MODIFIER_PROJECTED 1
1950 #define TEX_MODIFIER_LOD_BIAS 2
1951 #define TEX_MODIFIER_EXPLICIT_LOD 3
1952 #define TEX_MODIFIER_LEVEL_ZERO 4
1953 #define TEX_MODIFIER_GATHER 5
1954
1955 /*
1956 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1957 */
1958 static void
1959 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1960 const struct tgsi_full_instruction *inst,
1961 int8_t offsets[3])
1962 {
1963 if (inst->Texture.NumOffsets == 1) {
1964 union tgsi_exec_channel index;
1965 union tgsi_exec_channel offset[3];
1966 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1967 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1968 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1969 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1970 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1971 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1972 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1973 offsets[0] = offset[0].i[0];
1974 offsets[1] = offset[1].i[0];
1975 offsets[2] = offset[2].i[0];
1976 } else {
1977 assert(inst->Texture.NumOffsets == 0);
1978 offsets[0] = offsets[1] = offsets[2] = 0;
1979 }
1980 }
1981
1982
1983 /*
1984 * Fetch dx and dy values for one channel (s, t or r).
1985 * Put dx values into one float array, dy values into another.
1986 */
1987 static void
1988 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1989 const struct tgsi_full_instruction *inst,
1990 unsigned regdsrcx,
1991 unsigned chan,
1992 float derivs[2][TGSI_QUAD_SIZE])
1993 {
1994 union tgsi_exec_channel d;
1995 FETCH(&d, regdsrcx, chan);
1996 derivs[0][0] = d.f[0];
1997 derivs[0][1] = d.f[1];
1998 derivs[0][2] = d.f[2];
1999 derivs[0][3] = d.f[3];
2000 FETCH(&d, regdsrcx + 1, chan);
2001 derivs[1][0] = d.f[0];
2002 derivs[1][1] = d.f[1];
2003 derivs[1][2] = d.f[2];
2004 derivs[1][3] = d.f[3];
2005 }
2006
2007 static uint
2008 fetch_sampler_unit(struct tgsi_exec_machine *mach,
2009 const struct tgsi_full_instruction *inst,
2010 uint sampler)
2011 {
2012 uint unit = 0;
2013 int i;
2014 if (inst->Src[sampler].Register.Indirect) {
2015 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2016 union tgsi_exec_channel indir_index, index2;
2017 const uint execmask = mach->ExecMask;
2018 index2.i[0] =
2019 index2.i[1] =
2020 index2.i[2] =
2021 index2.i[3] = reg->Indirect.Index;
2022
2023 fetch_src_file_channel(mach,
2024 0,
2025 reg->Indirect.File,
2026 reg->Indirect.Swizzle,
2027 &index2,
2028 &ZeroVec,
2029 &indir_index);
2030 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2031 if (execmask & (1 << i)) {
2032 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2033 break;
2034 }
2035 }
2036
2037 } else {
2038 unit = inst->Src[sampler].Register.Index;
2039 }
2040 return unit;
2041 }
2042
2043 /*
2044 * execute a texture instruction.
2045 *
2046 * modifier is used to control the channel routing for the
2047 * instruction variants like proj, lod, and texture with lod bias.
2048 * sampler indicates which src register the sampler is contained in.
2049 */
2050 static void
2051 exec_tex(struct tgsi_exec_machine *mach,
2052 const struct tgsi_full_instruction *inst,
2053 uint modifier, uint sampler)
2054 {
2055 const union tgsi_exec_channel *args[5], *proj = NULL;
2056 union tgsi_exec_channel r[5];
2057 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2058 uint chan;
2059 uint unit;
2060 int8_t offsets[3];
2061 int dim, shadow_ref, i;
2062
2063 unit = fetch_sampler_unit(mach, inst, sampler);
2064 /* always fetch all 3 offsets, overkill but keeps code simple */
2065 fetch_texel_offsets(mach, inst, offsets);
2066
2067 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2068 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2069
2070 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2071 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2072
2073 assert(dim <= 4);
2074 if (shadow_ref >= 0)
2075 assert(shadow_ref >= dim && shadow_ref < ARRAY_SIZE(args));
2076
2077 /* fetch modifier to the last argument */
2078 if (modifier != TEX_MODIFIER_NONE) {
2079 const int last = ARRAY_SIZE(args) - 1;
2080
2081 /* fetch modifier from src0.w or src1.x */
2082 if (sampler == 1) {
2083 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2084 FETCH(&r[last], 0, TGSI_CHAN_W);
2085 }
2086 else {
2087 assert(shadow_ref != 4);
2088 FETCH(&r[last], 1, TGSI_CHAN_X);
2089 }
2090
2091 if (modifier != TEX_MODIFIER_PROJECTED) {
2092 args[last] = &r[last];
2093 }
2094 else {
2095 proj = &r[last];
2096 args[last] = &ZeroVec;
2097 }
2098
2099 /* point unused arguments to zero vector */
2100 for (i = dim; i < last; i++)
2101 args[i] = &ZeroVec;
2102
2103 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2104 control = TGSI_SAMPLER_LOD_EXPLICIT;
2105 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2106 control = TGSI_SAMPLER_LOD_BIAS;
2107 else if (modifier == TEX_MODIFIER_GATHER)
2108 control = TGSI_SAMPLER_GATHER;
2109 }
2110 else {
2111 for (i = dim; i < ARRAY_SIZE(args); i++)
2112 args[i] = &ZeroVec;
2113 }
2114
2115 /* fetch coordinates */
2116 for (i = 0; i < dim; i++) {
2117 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2118
2119 if (proj)
2120 micro_div(&r[i], &r[i], proj);
2121
2122 args[i] = &r[i];
2123 }
2124
2125 /* fetch reference value */
2126 if (shadow_ref >= 0) {
2127 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2128
2129 if (proj)
2130 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2131
2132 args[shadow_ref] = &r[shadow_ref];
2133 }
2134
2135 fetch_texel(mach->Sampler, unit, unit,
2136 args[0], args[1], args[2], args[3], args[4],
2137 NULL, offsets, control,
2138 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2139
2140 #if 0
2141 debug_printf("fetch r: %g %g %g %g\n",
2142 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2143 debug_printf("fetch g: %g %g %g %g\n",
2144 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2145 debug_printf("fetch b: %g %g %g %g\n",
2146 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2147 debug_printf("fetch a: %g %g %g %g\n",
2148 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2149 #endif
2150
2151 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2152 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2153 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2154 }
2155 }
2156 }
2157
2158 static void
2159 exec_lodq(struct tgsi_exec_machine *mach,
2160 const struct tgsi_full_instruction *inst)
2161 {
2162 uint unit;
2163 int dim;
2164 int i;
2165 union tgsi_exec_channel coords[4];
2166 const union tgsi_exec_channel *args[ARRAY_SIZE(coords)];
2167 union tgsi_exec_channel r[2];
2168
2169 unit = fetch_sampler_unit(mach, inst, 1);
2170 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2171 assert(dim <= ARRAY_SIZE(coords));
2172 /* fetch coordinates */
2173 for (i = 0; i < dim; i++) {
2174 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2175 args[i] = &coords[i];
2176 }
2177 for (i = dim; i < ARRAY_SIZE(coords); i++) {
2178 args[i] = &ZeroVec;
2179 }
2180 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2181 args[0]->f,
2182 args[1]->f,
2183 args[2]->f,
2184 args[3]->f,
2185 TGSI_SAMPLER_LOD_NONE,
2186 r[0].f,
2187 r[1].f);
2188
2189 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2190 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2191 TGSI_EXEC_DATA_FLOAT);
2192 }
2193 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2194 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2195 TGSI_EXEC_DATA_FLOAT);
2196 }
2197 }
2198
2199 static void
2200 exec_txd(struct tgsi_exec_machine *mach,
2201 const struct tgsi_full_instruction *inst)
2202 {
2203 union tgsi_exec_channel r[4];
2204 float derivs[3][2][TGSI_QUAD_SIZE];
2205 uint chan;
2206 uint unit;
2207 int8_t offsets[3];
2208
2209 unit = fetch_sampler_unit(mach, inst, 3);
2210 /* always fetch all 3 offsets, overkill but keeps code simple */
2211 fetch_texel_offsets(mach, inst, offsets);
2212
2213 switch (inst->Texture.Texture) {
2214 case TGSI_TEXTURE_1D:
2215 FETCH(&r[0], 0, TGSI_CHAN_X);
2216
2217 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2218
2219 fetch_texel(mach->Sampler, unit, unit,
2220 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2221 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2222 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2223 break;
2224
2225 case TGSI_TEXTURE_SHADOW1D:
2226 case TGSI_TEXTURE_1D_ARRAY:
2227 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2228 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2229 FETCH(&r[0], 0, TGSI_CHAN_X);
2230 FETCH(&r[1], 0, TGSI_CHAN_Y);
2231 FETCH(&r[2], 0, TGSI_CHAN_Z);
2232
2233 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2234
2235 fetch_texel(mach->Sampler, unit, unit,
2236 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2237 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2238 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2239 break;
2240
2241 case TGSI_TEXTURE_2D:
2242 case TGSI_TEXTURE_RECT:
2243 FETCH(&r[0], 0, TGSI_CHAN_X);
2244 FETCH(&r[1], 0, TGSI_CHAN_Y);
2245
2246 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2247 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2248
2249 fetch_texel(mach->Sampler, unit, unit,
2250 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2251 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2252 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2253 break;
2254
2255
2256 case TGSI_TEXTURE_SHADOW2D:
2257 case TGSI_TEXTURE_SHADOWRECT:
2258 case TGSI_TEXTURE_2D_ARRAY:
2259 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2260 /* only SHADOW2D_ARRAY actually needs W */
2261 FETCH(&r[0], 0, TGSI_CHAN_X);
2262 FETCH(&r[1], 0, TGSI_CHAN_Y);
2263 FETCH(&r[2], 0, TGSI_CHAN_Z);
2264 FETCH(&r[3], 0, TGSI_CHAN_W);
2265
2266 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2267 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2268
2269 fetch_texel(mach->Sampler, unit, unit,
2270 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2271 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2272 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2273 break;
2274
2275 case TGSI_TEXTURE_3D:
2276 case TGSI_TEXTURE_CUBE:
2277 case TGSI_TEXTURE_CUBE_ARRAY:
2278 case TGSI_TEXTURE_SHADOWCUBE:
2279 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2280 FETCH(&r[0], 0, TGSI_CHAN_X);
2281 FETCH(&r[1], 0, TGSI_CHAN_Y);
2282 FETCH(&r[2], 0, TGSI_CHAN_Z);
2283 FETCH(&r[3], 0, TGSI_CHAN_W);
2284
2285 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2286 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2287 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2288
2289 fetch_texel(mach->Sampler, unit, unit,
2290 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2291 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2292 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2293 break;
2294
2295 default:
2296 assert(0);
2297 }
2298
2299 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2300 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2301 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2302 }
2303 }
2304 }
2305
2306
2307 static void
2308 exec_txf(struct tgsi_exec_machine *mach,
2309 const struct tgsi_full_instruction *inst)
2310 {
2311 union tgsi_exec_channel r[4];
2312 uint chan;
2313 uint unit;
2314 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2315 int j;
2316 int8_t offsets[3];
2317 unsigned target;
2318
2319 unit = fetch_sampler_unit(mach, inst, 1);
2320 /* always fetch all 3 offsets, overkill but keeps code simple */
2321 fetch_texel_offsets(mach, inst, offsets);
2322
2323 IFETCH(&r[3], 0, TGSI_CHAN_W);
2324
2325 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2326 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2327 target = mach->SamplerViews[unit].Resource;
2328 }
2329 else {
2330 target = inst->Texture.Texture;
2331 }
2332 switch(target) {
2333 case TGSI_TEXTURE_3D:
2334 case TGSI_TEXTURE_2D_ARRAY:
2335 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2336 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2337 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2338 /* fallthrough */
2339 case TGSI_TEXTURE_2D:
2340 case TGSI_TEXTURE_RECT:
2341 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2342 case TGSI_TEXTURE_SHADOW2D:
2343 case TGSI_TEXTURE_SHADOWRECT:
2344 case TGSI_TEXTURE_1D_ARRAY:
2345 case TGSI_TEXTURE_2D_MSAA:
2346 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2347 /* fallthrough */
2348 case TGSI_TEXTURE_BUFFER:
2349 case TGSI_TEXTURE_1D:
2350 case TGSI_TEXTURE_SHADOW1D:
2351 IFETCH(&r[0], 0, TGSI_CHAN_X);
2352 break;
2353 default:
2354 assert(0);
2355 break;
2356 }
2357
2358 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2359 offsets, rgba);
2360
2361 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2362 r[0].f[j] = rgba[0][j];
2363 r[1].f[j] = rgba[1][j];
2364 r[2].f[j] = rgba[2][j];
2365 r[3].f[j] = rgba[3][j];
2366 }
2367
2368 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2369 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2370 unsigned char swizzles[4];
2371 swizzles[0] = inst->Src[1].Register.SwizzleX;
2372 swizzles[1] = inst->Src[1].Register.SwizzleY;
2373 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2374 swizzles[3] = inst->Src[1].Register.SwizzleW;
2375
2376 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2377 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2378 store_dest(mach, &r[swizzles[chan]],
2379 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2380 }
2381 }
2382 }
2383 else {
2384 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2385 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2386 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2387 }
2388 }
2389 }
2390 }
2391
2392 static void
2393 exec_txq(struct tgsi_exec_machine *mach,
2394 const struct tgsi_full_instruction *inst)
2395 {
2396 int result[4];
2397 union tgsi_exec_channel r[4], src;
2398 uint chan;
2399 uint unit;
2400 int i,j;
2401
2402 unit = fetch_sampler_unit(mach, inst, 1);
2403
2404 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2405
2406 /* XXX: This interface can't return per-pixel values */
2407 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2408
2409 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2410 for (j = 0; j < 4; j++) {
2411 r[j].i[i] = result[j];
2412 }
2413 }
2414
2415 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2416 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2417 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2418 TGSI_EXEC_DATA_INT);
2419 }
2420 }
2421 }
2422
2423 static void
2424 exec_sample(struct tgsi_exec_machine *mach,
2425 const struct tgsi_full_instruction *inst,
2426 uint modifier, boolean compare)
2427 {
2428 const uint resource_unit = inst->Src[1].Register.Index;
2429 const uint sampler_unit = inst->Src[2].Register.Index;
2430 union tgsi_exec_channel r[5], c1;
2431 const union tgsi_exec_channel *lod = &ZeroVec;
2432 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2433 uint chan;
2434 unsigned char swizzles[4];
2435 int8_t offsets[3];
2436
2437 /* always fetch all 3 offsets, overkill but keeps code simple */
2438 fetch_texel_offsets(mach, inst, offsets);
2439
2440 assert(modifier != TEX_MODIFIER_PROJECTED);
2441
2442 if (modifier != TEX_MODIFIER_NONE) {
2443 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2444 FETCH(&c1, 3, TGSI_CHAN_X);
2445 lod = &c1;
2446 control = TGSI_SAMPLER_LOD_BIAS;
2447 }
2448 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2449 FETCH(&c1, 3, TGSI_CHAN_X);
2450 lod = &c1;
2451 control = TGSI_SAMPLER_LOD_EXPLICIT;
2452 }
2453 else {
2454 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2455 control = TGSI_SAMPLER_LOD_ZERO;
2456 }
2457 }
2458
2459 FETCH(&r[0], 0, TGSI_CHAN_X);
2460
2461 switch (mach->SamplerViews[resource_unit].Resource) {
2462 case TGSI_TEXTURE_1D:
2463 if (compare) {
2464 FETCH(&r[2], 3, TGSI_CHAN_X);
2465 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2466 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2467 NULL, offsets, control,
2468 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2469 }
2470 else {
2471 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2472 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2473 NULL, offsets, control,
2474 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2475 }
2476 break;
2477
2478 case TGSI_TEXTURE_1D_ARRAY:
2479 case TGSI_TEXTURE_2D:
2480 case TGSI_TEXTURE_RECT:
2481 FETCH(&r[1], 0, TGSI_CHAN_Y);
2482 if (compare) {
2483 FETCH(&r[2], 3, TGSI_CHAN_X);
2484 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2485 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2486 NULL, offsets, control,
2487 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2488 }
2489 else {
2490 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2491 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2492 NULL, offsets, control,
2493 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2494 }
2495 break;
2496
2497 case TGSI_TEXTURE_2D_ARRAY:
2498 case TGSI_TEXTURE_3D:
2499 case TGSI_TEXTURE_CUBE:
2500 FETCH(&r[1], 0, TGSI_CHAN_Y);
2501 FETCH(&r[2], 0, TGSI_CHAN_Z);
2502 if(compare) {
2503 FETCH(&r[3], 3, TGSI_CHAN_X);
2504 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2505 &r[0], &r[1], &r[2], &r[3], lod,
2506 NULL, offsets, control,
2507 &r[0], &r[1], &r[2], &r[3]);
2508 }
2509 else {
2510 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2511 &r[0], &r[1], &r[2], &ZeroVec, lod,
2512 NULL, offsets, control,
2513 &r[0], &r[1], &r[2], &r[3]);
2514 }
2515 break;
2516
2517 case TGSI_TEXTURE_CUBE_ARRAY:
2518 FETCH(&r[1], 0, TGSI_CHAN_Y);
2519 FETCH(&r[2], 0, TGSI_CHAN_Z);
2520 FETCH(&r[3], 0, TGSI_CHAN_W);
2521 if(compare) {
2522 FETCH(&r[4], 3, TGSI_CHAN_X);
2523 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2524 &r[0], &r[1], &r[2], &r[3], &r[4],
2525 NULL, offsets, control,
2526 &r[0], &r[1], &r[2], &r[3]);
2527 }
2528 else {
2529 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2530 &r[0], &r[1], &r[2], &r[3], lod,
2531 NULL, offsets, control,
2532 &r[0], &r[1], &r[2], &r[3]);
2533 }
2534 break;
2535
2536
2537 default:
2538 assert(0);
2539 }
2540
2541 swizzles[0] = inst->Src[1].Register.SwizzleX;
2542 swizzles[1] = inst->Src[1].Register.SwizzleY;
2543 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2544 swizzles[3] = inst->Src[1].Register.SwizzleW;
2545
2546 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2547 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2548 store_dest(mach, &r[swizzles[chan]],
2549 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2550 }
2551 }
2552 }
2553
2554 static void
2555 exec_sample_d(struct tgsi_exec_machine *mach,
2556 const struct tgsi_full_instruction *inst)
2557 {
2558 const uint resource_unit = inst->Src[1].Register.Index;
2559 const uint sampler_unit = inst->Src[2].Register.Index;
2560 union tgsi_exec_channel r[4];
2561 float derivs[3][2][TGSI_QUAD_SIZE];
2562 uint chan;
2563 unsigned char swizzles[4];
2564 int8_t offsets[3];
2565
2566 /* always fetch all 3 offsets, overkill but keeps code simple */
2567 fetch_texel_offsets(mach, inst, offsets);
2568
2569 FETCH(&r[0], 0, TGSI_CHAN_X);
2570
2571 switch (mach->SamplerViews[resource_unit].Resource) {
2572 case TGSI_TEXTURE_1D:
2573 case TGSI_TEXTURE_1D_ARRAY:
2574 /* only 1D array actually needs Y */
2575 FETCH(&r[1], 0, TGSI_CHAN_Y);
2576
2577 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2578
2579 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2580 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2581 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2582 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2583 break;
2584
2585 case TGSI_TEXTURE_2D:
2586 case TGSI_TEXTURE_RECT:
2587 case TGSI_TEXTURE_2D_ARRAY:
2588 /* only 2D array actually needs Z */
2589 FETCH(&r[1], 0, TGSI_CHAN_Y);
2590 FETCH(&r[2], 0, TGSI_CHAN_Z);
2591
2592 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2593 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2594
2595 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2596 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2597 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2598 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2599 break;
2600
2601 case TGSI_TEXTURE_3D:
2602 case TGSI_TEXTURE_CUBE:
2603 case TGSI_TEXTURE_CUBE_ARRAY:
2604 /* only cube array actually needs W */
2605 FETCH(&r[1], 0, TGSI_CHAN_Y);
2606 FETCH(&r[2], 0, TGSI_CHAN_Z);
2607 FETCH(&r[3], 0, TGSI_CHAN_W);
2608
2609 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2610 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2611 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2612
2613 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2614 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2615 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2616 &r[0], &r[1], &r[2], &r[3]);
2617 break;
2618
2619 default:
2620 assert(0);
2621 }
2622
2623 swizzles[0] = inst->Src[1].Register.SwizzleX;
2624 swizzles[1] = inst->Src[1].Register.SwizzleY;
2625 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2626 swizzles[3] = inst->Src[1].Register.SwizzleW;
2627
2628 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2629 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2630 store_dest(mach, &r[swizzles[chan]],
2631 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2632 }
2633 }
2634 }
2635
2636
2637 /**
2638 * Evaluate a constant-valued coefficient at the position of the
2639 * current quad.
2640 */
2641 static void
2642 eval_constant_coef(
2643 struct tgsi_exec_machine *mach,
2644 unsigned attrib,
2645 unsigned chan )
2646 {
2647 unsigned i;
2648
2649 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2650 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2651 }
2652 }
2653
2654 /**
2655 * Evaluate a linear-valued coefficient at the position of the
2656 * current quad.
2657 */
2658 static void
2659 eval_linear_coef(
2660 struct tgsi_exec_machine *mach,
2661 unsigned attrib,
2662 unsigned chan )
2663 {
2664 const float x = mach->QuadPos.xyzw[0].f[0];
2665 const float y = mach->QuadPos.xyzw[1].f[0];
2666 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2667 const float dady = mach->InterpCoefs[attrib].dady[chan];
2668 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2669 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2670 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2671 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2672 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2673 }
2674
2675 /**
2676 * Evaluate a perspective-valued coefficient at the position of the
2677 * current quad.
2678 */
2679 static void
2680 eval_perspective_coef(
2681 struct tgsi_exec_machine *mach,
2682 unsigned attrib,
2683 unsigned chan )
2684 {
2685 const float x = mach->QuadPos.xyzw[0].f[0];
2686 const float y = mach->QuadPos.xyzw[1].f[0];
2687 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2688 const float dady = mach->InterpCoefs[attrib].dady[chan];
2689 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2690 const float *w = mach->QuadPos.xyzw[3].f;
2691 /* divide by W here */
2692 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2693 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2694 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2695 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2696 }
2697
2698
2699 typedef void (* eval_coef_func)(
2700 struct tgsi_exec_machine *mach,
2701 unsigned attrib,
2702 unsigned chan );
2703
2704 static void
2705 exec_declaration(struct tgsi_exec_machine *mach,
2706 const struct tgsi_full_declaration *decl)
2707 {
2708 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2709 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2710 return;
2711 }
2712
2713 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2714 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2715 uint first, last, mask;
2716
2717 first = decl->Range.First;
2718 last = decl->Range.Last;
2719 mask = decl->Declaration.UsageMask;
2720
2721 /* XXX we could remove this special-case code since
2722 * mach->InterpCoefs[first].a0 should already have the
2723 * front/back-face value. But we should first update the
2724 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2725 * Then, we could remove the tgsi_exec_machine::Face field.
2726 */
2727 /* XXX make FACE a system value */
2728 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2729 uint i;
2730
2731 assert(decl->Semantic.Index == 0);
2732 assert(first == last);
2733
2734 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2735 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2736 }
2737 } else {
2738 eval_coef_func eval;
2739 uint i, j;
2740
2741 switch (decl->Interp.Interpolate) {
2742 case TGSI_INTERPOLATE_CONSTANT:
2743 eval = eval_constant_coef;
2744 break;
2745
2746 case TGSI_INTERPOLATE_LINEAR:
2747 eval = eval_linear_coef;
2748 break;
2749
2750 case TGSI_INTERPOLATE_PERSPECTIVE:
2751 eval = eval_perspective_coef;
2752 break;
2753
2754 case TGSI_INTERPOLATE_COLOR:
2755 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2756 break;
2757
2758 default:
2759 assert(0);
2760 return;
2761 }
2762
2763 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2764 if (mask & (1 << j)) {
2765 for (i = first; i <= last; i++) {
2766 eval(mach, i, j);
2767 }
2768 }
2769 }
2770 }
2771
2772 if (DEBUG_EXECUTION) {
2773 uint i, j;
2774 for (i = first; i <= last; ++i) {
2775 debug_printf("IN[%2u] = ", i);
2776 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2777 if (j > 0) {
2778 debug_printf(" ");
2779 }
2780 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2781 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2782 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2783 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2784 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2785 }
2786 }
2787 }
2788 }
2789 }
2790
2791 }
2792
2793 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2794 const union tgsi_exec_channel *src);
2795
2796 static void
2797 exec_scalar_unary(struct tgsi_exec_machine *mach,
2798 const struct tgsi_full_instruction *inst,
2799 micro_unary_op op,
2800 enum tgsi_exec_datatype dst_datatype,
2801 enum tgsi_exec_datatype src_datatype)
2802 {
2803 unsigned int chan;
2804 union tgsi_exec_channel src;
2805 union tgsi_exec_channel dst;
2806
2807 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2808 op(&dst, &src);
2809 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2810 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2811 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2812 }
2813 }
2814 }
2815
2816 static void
2817 exec_vector_unary(struct tgsi_exec_machine *mach,
2818 const struct tgsi_full_instruction *inst,
2819 micro_unary_op op,
2820 enum tgsi_exec_datatype dst_datatype,
2821 enum tgsi_exec_datatype src_datatype)
2822 {
2823 unsigned int chan;
2824 struct tgsi_exec_vector dst;
2825
2826 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2827 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2828 union tgsi_exec_channel src;
2829
2830 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2831 op(&dst.xyzw[chan], &src);
2832 }
2833 }
2834 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2835 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2836 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2837 }
2838 }
2839 }
2840
2841 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2842 const union tgsi_exec_channel *src0,
2843 const union tgsi_exec_channel *src1);
2844
2845 static void
2846 exec_scalar_binary(struct tgsi_exec_machine *mach,
2847 const struct tgsi_full_instruction *inst,
2848 micro_binary_op op,
2849 enum tgsi_exec_datatype dst_datatype,
2850 enum tgsi_exec_datatype src_datatype)
2851 {
2852 unsigned int chan;
2853 union tgsi_exec_channel src[2];
2854 union tgsi_exec_channel dst;
2855
2856 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2857 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2858 op(&dst, &src[0], &src[1]);
2859 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2860 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2861 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2862 }
2863 }
2864 }
2865
2866 static void
2867 exec_vector_binary(struct tgsi_exec_machine *mach,
2868 const struct tgsi_full_instruction *inst,
2869 micro_binary_op op,
2870 enum tgsi_exec_datatype dst_datatype,
2871 enum tgsi_exec_datatype src_datatype)
2872 {
2873 unsigned int chan;
2874 struct tgsi_exec_vector dst;
2875
2876 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2877 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2878 union tgsi_exec_channel src[2];
2879
2880 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2881 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2882 op(&dst.xyzw[chan], &src[0], &src[1]);
2883 }
2884 }
2885 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2886 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2887 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2888 }
2889 }
2890 }
2891
2892 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2893 const union tgsi_exec_channel *src0,
2894 const union tgsi_exec_channel *src1,
2895 const union tgsi_exec_channel *src2);
2896
2897 static void
2898 exec_vector_trinary(struct tgsi_exec_machine *mach,
2899 const struct tgsi_full_instruction *inst,
2900 micro_trinary_op op,
2901 enum tgsi_exec_datatype dst_datatype,
2902 enum tgsi_exec_datatype src_datatype)
2903 {
2904 unsigned int chan;
2905 struct tgsi_exec_vector dst;
2906
2907 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2909 union tgsi_exec_channel src[3];
2910
2911 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2912 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2913 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2914 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2915 }
2916 }
2917 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2918 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2919 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2920 }
2921 }
2922 }
2923
2924 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2925 const union tgsi_exec_channel *src0,
2926 const union tgsi_exec_channel *src1,
2927 const union tgsi_exec_channel *src2,
2928 const union tgsi_exec_channel *src3);
2929
2930 static void
2931 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2932 const struct tgsi_full_instruction *inst,
2933 micro_quaternary_op op,
2934 enum tgsi_exec_datatype dst_datatype,
2935 enum tgsi_exec_datatype src_datatype)
2936 {
2937 unsigned int chan;
2938 struct tgsi_exec_vector dst;
2939
2940 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2941 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2942 union tgsi_exec_channel src[4];
2943
2944 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2945 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2946 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2947 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2948 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2949 }
2950 }
2951 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2952 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2953 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2954 }
2955 }
2956 }
2957
2958 static void
2959 exec_dp3(struct tgsi_exec_machine *mach,
2960 const struct tgsi_full_instruction *inst)
2961 {
2962 unsigned int chan;
2963 union tgsi_exec_channel arg[3];
2964
2965 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2966 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2967 micro_mul(&arg[2], &arg[0], &arg[1]);
2968
2969 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2970 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2971 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2972 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2973 }
2974
2975 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2976 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2977 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2978 }
2979 }
2980 }
2981
2982 static void
2983 exec_dp4(struct tgsi_exec_machine *mach,
2984 const struct tgsi_full_instruction *inst)
2985 {
2986 unsigned int chan;
2987 union tgsi_exec_channel arg[3];
2988
2989 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2990 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2991 micro_mul(&arg[2], &arg[0], &arg[1]);
2992
2993 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2994 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2995 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2996 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2997 }
2998
2999 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3000 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3001 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3002 }
3003 }
3004 }
3005
3006 static void
3007 exec_dp2a(struct tgsi_exec_machine *mach,
3008 const struct tgsi_full_instruction *inst)
3009 {
3010 unsigned int chan;
3011 union tgsi_exec_channel arg[3];
3012
3013 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3014 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3015 micro_mul(&arg[2], &arg[0], &arg[1]);
3016
3017 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3018 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3019 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3020
3021 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3022 micro_add(&arg[0], &arg[0], &arg[1]);
3023
3024 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3025 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3026 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3027 }
3028 }
3029 }
3030
3031 static void
3032 exec_dph(struct tgsi_exec_machine *mach,
3033 const struct tgsi_full_instruction *inst)
3034 {
3035 unsigned int chan;
3036 union tgsi_exec_channel arg[3];
3037
3038 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3039 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3040 micro_mul(&arg[2], &arg[0], &arg[1]);
3041
3042 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3043 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3044 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3045
3046 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3047 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3048 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3049
3050 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3051 micro_add(&arg[0], &arg[0], &arg[1]);
3052
3053 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3054 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3055 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3056 }
3057 }
3058 }
3059
3060 static void
3061 exec_dp2(struct tgsi_exec_machine *mach,
3062 const struct tgsi_full_instruction *inst)
3063 {
3064 unsigned int chan;
3065 union tgsi_exec_channel arg[3];
3066
3067 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3068 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3069 micro_mul(&arg[2], &arg[0], &arg[1]);
3070
3071 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3072 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3073 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3074
3075 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3076 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3077 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3078 }
3079 }
3080 }
3081
3082 static void
3083 exec_pk2h(struct tgsi_exec_machine *mach,
3084 const struct tgsi_full_instruction *inst)
3085 {
3086 unsigned chan;
3087 union tgsi_exec_channel arg[2], dst;
3088
3089 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3090 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3091 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3092 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3093 (util_float_to_half(arg[1].f[chan]) << 16);
3094 }
3095 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3096 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3097 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3098 }
3099 }
3100 }
3101
3102 static void
3103 exec_up2h(struct tgsi_exec_machine *mach,
3104 const struct tgsi_full_instruction *inst)
3105 {
3106 unsigned chan;
3107 union tgsi_exec_channel arg, dst[2];
3108
3109 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3110 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3111 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3112 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3113 }
3114 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3115 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3116 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3117 }
3118 }
3119 }
3120
3121 static void
3122 exec_scs(struct tgsi_exec_machine *mach,
3123 const struct tgsi_full_instruction *inst)
3124 {
3125 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3126 union tgsi_exec_channel arg;
3127 union tgsi_exec_channel result;
3128
3129 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3130
3131 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3132 micro_cos(&result, &arg);
3133 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3134 }
3135 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3136 micro_sin(&result, &arg);
3137 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3138 }
3139 }
3140 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3141 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3142 }
3143 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3144 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3145 }
3146 }
3147
3148 static void
3149 exec_xpd(struct tgsi_exec_machine *mach,
3150 const struct tgsi_full_instruction *inst)
3151 {
3152 union tgsi_exec_channel r[6];
3153 union tgsi_exec_channel d[3];
3154
3155 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3156 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3157
3158 micro_mul(&r[2], &r[0], &r[1]);
3159
3160 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3161 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3162
3163 micro_mul(&r[5], &r[3], &r[4] );
3164 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3165
3166 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3167
3168 micro_mul(&r[3], &r[3], &r[2]);
3169
3170 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3171
3172 micro_mul(&r[1], &r[1], &r[5]);
3173 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3174
3175 micro_mul(&r[5], &r[5], &r[4]);
3176 micro_mul(&r[0], &r[0], &r[2]);
3177 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3178
3179 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3180 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3181 }
3182 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3183 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3184 }
3185 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3186 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3187 }
3188 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3189 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3190 }
3191 }
3192
3193 static void
3194 exec_dst(struct tgsi_exec_machine *mach,
3195 const struct tgsi_full_instruction *inst)
3196 {
3197 union tgsi_exec_channel r[2];
3198 union tgsi_exec_channel d[4];
3199
3200 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3201 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3202 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3203 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3204 }
3205 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3206 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3207 }
3208 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3209 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3210 }
3211
3212 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3213 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3214 }
3215 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3216 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3217 }
3218 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3219 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3220 }
3221 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3222 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3223 }
3224 }
3225
3226 static void
3227 exec_log(struct tgsi_exec_machine *mach,
3228 const struct tgsi_full_instruction *inst)
3229 {
3230 union tgsi_exec_channel r[3];
3231
3232 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3233 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3234 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3235 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3236 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3237 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3238 }
3239 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3240 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3241 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3242 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3243 }
3244 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3245 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3246 }
3247 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3248 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3249 }
3250 }
3251
3252 static void
3253 exec_exp(struct tgsi_exec_machine *mach,
3254 const struct tgsi_full_instruction *inst)
3255 {
3256 union tgsi_exec_channel r[3];
3257
3258 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3259 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3260 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3261 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3262 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3263 }
3264 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3265 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3266 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3267 }
3268 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3269 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3270 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3271 }
3272 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3273 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3274 }
3275 }
3276
3277 static void
3278 exec_lit(struct tgsi_exec_machine *mach,
3279 const struct tgsi_full_instruction *inst)
3280 {
3281 union tgsi_exec_channel r[3];
3282 union tgsi_exec_channel d[3];
3283
3284 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3285 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3286 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3287 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3288 micro_max(&r[1], &r[1], &ZeroVec);
3289
3290 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3291 micro_min(&r[2], &r[2], &P128Vec);
3292 micro_max(&r[2], &r[2], &M128Vec);
3293 micro_pow(&r[1], &r[1], &r[2]);
3294 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3295 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3296 }
3297 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3298 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3299 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3300 }
3301 }
3302 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3303 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3304 }
3305
3306 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3307 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3308 }
3309 }
3310
3311 static void
3312 exec_break(struct tgsi_exec_machine *mach)
3313 {
3314 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3315 /* turn off loop channels for each enabled exec channel */
3316 mach->LoopMask &= ~mach->ExecMask;
3317 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3318 UPDATE_EXEC_MASK(mach);
3319 } else {
3320 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3321
3322 mach->Switch.mask = 0x0;
3323
3324 UPDATE_EXEC_MASK(mach);
3325 }
3326 }
3327
3328 static void
3329 exec_switch(struct tgsi_exec_machine *mach,
3330 const struct tgsi_full_instruction *inst)
3331 {
3332 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3333 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3334
3335 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3336 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3337 mach->Switch.mask = 0x0;
3338 mach->Switch.defaultMask = 0x0;
3339
3340 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3341 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3342
3343 UPDATE_EXEC_MASK(mach);
3344 }
3345
3346 static void
3347 exec_case(struct tgsi_exec_machine *mach,
3348 const struct tgsi_full_instruction *inst)
3349 {
3350 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3351 union tgsi_exec_channel src;
3352 uint mask = 0;
3353
3354 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3355
3356 if (mach->Switch.selector.u[0] == src.u[0]) {
3357 mask |= 0x1;
3358 }
3359 if (mach->Switch.selector.u[1] == src.u[1]) {
3360 mask |= 0x2;
3361 }
3362 if (mach->Switch.selector.u[2] == src.u[2]) {
3363 mask |= 0x4;
3364 }
3365 if (mach->Switch.selector.u[3] == src.u[3]) {
3366 mask |= 0x8;
3367 }
3368
3369 mach->Switch.defaultMask |= mask;
3370
3371 mach->Switch.mask |= mask & prevMask;
3372
3373 UPDATE_EXEC_MASK(mach);
3374 }
3375
3376 /* FIXME: this will only work if default is last */
3377 static void
3378 exec_default(struct tgsi_exec_machine *mach)
3379 {
3380 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3381
3382 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3383
3384 UPDATE_EXEC_MASK(mach);
3385 }
3386
3387 static void
3388 exec_endswitch(struct tgsi_exec_machine *mach)
3389 {
3390 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3391 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3392
3393 UPDATE_EXEC_MASK(mach);
3394 }
3395
3396 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3397 const union tgsi_double_channel *src);
3398
3399 static void
3400 fetch_double_channel(struct tgsi_exec_machine *mach,
3401 union tgsi_double_channel *chan,
3402 const struct tgsi_full_src_register *reg,
3403 uint chan_0,
3404 uint chan_1)
3405 {
3406 union tgsi_exec_channel src[2];
3407 uint i;
3408
3409 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3410 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3411
3412 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3413 chan->u[i][0] = src[0].u[i];
3414 chan->u[i][1] = src[1].u[i];
3415 }
3416 if (reg->Register.Absolute) {
3417 micro_dabs(chan, chan);
3418 }
3419 if (reg->Register.Negate) {
3420 micro_dneg(chan, chan);
3421 }
3422 }
3423
3424 static void
3425 store_double_channel(struct tgsi_exec_machine *mach,
3426 const union tgsi_double_channel *chan,
3427 const struct tgsi_full_dst_register *reg,
3428 const struct tgsi_full_instruction *inst,
3429 uint chan_0,
3430 uint chan_1)
3431 {
3432 union tgsi_exec_channel dst[2];
3433 uint i;
3434 union tgsi_double_channel temp;
3435 const uint execmask = mach->ExecMask;
3436
3437 if (!inst->Instruction.Saturate) {
3438 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3439 if (execmask & (1 << i)) {
3440 dst[0].u[i] = chan->u[i][0];
3441 dst[1].u[i] = chan->u[i][1];
3442 }
3443 }
3444 else {
3445 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3446 if (execmask & (1 << i)) {
3447 if (chan->d[i] < 0.0)
3448 temp.d[i] = 0.0;
3449 else if (chan->d[i] > 1.0)
3450 temp.d[i] = 1.0;
3451 else
3452 temp.d[i] = chan->d[i];
3453
3454 dst[0].u[i] = temp.u[i][0];
3455 dst[1].u[i] = temp.u[i][1];
3456 }
3457 }
3458
3459 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3460 if (chan_1 != -1)
3461 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3462 }
3463
3464 static void
3465 exec_double_unary(struct tgsi_exec_machine *mach,
3466 const struct tgsi_full_instruction *inst,
3467 micro_dop op)
3468 {
3469 union tgsi_double_channel src;
3470 union tgsi_double_channel dst;
3471
3472 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3473 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3474 op(&dst, &src);
3475 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3476 }
3477 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3478 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3479 op(&dst, &src);
3480 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3481 }
3482 }
3483
3484 static void
3485 exec_double_binary(struct tgsi_exec_machine *mach,
3486 const struct tgsi_full_instruction *inst,
3487 micro_dop op,
3488 enum tgsi_exec_datatype dst_datatype)
3489 {
3490 union tgsi_double_channel src[2];
3491 union tgsi_double_channel dst;
3492 int first_dest_chan, second_dest_chan;
3493 int wmask;
3494
3495 wmask = inst->Dst[0].Register.WriteMask;
3496 /* these are & because of the way DSLT etc store their destinations */
3497 if (wmask & TGSI_WRITEMASK_XY) {
3498 first_dest_chan = TGSI_CHAN_X;
3499 second_dest_chan = TGSI_CHAN_Y;
3500 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3501 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3502 second_dest_chan = -1;
3503 }
3504
3505 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3506 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3507 op(&dst, src);
3508 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3509 }
3510
3511 if (wmask & TGSI_WRITEMASK_ZW) {
3512 first_dest_chan = TGSI_CHAN_Z;
3513 second_dest_chan = TGSI_CHAN_W;
3514 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3515 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3516 second_dest_chan = -1;
3517 }
3518
3519 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3520 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3521 op(&dst, src);
3522 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3523 }
3524 }
3525
3526 static void
3527 exec_double_trinary(struct tgsi_exec_machine *mach,
3528 const struct tgsi_full_instruction *inst,
3529 micro_dop op)
3530 {
3531 union tgsi_double_channel src[3];
3532 union tgsi_double_channel dst;
3533
3534 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3535 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3536 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3537 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3538 op(&dst, src);
3539 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3540 }
3541 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3542 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3543 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3544 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3545 op(&dst, src);
3546 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3547 }
3548 }
3549
3550 static void
3551 exec_f2d(struct tgsi_exec_machine *mach,
3552 const struct tgsi_full_instruction *inst)
3553 {
3554 union tgsi_exec_channel src;
3555 union tgsi_double_channel dst;
3556
3557 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3558 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3559 micro_f2d(&dst, &src);
3560 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3561 }
3562 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3563 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3564 micro_f2d(&dst, &src);
3565 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3566 }
3567 }
3568
3569 static void
3570 exec_d2f(struct tgsi_exec_machine *mach,
3571 const struct tgsi_full_instruction *inst)
3572 {
3573 union tgsi_double_channel src;
3574 union tgsi_exec_channel dst;
3575 int wm = inst->Dst[0].Register.WriteMask;
3576 int i;
3577 int bit;
3578 for (i = 0; i < 2; i++) {
3579 bit = ffs(wm);
3580 if (bit) {
3581 wm &= ~(1 << (bit - 1));
3582 if (i == 0)
3583 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3584 else
3585 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3586 micro_d2f(&dst, &src);
3587 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3588 }
3589 }
3590 }
3591
3592 static void
3593 exec_i2d(struct tgsi_exec_machine *mach,
3594 const struct tgsi_full_instruction *inst)
3595 {
3596 union tgsi_exec_channel src;
3597 union tgsi_double_channel dst;
3598
3599 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3600 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3601 micro_i2d(&dst, &src);
3602 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3603 }
3604 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3605 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3606 micro_i2d(&dst, &src);
3607 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3608 }
3609 }
3610
3611 static void
3612 exec_d2i(struct tgsi_exec_machine *mach,
3613 const struct tgsi_full_instruction *inst)
3614 {
3615 union tgsi_double_channel src;
3616 union tgsi_exec_channel dst;
3617 int wm = inst->Dst[0].Register.WriteMask;
3618 int i;
3619 int bit;
3620 for (i = 0; i < 2; i++) {
3621 bit = ffs(wm);
3622 if (bit) {
3623 wm &= ~(1 << (bit - 1));
3624 if (i == 0)
3625 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3626 else
3627 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3628 micro_d2i(&dst, &src);
3629 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3630 }
3631 }
3632 }
3633 static void
3634 exec_u2d(struct tgsi_exec_machine *mach,
3635 const struct tgsi_full_instruction *inst)
3636 {
3637 union tgsi_exec_channel src;
3638 union tgsi_double_channel dst;
3639
3640 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3641 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3642 micro_u2d(&dst, &src);
3643 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3644 }
3645 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3646 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3647 micro_u2d(&dst, &src);
3648 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3649 }
3650 }
3651
3652 static void
3653 exec_d2u(struct tgsi_exec_machine *mach,
3654 const struct tgsi_full_instruction *inst)
3655 {
3656 union tgsi_double_channel src;
3657 union tgsi_exec_channel dst;
3658 int wm = inst->Dst[0].Register.WriteMask;
3659 int i;
3660 int bit;
3661 for (i = 0; i < 2; i++) {
3662 bit = ffs(wm);
3663 if (bit) {
3664 wm &= ~(1 << (bit - 1));
3665 if (i == 0)
3666 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3667 else
3668 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3669 micro_d2u(&dst, &src);
3670 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3671 }
3672 }
3673 }
3674
3675 static void
3676 exec_dldexp(struct tgsi_exec_machine *mach,
3677 const struct tgsi_full_instruction *inst)
3678 {
3679 union tgsi_double_channel src0;
3680 union tgsi_exec_channel src1;
3681 union tgsi_double_channel dst;
3682 int wmask;
3683
3684 wmask = inst->Dst[0].Register.WriteMask;
3685 if (wmask & TGSI_WRITEMASK_XY) {
3686 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3687 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3688 micro_dldexp(&dst, &src0, &src1);
3689 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3690 }
3691
3692 if (wmask & TGSI_WRITEMASK_ZW) {
3693 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3694 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3695 micro_dldexp(&dst, &src0, &src1);
3696 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3697 }
3698 }
3699
3700 static void
3701 exec_dfracexp(struct tgsi_exec_machine *mach,
3702 const struct tgsi_full_instruction *inst)
3703 {
3704 union tgsi_double_channel src;
3705 union tgsi_double_channel dst;
3706 union tgsi_exec_channel dst_exp;
3707
3708 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3709 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3710 micro_dfracexp(&dst, &dst_exp, &src);
3711 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3712 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3713 }
3714 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3715 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3716 micro_dfracexp(&dst, &dst_exp, &src);
3717 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3718 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3719 }
3720 }
3721
3722 static int
3723 get_image_coord_dim(unsigned tgsi_tex)
3724 {
3725 int dim;
3726 switch (tgsi_tex) {
3727 case TGSI_TEXTURE_BUFFER:
3728 case TGSI_TEXTURE_1D:
3729 dim = 1;
3730 break;
3731 case TGSI_TEXTURE_2D:
3732 case TGSI_TEXTURE_RECT:
3733 case TGSI_TEXTURE_1D_ARRAY:
3734 case TGSI_TEXTURE_2D_MSAA:
3735 dim = 2;
3736 break;
3737 case TGSI_TEXTURE_3D:
3738 case TGSI_TEXTURE_CUBE:
3739 case TGSI_TEXTURE_2D_ARRAY:
3740 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3741 case TGSI_TEXTURE_CUBE_ARRAY:
3742 dim = 3;
3743 break;
3744 default:
3745 assert(!"unknown texture target");
3746 dim = 0;
3747 break;
3748 }
3749
3750 return dim;
3751 }
3752
3753 static int
3754 get_image_coord_sample(unsigned tgsi_tex)
3755 {
3756 int sample = 0;
3757 switch (tgsi_tex) {
3758 case TGSI_TEXTURE_2D_MSAA:
3759 sample = 3;
3760 break;
3761 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3762 sample = 4;
3763 break;
3764 default:
3765 break;
3766 }
3767 return sample;
3768 }
3769
3770 static void
3771 exec_load_img(struct tgsi_exec_machine *mach,
3772 const struct tgsi_full_instruction *inst)
3773 {
3774 union tgsi_exec_channel r[4], sample_r;
3775 uint unit;
3776 int sample;
3777 int i, j;
3778 int dim;
3779 uint chan;
3780 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3781 struct tgsi_image_params params;
3782 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3783
3784 unit = fetch_sampler_unit(mach, inst, 0);
3785 dim = get_image_coord_dim(inst->Memory.Texture);
3786 sample = get_image_coord_sample(inst->Memory.Texture);
3787 assert(dim <= 3);
3788
3789 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3790 params.unit = unit;
3791 params.tgsi_tex_instr = inst->Memory.Texture;
3792 params.format = inst->Memory.Format;
3793
3794 for (i = 0; i < dim; i++) {
3795 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3796 }
3797
3798 if (sample)
3799 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3800
3801 mach->Image->load(mach->Image, &params,
3802 r[0].i, r[1].i, r[2].i, sample_r.i,
3803 rgba);
3804 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3805 r[0].f[j] = rgba[0][j];
3806 r[1].f[j] = rgba[1][j];
3807 r[2].f[j] = rgba[2][j];
3808 r[3].f[j] = rgba[3][j];
3809 }
3810 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3811 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3812 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3813 }
3814 }
3815 }
3816
3817 static void
3818 exec_load_buf(struct tgsi_exec_machine *mach,
3819 const struct tgsi_full_instruction *inst)
3820 {
3821 union tgsi_exec_channel r[4];
3822 uint unit;
3823 int j;
3824 uint chan;
3825 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3826 struct tgsi_buffer_params params;
3827 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3828
3829 unit = fetch_sampler_unit(mach, inst, 0);
3830
3831 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3832 params.unit = unit;
3833 IFETCH(&r[0], 1, TGSI_CHAN_X);
3834
3835 mach->Buffer->load(mach->Buffer, &params,
3836 r[0].i, rgba);
3837 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3838 r[0].f[j] = rgba[0][j];
3839 r[1].f[j] = rgba[1][j];
3840 r[2].f[j] = rgba[2][j];
3841 r[3].f[j] = rgba[3][j];
3842 }
3843 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3844 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3845 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3846 }
3847 }
3848 }
3849
3850 static void
3851 exec_load_mem(struct tgsi_exec_machine *mach,
3852 const struct tgsi_full_instruction *inst)
3853 {
3854 union tgsi_exec_channel r[4];
3855 uint chan;
3856 char *ptr = mach->LocalMem;
3857 uint32_t offset;
3858 int j;
3859
3860 IFETCH(&r[0], 1, TGSI_CHAN_X);
3861 if (r[0].u[0] >= mach->LocalMemSize)
3862 return;
3863
3864 offset = r[0].u[0];
3865 ptr += offset;
3866
3867 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3868 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3869 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3870 memcpy(&r[chan].u[j], ptr + (4 * chan), 4);
3871 }
3872 }
3873 }
3874
3875 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3876 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3877 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3878 }
3879 }
3880 }
3881
3882 static void
3883 exec_load(struct tgsi_exec_machine *mach,
3884 const struct tgsi_full_instruction *inst)
3885 {
3886 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3887 exec_load_img(mach, inst);
3888 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
3889 exec_load_buf(mach, inst);
3890 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
3891 exec_load_mem(mach, inst);
3892 }
3893
3894 static void
3895 exec_store_img(struct tgsi_exec_machine *mach,
3896 const struct tgsi_full_instruction *inst)
3897 {
3898 union tgsi_exec_channel r[3], sample_r;
3899 union tgsi_exec_channel value[4];
3900 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3901 struct tgsi_image_params params;
3902 int dim;
3903 int sample;
3904 int i, j;
3905 uint unit;
3906 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3907 unit = inst->Dst[0].Register.Index;
3908 dim = get_image_coord_dim(inst->Memory.Texture);
3909 sample = get_image_coord_sample(inst->Memory.Texture);
3910 assert(dim <= 3);
3911
3912 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3913 params.unit = unit;
3914 params.tgsi_tex_instr = inst->Memory.Texture;
3915 params.format = inst->Memory.Format;
3916
3917 for (i = 0; i < dim; i++) {
3918 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3919 }
3920
3921 for (i = 0; i < 4; i++) {
3922 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3923 }
3924 if (sample)
3925 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3926
3927 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3928 rgba[0][j] = value[0].f[j];
3929 rgba[1][j] = value[1].f[j];
3930 rgba[2][j] = value[2].f[j];
3931 rgba[3][j] = value[3].f[j];
3932 }
3933
3934 mach->Image->store(mach->Image, &params,
3935 r[0].i, r[1].i, r[2].i, sample_r.i,
3936 rgba);
3937 }
3938
3939 static void
3940 exec_store_buf(struct tgsi_exec_machine *mach,
3941 const struct tgsi_full_instruction *inst)
3942 {
3943 union tgsi_exec_channel r[3];
3944 union tgsi_exec_channel value[4];
3945 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3946 struct tgsi_buffer_params params;
3947 int i, j;
3948 uint unit;
3949 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3950
3951 unit = inst->Dst[0].Register.Index;
3952
3953 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3954 params.unit = unit;
3955 params.writemask = inst->Dst[0].Register.WriteMask;
3956
3957 IFETCH(&r[0], 0, TGSI_CHAN_X);
3958 for (i = 0; i < 4; i++) {
3959 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3960 }
3961
3962 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3963 rgba[0][j] = value[0].f[j];
3964 rgba[1][j] = value[1].f[j];
3965 rgba[2][j] = value[2].f[j];
3966 rgba[3][j] = value[3].f[j];
3967 }
3968
3969 mach->Buffer->store(mach->Buffer, &params,
3970 r[0].i,
3971 rgba);
3972 }
3973
3974 static void
3975 exec_store_mem(struct tgsi_exec_machine *mach,
3976 const struct tgsi_full_instruction *inst)
3977 {
3978 union tgsi_exec_channel r[3];
3979 union tgsi_exec_channel value[4];
3980 uint i, chan;
3981 char *ptr = mach->LocalMem;
3982 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3983 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3984
3985 IFETCH(&r[0], 0, TGSI_CHAN_X);
3986
3987 for (i = 0; i < 4; i++) {
3988 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3989 }
3990
3991 if (r[0].u[0] >= mach->LocalMemSize)
3992 return;
3993 ptr += r[0].u[0];
3994
3995 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3996 if (execmask & (1 << i)) {
3997 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3998 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3999 memcpy(ptr + (chan * 4), &value[chan].u[0], 4);
4000 }
4001 }
4002 }
4003 }
4004 }
4005
4006 static void
4007 exec_store(struct tgsi_exec_machine *mach,
4008 const struct tgsi_full_instruction *inst)
4009 {
4010 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
4011 exec_store_img(mach, inst);
4012 else if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
4013 exec_store_buf(mach, inst);
4014 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
4015 exec_store_mem(mach, inst);
4016 }
4017
4018 static void
4019 exec_atomop_img(struct tgsi_exec_machine *mach,
4020 const struct tgsi_full_instruction *inst)
4021 {
4022 union tgsi_exec_channel r[4], sample_r;
4023 union tgsi_exec_channel value[4], value2[4];
4024 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4025 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4026 struct tgsi_image_params params;
4027 int dim;
4028 int sample;
4029 int i, j;
4030 uint unit, chan;
4031 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4032 unit = fetch_sampler_unit(mach, inst, 0);
4033 dim = get_image_coord_dim(inst->Memory.Texture);
4034 sample = get_image_coord_sample(inst->Memory.Texture);
4035 assert(dim <= 3);
4036
4037 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4038 params.unit = unit;
4039 params.tgsi_tex_instr = inst->Memory.Texture;
4040 params.format = inst->Memory.Format;
4041
4042 for (i = 0; i < dim; i++) {
4043 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
4044 }
4045
4046 for (i = 0; i < 4; i++) {
4047 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4048 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4049 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4050 }
4051 if (sample)
4052 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
4053
4054 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4055 rgba[0][j] = value[0].f[j];
4056 rgba[1][j] = value[1].f[j];
4057 rgba[2][j] = value[2].f[j];
4058 rgba[3][j] = value[3].f[j];
4059 }
4060 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4061 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4062 rgba2[0][j] = value2[0].f[j];
4063 rgba2[1][j] = value2[1].f[j];
4064 rgba2[2][j] = value2[2].f[j];
4065 rgba2[3][j] = value2[3].f[j];
4066 }
4067 }
4068
4069 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
4070 r[0].i, r[1].i, r[2].i, sample_r.i,
4071 rgba, rgba2);
4072
4073 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4074 r[0].f[j] = rgba[0][j];
4075 r[1].f[j] = rgba[1][j];
4076 r[2].f[j] = rgba[2][j];
4077 r[3].f[j] = rgba[3][j];
4078 }
4079 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4080 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4081 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4082 }
4083 }
4084 }
4085
4086 static void
4087 exec_atomop_buf(struct tgsi_exec_machine *mach,
4088 const struct tgsi_full_instruction *inst)
4089 {
4090 union tgsi_exec_channel r[4];
4091 union tgsi_exec_channel value[4], value2[4];
4092 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4093 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4094 struct tgsi_buffer_params params;
4095 int i, j;
4096 uint unit, chan;
4097 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4098
4099 unit = fetch_sampler_unit(mach, inst, 0);
4100
4101 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4102 params.unit = unit;
4103 params.writemask = inst->Dst[0].Register.WriteMask;
4104
4105 IFETCH(&r[0], 1, TGSI_CHAN_X);
4106
4107 for (i = 0; i < 4; i++) {
4108 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4109 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4110 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4111 }
4112
4113 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4114 rgba[0][j] = value[0].f[j];
4115 rgba[1][j] = value[1].f[j];
4116 rgba[2][j] = value[2].f[j];
4117 rgba[3][j] = value[3].f[j];
4118 }
4119 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4120 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4121 rgba2[0][j] = value2[0].f[j];
4122 rgba2[1][j] = value2[1].f[j];
4123 rgba2[2][j] = value2[2].f[j];
4124 rgba2[3][j] = value2[3].f[j];
4125 }
4126 }
4127
4128 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4129 r[0].i,
4130 rgba, rgba2);
4131
4132 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4133 r[0].f[j] = rgba[0][j];
4134 r[1].f[j] = rgba[1][j];
4135 r[2].f[j] = rgba[2][j];
4136 r[3].f[j] = rgba[3][j];
4137 }
4138 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4139 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4140 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4141 }
4142 }
4143 }
4144
4145 static void
4146 exec_atomop_mem(struct tgsi_exec_machine *mach,
4147 const struct tgsi_full_instruction *inst)
4148 {
4149 union tgsi_exec_channel r[4];
4150 union tgsi_exec_channel value[4], value2[4];
4151 char *ptr = mach->LocalMem;
4152 uint32_t val;
4153 uint chan, i;
4154 uint32_t offset;
4155 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4156 int execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4157 IFETCH(&r[0], 1, TGSI_CHAN_X);
4158
4159 if (r[0].u[0] >= mach->LocalMemSize)
4160 return;
4161
4162 offset = r[0].u[0];
4163 ptr += offset;
4164 for (i = 0; i < 4; i++) {
4165 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4166 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4167 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4168 }
4169
4170 memcpy(&r[0].u[0], ptr, 4);
4171 val = r[0].u[0];
4172 switch (inst->Instruction.Opcode) {
4173 case TGSI_OPCODE_ATOMUADD:
4174 val += value[0].u[0];
4175 break;
4176 case TGSI_OPCODE_ATOMXOR:
4177 val ^= value[0].u[0];
4178 break;
4179 case TGSI_OPCODE_ATOMOR:
4180 val |= value[0].u[0];
4181 break;
4182 case TGSI_OPCODE_ATOMAND:
4183 val &= value[0].u[0];
4184 break;
4185 case TGSI_OPCODE_ATOMUMIN:
4186 val = MIN2(val, value[0].u[0]);
4187 break;
4188 case TGSI_OPCODE_ATOMUMAX:
4189 val = MAX2(val, value[0].u[0]);
4190 break;
4191 case TGSI_OPCODE_ATOMIMIN:
4192 val = MIN2(r[0].i[0], value[0].i[0]);
4193 break;
4194 case TGSI_OPCODE_ATOMIMAX:
4195 val = MAX2(r[0].i[0], value[0].i[0]);
4196 break;
4197 case TGSI_OPCODE_ATOMXCHG:
4198 val = value[0].i[0];
4199 break;
4200 case TGSI_OPCODE_ATOMCAS:
4201 if (val == value[0].u[0])
4202 val = value2[0].u[0];
4203 break;
4204 default:
4205 break;
4206 }
4207 for (i = 0; i < TGSI_QUAD_SIZE; i++)
4208 if (execmask & (1 << i))
4209 memcpy(ptr, &val, 4);
4210
4211 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4212 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4213 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4214 }
4215 }
4216 }
4217
4218 static void
4219 exec_atomop(struct tgsi_exec_machine *mach,
4220 const struct tgsi_full_instruction *inst)
4221 {
4222 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4223 exec_atomop_img(mach, inst);
4224 else if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
4225 exec_atomop_buf(mach, inst);
4226 else if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
4227 exec_atomop_mem(mach, inst);
4228 }
4229
4230 static void
4231 exec_resq_img(struct tgsi_exec_machine *mach,
4232 const struct tgsi_full_instruction *inst)
4233 {
4234 int result[4];
4235 union tgsi_exec_channel r[4];
4236 uint unit;
4237 int i, chan, j;
4238 struct tgsi_image_params params;
4239 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4240
4241 unit = fetch_sampler_unit(mach, inst, 0);
4242
4243 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4244 params.unit = unit;
4245 params.tgsi_tex_instr = inst->Memory.Texture;
4246 params.format = inst->Memory.Format;
4247
4248 mach->Image->get_dims(mach->Image, &params, result);
4249
4250 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4251 for (j = 0; j < 4; j++) {
4252 r[j].i[i] = result[j];
4253 }
4254 }
4255
4256 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4257 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4258 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4259 TGSI_EXEC_DATA_INT);
4260 }
4261 }
4262 }
4263
4264 static void
4265 exec_resq_buf(struct tgsi_exec_machine *mach,
4266 const struct tgsi_full_instruction *inst)
4267 {
4268 int result;
4269 union tgsi_exec_channel r[4];
4270 uint unit;
4271 int i, chan;
4272 struct tgsi_buffer_params params;
4273 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4274
4275 unit = fetch_sampler_unit(mach, inst, 0);
4276
4277 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4278 params.unit = unit;
4279
4280 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4281
4282 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4283 r[0].i[i] = result;
4284 }
4285
4286 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4287 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4288 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4289 TGSI_EXEC_DATA_INT);
4290 }
4291 }
4292 }
4293
4294 static void
4295 exec_resq(struct tgsi_exec_machine *mach,
4296 const struct tgsi_full_instruction *inst)
4297 {
4298 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4299 exec_resq_img(mach, inst);
4300 else
4301 exec_resq_buf(mach, inst);
4302 }
4303
4304 static void
4305 micro_i2f(union tgsi_exec_channel *dst,
4306 const union tgsi_exec_channel *src)
4307 {
4308 dst->f[0] = (float)src->i[0];
4309 dst->f[1] = (float)src->i[1];
4310 dst->f[2] = (float)src->i[2];
4311 dst->f[3] = (float)src->i[3];
4312 }
4313
4314 static void
4315 micro_not(union tgsi_exec_channel *dst,
4316 const union tgsi_exec_channel *src)
4317 {
4318 dst->u[0] = ~src->u[0];
4319 dst->u[1] = ~src->u[1];
4320 dst->u[2] = ~src->u[2];
4321 dst->u[3] = ~src->u[3];
4322 }
4323
4324 static void
4325 micro_shl(union tgsi_exec_channel *dst,
4326 const union tgsi_exec_channel *src0,
4327 const union tgsi_exec_channel *src1)
4328 {
4329 unsigned masked_count;
4330 masked_count = src1->u[0] & 0x1f;
4331 dst->u[0] = src0->u[0] << masked_count;
4332 masked_count = src1->u[1] & 0x1f;
4333 dst->u[1] = src0->u[1] << masked_count;
4334 masked_count = src1->u[2] & 0x1f;
4335 dst->u[2] = src0->u[2] << masked_count;
4336 masked_count = src1->u[3] & 0x1f;
4337 dst->u[3] = src0->u[3] << masked_count;
4338 }
4339
4340 static void
4341 micro_and(union tgsi_exec_channel *dst,
4342 const union tgsi_exec_channel *src0,
4343 const union tgsi_exec_channel *src1)
4344 {
4345 dst->u[0] = src0->u[0] & src1->u[0];
4346 dst->u[1] = src0->u[1] & src1->u[1];
4347 dst->u[2] = src0->u[2] & src1->u[2];
4348 dst->u[3] = src0->u[3] & src1->u[3];
4349 }
4350
4351 static void
4352 micro_or(union tgsi_exec_channel *dst,
4353 const union tgsi_exec_channel *src0,
4354 const union tgsi_exec_channel *src1)
4355 {
4356 dst->u[0] = src0->u[0] | src1->u[0];
4357 dst->u[1] = src0->u[1] | src1->u[1];
4358 dst->u[2] = src0->u[2] | src1->u[2];
4359 dst->u[3] = src0->u[3] | src1->u[3];
4360 }
4361
4362 static void
4363 micro_xor(union tgsi_exec_channel *dst,
4364 const union tgsi_exec_channel *src0,
4365 const union tgsi_exec_channel *src1)
4366 {
4367 dst->u[0] = src0->u[0] ^ src1->u[0];
4368 dst->u[1] = src0->u[1] ^ src1->u[1];
4369 dst->u[2] = src0->u[2] ^ src1->u[2];
4370 dst->u[3] = src0->u[3] ^ src1->u[3];
4371 }
4372
4373 static void
4374 micro_mod(union tgsi_exec_channel *dst,
4375 const union tgsi_exec_channel *src0,
4376 const union tgsi_exec_channel *src1)
4377 {
4378 dst->i[0] = src0->i[0] % src1->i[0];
4379 dst->i[1] = src0->i[1] % src1->i[1];
4380 dst->i[2] = src0->i[2] % src1->i[2];
4381 dst->i[3] = src0->i[3] % src1->i[3];
4382 }
4383
4384 static void
4385 micro_f2i(union tgsi_exec_channel *dst,
4386 const union tgsi_exec_channel *src)
4387 {
4388 dst->i[0] = (int)src->f[0];
4389 dst->i[1] = (int)src->f[1];
4390 dst->i[2] = (int)src->f[2];
4391 dst->i[3] = (int)src->f[3];
4392 }
4393
4394 static void
4395 micro_fseq(union tgsi_exec_channel *dst,
4396 const union tgsi_exec_channel *src0,
4397 const union tgsi_exec_channel *src1)
4398 {
4399 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4400 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4401 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4402 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4403 }
4404
4405 static void
4406 micro_fsge(union tgsi_exec_channel *dst,
4407 const union tgsi_exec_channel *src0,
4408 const union tgsi_exec_channel *src1)
4409 {
4410 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4411 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4412 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4413 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4414 }
4415
4416 static void
4417 micro_fslt(union tgsi_exec_channel *dst,
4418 const union tgsi_exec_channel *src0,
4419 const union tgsi_exec_channel *src1)
4420 {
4421 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4422 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4423 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4424 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4425 }
4426
4427 static void
4428 micro_fsne(union tgsi_exec_channel *dst,
4429 const union tgsi_exec_channel *src0,
4430 const union tgsi_exec_channel *src1)
4431 {
4432 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4433 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4434 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4435 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4436 }
4437
4438 static void
4439 micro_idiv(union tgsi_exec_channel *dst,
4440 const union tgsi_exec_channel *src0,
4441 const union tgsi_exec_channel *src1)
4442 {
4443 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4444 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4445 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4446 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4447 }
4448
4449 static void
4450 micro_imax(union tgsi_exec_channel *dst,
4451 const union tgsi_exec_channel *src0,
4452 const union tgsi_exec_channel *src1)
4453 {
4454 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4455 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4456 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4457 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4458 }
4459
4460 static void
4461 micro_imin(union tgsi_exec_channel *dst,
4462 const union tgsi_exec_channel *src0,
4463 const union tgsi_exec_channel *src1)
4464 {
4465 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4466 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4467 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4468 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4469 }
4470
4471 static void
4472 micro_isge(union tgsi_exec_channel *dst,
4473 const union tgsi_exec_channel *src0,
4474 const union tgsi_exec_channel *src1)
4475 {
4476 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4477 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4478 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4479 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4480 }
4481
4482 static void
4483 micro_ishr(union tgsi_exec_channel *dst,
4484 const union tgsi_exec_channel *src0,
4485 const union tgsi_exec_channel *src1)
4486 {
4487 unsigned masked_count;
4488 masked_count = src1->i[0] & 0x1f;
4489 dst->i[0] = src0->i[0] >> masked_count;
4490 masked_count = src1->i[1] & 0x1f;
4491 dst->i[1] = src0->i[1] >> masked_count;
4492 masked_count = src1->i[2] & 0x1f;
4493 dst->i[2] = src0->i[2] >> masked_count;
4494 masked_count = src1->i[3] & 0x1f;
4495 dst->i[3] = src0->i[3] >> masked_count;
4496 }
4497
4498 static void
4499 micro_islt(union tgsi_exec_channel *dst,
4500 const union tgsi_exec_channel *src0,
4501 const union tgsi_exec_channel *src1)
4502 {
4503 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4504 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4505 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4506 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4507 }
4508
4509 static void
4510 micro_f2u(union tgsi_exec_channel *dst,
4511 const union tgsi_exec_channel *src)
4512 {
4513 dst->u[0] = (uint)src->f[0];
4514 dst->u[1] = (uint)src->f[1];
4515 dst->u[2] = (uint)src->f[2];
4516 dst->u[3] = (uint)src->f[3];
4517 }
4518
4519 static void
4520 micro_u2f(union tgsi_exec_channel *dst,
4521 const union tgsi_exec_channel *src)
4522 {
4523 dst->f[0] = (float)src->u[0];
4524 dst->f[1] = (float)src->u[1];
4525 dst->f[2] = (float)src->u[2];
4526 dst->f[3] = (float)src->u[3];
4527 }
4528
4529 static void
4530 micro_uadd(union tgsi_exec_channel *dst,
4531 const union tgsi_exec_channel *src0,
4532 const union tgsi_exec_channel *src1)
4533 {
4534 dst->u[0] = src0->u[0] + src1->u[0];
4535 dst->u[1] = src0->u[1] + src1->u[1];
4536 dst->u[2] = src0->u[2] + src1->u[2];
4537 dst->u[3] = src0->u[3] + src1->u[3];
4538 }
4539
4540 static void
4541 micro_udiv(union tgsi_exec_channel *dst,
4542 const union tgsi_exec_channel *src0,
4543 const union tgsi_exec_channel *src1)
4544 {
4545 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4546 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4547 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4548 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4549 }
4550
4551 static void
4552 micro_umad(union tgsi_exec_channel *dst,
4553 const union tgsi_exec_channel *src0,
4554 const union tgsi_exec_channel *src1,
4555 const union tgsi_exec_channel *src2)
4556 {
4557 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4558 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4559 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4560 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4561 }
4562
4563 static void
4564 micro_umax(union tgsi_exec_channel *dst,
4565 const union tgsi_exec_channel *src0,
4566 const union tgsi_exec_channel *src1)
4567 {
4568 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4569 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4570 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4571 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4572 }
4573
4574 static void
4575 micro_umin(union tgsi_exec_channel *dst,
4576 const union tgsi_exec_channel *src0,
4577 const union tgsi_exec_channel *src1)
4578 {
4579 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4580 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4581 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4582 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4583 }
4584
4585 static void
4586 micro_umod(union tgsi_exec_channel *dst,
4587 const union tgsi_exec_channel *src0,
4588 const union tgsi_exec_channel *src1)
4589 {
4590 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4591 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4592 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4593 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4594 }
4595
4596 static void
4597 micro_umul(union tgsi_exec_channel *dst,
4598 const union tgsi_exec_channel *src0,
4599 const union tgsi_exec_channel *src1)
4600 {
4601 dst->u[0] = src0->u[0] * src1->u[0];
4602 dst->u[1] = src0->u[1] * src1->u[1];
4603 dst->u[2] = src0->u[2] * src1->u[2];
4604 dst->u[3] = src0->u[3] * src1->u[3];
4605 }
4606
4607 static void
4608 micro_imul_hi(union tgsi_exec_channel *dst,
4609 const union tgsi_exec_channel *src0,
4610 const union tgsi_exec_channel *src1)
4611 {
4612 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4613 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4614 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4615 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4616 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4617 #undef I64M
4618 }
4619
4620 static void
4621 micro_umul_hi(union tgsi_exec_channel *dst,
4622 const union tgsi_exec_channel *src0,
4623 const union tgsi_exec_channel *src1)
4624 {
4625 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4626 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4627 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4628 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4629 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4630 #undef U64M
4631 }
4632
4633 static void
4634 micro_useq(union tgsi_exec_channel *dst,
4635 const union tgsi_exec_channel *src0,
4636 const union tgsi_exec_channel *src1)
4637 {
4638 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4639 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4640 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4641 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4642 }
4643
4644 static void
4645 micro_usge(union tgsi_exec_channel *dst,
4646 const union tgsi_exec_channel *src0,
4647 const union tgsi_exec_channel *src1)
4648 {
4649 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4650 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4651 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4652 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4653 }
4654
4655 static void
4656 micro_ushr(union tgsi_exec_channel *dst,
4657 const union tgsi_exec_channel *src0,
4658 const union tgsi_exec_channel *src1)
4659 {
4660 unsigned masked_count;
4661 masked_count = src1->u[0] & 0x1f;
4662 dst->u[0] = src0->u[0] >> masked_count;
4663 masked_count = src1->u[1] & 0x1f;
4664 dst->u[1] = src0->u[1] >> masked_count;
4665 masked_count = src1->u[2] & 0x1f;
4666 dst->u[2] = src0->u[2] >> masked_count;
4667 masked_count = src1->u[3] & 0x1f;
4668 dst->u[3] = src0->u[3] >> masked_count;
4669 }
4670
4671 static void
4672 micro_uslt(union tgsi_exec_channel *dst,
4673 const union tgsi_exec_channel *src0,
4674 const union tgsi_exec_channel *src1)
4675 {
4676 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4677 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4678 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4679 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4680 }
4681
4682 static void
4683 micro_usne(union tgsi_exec_channel *dst,
4684 const union tgsi_exec_channel *src0,
4685 const union tgsi_exec_channel *src1)
4686 {
4687 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4688 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4689 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4690 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4691 }
4692
4693 static void
4694 micro_uarl(union tgsi_exec_channel *dst,
4695 const union tgsi_exec_channel *src)
4696 {
4697 dst->i[0] = src->u[0];
4698 dst->i[1] = src->u[1];
4699 dst->i[2] = src->u[2];
4700 dst->i[3] = src->u[3];
4701 }
4702
4703 static void
4704 micro_ucmp(union tgsi_exec_channel *dst,
4705 const union tgsi_exec_channel *src0,
4706 const union tgsi_exec_channel *src1,
4707 const union tgsi_exec_channel *src2)
4708 {
4709 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4710 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4711 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4712 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4713 }
4714
4715 /**
4716 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4717 */
4718 static void
4719 micro_ibfe(union tgsi_exec_channel *dst,
4720 const union tgsi_exec_channel *src0,
4721 const union tgsi_exec_channel *src1,
4722 const union tgsi_exec_channel *src2)
4723 {
4724 int i;
4725 for (i = 0; i < 4; i++) {
4726 int width = src2->i[i] & 0x1f;
4727 int offset = src1->i[i] & 0x1f;
4728 if (width == 0)
4729 dst->i[i] = 0;
4730 else if (width + offset < 32)
4731 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4732 else
4733 dst->i[i] = src0->i[i] >> offset;
4734 }
4735 }
4736
4737 /**
4738 * Unsigned bitfield extract
4739 */
4740 static void
4741 micro_ubfe(union tgsi_exec_channel *dst,
4742 const union tgsi_exec_channel *src0,
4743 const union tgsi_exec_channel *src1,
4744 const union tgsi_exec_channel *src2)
4745 {
4746 int i;
4747 for (i = 0; i < 4; i++) {
4748 int width = src2->u[i] & 0x1f;
4749 int offset = src1->u[i] & 0x1f;
4750 if (width == 0)
4751 dst->u[i] = 0;
4752 else if (width + offset < 32)
4753 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4754 else
4755 dst->u[i] = src0->u[i] >> offset;
4756 }
4757 }
4758
4759 /**
4760 * Bitfield insert: copy low bits from src1 into a region of src0.
4761 */
4762 static void
4763 micro_bfi(union tgsi_exec_channel *dst,
4764 const union tgsi_exec_channel *src0,
4765 const union tgsi_exec_channel *src1,
4766 const union tgsi_exec_channel *src2,
4767 const union tgsi_exec_channel *src3)
4768 {
4769 int i;
4770 for (i = 0; i < 4; i++) {
4771 int width = src3->u[i] & 0x1f;
4772 int offset = src2->u[i] & 0x1f;
4773 int bitmask = ((1 << width) - 1) << offset;
4774 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4775 }
4776 }
4777
4778 static void
4779 micro_brev(union tgsi_exec_channel *dst,
4780 const union tgsi_exec_channel *src)
4781 {
4782 dst->u[0] = util_bitreverse(src->u[0]);
4783 dst->u[1] = util_bitreverse(src->u[1]);
4784 dst->u[2] = util_bitreverse(src->u[2]);
4785 dst->u[3] = util_bitreverse(src->u[3]);
4786 }
4787
4788 static void
4789 micro_popc(union tgsi_exec_channel *dst,
4790 const union tgsi_exec_channel *src)
4791 {
4792 dst->u[0] = util_bitcount(src->u[0]);
4793 dst->u[1] = util_bitcount(src->u[1]);
4794 dst->u[2] = util_bitcount(src->u[2]);
4795 dst->u[3] = util_bitcount(src->u[3]);
4796 }
4797
4798 static void
4799 micro_lsb(union tgsi_exec_channel *dst,
4800 const union tgsi_exec_channel *src)
4801 {
4802 dst->i[0] = ffs(src->u[0]) - 1;
4803 dst->i[1] = ffs(src->u[1]) - 1;
4804 dst->i[2] = ffs(src->u[2]) - 1;
4805 dst->i[3] = ffs(src->u[3]) - 1;
4806 }
4807
4808 static void
4809 micro_imsb(union tgsi_exec_channel *dst,
4810 const union tgsi_exec_channel *src)
4811 {
4812 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4813 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4814 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4815 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4816 }
4817
4818 static void
4819 micro_umsb(union tgsi_exec_channel *dst,
4820 const union tgsi_exec_channel *src)
4821 {
4822 dst->i[0] = util_last_bit(src->u[0]) - 1;
4823 dst->i[1] = util_last_bit(src->u[1]) - 1;
4824 dst->i[2] = util_last_bit(src->u[2]) - 1;
4825 dst->i[3] = util_last_bit(src->u[3]) - 1;
4826 }
4827
4828 /**
4829 * Execute a TGSI instruction.
4830 * Returns TRUE if a barrier instruction is hit,
4831 * otherwise FALSE.
4832 */
4833 static boolean
4834 exec_instruction(
4835 struct tgsi_exec_machine *mach,
4836 const struct tgsi_full_instruction *inst,
4837 int *pc )
4838 {
4839 union tgsi_exec_channel r[10];
4840
4841 (*pc)++;
4842
4843 switch (inst->Instruction.Opcode) {
4844 case TGSI_OPCODE_ARL:
4845 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4846 break;
4847
4848 case TGSI_OPCODE_MOV:
4849 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4850 break;
4851
4852 case TGSI_OPCODE_LIT:
4853 exec_lit(mach, inst);
4854 break;
4855
4856 case TGSI_OPCODE_RCP:
4857 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4858 break;
4859
4860 case TGSI_OPCODE_RSQ:
4861 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4862 break;
4863
4864 case TGSI_OPCODE_EXP:
4865 exec_exp(mach, inst);
4866 break;
4867
4868 case TGSI_OPCODE_LOG:
4869 exec_log(mach, inst);
4870 break;
4871
4872 case TGSI_OPCODE_MUL:
4873 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4874 break;
4875
4876 case TGSI_OPCODE_ADD:
4877 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4878 break;
4879
4880 case TGSI_OPCODE_DP3:
4881 exec_dp3(mach, inst);
4882 break;
4883
4884 case TGSI_OPCODE_DP4:
4885 exec_dp4(mach, inst);
4886 break;
4887
4888 case TGSI_OPCODE_DST:
4889 exec_dst(mach, inst);
4890 break;
4891
4892 case TGSI_OPCODE_MIN:
4893 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4894 break;
4895
4896 case TGSI_OPCODE_MAX:
4897 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4898 break;
4899
4900 case TGSI_OPCODE_SLT:
4901 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4902 break;
4903
4904 case TGSI_OPCODE_SGE:
4905 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4906 break;
4907
4908 case TGSI_OPCODE_MAD:
4909 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4910 break;
4911
4912 case TGSI_OPCODE_SUB:
4913 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4914 break;
4915
4916 case TGSI_OPCODE_LRP:
4917 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4918 break;
4919
4920 case TGSI_OPCODE_SQRT:
4921 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4922 break;
4923
4924 case TGSI_OPCODE_DP2A:
4925 exec_dp2a(mach, inst);
4926 break;
4927
4928 case TGSI_OPCODE_FRC:
4929 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4930 break;
4931
4932 case TGSI_OPCODE_CLAMP:
4933 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4934 break;
4935
4936 case TGSI_OPCODE_FLR:
4937 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4938 break;
4939
4940 case TGSI_OPCODE_ROUND:
4941 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4942 break;
4943
4944 case TGSI_OPCODE_EX2:
4945 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4946 break;
4947
4948 case TGSI_OPCODE_LG2:
4949 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4950 break;
4951
4952 case TGSI_OPCODE_POW:
4953 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4954 break;
4955
4956 case TGSI_OPCODE_XPD:
4957 exec_xpd(mach, inst);
4958 break;
4959
4960 case TGSI_OPCODE_ABS:
4961 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4962 break;
4963
4964 case TGSI_OPCODE_DPH:
4965 exec_dph(mach, inst);
4966 break;
4967
4968 case TGSI_OPCODE_COS:
4969 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4970 break;
4971
4972 case TGSI_OPCODE_DDX:
4973 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4974 break;
4975
4976 case TGSI_OPCODE_DDY:
4977 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4978 break;
4979
4980 case TGSI_OPCODE_KILL:
4981 exec_kill (mach, inst);
4982 break;
4983
4984 case TGSI_OPCODE_KILL_IF:
4985 exec_kill_if (mach, inst);
4986 break;
4987
4988 case TGSI_OPCODE_PK2H:
4989 exec_pk2h(mach, inst);
4990 break;
4991
4992 case TGSI_OPCODE_PK2US:
4993 assert (0);
4994 break;
4995
4996 case TGSI_OPCODE_PK4B:
4997 assert (0);
4998 break;
4999
5000 case TGSI_OPCODE_PK4UB:
5001 assert (0);
5002 break;
5003
5004 case TGSI_OPCODE_SEQ:
5005 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5006 break;
5007
5008 case TGSI_OPCODE_SGT:
5009 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5010 break;
5011
5012 case TGSI_OPCODE_SIN:
5013 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5014 break;
5015
5016 case TGSI_OPCODE_SLE:
5017 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5018 break;
5019
5020 case TGSI_OPCODE_SNE:
5021 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5022 break;
5023
5024 case TGSI_OPCODE_TEX:
5025 /* simple texture lookup */
5026 /* src[0] = texcoord */
5027 /* src[1] = sampler unit */
5028 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
5029 break;
5030
5031 case TGSI_OPCODE_TXB:
5032 /* Texture lookup with lod bias */
5033 /* src[0] = texcoord (src[0].w = LOD bias) */
5034 /* src[1] = sampler unit */
5035 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
5036 break;
5037
5038 case TGSI_OPCODE_TXD:
5039 /* Texture lookup with explict partial derivatives */
5040 /* src[0] = texcoord */
5041 /* src[1] = d[strq]/dx */
5042 /* src[2] = d[strq]/dy */
5043 /* src[3] = sampler unit */
5044 exec_txd(mach, inst);
5045 break;
5046
5047 case TGSI_OPCODE_TXL:
5048 /* Texture lookup with explit LOD */
5049 /* src[0] = texcoord (src[0].w = LOD) */
5050 /* src[1] = sampler unit */
5051 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
5052 break;
5053
5054 case TGSI_OPCODE_TXP:
5055 /* Texture lookup with projection */
5056 /* src[0] = texcoord (src[0].w = projection) */
5057 /* src[1] = sampler unit */
5058 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
5059 break;
5060
5061 case TGSI_OPCODE_TG4:
5062 /* src[0] = texcoord */
5063 /* src[1] = component */
5064 /* src[2] = sampler unit */
5065 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
5066 break;
5067
5068 case TGSI_OPCODE_LODQ:
5069 /* src[0] = texcoord */
5070 /* src[1] = sampler unit */
5071 exec_lodq(mach, inst);
5072 break;
5073
5074 case TGSI_OPCODE_UP2H:
5075 exec_up2h(mach, inst);
5076 break;
5077
5078 case TGSI_OPCODE_UP2US:
5079 assert (0);
5080 break;
5081
5082 case TGSI_OPCODE_UP4B:
5083 assert (0);
5084 break;
5085
5086 case TGSI_OPCODE_UP4UB:
5087 assert (0);
5088 break;
5089
5090 case TGSI_OPCODE_ARR:
5091 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5092 break;
5093
5094 case TGSI_OPCODE_CAL:
5095 /* skip the call if no execution channels are enabled */
5096 if (mach->ExecMask) {
5097 /* do the call */
5098
5099 /* First, record the depths of the execution stacks.
5100 * This is important for deeply nested/looped return statements.
5101 * We have to unwind the stacks by the correct amount. For a
5102 * real code generator, we could determine the number of entries
5103 * to pop off each stack with simple static analysis and avoid
5104 * implementing this data structure at run time.
5105 */
5106 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
5107 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
5108 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
5109 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
5110 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
5111 /* note that PC was already incremented above */
5112 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
5113
5114 mach->CallStackTop++;
5115
5116 /* Second, push the Cond, Loop, Cont, Func stacks */
5117 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5118 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5119 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5120 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
5121 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5122 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
5123
5124 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5125 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5126 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5127 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
5128 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5129 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
5130
5131 /* Finally, jump to the subroutine. The label is a pointer
5132 * (an instruction number) to the BGNSUB instruction.
5133 */
5134 *pc = inst->Label.Label;
5135 assert(mach->Instructions[*pc].Instruction.Opcode
5136 == TGSI_OPCODE_BGNSUB);
5137 }
5138 break;
5139
5140 case TGSI_OPCODE_RET:
5141 mach->FuncMask &= ~mach->ExecMask;
5142 UPDATE_EXEC_MASK(mach);
5143
5144 if (mach->FuncMask == 0x0) {
5145 /* really return now (otherwise, keep executing */
5146
5147 if (mach->CallStackTop == 0) {
5148 /* returning from main() */
5149 mach->CondStackTop = 0;
5150 mach->LoopStackTop = 0;
5151 mach->ContStackTop = 0;
5152 mach->LoopLabelStackTop = 0;
5153 mach->SwitchStackTop = 0;
5154 mach->BreakStackTop = 0;
5155 *pc = -1;
5156 return FALSE;
5157 }
5158
5159 assert(mach->CallStackTop > 0);
5160 mach->CallStackTop--;
5161
5162 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5163 mach->CondMask = mach->CondStack[mach->CondStackTop];
5164
5165 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5166 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5167
5168 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5169 mach->ContMask = mach->ContStack[mach->ContStackTop];
5170
5171 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5172 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5173
5174 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5175 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5176
5177 assert(mach->FuncStackTop > 0);
5178 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5179
5180 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5181
5182 UPDATE_EXEC_MASK(mach);
5183 }
5184 break;
5185
5186 case TGSI_OPCODE_SSG:
5187 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5188 break;
5189
5190 case TGSI_OPCODE_CMP:
5191 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5192 break;
5193
5194 case TGSI_OPCODE_SCS:
5195 exec_scs(mach, inst);
5196 break;
5197
5198 case TGSI_OPCODE_DIV:
5199 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5200 break;
5201
5202 case TGSI_OPCODE_DP2:
5203 exec_dp2(mach, inst);
5204 break;
5205
5206 case TGSI_OPCODE_IF:
5207 /* push CondMask */
5208 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5209 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5210 FETCH( &r[0], 0, TGSI_CHAN_X );
5211 /* update CondMask */
5212 if( ! r[0].f[0] ) {
5213 mach->CondMask &= ~0x1;
5214 }
5215 if( ! r[0].f[1] ) {
5216 mach->CondMask &= ~0x2;
5217 }
5218 if( ! r[0].f[2] ) {
5219 mach->CondMask &= ~0x4;
5220 }
5221 if( ! r[0].f[3] ) {
5222 mach->CondMask &= ~0x8;
5223 }
5224 UPDATE_EXEC_MASK(mach);
5225 /* Todo: If CondMask==0, jump to ELSE */
5226 break;
5227
5228 case TGSI_OPCODE_UIF:
5229 /* push CondMask */
5230 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5231 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5232 IFETCH( &r[0], 0, TGSI_CHAN_X );
5233 /* update CondMask */
5234 if( ! r[0].u[0] ) {
5235 mach->CondMask &= ~0x1;
5236 }
5237 if( ! r[0].u[1] ) {
5238 mach->CondMask &= ~0x2;
5239 }
5240 if( ! r[0].u[2] ) {
5241 mach->CondMask &= ~0x4;
5242 }
5243 if( ! r[0].u[3] ) {
5244 mach->CondMask &= ~0x8;
5245 }
5246 UPDATE_EXEC_MASK(mach);
5247 /* Todo: If CondMask==0, jump to ELSE */
5248 break;
5249
5250 case TGSI_OPCODE_ELSE:
5251 /* invert CondMask wrt previous mask */
5252 {
5253 uint prevMask;
5254 assert(mach->CondStackTop > 0);
5255 prevMask = mach->CondStack[mach->CondStackTop - 1];
5256 mach->CondMask = ~mach->CondMask & prevMask;
5257 UPDATE_EXEC_MASK(mach);
5258 /* Todo: If CondMask==0, jump to ENDIF */
5259 }
5260 break;
5261
5262 case TGSI_OPCODE_ENDIF:
5263 /* pop CondMask */
5264 assert(mach->CondStackTop > 0);
5265 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5266 UPDATE_EXEC_MASK(mach);
5267 break;
5268
5269 case TGSI_OPCODE_END:
5270 /* make sure we end primitives which haven't
5271 * been explicitly emitted */
5272 conditional_emit_primitive(mach);
5273 /* halt execution */
5274 *pc = -1;
5275 break;
5276
5277 case TGSI_OPCODE_PUSHA:
5278 assert (0);
5279 break;
5280
5281 case TGSI_OPCODE_POPA:
5282 assert (0);
5283 break;
5284
5285 case TGSI_OPCODE_CEIL:
5286 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5287 break;
5288
5289 case TGSI_OPCODE_I2F:
5290 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5291 break;
5292
5293 case TGSI_OPCODE_NOT:
5294 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5295 break;
5296
5297 case TGSI_OPCODE_TRUNC:
5298 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5299 break;
5300
5301 case TGSI_OPCODE_SHL:
5302 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5303 break;
5304
5305 case TGSI_OPCODE_AND:
5306 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5307 break;
5308
5309 case TGSI_OPCODE_OR:
5310 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5311 break;
5312
5313 case TGSI_OPCODE_MOD:
5314 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5315 break;
5316
5317 case TGSI_OPCODE_XOR:
5318 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5319 break;
5320
5321 case TGSI_OPCODE_SAD:
5322 assert (0);
5323 break;
5324
5325 case TGSI_OPCODE_TXF:
5326 exec_txf(mach, inst);
5327 break;
5328
5329 case TGSI_OPCODE_TXQ:
5330 exec_txq(mach, inst);
5331 break;
5332
5333 case TGSI_OPCODE_EMIT:
5334 emit_vertex(mach);
5335 break;
5336
5337 case TGSI_OPCODE_ENDPRIM:
5338 emit_primitive(mach);
5339 break;
5340
5341 case TGSI_OPCODE_BGNLOOP:
5342 /* push LoopMask and ContMasks */
5343 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5344 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5345 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5346 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5347
5348 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5349 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5350 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5351 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5352 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5353 break;
5354
5355 case TGSI_OPCODE_ENDLOOP:
5356 /* Restore ContMask, but don't pop */
5357 assert(mach->ContStackTop > 0);
5358 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5359 UPDATE_EXEC_MASK(mach);
5360 if (mach->ExecMask) {
5361 /* repeat loop: jump to instruction just past BGNLOOP */
5362 assert(mach->LoopLabelStackTop > 0);
5363 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5364 }
5365 else {
5366 /* exit loop: pop LoopMask */
5367 assert(mach->LoopStackTop > 0);
5368 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5369 /* pop ContMask */
5370 assert(mach->ContStackTop > 0);
5371 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5372 assert(mach->LoopLabelStackTop > 0);
5373 --mach->LoopLabelStackTop;
5374
5375 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5376 }
5377 UPDATE_EXEC_MASK(mach);
5378 break;
5379
5380 case TGSI_OPCODE_BRK:
5381 exec_break(mach);
5382 break;
5383
5384 case TGSI_OPCODE_CONT:
5385 /* turn off cont channels for each enabled exec channel */
5386 mach->ContMask &= ~mach->ExecMask;
5387 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5388 UPDATE_EXEC_MASK(mach);
5389 break;
5390
5391 case TGSI_OPCODE_BGNSUB:
5392 /* no-op */
5393 break;
5394
5395 case TGSI_OPCODE_ENDSUB:
5396 /*
5397 * XXX: This really should be a no-op. We should never reach this opcode.
5398 */
5399
5400 assert(mach->CallStackTop > 0);
5401 mach->CallStackTop--;
5402
5403 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5404 mach->CondMask = mach->CondStack[mach->CondStackTop];
5405
5406 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5407 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5408
5409 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5410 mach->ContMask = mach->ContStack[mach->ContStackTop];
5411
5412 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5413 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5414
5415 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5416 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5417
5418 assert(mach->FuncStackTop > 0);
5419 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5420
5421 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5422
5423 UPDATE_EXEC_MASK(mach);
5424 break;
5425
5426 case TGSI_OPCODE_NOP:
5427 break;
5428
5429 case TGSI_OPCODE_BREAKC:
5430 IFETCH(&r[0], 0, TGSI_CHAN_X);
5431 /* update CondMask */
5432 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5433 mach->LoopMask &= ~0x1;
5434 }
5435 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5436 mach->LoopMask &= ~0x2;
5437 }
5438 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5439 mach->LoopMask &= ~0x4;
5440 }
5441 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5442 mach->LoopMask &= ~0x8;
5443 }
5444 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5445 UPDATE_EXEC_MASK(mach);
5446 break;
5447
5448 case TGSI_OPCODE_F2I:
5449 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5450 break;
5451
5452 case TGSI_OPCODE_FSEQ:
5453 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5454 break;
5455
5456 case TGSI_OPCODE_FSGE:
5457 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5458 break;
5459
5460 case TGSI_OPCODE_FSLT:
5461 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5462 break;
5463
5464 case TGSI_OPCODE_FSNE:
5465 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5466 break;
5467
5468 case TGSI_OPCODE_IDIV:
5469 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5470 break;
5471
5472 case TGSI_OPCODE_IMAX:
5473 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5474 break;
5475
5476 case TGSI_OPCODE_IMIN:
5477 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5478 break;
5479
5480 case TGSI_OPCODE_INEG:
5481 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5482 break;
5483
5484 case TGSI_OPCODE_ISGE:
5485 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5486 break;
5487
5488 case TGSI_OPCODE_ISHR:
5489 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5490 break;
5491
5492 case TGSI_OPCODE_ISLT:
5493 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5494 break;
5495
5496 case TGSI_OPCODE_F2U:
5497 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5498 break;
5499
5500 case TGSI_OPCODE_U2F:
5501 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5502 break;
5503
5504 case TGSI_OPCODE_UADD:
5505 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5506 break;
5507
5508 case TGSI_OPCODE_UDIV:
5509 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5510 break;
5511
5512 case TGSI_OPCODE_UMAD:
5513 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5514 break;
5515
5516 case TGSI_OPCODE_UMAX:
5517 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5518 break;
5519
5520 case TGSI_OPCODE_UMIN:
5521 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5522 break;
5523
5524 case TGSI_OPCODE_UMOD:
5525 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5526 break;
5527
5528 case TGSI_OPCODE_UMUL:
5529 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5530 break;
5531
5532 case TGSI_OPCODE_IMUL_HI:
5533 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5534 break;
5535
5536 case TGSI_OPCODE_UMUL_HI:
5537 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5538 break;
5539
5540 case TGSI_OPCODE_USEQ:
5541 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5542 break;
5543
5544 case TGSI_OPCODE_USGE:
5545 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5546 break;
5547
5548 case TGSI_OPCODE_USHR:
5549 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5550 break;
5551
5552 case TGSI_OPCODE_USLT:
5553 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5554 break;
5555
5556 case TGSI_OPCODE_USNE:
5557 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5558 break;
5559
5560 case TGSI_OPCODE_SWITCH:
5561 exec_switch(mach, inst);
5562 break;
5563
5564 case TGSI_OPCODE_CASE:
5565 exec_case(mach, inst);
5566 break;
5567
5568 case TGSI_OPCODE_DEFAULT:
5569 exec_default(mach);
5570 break;
5571
5572 case TGSI_OPCODE_ENDSWITCH:
5573 exec_endswitch(mach);
5574 break;
5575
5576 case TGSI_OPCODE_SAMPLE_I:
5577 exec_txf(mach, inst);
5578 break;
5579
5580 case TGSI_OPCODE_SAMPLE_I_MS:
5581 exec_txf(mach, inst);
5582 break;
5583
5584 case TGSI_OPCODE_SAMPLE:
5585 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5586 break;
5587
5588 case TGSI_OPCODE_SAMPLE_B:
5589 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5590 break;
5591
5592 case TGSI_OPCODE_SAMPLE_C:
5593 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5594 break;
5595
5596 case TGSI_OPCODE_SAMPLE_C_LZ:
5597 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5598 break;
5599
5600 case TGSI_OPCODE_SAMPLE_D:
5601 exec_sample_d(mach, inst);
5602 break;
5603
5604 case TGSI_OPCODE_SAMPLE_L:
5605 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5606 break;
5607
5608 case TGSI_OPCODE_GATHER4:
5609 assert(0);
5610 break;
5611
5612 case TGSI_OPCODE_SVIEWINFO:
5613 exec_txq(mach, inst);
5614 break;
5615
5616 case TGSI_OPCODE_SAMPLE_POS:
5617 assert(0);
5618 break;
5619
5620 case TGSI_OPCODE_SAMPLE_INFO:
5621 assert(0);
5622 break;
5623
5624 case TGSI_OPCODE_UARL:
5625 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5626 break;
5627
5628 case TGSI_OPCODE_UCMP:
5629 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5630 break;
5631
5632 case TGSI_OPCODE_IABS:
5633 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5634 break;
5635
5636 case TGSI_OPCODE_ISSG:
5637 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5638 break;
5639
5640 case TGSI_OPCODE_TEX2:
5641 /* simple texture lookup */
5642 /* src[0] = texcoord */
5643 /* src[1] = compare */
5644 /* src[2] = sampler unit */
5645 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5646 break;
5647 case TGSI_OPCODE_TXB2:
5648 /* simple texture lookup */
5649 /* src[0] = texcoord */
5650 /* src[1] = bias */
5651 /* src[2] = sampler unit */
5652 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5653 break;
5654 case TGSI_OPCODE_TXL2:
5655 /* simple texture lookup */
5656 /* src[0] = texcoord */
5657 /* src[1] = lod */
5658 /* src[2] = sampler unit */
5659 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5660 break;
5661
5662 case TGSI_OPCODE_IBFE:
5663 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5664 break;
5665 case TGSI_OPCODE_UBFE:
5666 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5667 break;
5668 case TGSI_OPCODE_BFI:
5669 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5670 break;
5671 case TGSI_OPCODE_BREV:
5672 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5673 break;
5674 case TGSI_OPCODE_POPC:
5675 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5676 break;
5677 case TGSI_OPCODE_LSB:
5678 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5679 break;
5680 case TGSI_OPCODE_IMSB:
5681 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5682 break;
5683 case TGSI_OPCODE_UMSB:
5684 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5685 break;
5686
5687 case TGSI_OPCODE_F2D:
5688 exec_f2d(mach, inst);
5689 break;
5690
5691 case TGSI_OPCODE_D2F:
5692 exec_d2f(mach, inst);
5693 break;
5694
5695 case TGSI_OPCODE_DABS:
5696 exec_double_unary(mach, inst, micro_dabs);
5697 break;
5698
5699 case TGSI_OPCODE_DNEG:
5700 exec_double_unary(mach, inst, micro_dneg);
5701 break;
5702
5703 case TGSI_OPCODE_DADD:
5704 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5705 break;
5706
5707 case TGSI_OPCODE_DMUL:
5708 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5709 break;
5710
5711 case TGSI_OPCODE_DMAX:
5712 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5713 break;
5714
5715 case TGSI_OPCODE_DMIN:
5716 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5717 break;
5718
5719 case TGSI_OPCODE_DSLT:
5720 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5721 break;
5722
5723 case TGSI_OPCODE_DSGE:
5724 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5725 break;
5726
5727 case TGSI_OPCODE_DSEQ:
5728 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5729 break;
5730
5731 case TGSI_OPCODE_DSNE:
5732 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5733 break;
5734
5735 case TGSI_OPCODE_DRCP:
5736 exec_double_unary(mach, inst, micro_drcp);
5737 break;
5738
5739 case TGSI_OPCODE_DSQRT:
5740 exec_double_unary(mach, inst, micro_dsqrt);
5741 break;
5742
5743 case TGSI_OPCODE_DRSQ:
5744 exec_double_unary(mach, inst, micro_drsq);
5745 break;
5746
5747 case TGSI_OPCODE_DMAD:
5748 exec_double_trinary(mach, inst, micro_dmad);
5749 break;
5750
5751 case TGSI_OPCODE_DFRAC:
5752 exec_double_unary(mach, inst, micro_dfrac);
5753 break;
5754
5755 case TGSI_OPCODE_DLDEXP:
5756 exec_dldexp(mach, inst);
5757 break;
5758
5759 case TGSI_OPCODE_DFRACEXP:
5760 exec_dfracexp(mach, inst);
5761 break;
5762
5763 case TGSI_OPCODE_I2D:
5764 exec_i2d(mach, inst);
5765 break;
5766
5767 case TGSI_OPCODE_D2I:
5768 exec_d2i(mach, inst);
5769 break;
5770
5771 case TGSI_OPCODE_U2D:
5772 exec_u2d(mach, inst);
5773 break;
5774
5775 case TGSI_OPCODE_D2U:
5776 exec_d2u(mach, inst);
5777 break;
5778
5779 case TGSI_OPCODE_LOAD:
5780 exec_load(mach, inst);
5781 break;
5782
5783 case TGSI_OPCODE_STORE:
5784 exec_store(mach, inst);
5785 break;
5786
5787 case TGSI_OPCODE_ATOMUADD:
5788 case TGSI_OPCODE_ATOMXCHG:
5789 case TGSI_OPCODE_ATOMCAS:
5790 case TGSI_OPCODE_ATOMAND:
5791 case TGSI_OPCODE_ATOMOR:
5792 case TGSI_OPCODE_ATOMXOR:
5793 case TGSI_OPCODE_ATOMUMIN:
5794 case TGSI_OPCODE_ATOMUMAX:
5795 case TGSI_OPCODE_ATOMIMIN:
5796 case TGSI_OPCODE_ATOMIMAX:
5797 exec_atomop(mach, inst);
5798 break;
5799
5800 case TGSI_OPCODE_RESQ:
5801 exec_resq(mach, inst);
5802 break;
5803 case TGSI_OPCODE_BARRIER:
5804 case TGSI_OPCODE_MEMBAR:
5805 return TRUE;
5806 break;
5807 default:
5808 assert( 0 );
5809 }
5810 return FALSE;
5811 }
5812
5813 static void
5814 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine *mach)
5815 {
5816 uint default_mask = 0xf;
5817
5818 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5819 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5820
5821 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
5822 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5823 mach->Primitives[0] = 0;
5824 /* GS runs on a single primitive for now */
5825 default_mask = 0x1;
5826 }
5827
5828 if (mach->NonHelperMask == 0)
5829 mach->NonHelperMask = default_mask;
5830 mach->CondMask = default_mask;
5831 mach->LoopMask = default_mask;
5832 mach->ContMask = default_mask;
5833 mach->FuncMask = default_mask;
5834 mach->ExecMask = default_mask;
5835
5836 mach->Switch.mask = default_mask;
5837
5838 assert(mach->CondStackTop == 0);
5839 assert(mach->LoopStackTop == 0);
5840 assert(mach->ContStackTop == 0);
5841 assert(mach->SwitchStackTop == 0);
5842 assert(mach->BreakStackTop == 0);
5843 assert(mach->CallStackTop == 0);
5844 }
5845
5846 /**
5847 * Run TGSI interpreter.
5848 * \return bitmask of "alive" quad components
5849 */
5850 uint
5851 tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
5852 {
5853 uint i;
5854
5855 mach->pc = start_pc;
5856
5857 if (!start_pc) {
5858 tgsi_exec_machine_setup_masks(mach);
5859
5860 /* execute declarations (interpolants) */
5861 for (i = 0; i < mach->NumDeclarations; i++) {
5862 exec_declaration( mach, mach->Declarations+i );
5863 }
5864 }
5865
5866 {
5867 #if DEBUG_EXECUTION
5868 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5869 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5870 uint inst = 1;
5871
5872 if (!start_pc) {
5873 memset(mach->Temps, 0, sizeof(temps));
5874 if (mach->Outputs)
5875 memset(mach->Outputs, 0, sizeof(outputs));
5876 memset(temps, 0, sizeof(temps));
5877 memset(outputs, 0, sizeof(outputs));
5878 }
5879 #endif
5880
5881 /* execute instructions, until pc is set to -1 */
5882 while (mach->pc != -1) {
5883 boolean barrier_hit;
5884 #if DEBUG_EXECUTION
5885 uint i;
5886
5887 tgsi_dump_instruction(&mach->Instructions[mach->pc], inst++);
5888 #endif
5889
5890 assert(mach->pc < (int) mach->NumInstructions);
5891 barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
5892
5893 /* for compute shaders if we hit a barrier return now for later rescheduling */
5894 if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
5895 return 0;
5896
5897 #if DEBUG_EXECUTION
5898 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5899 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5900 uint j;
5901
5902 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5903 debug_printf("TEMP[%2u] = ", i);
5904 for (j = 0; j < 4; j++) {
5905 if (j > 0) {
5906 debug_printf(" ");
5907 }
5908 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5909 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5910 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5911 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5912 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5913 }
5914 }
5915 }
5916 if (mach->Outputs) {
5917 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5918 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5919 uint j;
5920
5921 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5922 debug_printf("OUT[%2u] = ", i);
5923 for (j = 0; j < 4; j++) {
5924 if (j > 0) {
5925 debug_printf(" ");
5926 }
5927 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5928 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5929 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5930 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5931 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5932 }
5933 }
5934 }
5935 }
5936 #endif
5937 }
5938 }
5939
5940 #if 0
5941 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5942 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
5943 /*
5944 * Scale back depth component.
5945 */
5946 for (i = 0; i < 4; i++)
5947 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5948 }
5949 #endif
5950
5951 /* Strictly speaking, these assertions aren't really needed but they
5952 * can potentially catch some bugs in the control flow code.
5953 */
5954 assert(mach->CondStackTop == 0);
5955 assert(mach->LoopStackTop == 0);
5956 assert(mach->ContStackTop == 0);
5957 assert(mach->SwitchStackTop == 0);
5958 assert(mach->BreakStackTop == 0);
5959 assert(mach->CallStackTop == 0);
5960
5961 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5962 }