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tgsi: pass a shader type to the machine create and clean up.
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 VMware, Inc.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 /**
30 * TGSI interpreter/executor.
31 *
32 * Flow control information:
33 *
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
38 *
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
42 * See store_dest().
43 *
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
47 *
48 *
49 * Authors:
50 * Michal Krol
51 * Brian Paul
52 */
53
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64
65
66 #define DEBUG_EXECUTION 0
67
68
69 #define FAST_MATH 0
70
71 #define TILE_TOP_LEFT 0
72 #define TILE_TOP_RIGHT 1
73 #define TILE_BOTTOM_LEFT 2
74 #define TILE_BOTTOM_RIGHT 3
75
76 union tgsi_double_channel {
77 double d[TGSI_QUAD_SIZE];
78 unsigned u[TGSI_QUAD_SIZE][2];
79 };
80
81 struct tgsi_double_vector {
82 union tgsi_double_channel xy;
83 union tgsi_double_channel zw;
84 };
85
86 static void
87 micro_abs(union tgsi_exec_channel *dst,
88 const union tgsi_exec_channel *src)
89 {
90 dst->f[0] = fabsf(src->f[0]);
91 dst->f[1] = fabsf(src->f[1]);
92 dst->f[2] = fabsf(src->f[2]);
93 dst->f[3] = fabsf(src->f[3]);
94 }
95
96 static void
97 micro_arl(union tgsi_exec_channel *dst,
98 const union tgsi_exec_channel *src)
99 {
100 dst->i[0] = (int)floorf(src->f[0]);
101 dst->i[1] = (int)floorf(src->f[1]);
102 dst->i[2] = (int)floorf(src->f[2]);
103 dst->i[3] = (int)floorf(src->f[3]);
104 }
105
106 static void
107 micro_arr(union tgsi_exec_channel *dst,
108 const union tgsi_exec_channel *src)
109 {
110 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
111 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
112 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
113 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
114 }
115
116 static void
117 micro_ceil(union tgsi_exec_channel *dst,
118 const union tgsi_exec_channel *src)
119 {
120 dst->f[0] = ceilf(src->f[0]);
121 dst->f[1] = ceilf(src->f[1]);
122 dst->f[2] = ceilf(src->f[2]);
123 dst->f[3] = ceilf(src->f[3]);
124 }
125
126 static void
127 micro_clamp(union tgsi_exec_channel *dst,
128 const union tgsi_exec_channel *src0,
129 const union tgsi_exec_channel *src1,
130 const union tgsi_exec_channel *src2)
131 {
132 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
133 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
134 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
135 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
136 }
137
138 static void
139 micro_cmp(union tgsi_exec_channel *dst,
140 const union tgsi_exec_channel *src0,
141 const union tgsi_exec_channel *src1,
142 const union tgsi_exec_channel *src2)
143 {
144 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
145 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
146 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
147 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
148 }
149
150 static void
151 micro_cos(union tgsi_exec_channel *dst,
152 const union tgsi_exec_channel *src)
153 {
154 dst->f[0] = cosf(src->f[0]);
155 dst->f[1] = cosf(src->f[1]);
156 dst->f[2] = cosf(src->f[2]);
157 dst->f[3] = cosf(src->f[3]);
158 }
159
160 static void
161 micro_d2f(union tgsi_exec_channel *dst,
162 const union tgsi_double_channel *src)
163 {
164 dst->f[0] = (float)src->d[0];
165 dst->f[1] = (float)src->d[1];
166 dst->f[2] = (float)src->d[2];
167 dst->f[3] = (float)src->d[3];
168 }
169
170 static void
171 micro_d2i(union tgsi_exec_channel *dst,
172 const union tgsi_double_channel *src)
173 {
174 dst->i[0] = (int)src->d[0];
175 dst->i[1] = (int)src->d[1];
176 dst->i[2] = (int)src->d[2];
177 dst->i[3] = (int)src->d[3];
178 }
179
180 static void
181 micro_d2u(union tgsi_exec_channel *dst,
182 const union tgsi_double_channel *src)
183 {
184 dst->u[0] = (unsigned)src->d[0];
185 dst->u[1] = (unsigned)src->d[1];
186 dst->u[2] = (unsigned)src->d[2];
187 dst->u[3] = (unsigned)src->d[3];
188 }
189 static void
190 micro_dabs(union tgsi_double_channel *dst,
191 const union tgsi_double_channel *src)
192 {
193 dst->d[0] = src->d[0] >= 0.0 ? src->d[0] : -src->d[0];
194 dst->d[1] = src->d[1] >= 0.0 ? src->d[1] : -src->d[1];
195 dst->d[2] = src->d[2] >= 0.0 ? src->d[2] : -src->d[2];
196 dst->d[3] = src->d[3] >= 0.0 ? src->d[3] : -src->d[3];
197 }
198
199 static void
200 micro_dadd(union tgsi_double_channel *dst,
201 const union tgsi_double_channel *src)
202 {
203 dst->d[0] = src[0].d[0] + src[1].d[0];
204 dst->d[1] = src[0].d[1] + src[1].d[1];
205 dst->d[2] = src[0].d[2] + src[1].d[2];
206 dst->d[3] = src[0].d[3] + src[1].d[3];
207 }
208
209 static void
210 micro_ddx(union tgsi_exec_channel *dst,
211 const union tgsi_exec_channel *src)
212 {
213 dst->f[0] =
214 dst->f[1] =
215 dst->f[2] =
216 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
217 }
218
219 static void
220 micro_ddy(union tgsi_exec_channel *dst,
221 const union tgsi_exec_channel *src)
222 {
223 dst->f[0] =
224 dst->f[1] =
225 dst->f[2] =
226 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
227 }
228
229 static void
230 micro_dmul(union tgsi_double_channel *dst,
231 const union tgsi_double_channel *src)
232 {
233 dst->d[0] = src[0].d[0] * src[1].d[0];
234 dst->d[1] = src[0].d[1] * src[1].d[1];
235 dst->d[2] = src[0].d[2] * src[1].d[2];
236 dst->d[3] = src[0].d[3] * src[1].d[3];
237 }
238
239 static void
240 micro_dmax(union tgsi_double_channel *dst,
241 const union tgsi_double_channel *src)
242 {
243 dst->d[0] = src[0].d[0] > src[1].d[0] ? src[0].d[0] : src[1].d[0];
244 dst->d[1] = src[0].d[1] > src[1].d[1] ? src[0].d[1] : src[1].d[1];
245 dst->d[2] = src[0].d[2] > src[1].d[2] ? src[0].d[2] : src[1].d[2];
246 dst->d[3] = src[0].d[3] > src[1].d[3] ? src[0].d[3] : src[1].d[3];
247 }
248
249 static void
250 micro_dmin(union tgsi_double_channel *dst,
251 const union tgsi_double_channel *src)
252 {
253 dst->d[0] = src[0].d[0] < src[1].d[0] ? src[0].d[0] : src[1].d[0];
254 dst->d[1] = src[0].d[1] < src[1].d[1] ? src[0].d[1] : src[1].d[1];
255 dst->d[2] = src[0].d[2] < src[1].d[2] ? src[0].d[2] : src[1].d[2];
256 dst->d[3] = src[0].d[3] < src[1].d[3] ? src[0].d[3] : src[1].d[3];
257 }
258
259 static void
260 micro_dneg(union tgsi_double_channel *dst,
261 const union tgsi_double_channel *src)
262 {
263 dst->d[0] = -src->d[0];
264 dst->d[1] = -src->d[1];
265 dst->d[2] = -src->d[2];
266 dst->d[3] = -src->d[3];
267 }
268
269 static void
270 micro_dslt(union tgsi_double_channel *dst,
271 const union tgsi_double_channel *src)
272 {
273 dst->u[0][0] = src[0].d[0] < src[1].d[0] ? ~0U : 0U;
274 dst->u[1][0] = src[0].d[1] < src[1].d[1] ? ~0U : 0U;
275 dst->u[2][0] = src[0].d[2] < src[1].d[2] ? ~0U : 0U;
276 dst->u[3][0] = src[0].d[3] < src[1].d[3] ? ~0U : 0U;
277 }
278
279 static void
280 micro_dsne(union tgsi_double_channel *dst,
281 const union tgsi_double_channel *src)
282 {
283 dst->u[0][0] = src[0].d[0] != src[1].d[0] ? ~0U : 0U;
284 dst->u[1][0] = src[0].d[1] != src[1].d[1] ? ~0U : 0U;
285 dst->u[2][0] = src[0].d[2] != src[1].d[2] ? ~0U : 0U;
286 dst->u[3][0] = src[0].d[3] != src[1].d[3] ? ~0U : 0U;
287 }
288
289 static void
290 micro_dsge(union tgsi_double_channel *dst,
291 const union tgsi_double_channel *src)
292 {
293 dst->u[0][0] = src[0].d[0] >= src[1].d[0] ? ~0U : 0U;
294 dst->u[1][0] = src[0].d[1] >= src[1].d[1] ? ~0U : 0U;
295 dst->u[2][0] = src[0].d[2] >= src[1].d[2] ? ~0U : 0U;
296 dst->u[3][0] = src[0].d[3] >= src[1].d[3] ? ~0U : 0U;
297 }
298
299 static void
300 micro_dseq(union tgsi_double_channel *dst,
301 const union tgsi_double_channel *src)
302 {
303 dst->u[0][0] = src[0].d[0] == src[1].d[0] ? ~0U : 0U;
304 dst->u[1][0] = src[0].d[1] == src[1].d[1] ? ~0U : 0U;
305 dst->u[2][0] = src[0].d[2] == src[1].d[2] ? ~0U : 0U;
306 dst->u[3][0] = src[0].d[3] == src[1].d[3] ? ~0U : 0U;
307 }
308
309 static void
310 micro_drcp(union tgsi_double_channel *dst,
311 const union tgsi_double_channel *src)
312 {
313 dst->d[0] = 1.0 / src->d[0];
314 dst->d[1] = 1.0 / src->d[1];
315 dst->d[2] = 1.0 / src->d[2];
316 dst->d[3] = 1.0 / src->d[3];
317 }
318
319 static void
320 micro_dsqrt(union tgsi_double_channel *dst,
321 const union tgsi_double_channel *src)
322 {
323 dst->d[0] = sqrt(src->d[0]);
324 dst->d[1] = sqrt(src->d[1]);
325 dst->d[2] = sqrt(src->d[2]);
326 dst->d[3] = sqrt(src->d[3]);
327 }
328
329 static void
330 micro_drsq(union tgsi_double_channel *dst,
331 const union tgsi_double_channel *src)
332 {
333 dst->d[0] = 1.0 / sqrt(src->d[0]);
334 dst->d[1] = 1.0 / sqrt(src->d[1]);
335 dst->d[2] = 1.0 / sqrt(src->d[2]);
336 dst->d[3] = 1.0 / sqrt(src->d[3]);
337 }
338
339 static void
340 micro_dmad(union tgsi_double_channel *dst,
341 const union tgsi_double_channel *src)
342 {
343 dst->d[0] = src[0].d[0] * src[1].d[0] + src[2].d[0];
344 dst->d[1] = src[0].d[1] * src[1].d[1] + src[2].d[1];
345 dst->d[2] = src[0].d[2] * src[1].d[2] + src[2].d[2];
346 dst->d[3] = src[0].d[3] * src[1].d[3] + src[2].d[3];
347 }
348
349 static void
350 micro_dfrac(union tgsi_double_channel *dst,
351 const union tgsi_double_channel *src)
352 {
353 dst->d[0] = src->d[0] - floor(src->d[0]);
354 dst->d[1] = src->d[1] - floor(src->d[1]);
355 dst->d[2] = src->d[2] - floor(src->d[2]);
356 dst->d[3] = src->d[3] - floor(src->d[3]);
357 }
358
359 static void
360 micro_dldexp(union tgsi_double_channel *dst,
361 const union tgsi_double_channel *src0,
362 union tgsi_exec_channel *src1)
363 {
364 dst->d[0] = ldexp(src0->d[0], src1->i[0]);
365 dst->d[1] = ldexp(src0->d[1], src1->i[1]);
366 dst->d[2] = ldexp(src0->d[2], src1->i[2]);
367 dst->d[3] = ldexp(src0->d[3], src1->i[3]);
368 }
369
370 static void
371 micro_dfracexp(union tgsi_double_channel *dst,
372 union tgsi_exec_channel *dst_exp,
373 const union tgsi_double_channel *src)
374 {
375 dst->d[0] = frexp(src->d[0], &dst_exp->i[0]);
376 dst->d[1] = frexp(src->d[1], &dst_exp->i[1]);
377 dst->d[2] = frexp(src->d[2], &dst_exp->i[2]);
378 dst->d[3] = frexp(src->d[3], &dst_exp->i[3]);
379 }
380
381 static void
382 micro_exp2(union tgsi_exec_channel *dst,
383 const union tgsi_exec_channel *src)
384 {
385 #if FAST_MATH
386 dst->f[0] = util_fast_exp2(src->f[0]);
387 dst->f[1] = util_fast_exp2(src->f[1]);
388 dst->f[2] = util_fast_exp2(src->f[2]);
389 dst->f[3] = util_fast_exp2(src->f[3]);
390 #else
391 #if DEBUG
392 /* Inf is okay for this instruction, so clamp it to silence assertions. */
393 uint i;
394 union tgsi_exec_channel clamped;
395
396 for (i = 0; i < 4; i++) {
397 if (src->f[i] > 127.99999f) {
398 clamped.f[i] = 127.99999f;
399 } else if (src->f[i] < -126.99999f) {
400 clamped.f[i] = -126.99999f;
401 } else {
402 clamped.f[i] = src->f[i];
403 }
404 }
405 src = &clamped;
406 #endif /* DEBUG */
407
408 dst->f[0] = powf(2.0f, src->f[0]);
409 dst->f[1] = powf(2.0f, src->f[1]);
410 dst->f[2] = powf(2.0f, src->f[2]);
411 dst->f[3] = powf(2.0f, src->f[3]);
412 #endif /* FAST_MATH */
413 }
414
415 static void
416 micro_f2d(union tgsi_double_channel *dst,
417 const union tgsi_exec_channel *src)
418 {
419 dst->d[0] = (double)src->f[0];
420 dst->d[1] = (double)src->f[1];
421 dst->d[2] = (double)src->f[2];
422 dst->d[3] = (double)src->f[3];
423 }
424
425 static void
426 micro_flr(union tgsi_exec_channel *dst,
427 const union tgsi_exec_channel *src)
428 {
429 dst->f[0] = floorf(src->f[0]);
430 dst->f[1] = floorf(src->f[1]);
431 dst->f[2] = floorf(src->f[2]);
432 dst->f[3] = floorf(src->f[3]);
433 }
434
435 static void
436 micro_frc(union tgsi_exec_channel *dst,
437 const union tgsi_exec_channel *src)
438 {
439 dst->f[0] = src->f[0] - floorf(src->f[0]);
440 dst->f[1] = src->f[1] - floorf(src->f[1]);
441 dst->f[2] = src->f[2] - floorf(src->f[2]);
442 dst->f[3] = src->f[3] - floorf(src->f[3]);
443 }
444
445 static void
446 micro_i2d(union tgsi_double_channel *dst,
447 const union tgsi_exec_channel *src)
448 {
449 dst->d[0] = (double)src->i[0];
450 dst->d[1] = (double)src->i[1];
451 dst->d[2] = (double)src->i[2];
452 dst->d[3] = (double)src->i[3];
453 }
454
455 static void
456 micro_iabs(union tgsi_exec_channel *dst,
457 const union tgsi_exec_channel *src)
458 {
459 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
460 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
461 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
462 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
463 }
464
465 static void
466 micro_ineg(union tgsi_exec_channel *dst,
467 const union tgsi_exec_channel *src)
468 {
469 dst->i[0] = -src->i[0];
470 dst->i[1] = -src->i[1];
471 dst->i[2] = -src->i[2];
472 dst->i[3] = -src->i[3];
473 }
474
475 static void
476 micro_lg2(union tgsi_exec_channel *dst,
477 const union tgsi_exec_channel *src)
478 {
479 #if FAST_MATH
480 dst->f[0] = util_fast_log2(src->f[0]);
481 dst->f[1] = util_fast_log2(src->f[1]);
482 dst->f[2] = util_fast_log2(src->f[2]);
483 dst->f[3] = util_fast_log2(src->f[3]);
484 #else
485 dst->f[0] = logf(src->f[0]) * 1.442695f;
486 dst->f[1] = logf(src->f[1]) * 1.442695f;
487 dst->f[2] = logf(src->f[2]) * 1.442695f;
488 dst->f[3] = logf(src->f[3]) * 1.442695f;
489 #endif
490 }
491
492 static void
493 micro_lrp(union tgsi_exec_channel *dst,
494 const union tgsi_exec_channel *src0,
495 const union tgsi_exec_channel *src1,
496 const union tgsi_exec_channel *src2)
497 {
498 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
499 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
500 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
501 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
502 }
503
504 static void
505 micro_mad(union tgsi_exec_channel *dst,
506 const union tgsi_exec_channel *src0,
507 const union tgsi_exec_channel *src1,
508 const union tgsi_exec_channel *src2)
509 {
510 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
511 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
512 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
513 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
514 }
515
516 static void
517 micro_mov(union tgsi_exec_channel *dst,
518 const union tgsi_exec_channel *src)
519 {
520 dst->u[0] = src->u[0];
521 dst->u[1] = src->u[1];
522 dst->u[2] = src->u[2];
523 dst->u[3] = src->u[3];
524 }
525
526 static void
527 micro_rcp(union tgsi_exec_channel *dst,
528 const union tgsi_exec_channel *src)
529 {
530 #if 0 /* for debugging */
531 assert(src->f[0] != 0.0f);
532 assert(src->f[1] != 0.0f);
533 assert(src->f[2] != 0.0f);
534 assert(src->f[3] != 0.0f);
535 #endif
536 dst->f[0] = 1.0f / src->f[0];
537 dst->f[1] = 1.0f / src->f[1];
538 dst->f[2] = 1.0f / src->f[2];
539 dst->f[3] = 1.0f / src->f[3];
540 }
541
542 static void
543 micro_rnd(union tgsi_exec_channel *dst,
544 const union tgsi_exec_channel *src)
545 {
546 dst->f[0] = floorf(src->f[0] + 0.5f);
547 dst->f[1] = floorf(src->f[1] + 0.5f);
548 dst->f[2] = floorf(src->f[2] + 0.5f);
549 dst->f[3] = floorf(src->f[3] + 0.5f);
550 }
551
552 static void
553 micro_rsq(union tgsi_exec_channel *dst,
554 const union tgsi_exec_channel *src)
555 {
556 #if 0 /* for debugging */
557 assert(src->f[0] != 0.0f);
558 assert(src->f[1] != 0.0f);
559 assert(src->f[2] != 0.0f);
560 assert(src->f[3] != 0.0f);
561 #endif
562 dst->f[0] = 1.0f / sqrtf(src->f[0]);
563 dst->f[1] = 1.0f / sqrtf(src->f[1]);
564 dst->f[2] = 1.0f / sqrtf(src->f[2]);
565 dst->f[3] = 1.0f / sqrtf(src->f[3]);
566 }
567
568 static void
569 micro_sqrt(union tgsi_exec_channel *dst,
570 const union tgsi_exec_channel *src)
571 {
572 dst->f[0] = sqrtf(src->f[0]);
573 dst->f[1] = sqrtf(src->f[1]);
574 dst->f[2] = sqrtf(src->f[2]);
575 dst->f[3] = sqrtf(src->f[3]);
576 }
577
578 static void
579 micro_seq(union tgsi_exec_channel *dst,
580 const union tgsi_exec_channel *src0,
581 const union tgsi_exec_channel *src1)
582 {
583 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
584 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
585 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
586 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
587 }
588
589 static void
590 micro_sge(union tgsi_exec_channel *dst,
591 const union tgsi_exec_channel *src0,
592 const union tgsi_exec_channel *src1)
593 {
594 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
595 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
596 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
597 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
598 }
599
600 static void
601 micro_sgn(union tgsi_exec_channel *dst,
602 const union tgsi_exec_channel *src)
603 {
604 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
605 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
606 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
607 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
608 }
609
610 static void
611 micro_isgn(union tgsi_exec_channel *dst,
612 const union tgsi_exec_channel *src)
613 {
614 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
615 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
616 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
617 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
618 }
619
620 static void
621 micro_sgt(union tgsi_exec_channel *dst,
622 const union tgsi_exec_channel *src0,
623 const union tgsi_exec_channel *src1)
624 {
625 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
626 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
627 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
628 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
629 }
630
631 static void
632 micro_sin(union tgsi_exec_channel *dst,
633 const union tgsi_exec_channel *src)
634 {
635 dst->f[0] = sinf(src->f[0]);
636 dst->f[1] = sinf(src->f[1]);
637 dst->f[2] = sinf(src->f[2]);
638 dst->f[3] = sinf(src->f[3]);
639 }
640
641 static void
642 micro_sle(union tgsi_exec_channel *dst,
643 const union tgsi_exec_channel *src0,
644 const union tgsi_exec_channel *src1)
645 {
646 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
647 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
648 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
649 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
650 }
651
652 static void
653 micro_slt(union tgsi_exec_channel *dst,
654 const union tgsi_exec_channel *src0,
655 const union tgsi_exec_channel *src1)
656 {
657 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
658 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
659 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
660 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
661 }
662
663 static void
664 micro_sne(union tgsi_exec_channel *dst,
665 const union tgsi_exec_channel *src0,
666 const union tgsi_exec_channel *src1)
667 {
668 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
669 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
670 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
671 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
672 }
673
674 static void
675 micro_trunc(union tgsi_exec_channel *dst,
676 const union tgsi_exec_channel *src)
677 {
678 dst->f[0] = (float)(int)src->f[0];
679 dst->f[1] = (float)(int)src->f[1];
680 dst->f[2] = (float)(int)src->f[2];
681 dst->f[3] = (float)(int)src->f[3];
682 }
683
684 static void
685 micro_u2d(union tgsi_double_channel *dst,
686 const union tgsi_exec_channel *src)
687 {
688 dst->d[0] = (double)src->u[0];
689 dst->d[1] = (double)src->u[1];
690 dst->d[2] = (double)src->u[2];
691 dst->d[3] = (double)src->u[3];
692 }
693
694 enum tgsi_exec_datatype {
695 TGSI_EXEC_DATA_FLOAT,
696 TGSI_EXEC_DATA_INT,
697 TGSI_EXEC_DATA_UINT,
698 TGSI_EXEC_DATA_DOUBLE
699 };
700
701 /*
702 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
703 */
704 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
705 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
706 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
707 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
708 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
709 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
710
711
712 /** The execution mask depends on the conditional mask and the loop mask */
713 #define UPDATE_EXEC_MASK(MACH) \
714 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
715
716
717 static const union tgsi_exec_channel ZeroVec =
718 { { 0.0, 0.0, 0.0, 0.0 } };
719
720 static const union tgsi_exec_channel OneVec = {
721 {1.0f, 1.0f, 1.0f, 1.0f}
722 };
723
724 static const union tgsi_exec_channel P128Vec = {
725 {128.0f, 128.0f, 128.0f, 128.0f}
726 };
727
728 static const union tgsi_exec_channel M128Vec = {
729 {-128.0f, -128.0f, -128.0f, -128.0f}
730 };
731
732
733 /**
734 * Assert that none of the float values in 'chan' are infinite or NaN.
735 * NaN and Inf may occur normally during program execution and should
736 * not lead to crashes, etc. But when debugging, it's helpful to catch
737 * them.
738 */
739 static inline void
740 check_inf_or_nan(const union tgsi_exec_channel *chan)
741 {
742 assert(!util_is_inf_or_nan((chan)->f[0]));
743 assert(!util_is_inf_or_nan((chan)->f[1]));
744 assert(!util_is_inf_or_nan((chan)->f[2]));
745 assert(!util_is_inf_or_nan((chan)->f[3]));
746 }
747
748
749 #ifdef DEBUG
750 static void
751 print_chan(const char *msg, const union tgsi_exec_channel *chan)
752 {
753 debug_printf("%s = {%f, %f, %f, %f}\n",
754 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
755 }
756 #endif
757
758
759 #ifdef DEBUG
760 static void
761 print_temp(const struct tgsi_exec_machine *mach, uint index)
762 {
763 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
764 int i;
765 debug_printf("Temp[%u] =\n", index);
766 for (i = 0; i < 4; i++) {
767 debug_printf(" %c: { %f, %f, %f, %f }\n",
768 "XYZW"[i],
769 tmp->xyzw[i].f[0],
770 tmp->xyzw[i].f[1],
771 tmp->xyzw[i].f[2],
772 tmp->xyzw[i].f[3]);
773 }
774 }
775 #endif
776
777
778 void
779 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
780 unsigned num_bufs,
781 const void **bufs,
782 const unsigned *buf_sizes)
783 {
784 unsigned i;
785
786 for (i = 0; i < num_bufs; i++) {
787 mach->Consts[i] = bufs[i];
788 mach->ConstsSize[i] = buf_sizes[i];
789 }
790 }
791
792
793 /**
794 * Check if there's a potential src/dst register data dependency when
795 * using SOA execution.
796 * Example:
797 * MOV T, T.yxwz;
798 * This would expand into:
799 * MOV t0, t1;
800 * MOV t1, t0;
801 * MOV t2, t3;
802 * MOV t3, t2;
803 * The second instruction will have the wrong value for t0 if executed as-is.
804 */
805 boolean
806 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
807 {
808 uint i, chan;
809
810 uint writemask = inst->Dst[0].Register.WriteMask;
811 if (writemask == TGSI_WRITEMASK_X ||
812 writemask == TGSI_WRITEMASK_Y ||
813 writemask == TGSI_WRITEMASK_Z ||
814 writemask == TGSI_WRITEMASK_W ||
815 writemask == TGSI_WRITEMASK_NONE) {
816 /* no chance of data dependency */
817 return FALSE;
818 }
819
820 /* loop over src regs */
821 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
822 if ((inst->Src[i].Register.File ==
823 inst->Dst[0].Register.File) &&
824 ((inst->Src[i].Register.Index ==
825 inst->Dst[0].Register.Index) ||
826 inst->Src[i].Register.Indirect ||
827 inst->Dst[0].Register.Indirect)) {
828 /* loop over dest channels */
829 uint channelsWritten = 0x0;
830 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
831 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
832 /* check if we're reading a channel that's been written */
833 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
834 if (channelsWritten & (1 << swizzle)) {
835 return TRUE;
836 }
837
838 channelsWritten |= (1 << chan);
839 }
840 }
841 }
842 }
843 return FALSE;
844 }
845
846
847 /**
848 * Initialize machine state by expanding tokens to full instructions,
849 * allocating temporary storage, setting up constants, etc.
850 * After this, we can call tgsi_exec_machine_run() many times.
851 */
852 void
853 tgsi_exec_machine_bind_shader(
854 struct tgsi_exec_machine *mach,
855 const struct tgsi_token *tokens,
856 struct tgsi_sampler *sampler,
857 struct tgsi_image *image,
858 struct tgsi_buffer *buffer)
859 {
860 uint k;
861 struct tgsi_parse_context parse;
862 struct tgsi_full_instruction *instructions;
863 struct tgsi_full_declaration *declarations;
864 uint maxInstructions = 10, numInstructions = 0;
865 uint maxDeclarations = 10, numDeclarations = 0;
866
867 #if 0
868 tgsi_dump(tokens, 0);
869 #endif
870
871 util_init_math();
872
873
874 mach->Tokens = tokens;
875 mach->Sampler = sampler;
876 mach->Image = image;
877 mach->Buffer = buffer;
878
879 if (!tokens) {
880 /* unbind and free all */
881 FREE(mach->Declarations);
882 mach->Declarations = NULL;
883 mach->NumDeclarations = 0;
884
885 FREE(mach->Instructions);
886 mach->Instructions = NULL;
887 mach->NumInstructions = 0;
888
889 return;
890 }
891
892 k = tgsi_parse_init (&parse, mach->Tokens);
893 if (k != TGSI_PARSE_OK) {
894 debug_printf( "Problem parsing!\n" );
895 return;
896 }
897
898 mach->ImmLimit = 0;
899 mach->NumOutputs = 0;
900
901 if (mach->ShaderType == PIPE_SHADER_GEOMETRY &&
902 !mach->UsedGeometryShader) {
903 struct tgsi_exec_vector *inputs;
904 struct tgsi_exec_vector *outputs;
905
906 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
907 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_SHADER_INPUTS,
908 16);
909
910 if (!inputs)
911 return;
912
913 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
914 TGSI_MAX_TOTAL_VERTICES, 16);
915
916 if (!outputs) {
917 align_free(inputs);
918 return;
919 }
920
921 align_free(mach->Inputs);
922 align_free(mach->Outputs);
923
924 mach->Inputs = inputs;
925 mach->Outputs = outputs;
926 mach->UsedGeometryShader = TRUE;
927 }
928
929 declarations = (struct tgsi_full_declaration *)
930 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
931
932 if (!declarations) {
933 return;
934 }
935
936 instructions = (struct tgsi_full_instruction *)
937 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
938
939 if (!instructions) {
940 FREE( declarations );
941 return;
942 }
943
944 while( !tgsi_parse_end_of_tokens( &parse ) ) {
945 uint i;
946
947 tgsi_parse_token( &parse );
948 switch( parse.FullToken.Token.Type ) {
949 case TGSI_TOKEN_TYPE_DECLARATION:
950 /* save expanded declaration */
951 if (numDeclarations == maxDeclarations) {
952 declarations = REALLOC(declarations,
953 maxDeclarations
954 * sizeof(struct tgsi_full_declaration),
955 (maxDeclarations + 10)
956 * sizeof(struct tgsi_full_declaration));
957 maxDeclarations += 10;
958 }
959 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
960 unsigned reg;
961 for (reg = parse.FullToken.FullDeclaration.Range.First;
962 reg <= parse.FullToken.FullDeclaration.Range.Last;
963 ++reg) {
964 ++mach->NumOutputs;
965 }
966 }
967 memcpy(declarations + numDeclarations,
968 &parse.FullToken.FullDeclaration,
969 sizeof(declarations[0]));
970 numDeclarations++;
971 break;
972
973 case TGSI_TOKEN_TYPE_IMMEDIATE:
974 {
975 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
976 assert( size <= 4 );
977 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
978
979 for( i = 0; i < size; i++ ) {
980 mach->Imms[mach->ImmLimit][i] =
981 parse.FullToken.FullImmediate.u[i].Float;
982 }
983 mach->ImmLimit += 1;
984 }
985 break;
986
987 case TGSI_TOKEN_TYPE_INSTRUCTION:
988
989 /* save expanded instruction */
990 if (numInstructions == maxInstructions) {
991 instructions = REALLOC(instructions,
992 maxInstructions
993 * sizeof(struct tgsi_full_instruction),
994 (maxInstructions + 10)
995 * sizeof(struct tgsi_full_instruction));
996 maxInstructions += 10;
997 }
998
999 memcpy(instructions + numInstructions,
1000 &parse.FullToken.FullInstruction,
1001 sizeof(instructions[0]));
1002
1003 numInstructions++;
1004 break;
1005
1006 case TGSI_TOKEN_TYPE_PROPERTY:
1007 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
1008 if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) {
1009 mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data;
1010 }
1011 }
1012 break;
1013
1014 default:
1015 assert( 0 );
1016 }
1017 }
1018 tgsi_parse_free (&parse);
1019
1020 FREE(mach->Declarations);
1021 mach->Declarations = declarations;
1022 mach->NumDeclarations = numDeclarations;
1023
1024 FREE(mach->Instructions);
1025 mach->Instructions = instructions;
1026 mach->NumInstructions = numInstructions;
1027 }
1028
1029
1030 struct tgsi_exec_machine *
1031 tgsi_exec_machine_create(enum pipe_shader_type shader_type)
1032 {
1033 struct tgsi_exec_machine *mach;
1034 uint i;
1035
1036 mach = align_malloc( sizeof *mach, 16 );
1037 if (!mach)
1038 goto fail;
1039
1040 memset(mach, 0, sizeof(*mach));
1041
1042 mach->ShaderType = shader_type;
1043 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
1044 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
1045 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
1046
1047 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
1048 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
1049 if (!mach->Inputs || !mach->Outputs)
1050 goto fail;
1051
1052 /* Setup constants needed by the SSE2 executor. */
1053 for( i = 0; i < 4; i++ ) {
1054 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
1055 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
1056 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
1057 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
1058 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
1059 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
1060 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
1061 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
1062 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
1063 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
1064 }
1065
1066 #ifdef DEBUG
1067 /* silence warnings */
1068 (void) print_chan;
1069 (void) print_temp;
1070 #endif
1071
1072 return mach;
1073
1074 fail:
1075 if (mach) {
1076 align_free(mach->Inputs);
1077 align_free(mach->Outputs);
1078 align_free(mach);
1079 }
1080 return NULL;
1081 }
1082
1083
1084 void
1085 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
1086 {
1087 if (mach) {
1088 FREE(mach->Instructions);
1089 FREE(mach->Declarations);
1090
1091 align_free(mach->Inputs);
1092 align_free(mach->Outputs);
1093
1094 align_free(mach);
1095 }
1096 }
1097
1098 static void
1099 micro_add(union tgsi_exec_channel *dst,
1100 const union tgsi_exec_channel *src0,
1101 const union tgsi_exec_channel *src1)
1102 {
1103 dst->f[0] = src0->f[0] + src1->f[0];
1104 dst->f[1] = src0->f[1] + src1->f[1];
1105 dst->f[2] = src0->f[2] + src1->f[2];
1106 dst->f[3] = src0->f[3] + src1->f[3];
1107 }
1108
1109 static void
1110 micro_div(
1111 union tgsi_exec_channel *dst,
1112 const union tgsi_exec_channel *src0,
1113 const union tgsi_exec_channel *src1 )
1114 {
1115 if (src1->f[0] != 0) {
1116 dst->f[0] = src0->f[0] / src1->f[0];
1117 }
1118 if (src1->f[1] != 0) {
1119 dst->f[1] = src0->f[1] / src1->f[1];
1120 }
1121 if (src1->f[2] != 0) {
1122 dst->f[2] = src0->f[2] / src1->f[2];
1123 }
1124 if (src1->f[3] != 0) {
1125 dst->f[3] = src0->f[3] / src1->f[3];
1126 }
1127 }
1128
1129 static void
1130 micro_lt(
1131 union tgsi_exec_channel *dst,
1132 const union tgsi_exec_channel *src0,
1133 const union tgsi_exec_channel *src1,
1134 const union tgsi_exec_channel *src2,
1135 const union tgsi_exec_channel *src3 )
1136 {
1137 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
1138 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
1139 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
1140 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
1141 }
1142
1143 static void
1144 micro_max(union tgsi_exec_channel *dst,
1145 const union tgsi_exec_channel *src0,
1146 const union tgsi_exec_channel *src1)
1147 {
1148 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
1149 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
1150 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
1151 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
1152 }
1153
1154 static void
1155 micro_min(union tgsi_exec_channel *dst,
1156 const union tgsi_exec_channel *src0,
1157 const union tgsi_exec_channel *src1)
1158 {
1159 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
1160 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
1161 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
1162 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
1163 }
1164
1165 static void
1166 micro_mul(union tgsi_exec_channel *dst,
1167 const union tgsi_exec_channel *src0,
1168 const union tgsi_exec_channel *src1)
1169 {
1170 dst->f[0] = src0->f[0] * src1->f[0];
1171 dst->f[1] = src0->f[1] * src1->f[1];
1172 dst->f[2] = src0->f[2] * src1->f[2];
1173 dst->f[3] = src0->f[3] * src1->f[3];
1174 }
1175
1176 static void
1177 micro_neg(
1178 union tgsi_exec_channel *dst,
1179 const union tgsi_exec_channel *src )
1180 {
1181 dst->f[0] = -src->f[0];
1182 dst->f[1] = -src->f[1];
1183 dst->f[2] = -src->f[2];
1184 dst->f[3] = -src->f[3];
1185 }
1186
1187 static void
1188 micro_pow(
1189 union tgsi_exec_channel *dst,
1190 const union tgsi_exec_channel *src0,
1191 const union tgsi_exec_channel *src1 )
1192 {
1193 #if FAST_MATH
1194 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
1195 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
1196 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
1197 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
1198 #else
1199 dst->f[0] = powf( src0->f[0], src1->f[0] );
1200 dst->f[1] = powf( src0->f[1], src1->f[1] );
1201 dst->f[2] = powf( src0->f[2], src1->f[2] );
1202 dst->f[3] = powf( src0->f[3], src1->f[3] );
1203 #endif
1204 }
1205
1206 static void
1207 micro_sub(union tgsi_exec_channel *dst,
1208 const union tgsi_exec_channel *src0,
1209 const union tgsi_exec_channel *src1)
1210 {
1211 dst->f[0] = src0->f[0] - src1->f[0];
1212 dst->f[1] = src0->f[1] - src1->f[1];
1213 dst->f[2] = src0->f[2] - src1->f[2];
1214 dst->f[3] = src0->f[3] - src1->f[3];
1215 }
1216
1217 static void
1218 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1219 const uint chan_index,
1220 const uint file,
1221 const uint swizzle,
1222 const union tgsi_exec_channel *index,
1223 const union tgsi_exec_channel *index2D,
1224 union tgsi_exec_channel *chan)
1225 {
1226 uint i;
1227
1228 assert(swizzle < 4);
1229
1230 switch (file) {
1231 case TGSI_FILE_CONSTANT:
1232 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1233 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1234 assert(mach->Consts[index2D->i[i]]);
1235
1236 if (index->i[i] < 0) {
1237 chan->u[i] = 0;
1238 } else {
1239 /* NOTE: copying the const value as a uint instead of float */
1240 const uint constbuf = index2D->i[i];
1241 const uint *buf = (const uint *)mach->Consts[constbuf];
1242 const int pos = index->i[i] * 4 + swizzle;
1243 /* const buffer bounds check */
1244 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1245 if (0) {
1246 /* Debug: print warning */
1247 static int count = 0;
1248 if (count++ < 100)
1249 debug_printf("TGSI Exec: const buffer index %d"
1250 " out of bounds\n", pos);
1251 }
1252 chan->u[i] = 0;
1253 }
1254 else
1255 chan->u[i] = buf[pos];
1256 }
1257 }
1258 break;
1259
1260 case TGSI_FILE_INPUT:
1261 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1262 /*
1263 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1264 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1265 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1266 index2D->i[i], index->i[i]);
1267 }*/
1268 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1269 assert(pos >= 0);
1270 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1271 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1272 }
1273 break;
1274
1275 case TGSI_FILE_SYSTEM_VALUE:
1276 /* XXX no swizzling at this point. Will be needed if we put
1277 * gl_FragCoord, for example, in a sys value register.
1278 */
1279 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1280 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1281 }
1282 break;
1283
1284 case TGSI_FILE_TEMPORARY:
1285 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1286 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1287 assert(index2D->i[i] == 0);
1288
1289 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1290 }
1291 break;
1292
1293 case TGSI_FILE_IMMEDIATE:
1294 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1295 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1296 assert(index2D->i[i] == 0);
1297
1298 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1299 }
1300 break;
1301
1302 case TGSI_FILE_ADDRESS:
1303 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1304 assert(index->i[i] >= 0);
1305 assert(index2D->i[i] == 0);
1306
1307 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1308 }
1309 break;
1310
1311 case TGSI_FILE_PREDICATE:
1312 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1313 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1314 assert(index2D->i[i] == 0);
1315
1316 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1317 }
1318 break;
1319
1320 case TGSI_FILE_OUTPUT:
1321 /* vertex/fragment output vars can be read too */
1322 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1323 assert(index->i[i] >= 0);
1324 assert(index2D->i[i] == 0);
1325
1326 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1327 }
1328 break;
1329
1330 default:
1331 assert(0);
1332 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1333 chan->u[i] = 0;
1334 }
1335 }
1336 }
1337
1338 static void
1339 fetch_source_d(const struct tgsi_exec_machine *mach,
1340 union tgsi_exec_channel *chan,
1341 const struct tgsi_full_src_register *reg,
1342 const uint chan_index,
1343 enum tgsi_exec_datatype src_datatype)
1344 {
1345 union tgsi_exec_channel index;
1346 union tgsi_exec_channel index2D;
1347 uint swizzle;
1348
1349 /* We start with a direct index into a register file.
1350 *
1351 * file[1],
1352 * where:
1353 * file = Register.File
1354 * [1] = Register.Index
1355 */
1356 index.i[0] =
1357 index.i[1] =
1358 index.i[2] =
1359 index.i[3] = reg->Register.Index;
1360
1361 /* There is an extra source register that indirectly subscripts
1362 * a register file. The direct index now becomes an offset
1363 * that is being added to the indirect register.
1364 *
1365 * file[ind[2].x+1],
1366 * where:
1367 * ind = Indirect.File
1368 * [2] = Indirect.Index
1369 * .x = Indirect.SwizzleX
1370 */
1371 if (reg->Register.Indirect) {
1372 union tgsi_exec_channel index2;
1373 union tgsi_exec_channel indir_index;
1374 const uint execmask = mach->ExecMask;
1375 uint i;
1376
1377 /* which address register (always zero now) */
1378 index2.i[0] =
1379 index2.i[1] =
1380 index2.i[2] =
1381 index2.i[3] = reg->Indirect.Index;
1382 /* get current value of address register[swizzle] */
1383 swizzle = reg->Indirect.Swizzle;
1384 fetch_src_file_channel(mach,
1385 chan_index,
1386 reg->Indirect.File,
1387 swizzle,
1388 &index2,
1389 &ZeroVec,
1390 &indir_index);
1391
1392 /* add value of address register to the offset */
1393 index.i[0] += indir_index.i[0];
1394 index.i[1] += indir_index.i[1];
1395 index.i[2] += indir_index.i[2];
1396 index.i[3] += indir_index.i[3];
1397
1398 /* for disabled execution channels, zero-out the index to
1399 * avoid using a potential garbage value.
1400 */
1401 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1402 if ((execmask & (1 << i)) == 0)
1403 index.i[i] = 0;
1404 }
1405 }
1406
1407 /* There is an extra source register that is a second
1408 * subscript to a register file. Effectively it means that
1409 * the register file is actually a 2D array of registers.
1410 *
1411 * file[3][1],
1412 * where:
1413 * [3] = Dimension.Index
1414 */
1415 if (reg->Register.Dimension) {
1416 index2D.i[0] =
1417 index2D.i[1] =
1418 index2D.i[2] =
1419 index2D.i[3] = reg->Dimension.Index;
1420
1421 /* Again, the second subscript index can be addressed indirectly
1422 * identically to the first one.
1423 * Nothing stops us from indirectly addressing the indirect register,
1424 * but there is no need for that, so we won't exercise it.
1425 *
1426 * file[ind[4].y+3][1],
1427 * where:
1428 * ind = DimIndirect.File
1429 * [4] = DimIndirect.Index
1430 * .y = DimIndirect.SwizzleX
1431 */
1432 if (reg->Dimension.Indirect) {
1433 union tgsi_exec_channel index2;
1434 union tgsi_exec_channel indir_index;
1435 const uint execmask = mach->ExecMask;
1436 uint i;
1437
1438 index2.i[0] =
1439 index2.i[1] =
1440 index2.i[2] =
1441 index2.i[3] = reg->DimIndirect.Index;
1442
1443 swizzle = reg->DimIndirect.Swizzle;
1444 fetch_src_file_channel(mach,
1445 chan_index,
1446 reg->DimIndirect.File,
1447 swizzle,
1448 &index2,
1449 &ZeroVec,
1450 &indir_index);
1451
1452 index2D.i[0] += indir_index.i[0];
1453 index2D.i[1] += indir_index.i[1];
1454 index2D.i[2] += indir_index.i[2];
1455 index2D.i[3] += indir_index.i[3];
1456
1457 /* for disabled execution channels, zero-out the index to
1458 * avoid using a potential garbage value.
1459 */
1460 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1461 if ((execmask & (1 << i)) == 0) {
1462 index2D.i[i] = 0;
1463 }
1464 }
1465 }
1466
1467 /* If by any chance there was a need for a 3D array of register
1468 * files, we would have to check whether Dimension is followed
1469 * by a dimension register and continue the saga.
1470 */
1471 } else {
1472 index2D.i[0] =
1473 index2D.i[1] =
1474 index2D.i[2] =
1475 index2D.i[3] = 0;
1476 }
1477
1478 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1479 fetch_src_file_channel(mach,
1480 chan_index,
1481 reg->Register.File,
1482 swizzle,
1483 &index,
1484 &index2D,
1485 chan);
1486 }
1487
1488 static void
1489 fetch_source(const struct tgsi_exec_machine *mach,
1490 union tgsi_exec_channel *chan,
1491 const struct tgsi_full_src_register *reg,
1492 const uint chan_index,
1493 enum tgsi_exec_datatype src_datatype)
1494 {
1495 fetch_source_d(mach, chan, reg, chan_index, src_datatype);
1496
1497 if (reg->Register.Absolute) {
1498 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1499 micro_abs(chan, chan);
1500 } else {
1501 micro_iabs(chan, chan);
1502 }
1503 }
1504
1505 if (reg->Register.Negate) {
1506 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1507 micro_neg(chan, chan);
1508 } else {
1509 micro_ineg(chan, chan);
1510 }
1511 }
1512 }
1513
1514 static union tgsi_exec_channel *
1515 store_dest_dstret(struct tgsi_exec_machine *mach,
1516 const union tgsi_exec_channel *chan,
1517 const struct tgsi_full_dst_register *reg,
1518 const struct tgsi_full_instruction *inst,
1519 uint chan_index,
1520 enum tgsi_exec_datatype dst_datatype)
1521 {
1522 uint i;
1523 static union tgsi_exec_channel null;
1524 union tgsi_exec_channel *dst;
1525 union tgsi_exec_channel index2D;
1526 uint execmask = mach->ExecMask;
1527 int offset = 0; /* indirection offset */
1528 int index;
1529
1530 /* for debugging */
1531 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1532 check_inf_or_nan(chan);
1533 }
1534
1535 /* There is an extra source register that indirectly subscripts
1536 * a register file. The direct index now becomes an offset
1537 * that is being added to the indirect register.
1538 *
1539 * file[ind[2].x+1],
1540 * where:
1541 * ind = Indirect.File
1542 * [2] = Indirect.Index
1543 * .x = Indirect.SwizzleX
1544 */
1545 if (reg->Register.Indirect) {
1546 union tgsi_exec_channel index;
1547 union tgsi_exec_channel indir_index;
1548 uint swizzle;
1549
1550 /* which address register (always zero for now) */
1551 index.i[0] =
1552 index.i[1] =
1553 index.i[2] =
1554 index.i[3] = reg->Indirect.Index;
1555
1556 /* get current value of address register[swizzle] */
1557 swizzle = reg->Indirect.Swizzle;
1558
1559 /* fetch values from the address/indirection register */
1560 fetch_src_file_channel(mach,
1561 chan_index,
1562 reg->Indirect.File,
1563 swizzle,
1564 &index,
1565 &ZeroVec,
1566 &indir_index);
1567
1568 /* save indirection offset */
1569 offset = indir_index.i[0];
1570 }
1571
1572 /* There is an extra source register that is a second
1573 * subscript to a register file. Effectively it means that
1574 * the register file is actually a 2D array of registers.
1575 *
1576 * file[3][1],
1577 * where:
1578 * [3] = Dimension.Index
1579 */
1580 if (reg->Register.Dimension) {
1581 index2D.i[0] =
1582 index2D.i[1] =
1583 index2D.i[2] =
1584 index2D.i[3] = reg->Dimension.Index;
1585
1586 /* Again, the second subscript index can be addressed indirectly
1587 * identically to the first one.
1588 * Nothing stops us from indirectly addressing the indirect register,
1589 * but there is no need for that, so we won't exercise it.
1590 *
1591 * file[ind[4].y+3][1],
1592 * where:
1593 * ind = DimIndirect.File
1594 * [4] = DimIndirect.Index
1595 * .y = DimIndirect.SwizzleX
1596 */
1597 if (reg->Dimension.Indirect) {
1598 union tgsi_exec_channel index2;
1599 union tgsi_exec_channel indir_index;
1600 const uint execmask = mach->ExecMask;
1601 unsigned swizzle;
1602 uint i;
1603
1604 index2.i[0] =
1605 index2.i[1] =
1606 index2.i[2] =
1607 index2.i[3] = reg->DimIndirect.Index;
1608
1609 swizzle = reg->DimIndirect.Swizzle;
1610 fetch_src_file_channel(mach,
1611 chan_index,
1612 reg->DimIndirect.File,
1613 swizzle,
1614 &index2,
1615 &ZeroVec,
1616 &indir_index);
1617
1618 index2D.i[0] += indir_index.i[0];
1619 index2D.i[1] += indir_index.i[1];
1620 index2D.i[2] += indir_index.i[2];
1621 index2D.i[3] += indir_index.i[3];
1622
1623 /* for disabled execution channels, zero-out the index to
1624 * avoid using a potential garbage value.
1625 */
1626 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1627 if ((execmask & (1 << i)) == 0) {
1628 index2D.i[i] = 0;
1629 }
1630 }
1631 }
1632
1633 /* If by any chance there was a need for a 3D array of register
1634 * files, we would have to check whether Dimension is followed
1635 * by a dimension register and continue the saga.
1636 */
1637 } else {
1638 index2D.i[0] =
1639 index2D.i[1] =
1640 index2D.i[2] =
1641 index2D.i[3] = 0;
1642 }
1643
1644 switch (reg->Register.File) {
1645 case TGSI_FILE_NULL:
1646 dst = &null;
1647 break;
1648
1649 case TGSI_FILE_OUTPUT:
1650 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1651 + reg->Register.Index;
1652 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1653 #if 0
1654 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1655 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1656 reg->Register.Index);
1657 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1658 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1659 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1660 if (execmask & (1 << i))
1661 debug_printf("%f, ", chan->f[i]);
1662 debug_printf(")\n");
1663 }
1664 #endif
1665 break;
1666
1667 case TGSI_FILE_TEMPORARY:
1668 index = reg->Register.Index;
1669 assert( index < TGSI_EXEC_NUM_TEMPS );
1670 dst = &mach->Temps[offset + index].xyzw[chan_index];
1671 break;
1672
1673 case TGSI_FILE_ADDRESS:
1674 index = reg->Register.Index;
1675 dst = &mach->Addrs[index].xyzw[chan_index];
1676 break;
1677
1678 case TGSI_FILE_PREDICATE:
1679 index = reg->Register.Index;
1680 assert(index < TGSI_EXEC_NUM_PREDS);
1681 dst = &mach->Predicates[index].xyzw[chan_index];
1682 break;
1683
1684 default:
1685 assert( 0 );
1686 return NULL;
1687 }
1688
1689 if (inst->Instruction.Predicate) {
1690 uint swizzle;
1691 union tgsi_exec_channel *pred;
1692
1693 switch (chan_index) {
1694 case TGSI_CHAN_X:
1695 swizzle = inst->Predicate.SwizzleX;
1696 break;
1697 case TGSI_CHAN_Y:
1698 swizzle = inst->Predicate.SwizzleY;
1699 break;
1700 case TGSI_CHAN_Z:
1701 swizzle = inst->Predicate.SwizzleZ;
1702 break;
1703 case TGSI_CHAN_W:
1704 swizzle = inst->Predicate.SwizzleW;
1705 break;
1706 default:
1707 assert(0);
1708 return NULL;
1709 }
1710
1711 assert(inst->Predicate.Index == 0);
1712
1713 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1714
1715 if (inst->Predicate.Negate) {
1716 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1717 if (pred->u[i]) {
1718 execmask &= ~(1 << i);
1719 }
1720 }
1721 } else {
1722 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1723 if (!pred->u[i]) {
1724 execmask &= ~(1 << i);
1725 }
1726 }
1727 }
1728 }
1729
1730 return dst;
1731 }
1732
1733 static void
1734 store_dest_double(struct tgsi_exec_machine *mach,
1735 const union tgsi_exec_channel *chan,
1736 const struct tgsi_full_dst_register *reg,
1737 const struct tgsi_full_instruction *inst,
1738 uint chan_index,
1739 enum tgsi_exec_datatype dst_datatype)
1740 {
1741 union tgsi_exec_channel *dst;
1742 const uint execmask = mach->ExecMask;
1743 int i;
1744
1745 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1746 dst_datatype);
1747 if (!dst)
1748 return;
1749
1750 /* doubles path */
1751 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1752 if (execmask & (1 << i))
1753 dst->i[i] = chan->i[i];
1754 }
1755
1756 static void
1757 store_dest(struct tgsi_exec_machine *mach,
1758 const union tgsi_exec_channel *chan,
1759 const struct tgsi_full_dst_register *reg,
1760 const struct tgsi_full_instruction *inst,
1761 uint chan_index,
1762 enum tgsi_exec_datatype dst_datatype)
1763 {
1764 union tgsi_exec_channel *dst;
1765 const uint execmask = mach->ExecMask;
1766 int i;
1767
1768 dst = store_dest_dstret(mach, chan, reg, inst, chan_index,
1769 dst_datatype);
1770 if (!dst)
1771 return;
1772
1773 if (!inst->Instruction.Saturate) {
1774 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1775 if (execmask & (1 << i))
1776 dst->i[i] = chan->i[i];
1777 }
1778 else {
1779 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1780 if (execmask & (1 << i)) {
1781 if (chan->f[i] < 0.0f)
1782 dst->f[i] = 0.0f;
1783 else if (chan->f[i] > 1.0f)
1784 dst->f[i] = 1.0f;
1785 else
1786 dst->i[i] = chan->i[i];
1787 }
1788 }
1789 }
1790
1791 #define FETCH(VAL,INDEX,CHAN)\
1792 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1793
1794 #define IFETCH(VAL,INDEX,CHAN)\
1795 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1796
1797
1798 /**
1799 * Execute ARB-style KIL which is predicated by a src register.
1800 * Kill fragment if any of the four values is less than zero.
1801 */
1802 static void
1803 exec_kill_if(struct tgsi_exec_machine *mach,
1804 const struct tgsi_full_instruction *inst)
1805 {
1806 uint uniquemask;
1807 uint chan_index;
1808 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1809 union tgsi_exec_channel r[1];
1810
1811 /* This mask stores component bits that were already tested. */
1812 uniquemask = 0;
1813
1814 for (chan_index = 0; chan_index < 4; chan_index++)
1815 {
1816 uint swizzle;
1817 uint i;
1818
1819 /* unswizzle channel */
1820 swizzle = tgsi_util_get_full_src_register_swizzle (
1821 &inst->Src[0],
1822 chan_index);
1823
1824 /* check if the component has not been already tested */
1825 if (uniquemask & (1 << swizzle))
1826 continue;
1827 uniquemask |= 1 << swizzle;
1828
1829 FETCH(&r[0], 0, chan_index);
1830 for (i = 0; i < 4; i++)
1831 if (r[0].f[i] < 0.0f)
1832 kilmask |= 1 << i;
1833 }
1834
1835 /* restrict to fragments currently executing */
1836 kilmask &= mach->ExecMask;
1837
1838 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1839 }
1840
1841 /**
1842 * Unconditional fragment kill/discard.
1843 */
1844 static void
1845 exec_kill(struct tgsi_exec_machine *mach,
1846 const struct tgsi_full_instruction *inst)
1847 {
1848 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1849
1850 /* kill fragment for all fragments currently executing */
1851 kilmask = mach->ExecMask;
1852 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1853 }
1854
1855 static void
1856 emit_vertex(struct tgsi_exec_machine *mach)
1857 {
1858 /* FIXME: check for exec mask correctly
1859 unsigned i;
1860 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1861 if ((mach->ExecMask & (1 << i)))
1862 */
1863 if (mach->ExecMask) {
1864 if (mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]] >= mach->MaxOutputVertices)
1865 return;
1866
1867 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1868 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1869 }
1870 }
1871
1872 static void
1873 emit_primitive(struct tgsi_exec_machine *mach)
1874 {
1875 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1876 /* FIXME: check for exec mask correctly
1877 unsigned i;
1878 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1879 if ((mach->ExecMask & (1 << i)))
1880 */
1881 if (mach->ExecMask) {
1882 ++(*prim_count);
1883 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1884 mach->Primitives[*prim_count] = 0;
1885 }
1886 }
1887
1888 static void
1889 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1890 {
1891 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1892 int emitted_verts =
1893 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1894 if (emitted_verts) {
1895 emit_primitive(mach);
1896 }
1897 }
1898 }
1899
1900
1901 /*
1902 * Fetch four texture samples using STR texture coordinates.
1903 */
1904 static void
1905 fetch_texel( struct tgsi_sampler *sampler,
1906 const unsigned sview_idx,
1907 const unsigned sampler_idx,
1908 const union tgsi_exec_channel *s,
1909 const union tgsi_exec_channel *t,
1910 const union tgsi_exec_channel *p,
1911 const union tgsi_exec_channel *c0,
1912 const union tgsi_exec_channel *c1,
1913 float derivs[3][2][TGSI_QUAD_SIZE],
1914 const int8_t offset[3],
1915 enum tgsi_sampler_control control,
1916 union tgsi_exec_channel *r,
1917 union tgsi_exec_channel *g,
1918 union tgsi_exec_channel *b,
1919 union tgsi_exec_channel *a )
1920 {
1921 uint j;
1922 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1923
1924 /* FIXME: handle explicit derivs, offsets */
1925 sampler->get_samples(sampler, sview_idx, sampler_idx,
1926 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1927
1928 for (j = 0; j < 4; j++) {
1929 r->f[j] = rgba[0][j];
1930 g->f[j] = rgba[1][j];
1931 b->f[j] = rgba[2][j];
1932 a->f[j] = rgba[3][j];
1933 }
1934 }
1935
1936
1937 #define TEX_MODIFIER_NONE 0
1938 #define TEX_MODIFIER_PROJECTED 1
1939 #define TEX_MODIFIER_LOD_BIAS 2
1940 #define TEX_MODIFIER_EXPLICIT_LOD 3
1941 #define TEX_MODIFIER_LEVEL_ZERO 4
1942 #define TEX_MODIFIER_GATHER 5
1943
1944 /*
1945 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1946 */
1947 static void
1948 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1949 const struct tgsi_full_instruction *inst,
1950 int8_t offsets[3])
1951 {
1952 if (inst->Texture.NumOffsets == 1) {
1953 union tgsi_exec_channel index;
1954 union tgsi_exec_channel offset[3];
1955 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1956 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1957 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1958 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1959 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1960 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1961 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1962 offsets[0] = offset[0].i[0];
1963 offsets[1] = offset[1].i[0];
1964 offsets[2] = offset[2].i[0];
1965 } else {
1966 assert(inst->Texture.NumOffsets == 0);
1967 offsets[0] = offsets[1] = offsets[2] = 0;
1968 }
1969 }
1970
1971
1972 /*
1973 * Fetch dx and dy values for one channel (s, t or r).
1974 * Put dx values into one float array, dy values into another.
1975 */
1976 static void
1977 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1978 const struct tgsi_full_instruction *inst,
1979 unsigned regdsrcx,
1980 unsigned chan,
1981 float derivs[2][TGSI_QUAD_SIZE])
1982 {
1983 union tgsi_exec_channel d;
1984 FETCH(&d, regdsrcx, chan);
1985 derivs[0][0] = d.f[0];
1986 derivs[0][1] = d.f[1];
1987 derivs[0][2] = d.f[2];
1988 derivs[0][3] = d.f[3];
1989 FETCH(&d, regdsrcx + 1, chan);
1990 derivs[1][0] = d.f[0];
1991 derivs[1][1] = d.f[1];
1992 derivs[1][2] = d.f[2];
1993 derivs[1][3] = d.f[3];
1994 }
1995
1996 static uint
1997 fetch_sampler_unit(struct tgsi_exec_machine *mach,
1998 const struct tgsi_full_instruction *inst,
1999 uint sampler)
2000 {
2001 uint unit = 0;
2002 int i;
2003 if (inst->Src[sampler].Register.Indirect) {
2004 const struct tgsi_full_src_register *reg = &inst->Src[sampler];
2005 union tgsi_exec_channel indir_index, index2;
2006 const uint execmask = mach->ExecMask;
2007 index2.i[0] =
2008 index2.i[1] =
2009 index2.i[2] =
2010 index2.i[3] = reg->Indirect.Index;
2011
2012 fetch_src_file_channel(mach,
2013 0,
2014 reg->Indirect.File,
2015 reg->Indirect.Swizzle,
2016 &index2,
2017 &ZeroVec,
2018 &indir_index);
2019 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2020 if (execmask & (1 << i)) {
2021 unit = inst->Src[sampler].Register.Index + indir_index.i[i];
2022 break;
2023 }
2024 }
2025
2026 } else {
2027 unit = inst->Src[sampler].Register.Index;
2028 }
2029 return unit;
2030 }
2031
2032 /*
2033 * execute a texture instruction.
2034 *
2035 * modifier is used to control the channel routing for the
2036 * instruction variants like proj, lod, and texture with lod bias.
2037 * sampler indicates which src register the sampler is contained in.
2038 */
2039 static void
2040 exec_tex(struct tgsi_exec_machine *mach,
2041 const struct tgsi_full_instruction *inst,
2042 uint modifier, uint sampler)
2043 {
2044 const union tgsi_exec_channel *args[5], *proj = NULL;
2045 union tgsi_exec_channel r[5];
2046 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2047 uint chan;
2048 uint unit;
2049 int8_t offsets[3];
2050 int dim, shadow_ref, i;
2051
2052 unit = fetch_sampler_unit(mach, inst, sampler);
2053 /* always fetch all 3 offsets, overkill but keeps code simple */
2054 fetch_texel_offsets(mach, inst, offsets);
2055
2056 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
2057 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
2058
2059 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2060 shadow_ref = tgsi_util_get_shadow_ref_src_index(inst->Texture.Texture);
2061
2062 assert(dim <= 4);
2063 if (shadow_ref >= 0)
2064 assert(shadow_ref >= dim && shadow_ref < Elements(args));
2065
2066 /* fetch modifier to the last argument */
2067 if (modifier != TEX_MODIFIER_NONE) {
2068 const int last = Elements(args) - 1;
2069
2070 /* fetch modifier from src0.w or src1.x */
2071 if (sampler == 1) {
2072 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
2073 FETCH(&r[last], 0, TGSI_CHAN_W);
2074 }
2075 else {
2076 assert(shadow_ref != 4);
2077 FETCH(&r[last], 1, TGSI_CHAN_X);
2078 }
2079
2080 if (modifier != TEX_MODIFIER_PROJECTED) {
2081 args[last] = &r[last];
2082 }
2083 else {
2084 proj = &r[last];
2085 args[last] = &ZeroVec;
2086 }
2087
2088 /* point unused arguments to zero vector */
2089 for (i = dim; i < last; i++)
2090 args[i] = &ZeroVec;
2091
2092 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
2093 control = TGSI_SAMPLER_LOD_EXPLICIT;
2094 else if (modifier == TEX_MODIFIER_LOD_BIAS)
2095 control = TGSI_SAMPLER_LOD_BIAS;
2096 else if (modifier == TEX_MODIFIER_GATHER)
2097 control = TGSI_SAMPLER_GATHER;
2098 }
2099 else {
2100 for (i = dim; i < Elements(args); i++)
2101 args[i] = &ZeroVec;
2102 }
2103
2104 /* fetch coordinates */
2105 for (i = 0; i < dim; i++) {
2106 FETCH(&r[i], 0, TGSI_CHAN_X + i);
2107
2108 if (proj)
2109 micro_div(&r[i], &r[i], proj);
2110
2111 args[i] = &r[i];
2112 }
2113
2114 /* fetch reference value */
2115 if (shadow_ref >= 0) {
2116 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
2117
2118 if (proj)
2119 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
2120
2121 args[shadow_ref] = &r[shadow_ref];
2122 }
2123
2124 fetch_texel(mach->Sampler, unit, unit,
2125 args[0], args[1], args[2], args[3], args[4],
2126 NULL, offsets, control,
2127 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2128
2129 #if 0
2130 debug_printf("fetch r: %g %g %g %g\n",
2131 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
2132 debug_printf("fetch g: %g %g %g %g\n",
2133 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
2134 debug_printf("fetch b: %g %g %g %g\n",
2135 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
2136 debug_printf("fetch a: %g %g %g %g\n",
2137 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
2138 #endif
2139
2140 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2141 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2142 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2143 }
2144 }
2145 }
2146
2147 static void
2148 exec_lodq(struct tgsi_exec_machine *mach,
2149 const struct tgsi_full_instruction *inst)
2150 {
2151 uint unit;
2152 int dim;
2153 int i;
2154 union tgsi_exec_channel coords[4];
2155 const union tgsi_exec_channel *args[Elements(coords)];
2156 union tgsi_exec_channel r[2];
2157
2158 unit = fetch_sampler_unit(mach, inst, 1);
2159 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture);
2160 assert(dim <= Elements(coords));
2161 /* fetch coordinates */
2162 for (i = 0; i < dim; i++) {
2163 FETCH(&coords[i], 0, TGSI_CHAN_X + i);
2164 args[i] = &coords[i];
2165 }
2166 for (i = dim; i < Elements(coords); i++) {
2167 args[i] = &ZeroVec;
2168 }
2169 mach->Sampler->query_lod(mach->Sampler, unit, unit,
2170 args[0]->f,
2171 args[1]->f,
2172 args[2]->f,
2173 args[3]->f,
2174 TGSI_SAMPLER_LOD_NONE,
2175 r[0].f,
2176 r[1].f);
2177
2178 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2179 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X,
2180 TGSI_EXEC_DATA_FLOAT);
2181 }
2182 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2183 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Y,
2184 TGSI_EXEC_DATA_FLOAT);
2185 }
2186 }
2187
2188 static void
2189 exec_txd(struct tgsi_exec_machine *mach,
2190 const struct tgsi_full_instruction *inst)
2191 {
2192 union tgsi_exec_channel r[4];
2193 float derivs[3][2][TGSI_QUAD_SIZE];
2194 uint chan;
2195 uint unit;
2196 int8_t offsets[3];
2197
2198 unit = fetch_sampler_unit(mach, inst, 3);
2199 /* always fetch all 3 offsets, overkill but keeps code simple */
2200 fetch_texel_offsets(mach, inst, offsets);
2201
2202 switch (inst->Texture.Texture) {
2203 case TGSI_TEXTURE_1D:
2204 FETCH(&r[0], 0, TGSI_CHAN_X);
2205
2206 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2207
2208 fetch_texel(mach->Sampler, unit, unit,
2209 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2210 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2211 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2212 break;
2213
2214 case TGSI_TEXTURE_SHADOW1D:
2215 case TGSI_TEXTURE_1D_ARRAY:
2216 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2217 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2218 FETCH(&r[0], 0, TGSI_CHAN_X);
2219 FETCH(&r[1], 0, TGSI_CHAN_Y);
2220 FETCH(&r[2], 0, TGSI_CHAN_Z);
2221
2222 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2223
2224 fetch_texel(mach->Sampler, unit, unit,
2225 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2226 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2227 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2228 break;
2229
2230 case TGSI_TEXTURE_2D:
2231 case TGSI_TEXTURE_RECT:
2232 FETCH(&r[0], 0, TGSI_CHAN_X);
2233 FETCH(&r[1], 0, TGSI_CHAN_Y);
2234
2235 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2236 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2237
2238 fetch_texel(mach->Sampler, unit, unit,
2239 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2240 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2241 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2242 break;
2243
2244
2245 case TGSI_TEXTURE_SHADOW2D:
2246 case TGSI_TEXTURE_SHADOWRECT:
2247 case TGSI_TEXTURE_2D_ARRAY:
2248 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2249 /* only SHADOW2D_ARRAY actually needs W */
2250 FETCH(&r[0], 0, TGSI_CHAN_X);
2251 FETCH(&r[1], 0, TGSI_CHAN_Y);
2252 FETCH(&r[2], 0, TGSI_CHAN_Z);
2253 FETCH(&r[3], 0, TGSI_CHAN_W);
2254
2255 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2256 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2257
2258 fetch_texel(mach->Sampler, unit, unit,
2259 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2260 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2261 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2262 break;
2263
2264 case TGSI_TEXTURE_3D:
2265 case TGSI_TEXTURE_CUBE:
2266 case TGSI_TEXTURE_CUBE_ARRAY:
2267 case TGSI_TEXTURE_SHADOWCUBE:
2268 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2269 FETCH(&r[0], 0, TGSI_CHAN_X);
2270 FETCH(&r[1], 0, TGSI_CHAN_Y);
2271 FETCH(&r[2], 0, TGSI_CHAN_Z);
2272 FETCH(&r[3], 0, TGSI_CHAN_W);
2273
2274 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
2275 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
2276 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
2277
2278 fetch_texel(mach->Sampler, unit, unit,
2279 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
2280 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2281 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2282 break;
2283
2284 default:
2285 assert(0);
2286 }
2287
2288 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2289 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2290 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2291 }
2292 }
2293 }
2294
2295
2296 static void
2297 exec_txf(struct tgsi_exec_machine *mach,
2298 const struct tgsi_full_instruction *inst)
2299 {
2300 union tgsi_exec_channel r[4];
2301 uint chan;
2302 uint unit;
2303 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
2304 int j;
2305 int8_t offsets[3];
2306 unsigned target;
2307
2308 unit = fetch_sampler_unit(mach, inst, 1);
2309 /* always fetch all 3 offsets, overkill but keeps code simple */
2310 fetch_texel_offsets(mach, inst, offsets);
2311
2312 IFETCH(&r[3], 0, TGSI_CHAN_W);
2313
2314 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2315 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2316 target = mach->SamplerViews[unit].Resource;
2317 }
2318 else {
2319 target = inst->Texture.Texture;
2320 }
2321 switch(target) {
2322 case TGSI_TEXTURE_3D:
2323 case TGSI_TEXTURE_2D_ARRAY:
2324 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2325 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2326 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2327 /* fallthrough */
2328 case TGSI_TEXTURE_2D:
2329 case TGSI_TEXTURE_RECT:
2330 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2331 case TGSI_TEXTURE_SHADOW2D:
2332 case TGSI_TEXTURE_SHADOWRECT:
2333 case TGSI_TEXTURE_1D_ARRAY:
2334 case TGSI_TEXTURE_2D_MSAA:
2335 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2336 /* fallthrough */
2337 case TGSI_TEXTURE_BUFFER:
2338 case TGSI_TEXTURE_1D:
2339 case TGSI_TEXTURE_SHADOW1D:
2340 IFETCH(&r[0], 0, TGSI_CHAN_X);
2341 break;
2342 default:
2343 assert(0);
2344 break;
2345 }
2346
2347 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2348 offsets, rgba);
2349
2350 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2351 r[0].f[j] = rgba[0][j];
2352 r[1].f[j] = rgba[1][j];
2353 r[2].f[j] = rgba[2][j];
2354 r[3].f[j] = rgba[3][j];
2355 }
2356
2357 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I ||
2358 inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I_MS) {
2359 unsigned char swizzles[4];
2360 swizzles[0] = inst->Src[1].Register.SwizzleX;
2361 swizzles[1] = inst->Src[1].Register.SwizzleY;
2362 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2363 swizzles[3] = inst->Src[1].Register.SwizzleW;
2364
2365 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2366 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2367 store_dest(mach, &r[swizzles[chan]],
2368 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2369 }
2370 }
2371 }
2372 else {
2373 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2374 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2375 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2376 }
2377 }
2378 }
2379 }
2380
2381 static void
2382 exec_txq(struct tgsi_exec_machine *mach,
2383 const struct tgsi_full_instruction *inst)
2384 {
2385 int result[4];
2386 union tgsi_exec_channel r[4], src;
2387 uint chan;
2388 uint unit;
2389 int i,j;
2390
2391 unit = fetch_sampler_unit(mach, inst, 1);
2392
2393 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2394
2395 /* XXX: This interface can't return per-pixel values */
2396 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2397
2398 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2399 for (j = 0; j < 4; j++) {
2400 r[j].i[i] = result[j];
2401 }
2402 }
2403
2404 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2405 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2406 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2407 TGSI_EXEC_DATA_INT);
2408 }
2409 }
2410 }
2411
2412 static void
2413 exec_sample(struct tgsi_exec_machine *mach,
2414 const struct tgsi_full_instruction *inst,
2415 uint modifier, boolean compare)
2416 {
2417 const uint resource_unit = inst->Src[1].Register.Index;
2418 const uint sampler_unit = inst->Src[2].Register.Index;
2419 union tgsi_exec_channel r[5], c1;
2420 const union tgsi_exec_channel *lod = &ZeroVec;
2421 enum tgsi_sampler_control control = TGSI_SAMPLER_LOD_NONE;
2422 uint chan;
2423 unsigned char swizzles[4];
2424 int8_t offsets[3];
2425
2426 /* always fetch all 3 offsets, overkill but keeps code simple */
2427 fetch_texel_offsets(mach, inst, offsets);
2428
2429 assert(modifier != TEX_MODIFIER_PROJECTED);
2430
2431 if (modifier != TEX_MODIFIER_NONE) {
2432 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2433 FETCH(&c1, 3, TGSI_CHAN_X);
2434 lod = &c1;
2435 control = TGSI_SAMPLER_LOD_BIAS;
2436 }
2437 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2438 FETCH(&c1, 3, TGSI_CHAN_X);
2439 lod = &c1;
2440 control = TGSI_SAMPLER_LOD_EXPLICIT;
2441 }
2442 else {
2443 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2444 control = TGSI_SAMPLER_LOD_ZERO;
2445 }
2446 }
2447
2448 FETCH(&r[0], 0, TGSI_CHAN_X);
2449
2450 switch (mach->SamplerViews[resource_unit].Resource) {
2451 case TGSI_TEXTURE_1D:
2452 if (compare) {
2453 FETCH(&r[2], 3, TGSI_CHAN_X);
2454 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2455 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2456 NULL, offsets, control,
2457 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2458 }
2459 else {
2460 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2461 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2462 NULL, offsets, control,
2463 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2464 }
2465 break;
2466
2467 case TGSI_TEXTURE_1D_ARRAY:
2468 case TGSI_TEXTURE_2D:
2469 case TGSI_TEXTURE_RECT:
2470 FETCH(&r[1], 0, TGSI_CHAN_Y);
2471 if (compare) {
2472 FETCH(&r[2], 3, TGSI_CHAN_X);
2473 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2474 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2475 NULL, offsets, control,
2476 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2477 }
2478 else {
2479 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2480 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2481 NULL, offsets, control,
2482 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2483 }
2484 break;
2485
2486 case TGSI_TEXTURE_2D_ARRAY:
2487 case TGSI_TEXTURE_3D:
2488 case TGSI_TEXTURE_CUBE:
2489 FETCH(&r[1], 0, TGSI_CHAN_Y);
2490 FETCH(&r[2], 0, TGSI_CHAN_Z);
2491 if(compare) {
2492 FETCH(&r[3], 3, TGSI_CHAN_X);
2493 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2494 &r[0], &r[1], &r[2], &r[3], lod,
2495 NULL, offsets, control,
2496 &r[0], &r[1], &r[2], &r[3]);
2497 }
2498 else {
2499 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2500 &r[0], &r[1], &r[2], &ZeroVec, lod,
2501 NULL, offsets, control,
2502 &r[0], &r[1], &r[2], &r[3]);
2503 }
2504 break;
2505
2506 case TGSI_TEXTURE_CUBE_ARRAY:
2507 FETCH(&r[1], 0, TGSI_CHAN_Y);
2508 FETCH(&r[2], 0, TGSI_CHAN_Z);
2509 FETCH(&r[3], 0, TGSI_CHAN_W);
2510 if(compare) {
2511 FETCH(&r[4], 3, TGSI_CHAN_X);
2512 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2513 &r[0], &r[1], &r[2], &r[3], &r[4],
2514 NULL, offsets, control,
2515 &r[0], &r[1], &r[2], &r[3]);
2516 }
2517 else {
2518 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2519 &r[0], &r[1], &r[2], &r[3], lod,
2520 NULL, offsets, control,
2521 &r[0], &r[1], &r[2], &r[3]);
2522 }
2523 break;
2524
2525
2526 default:
2527 assert(0);
2528 }
2529
2530 swizzles[0] = inst->Src[1].Register.SwizzleX;
2531 swizzles[1] = inst->Src[1].Register.SwizzleY;
2532 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2533 swizzles[3] = inst->Src[1].Register.SwizzleW;
2534
2535 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2536 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2537 store_dest(mach, &r[swizzles[chan]],
2538 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2539 }
2540 }
2541 }
2542
2543 static void
2544 exec_sample_d(struct tgsi_exec_machine *mach,
2545 const struct tgsi_full_instruction *inst)
2546 {
2547 const uint resource_unit = inst->Src[1].Register.Index;
2548 const uint sampler_unit = inst->Src[2].Register.Index;
2549 union tgsi_exec_channel r[4];
2550 float derivs[3][2][TGSI_QUAD_SIZE];
2551 uint chan;
2552 unsigned char swizzles[4];
2553 int8_t offsets[3];
2554
2555 /* always fetch all 3 offsets, overkill but keeps code simple */
2556 fetch_texel_offsets(mach, inst, offsets);
2557
2558 FETCH(&r[0], 0, TGSI_CHAN_X);
2559
2560 switch (mach->SamplerViews[resource_unit].Resource) {
2561 case TGSI_TEXTURE_1D:
2562 case TGSI_TEXTURE_1D_ARRAY:
2563 /* only 1D array actually needs Y */
2564 FETCH(&r[1], 0, TGSI_CHAN_Y);
2565
2566 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2567
2568 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2569 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2570 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2571 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2572 break;
2573
2574 case TGSI_TEXTURE_2D:
2575 case TGSI_TEXTURE_RECT:
2576 case TGSI_TEXTURE_2D_ARRAY:
2577 /* only 2D array actually needs Z */
2578 FETCH(&r[1], 0, TGSI_CHAN_Y);
2579 FETCH(&r[2], 0, TGSI_CHAN_Z);
2580
2581 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2582 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2583
2584 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2585 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2586 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2587 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2588 break;
2589
2590 case TGSI_TEXTURE_3D:
2591 case TGSI_TEXTURE_CUBE:
2592 case TGSI_TEXTURE_CUBE_ARRAY:
2593 /* only cube array actually needs W */
2594 FETCH(&r[1], 0, TGSI_CHAN_Y);
2595 FETCH(&r[2], 0, TGSI_CHAN_Z);
2596 FETCH(&r[3], 0, TGSI_CHAN_W);
2597
2598 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2599 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2600 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2601
2602 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2603 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2604 derivs, offsets, TGSI_SAMPLER_DERIVS_EXPLICIT,
2605 &r[0], &r[1], &r[2], &r[3]);
2606 break;
2607
2608 default:
2609 assert(0);
2610 }
2611
2612 swizzles[0] = inst->Src[1].Register.SwizzleX;
2613 swizzles[1] = inst->Src[1].Register.SwizzleY;
2614 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2615 swizzles[3] = inst->Src[1].Register.SwizzleW;
2616
2617 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2618 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2619 store_dest(mach, &r[swizzles[chan]],
2620 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2621 }
2622 }
2623 }
2624
2625
2626 /**
2627 * Evaluate a constant-valued coefficient at the position of the
2628 * current quad.
2629 */
2630 static void
2631 eval_constant_coef(
2632 struct tgsi_exec_machine *mach,
2633 unsigned attrib,
2634 unsigned chan )
2635 {
2636 unsigned i;
2637
2638 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2639 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2640 }
2641 }
2642
2643 /**
2644 * Evaluate a linear-valued coefficient at the position of the
2645 * current quad.
2646 */
2647 static void
2648 eval_linear_coef(
2649 struct tgsi_exec_machine *mach,
2650 unsigned attrib,
2651 unsigned chan )
2652 {
2653 const float x = mach->QuadPos.xyzw[0].f[0];
2654 const float y = mach->QuadPos.xyzw[1].f[0];
2655 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2656 const float dady = mach->InterpCoefs[attrib].dady[chan];
2657 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2658 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2659 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2660 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2661 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2662 }
2663
2664 /**
2665 * Evaluate a perspective-valued coefficient at the position of the
2666 * current quad.
2667 */
2668 static void
2669 eval_perspective_coef(
2670 struct tgsi_exec_machine *mach,
2671 unsigned attrib,
2672 unsigned chan )
2673 {
2674 const float x = mach->QuadPos.xyzw[0].f[0];
2675 const float y = mach->QuadPos.xyzw[1].f[0];
2676 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2677 const float dady = mach->InterpCoefs[attrib].dady[chan];
2678 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2679 const float *w = mach->QuadPos.xyzw[3].f;
2680 /* divide by W here */
2681 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2682 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2683 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2684 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2685 }
2686
2687
2688 typedef void (* eval_coef_func)(
2689 struct tgsi_exec_machine *mach,
2690 unsigned attrib,
2691 unsigned chan );
2692
2693 static void
2694 exec_declaration(struct tgsi_exec_machine *mach,
2695 const struct tgsi_full_declaration *decl)
2696 {
2697 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2698 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2699 return;
2700 }
2701
2702 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
2703 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2704 uint first, last, mask;
2705
2706 first = decl->Range.First;
2707 last = decl->Range.Last;
2708 mask = decl->Declaration.UsageMask;
2709
2710 /* XXX we could remove this special-case code since
2711 * mach->InterpCoefs[first].a0 should already have the
2712 * front/back-face value. But we should first update the
2713 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2714 * Then, we could remove the tgsi_exec_machine::Face field.
2715 */
2716 /* XXX make FACE a system value */
2717 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2718 uint i;
2719
2720 assert(decl->Semantic.Index == 0);
2721 assert(first == last);
2722
2723 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2724 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2725 }
2726 } else {
2727 eval_coef_func eval;
2728 uint i, j;
2729
2730 switch (decl->Interp.Interpolate) {
2731 case TGSI_INTERPOLATE_CONSTANT:
2732 eval = eval_constant_coef;
2733 break;
2734
2735 case TGSI_INTERPOLATE_LINEAR:
2736 eval = eval_linear_coef;
2737 break;
2738
2739 case TGSI_INTERPOLATE_PERSPECTIVE:
2740 eval = eval_perspective_coef;
2741 break;
2742
2743 case TGSI_INTERPOLATE_COLOR:
2744 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2745 break;
2746
2747 default:
2748 assert(0);
2749 return;
2750 }
2751
2752 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2753 if (mask & (1 << j)) {
2754 for (i = first; i <= last; i++) {
2755 eval(mach, i, j);
2756 }
2757 }
2758 }
2759 }
2760
2761 if (DEBUG_EXECUTION) {
2762 uint i, j;
2763 for (i = first; i <= last; ++i) {
2764 debug_printf("IN[%2u] = ", i);
2765 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2766 if (j > 0) {
2767 debug_printf(" ");
2768 }
2769 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2770 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2771 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2772 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2773 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2774 }
2775 }
2776 }
2777 }
2778 }
2779
2780 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2781 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2782 }
2783 }
2784
2785 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2786 const union tgsi_exec_channel *src);
2787
2788 static void
2789 exec_scalar_unary(struct tgsi_exec_machine *mach,
2790 const struct tgsi_full_instruction *inst,
2791 micro_unary_op op,
2792 enum tgsi_exec_datatype dst_datatype,
2793 enum tgsi_exec_datatype src_datatype)
2794 {
2795 unsigned int chan;
2796 union tgsi_exec_channel src;
2797 union tgsi_exec_channel dst;
2798
2799 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2800 op(&dst, &src);
2801 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2802 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2803 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2804 }
2805 }
2806 }
2807
2808 static void
2809 exec_vector_unary(struct tgsi_exec_machine *mach,
2810 const struct tgsi_full_instruction *inst,
2811 micro_unary_op op,
2812 enum tgsi_exec_datatype dst_datatype,
2813 enum tgsi_exec_datatype src_datatype)
2814 {
2815 unsigned int chan;
2816 struct tgsi_exec_vector dst;
2817
2818 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2819 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2820 union tgsi_exec_channel src;
2821
2822 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2823 op(&dst.xyzw[chan], &src);
2824 }
2825 }
2826 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2827 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2828 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2829 }
2830 }
2831 }
2832
2833 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2834 const union tgsi_exec_channel *src0,
2835 const union tgsi_exec_channel *src1);
2836
2837 static void
2838 exec_scalar_binary(struct tgsi_exec_machine *mach,
2839 const struct tgsi_full_instruction *inst,
2840 micro_binary_op op,
2841 enum tgsi_exec_datatype dst_datatype,
2842 enum tgsi_exec_datatype src_datatype)
2843 {
2844 unsigned int chan;
2845 union tgsi_exec_channel src[2];
2846 union tgsi_exec_channel dst;
2847
2848 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2849 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2850 op(&dst, &src[0], &src[1]);
2851 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2852 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2853 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2854 }
2855 }
2856 }
2857
2858 static void
2859 exec_vector_binary(struct tgsi_exec_machine *mach,
2860 const struct tgsi_full_instruction *inst,
2861 micro_binary_op op,
2862 enum tgsi_exec_datatype dst_datatype,
2863 enum tgsi_exec_datatype src_datatype)
2864 {
2865 unsigned int chan;
2866 struct tgsi_exec_vector dst;
2867
2868 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2869 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2870 union tgsi_exec_channel src[2];
2871
2872 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2873 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2874 op(&dst.xyzw[chan], &src[0], &src[1]);
2875 }
2876 }
2877 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2878 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2879 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2880 }
2881 }
2882 }
2883
2884 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2885 const union tgsi_exec_channel *src0,
2886 const union tgsi_exec_channel *src1,
2887 const union tgsi_exec_channel *src2);
2888
2889 static void
2890 exec_vector_trinary(struct tgsi_exec_machine *mach,
2891 const struct tgsi_full_instruction *inst,
2892 micro_trinary_op op,
2893 enum tgsi_exec_datatype dst_datatype,
2894 enum tgsi_exec_datatype src_datatype)
2895 {
2896 unsigned int chan;
2897 struct tgsi_exec_vector dst;
2898
2899 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2900 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2901 union tgsi_exec_channel src[3];
2902
2903 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2904 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2905 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2906 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2907 }
2908 }
2909 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2910 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2911 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2912 }
2913 }
2914 }
2915
2916 typedef void (* micro_quaternary_op)(union tgsi_exec_channel *dst,
2917 const union tgsi_exec_channel *src0,
2918 const union tgsi_exec_channel *src1,
2919 const union tgsi_exec_channel *src2,
2920 const union tgsi_exec_channel *src3);
2921
2922 static void
2923 exec_vector_quaternary(struct tgsi_exec_machine *mach,
2924 const struct tgsi_full_instruction *inst,
2925 micro_quaternary_op op,
2926 enum tgsi_exec_datatype dst_datatype,
2927 enum tgsi_exec_datatype src_datatype)
2928 {
2929 unsigned int chan;
2930 struct tgsi_exec_vector dst;
2931
2932 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2933 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2934 union tgsi_exec_channel src[4];
2935
2936 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2937 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2938 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2939 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
2940 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
2941 }
2942 }
2943 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2944 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2945 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2946 }
2947 }
2948 }
2949
2950 static void
2951 exec_dp3(struct tgsi_exec_machine *mach,
2952 const struct tgsi_full_instruction *inst)
2953 {
2954 unsigned int chan;
2955 union tgsi_exec_channel arg[3];
2956
2957 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2958 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2959 micro_mul(&arg[2], &arg[0], &arg[1]);
2960
2961 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2962 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2963 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2964 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2965 }
2966
2967 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2968 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2969 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2970 }
2971 }
2972 }
2973
2974 static void
2975 exec_dp4(struct tgsi_exec_machine *mach,
2976 const struct tgsi_full_instruction *inst)
2977 {
2978 unsigned int chan;
2979 union tgsi_exec_channel arg[3];
2980
2981 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2982 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2983 micro_mul(&arg[2], &arg[0], &arg[1]);
2984
2985 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2986 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2987 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2988 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2989 }
2990
2991 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2992 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2993 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2994 }
2995 }
2996 }
2997
2998 static void
2999 exec_dp2a(struct tgsi_exec_machine *mach,
3000 const struct tgsi_full_instruction *inst)
3001 {
3002 unsigned int chan;
3003 union tgsi_exec_channel arg[3];
3004
3005 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3006 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3007 micro_mul(&arg[2], &arg[0], &arg[1]);
3008
3009 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3010 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3011 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3012
3013 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3014 micro_add(&arg[0], &arg[0], &arg[1]);
3015
3016 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3017 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3018 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3019 }
3020 }
3021 }
3022
3023 static void
3024 exec_dph(struct tgsi_exec_machine *mach,
3025 const struct tgsi_full_instruction *inst)
3026 {
3027 unsigned int chan;
3028 union tgsi_exec_channel arg[3];
3029
3030 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3031 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3032 micro_mul(&arg[2], &arg[0], &arg[1]);
3033
3034 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3035 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3036 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3037
3038 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3039 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3040 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
3041
3042 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3043 micro_add(&arg[0], &arg[0], &arg[1]);
3044
3045 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3046 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3047 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3048 }
3049 }
3050 }
3051
3052 static void
3053 exec_dp2(struct tgsi_exec_machine *mach,
3054 const struct tgsi_full_instruction *inst)
3055 {
3056 unsigned int chan;
3057 union tgsi_exec_channel arg[3];
3058
3059 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3060 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3061 micro_mul(&arg[2], &arg[0], &arg[1]);
3062
3063 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3064 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3065 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
3066
3067 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3068 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3069 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3070 }
3071 }
3072 }
3073
3074 static void
3075 exec_pk2h(struct tgsi_exec_machine *mach,
3076 const struct tgsi_full_instruction *inst)
3077 {
3078 unsigned chan;
3079 union tgsi_exec_channel arg[2], dst;
3080
3081 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3082 fetch_source(mach, &arg[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3083 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3084 dst.u[chan] = util_float_to_half(arg[0].f[chan]) |
3085 (util_float_to_half(arg[1].f[chan]) << 16);
3086 }
3087 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3088 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3089 store_dest(mach, &dst, &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_UINT);
3090 }
3091 }
3092 }
3093
3094 static void
3095 exec_up2h(struct tgsi_exec_machine *mach,
3096 const struct tgsi_full_instruction *inst)
3097 {
3098 unsigned chan;
3099 union tgsi_exec_channel arg, dst[2];
3100
3101 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3102 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3103 dst[0].f[chan] = util_half_to_float(arg.u[chan] & 0xffff);
3104 dst[1].f[chan] = util_half_to_float(arg.u[chan] >> 16);
3105 }
3106 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3107 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3108 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3109 }
3110 }
3111 }
3112
3113 static void
3114 exec_scs(struct tgsi_exec_machine *mach,
3115 const struct tgsi_full_instruction *inst)
3116 {
3117 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
3118 union tgsi_exec_channel arg;
3119 union tgsi_exec_channel result;
3120
3121 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3122
3123 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3124 micro_cos(&result, &arg);
3125 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3126 }
3127 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3128 micro_sin(&result, &arg);
3129 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3130 }
3131 }
3132 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3133 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3134 }
3135 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3136 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3137 }
3138 }
3139
3140 static void
3141 exec_xpd(struct tgsi_exec_machine *mach,
3142 const struct tgsi_full_instruction *inst)
3143 {
3144 union tgsi_exec_channel r[6];
3145 union tgsi_exec_channel d[3];
3146
3147 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3148 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3149
3150 micro_mul(&r[2], &r[0], &r[1]);
3151
3152 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3153 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3154
3155 micro_mul(&r[5], &r[3], &r[4] );
3156 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
3157
3158 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3159
3160 micro_mul(&r[3], &r[3], &r[2]);
3161
3162 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3163
3164 micro_mul(&r[1], &r[1], &r[5]);
3165 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
3166
3167 micro_mul(&r[5], &r[5], &r[4]);
3168 micro_mul(&r[0], &r[0], &r[2]);
3169 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
3170
3171 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3172 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3173 }
3174 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3175 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3176 }
3177 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3178 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3179 }
3180 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3181 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3182 }
3183 }
3184
3185 static void
3186 exec_dst(struct tgsi_exec_machine *mach,
3187 const struct tgsi_full_instruction *inst)
3188 {
3189 union tgsi_exec_channel r[2];
3190 union tgsi_exec_channel d[4];
3191
3192 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3193 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3194 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3195 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
3196 }
3197 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3198 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3199 }
3200 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3201 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3202 }
3203
3204 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3205 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3206 }
3207 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3208 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3209 }
3210 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3211 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3212 }
3213 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3214 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3215 }
3216 }
3217
3218 static void
3219 exec_log(struct tgsi_exec_machine *mach,
3220 const struct tgsi_full_instruction *inst)
3221 {
3222 union tgsi_exec_channel r[3];
3223
3224 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3225 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3226 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3227 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3228 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3229 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3230 }
3231 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3232 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3233 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3234 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3235 }
3236 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3237 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3238 }
3239 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3240 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3241 }
3242 }
3243
3244 static void
3245 exec_exp(struct tgsi_exec_machine *mach,
3246 const struct tgsi_full_instruction *inst)
3247 {
3248 union tgsi_exec_channel r[3];
3249
3250 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3251 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3252 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3253 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3254 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3255 }
3256 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3257 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3258 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3259 }
3260 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3261 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3262 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3263 }
3264 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3265 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3266 }
3267 }
3268
3269 static void
3270 exec_lit(struct tgsi_exec_machine *mach,
3271 const struct tgsi_full_instruction *inst)
3272 {
3273 union tgsi_exec_channel r[3];
3274 union tgsi_exec_channel d[3];
3275
3276 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3277 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3278 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3279 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3280 micro_max(&r[1], &r[1], &ZeroVec);
3281
3282 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3283 micro_min(&r[2], &r[2], &P128Vec);
3284 micro_max(&r[2], &r[2], &M128Vec);
3285 micro_pow(&r[1], &r[1], &r[2]);
3286 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3287 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3288 }
3289 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3290 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3291 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3292 }
3293 }
3294 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3295 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3296 }
3297
3298 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3299 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3300 }
3301 }
3302
3303 static void
3304 exec_break(struct tgsi_exec_machine *mach)
3305 {
3306 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3307 /* turn off loop channels for each enabled exec channel */
3308 mach->LoopMask &= ~mach->ExecMask;
3309 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3310 UPDATE_EXEC_MASK(mach);
3311 } else {
3312 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3313
3314 mach->Switch.mask = 0x0;
3315
3316 UPDATE_EXEC_MASK(mach);
3317 }
3318 }
3319
3320 static void
3321 exec_switch(struct tgsi_exec_machine *mach,
3322 const struct tgsi_full_instruction *inst)
3323 {
3324 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3325 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3326
3327 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3328 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3329 mach->Switch.mask = 0x0;
3330 mach->Switch.defaultMask = 0x0;
3331
3332 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3333 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3334
3335 UPDATE_EXEC_MASK(mach);
3336 }
3337
3338 static void
3339 exec_case(struct tgsi_exec_machine *mach,
3340 const struct tgsi_full_instruction *inst)
3341 {
3342 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3343 union tgsi_exec_channel src;
3344 uint mask = 0;
3345
3346 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3347
3348 if (mach->Switch.selector.u[0] == src.u[0]) {
3349 mask |= 0x1;
3350 }
3351 if (mach->Switch.selector.u[1] == src.u[1]) {
3352 mask |= 0x2;
3353 }
3354 if (mach->Switch.selector.u[2] == src.u[2]) {
3355 mask |= 0x4;
3356 }
3357 if (mach->Switch.selector.u[3] == src.u[3]) {
3358 mask |= 0x8;
3359 }
3360
3361 mach->Switch.defaultMask |= mask;
3362
3363 mach->Switch.mask |= mask & prevMask;
3364
3365 UPDATE_EXEC_MASK(mach);
3366 }
3367
3368 /* FIXME: this will only work if default is last */
3369 static void
3370 exec_default(struct tgsi_exec_machine *mach)
3371 {
3372 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3373
3374 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3375
3376 UPDATE_EXEC_MASK(mach);
3377 }
3378
3379 static void
3380 exec_endswitch(struct tgsi_exec_machine *mach)
3381 {
3382 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3383 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3384
3385 UPDATE_EXEC_MASK(mach);
3386 }
3387
3388 typedef void (* micro_dop)(union tgsi_double_channel *dst,
3389 const union tgsi_double_channel *src);
3390
3391 static void
3392 fetch_double_channel(struct tgsi_exec_machine *mach,
3393 union tgsi_double_channel *chan,
3394 const struct tgsi_full_src_register *reg,
3395 uint chan_0,
3396 uint chan_1)
3397 {
3398 union tgsi_exec_channel src[2];
3399 uint i;
3400
3401 fetch_source_d(mach, &src[0], reg, chan_0, TGSI_EXEC_DATA_UINT);
3402 fetch_source_d(mach, &src[1], reg, chan_1, TGSI_EXEC_DATA_UINT);
3403
3404 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
3405 chan->u[i][0] = src[0].u[i];
3406 chan->u[i][1] = src[1].u[i];
3407 }
3408 if (reg->Register.Absolute) {
3409 micro_dabs(chan, chan);
3410 }
3411 if (reg->Register.Negate) {
3412 micro_dneg(chan, chan);
3413 }
3414 }
3415
3416 static void
3417 store_double_channel(struct tgsi_exec_machine *mach,
3418 const union tgsi_double_channel *chan,
3419 const struct tgsi_full_dst_register *reg,
3420 const struct tgsi_full_instruction *inst,
3421 uint chan_0,
3422 uint chan_1)
3423 {
3424 union tgsi_exec_channel dst[2];
3425 uint i;
3426 union tgsi_double_channel temp;
3427 const uint execmask = mach->ExecMask;
3428
3429 if (!inst->Instruction.Saturate) {
3430 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3431 if (execmask & (1 << i)) {
3432 dst[0].u[i] = chan->u[i][0];
3433 dst[1].u[i] = chan->u[i][1];
3434 }
3435 }
3436 else {
3437 for (i = 0; i < TGSI_QUAD_SIZE; i++)
3438 if (execmask & (1 << i)) {
3439 if (chan->d[i] < 0.0)
3440 temp.d[i] = 0.0;
3441 else if (chan->d[i] > 1.0)
3442 temp.d[i] = 1.0;
3443 else
3444 temp.d[i] = chan->d[i];
3445
3446 dst[0].u[i] = temp.u[i][0];
3447 dst[1].u[i] = temp.u[i][1];
3448 }
3449 }
3450
3451 store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
3452 if (chan_1 != -1)
3453 store_dest_double(mach, &dst[1], reg, inst, chan_1, TGSI_EXEC_DATA_UINT);
3454 }
3455
3456 static void
3457 exec_double_unary(struct tgsi_exec_machine *mach,
3458 const struct tgsi_full_instruction *inst,
3459 micro_dop op)
3460 {
3461 union tgsi_double_channel src;
3462 union tgsi_double_channel dst;
3463
3464 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3465 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3466 op(&dst, &src);
3467 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3468 }
3469 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3470 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3471 op(&dst, &src);
3472 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3473 }
3474 }
3475
3476 static void
3477 exec_double_binary(struct tgsi_exec_machine *mach,
3478 const struct tgsi_full_instruction *inst,
3479 micro_dop op,
3480 enum tgsi_exec_datatype dst_datatype)
3481 {
3482 union tgsi_double_channel src[2];
3483 union tgsi_double_channel dst;
3484 int first_dest_chan, second_dest_chan;
3485 int wmask;
3486
3487 wmask = inst->Dst[0].Register.WriteMask;
3488 /* these are & because of the way DSLT etc store their destinations */
3489 if (wmask & TGSI_WRITEMASK_XY) {
3490 first_dest_chan = TGSI_CHAN_X;
3491 second_dest_chan = TGSI_CHAN_Y;
3492 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3493 first_dest_chan = (wmask & TGSI_WRITEMASK_X) ? TGSI_CHAN_X : TGSI_CHAN_Y;
3494 second_dest_chan = -1;
3495 }
3496
3497 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3498 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3499 op(&dst, src);
3500 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3501 }
3502
3503 if (wmask & TGSI_WRITEMASK_ZW) {
3504 first_dest_chan = TGSI_CHAN_Z;
3505 second_dest_chan = TGSI_CHAN_W;
3506 if (dst_datatype == TGSI_EXEC_DATA_UINT) {
3507 first_dest_chan = (wmask & TGSI_WRITEMASK_Z) ? TGSI_CHAN_Z : TGSI_CHAN_W;
3508 second_dest_chan = -1;
3509 }
3510
3511 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3512 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3513 op(&dst, src);
3514 store_double_channel(mach, &dst, &inst->Dst[0], inst, first_dest_chan, second_dest_chan);
3515 }
3516 }
3517
3518 static void
3519 exec_double_trinary(struct tgsi_exec_machine *mach,
3520 const struct tgsi_full_instruction *inst,
3521 micro_dop op)
3522 {
3523 union tgsi_double_channel src[3];
3524 union tgsi_double_channel dst;
3525
3526 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3527 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3528 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, TGSI_CHAN_Y);
3529 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_X, TGSI_CHAN_Y);
3530 op(&dst, src);
3531 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3532 }
3533 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3534 fetch_double_channel(mach, &src[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3535 fetch_double_channel(mach, &src[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_CHAN_W);
3536 fetch_double_channel(mach, &src[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_CHAN_W);
3537 op(&dst, src);
3538 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3539 }
3540 }
3541
3542 static void
3543 exec_f2d(struct tgsi_exec_machine *mach,
3544 const struct tgsi_full_instruction *inst)
3545 {
3546 union tgsi_exec_channel src;
3547 union tgsi_double_channel dst;
3548
3549 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3550 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3551 micro_f2d(&dst, &src);
3552 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3553 }
3554 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3555 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3556 micro_f2d(&dst, &src);
3557 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3558 }
3559 }
3560
3561 static void
3562 exec_d2f(struct tgsi_exec_machine *mach,
3563 const struct tgsi_full_instruction *inst)
3564 {
3565 union tgsi_double_channel src;
3566 union tgsi_exec_channel dst;
3567 int wm = inst->Dst[0].Register.WriteMask;
3568 int i;
3569 int bit;
3570 for (i = 0; i < 2; i++) {
3571 bit = ffs(wm);
3572 if (bit) {
3573 wm &= ~(1 << (bit - 1));
3574 if (i == 0)
3575 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3576 else
3577 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3578 micro_d2f(&dst, &src);
3579 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_FLOAT);
3580 }
3581 }
3582 }
3583
3584 static void
3585 exec_i2d(struct tgsi_exec_machine *mach,
3586 const struct tgsi_full_instruction *inst)
3587 {
3588 union tgsi_exec_channel src;
3589 union tgsi_double_channel dst;
3590
3591 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3592 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3593 micro_i2d(&dst, &src);
3594 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3595 }
3596 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3597 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_INT);
3598 micro_i2d(&dst, &src);
3599 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3600 }
3601 }
3602
3603 static void
3604 exec_d2i(struct tgsi_exec_machine *mach,
3605 const struct tgsi_full_instruction *inst)
3606 {
3607 union tgsi_double_channel src;
3608 union tgsi_exec_channel dst;
3609 int wm = inst->Dst[0].Register.WriteMask;
3610 int i;
3611 int bit;
3612 for (i = 0; i < 2; i++) {
3613 bit = ffs(wm);
3614 if (bit) {
3615 wm &= ~(1 << (bit - 1));
3616 if (i == 0)
3617 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3618 else
3619 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3620 micro_d2i(&dst, &src);
3621 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_INT);
3622 }
3623 }
3624 }
3625 static void
3626 exec_u2d(struct tgsi_exec_machine *mach,
3627 const struct tgsi_full_instruction *inst)
3628 {
3629 union tgsi_exec_channel src;
3630 union tgsi_double_channel dst;
3631
3632 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) {
3633 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3634 micro_u2d(&dst, &src);
3635 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3636 }
3637 if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) {
3638 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_UINT);
3639 micro_u2d(&dst, &src);
3640 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3641 }
3642 }
3643
3644 static void
3645 exec_d2u(struct tgsi_exec_machine *mach,
3646 const struct tgsi_full_instruction *inst)
3647 {
3648 union tgsi_double_channel src;
3649 union tgsi_exec_channel dst;
3650 int wm = inst->Dst[0].Register.WriteMask;
3651 int i;
3652 int bit;
3653 for (i = 0; i < 2; i++) {
3654 bit = ffs(wm);
3655 if (bit) {
3656 wm &= ~(1 << (bit - 1));
3657 if (i == 0)
3658 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3659 else
3660 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3661 micro_d2u(&dst, &src);
3662 store_dest(mach, &dst, &inst->Dst[0], inst, bit - 1, TGSI_EXEC_DATA_UINT);
3663 }
3664 }
3665 }
3666
3667 static void
3668 exec_dldexp(struct tgsi_exec_machine *mach,
3669 const struct tgsi_full_instruction *inst)
3670 {
3671 union tgsi_double_channel src0;
3672 union tgsi_exec_channel src1;
3673 union tgsi_double_channel dst;
3674 int wmask;
3675
3676 wmask = inst->Dst[0].Register.WriteMask;
3677 if (wmask & TGSI_WRITEMASK_XY) {
3678 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3679 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
3680 micro_dldexp(&dst, &src0, &src1);
3681 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3682 }
3683
3684 if (wmask & TGSI_WRITEMASK_ZW) {
3685 fetch_double_channel(mach, &src0, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3686 fetch_source(mach, &src1, &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_INT);
3687 micro_dldexp(&dst, &src0, &src1);
3688 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3689 }
3690 }
3691
3692 static void
3693 exec_dfracexp(struct tgsi_exec_machine *mach,
3694 const struct tgsi_full_instruction *inst)
3695 {
3696 union tgsi_double_channel src;
3697 union tgsi_double_channel dst;
3698 union tgsi_exec_channel dst_exp;
3699
3700 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY)) {
3701 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y);
3702 micro_dfracexp(&dst, &dst_exp, &src);
3703 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y);
3704 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3705 }
3706 if (((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW)) {
3707 fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_Z, TGSI_CHAN_W);
3708 micro_dfracexp(&dst, &dst_exp, &src);
3709 store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W);
3710 store_dest(mach, &dst_exp, &inst->Dst[1], inst, ffs(inst->Dst[1].Register.WriteMask) - 1, TGSI_EXEC_DATA_INT);
3711 }
3712 }
3713
3714 static int
3715 get_image_coord_dim(unsigned tgsi_tex)
3716 {
3717 int dim;
3718 switch (tgsi_tex) {
3719 case TGSI_TEXTURE_BUFFER:
3720 case TGSI_TEXTURE_1D:
3721 dim = 1;
3722 break;
3723 case TGSI_TEXTURE_2D:
3724 case TGSI_TEXTURE_RECT:
3725 case TGSI_TEXTURE_1D_ARRAY:
3726 case TGSI_TEXTURE_2D_MSAA:
3727 dim = 2;
3728 break;
3729 case TGSI_TEXTURE_3D:
3730 case TGSI_TEXTURE_CUBE:
3731 case TGSI_TEXTURE_2D_ARRAY:
3732 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3733 case TGSI_TEXTURE_CUBE_ARRAY:
3734 dim = 3;
3735 break;
3736 default:
3737 assert(!"unknown texture target");
3738 dim = 0;
3739 break;
3740 }
3741
3742 return dim;
3743 }
3744
3745 static int
3746 get_image_coord_sample(unsigned tgsi_tex)
3747 {
3748 int sample = 0;
3749 switch (tgsi_tex) {
3750 case TGSI_TEXTURE_2D_MSAA:
3751 sample = 3;
3752 break;
3753 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3754 sample = 4;
3755 break;
3756 default:
3757 break;
3758 }
3759 return sample;
3760 }
3761
3762 static void
3763 exec_load_img(struct tgsi_exec_machine *mach,
3764 const struct tgsi_full_instruction *inst)
3765 {
3766 union tgsi_exec_channel r[4], sample_r;
3767 uint unit;
3768 int sample;
3769 int i, j;
3770 int dim;
3771 uint chan;
3772 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3773 struct tgsi_image_params params;
3774 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3775
3776 unit = fetch_sampler_unit(mach, inst, 0);
3777 dim = get_image_coord_dim(inst->Memory.Texture);
3778 sample = get_image_coord_sample(inst->Memory.Texture);
3779 assert(dim <= 3);
3780
3781 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3782 params.unit = unit;
3783 params.tgsi_tex_instr = inst->Memory.Texture;
3784 params.format = inst->Memory.Format;
3785
3786 for (i = 0; i < dim; i++) {
3787 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3788 }
3789
3790 if (sample)
3791 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3792
3793 mach->Image->load(mach->Image, &params,
3794 r[0].i, r[1].i, r[2].i, sample_r.i,
3795 rgba);
3796 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3797 r[0].f[j] = rgba[0][j];
3798 r[1].f[j] = rgba[1][j];
3799 r[2].f[j] = rgba[2][j];
3800 r[3].f[j] = rgba[3][j];
3801 }
3802 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3803 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3804 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3805 }
3806 }
3807 }
3808
3809 static void
3810 exec_load_buf(struct tgsi_exec_machine *mach,
3811 const struct tgsi_full_instruction *inst)
3812 {
3813 union tgsi_exec_channel r[4];
3814 uint unit;
3815 int j;
3816 uint chan;
3817 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3818 struct tgsi_buffer_params params;
3819 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3820
3821 unit = fetch_sampler_unit(mach, inst, 0);
3822
3823 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3824 params.unit = unit;
3825 IFETCH(&r[0], 1, TGSI_CHAN_X);
3826
3827 mach->Buffer->load(mach->Buffer, &params,
3828 r[0].i, rgba);
3829 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3830 r[0].f[j] = rgba[0][j];
3831 r[1].f[j] = rgba[1][j];
3832 r[2].f[j] = rgba[2][j];
3833 r[3].f[j] = rgba[3][j];
3834 }
3835 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3836 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3837 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
3838 }
3839 }
3840 }
3841
3842 static void
3843 exec_load(struct tgsi_exec_machine *mach,
3844 const struct tgsi_full_instruction *inst)
3845 {
3846 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
3847 exec_load_img(mach, inst);
3848 else
3849 exec_load_buf(mach, inst);
3850 }
3851
3852 static void
3853 exec_store_img(struct tgsi_exec_machine *mach,
3854 const struct tgsi_full_instruction *inst)
3855 {
3856 union tgsi_exec_channel r[3], sample_r;
3857 union tgsi_exec_channel value[4];
3858 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3859 struct tgsi_image_params params;
3860 int dim;
3861 int sample;
3862 int i, j;
3863 uint unit;
3864 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3865 unit = inst->Dst[0].Register.Index;
3866 dim = get_image_coord_dim(inst->Memory.Texture);
3867 sample = get_image_coord_sample(inst->Memory.Texture);
3868 assert(dim <= 3);
3869
3870 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3871 params.unit = unit;
3872 params.tgsi_tex_instr = inst->Memory.Texture;
3873 params.format = inst->Memory.Format;
3874
3875 for (i = 0; i < dim; i++) {
3876 IFETCH(&r[i], 0, TGSI_CHAN_X + i);
3877 }
3878
3879 for (i = 0; i < 4; i++) {
3880 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3881 }
3882 if (sample)
3883 IFETCH(&sample_r, 0, TGSI_CHAN_X + sample);
3884
3885 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3886 rgba[0][j] = value[0].f[j];
3887 rgba[1][j] = value[1].f[j];
3888 rgba[2][j] = value[2].f[j];
3889 rgba[3][j] = value[3].f[j];
3890 }
3891
3892 mach->Image->store(mach->Image, &params,
3893 r[0].i, r[1].i, r[2].i, sample_r.i,
3894 rgba);
3895 }
3896
3897 static void
3898 exec_store_buf(struct tgsi_exec_machine *mach,
3899 const struct tgsi_full_instruction *inst)
3900 {
3901 union tgsi_exec_channel r[3];
3902 union tgsi_exec_channel value[4];
3903 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3904 struct tgsi_buffer_params params;
3905 int i, j;
3906 uint unit;
3907 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3908
3909 unit = inst->Dst[0].Register.Index;
3910
3911 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3912 params.unit = unit;
3913 params.writemask = inst->Dst[0].Register.WriteMask;
3914
3915 IFETCH(&r[0], 0, TGSI_CHAN_X);
3916 for (i = 0; i < 4; i++) {
3917 FETCH(&value[i], 1, TGSI_CHAN_X + i);
3918 }
3919
3920 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3921 rgba[0][j] = value[0].f[j];
3922 rgba[1][j] = value[1].f[j];
3923 rgba[2][j] = value[2].f[j];
3924 rgba[3][j] = value[3].f[j];
3925 }
3926
3927 mach->Buffer->store(mach->Buffer, &params,
3928 r[0].i,
3929 rgba);
3930 }
3931
3932 static void
3933 exec_store(struct tgsi_exec_machine *mach,
3934 const struct tgsi_full_instruction *inst)
3935 {
3936 if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE)
3937 exec_store_img(mach, inst);
3938 else
3939 exec_store_buf(mach, inst);
3940 }
3941
3942 static void
3943 exec_atomop_img(struct tgsi_exec_machine *mach,
3944 const struct tgsi_full_instruction *inst)
3945 {
3946 union tgsi_exec_channel r[4], sample_r;
3947 union tgsi_exec_channel value[4], value2[4];
3948 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3949 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
3950 struct tgsi_image_params params;
3951 int dim;
3952 int sample;
3953 int i, j;
3954 uint unit, chan;
3955 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
3956 unit = fetch_sampler_unit(mach, inst, 0);
3957 dim = get_image_coord_dim(inst->Memory.Texture);
3958 sample = get_image_coord_sample(inst->Memory.Texture);
3959 assert(dim <= 3);
3960
3961 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
3962 params.unit = unit;
3963 params.tgsi_tex_instr = inst->Memory.Texture;
3964 params.format = inst->Memory.Format;
3965
3966 for (i = 0; i < dim; i++) {
3967 IFETCH(&r[i], 1, TGSI_CHAN_X + i);
3968 }
3969
3970 for (i = 0; i < 4; i++) {
3971 FETCH(&value[i], 2, TGSI_CHAN_X + i);
3972 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3973 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
3974 }
3975 if (sample)
3976 IFETCH(&sample_r, 1, TGSI_CHAN_X + sample);
3977
3978 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3979 rgba[0][j] = value[0].f[j];
3980 rgba[1][j] = value[1].f[j];
3981 rgba[2][j] = value[2].f[j];
3982 rgba[3][j] = value[3].f[j];
3983 }
3984 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3985 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3986 rgba2[0][j] = value2[0].f[j];
3987 rgba2[1][j] = value2[1].f[j];
3988 rgba2[2][j] = value2[2].f[j];
3989 rgba2[3][j] = value2[3].f[j];
3990 }
3991 }
3992
3993 mach->Image->op(mach->Image, &params, inst->Instruction.Opcode,
3994 r[0].i, r[1].i, r[2].i, sample_r.i,
3995 rgba, rgba2);
3996
3997 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
3998 r[0].f[j] = rgba[0][j];
3999 r[1].f[j] = rgba[1][j];
4000 r[2].f[j] = rgba[2][j];
4001 r[3].f[j] = rgba[3][j];
4002 }
4003 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4004 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4005 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4006 }
4007 }
4008 }
4009
4010 static void
4011 exec_atomop_buf(struct tgsi_exec_machine *mach,
4012 const struct tgsi_full_instruction *inst)
4013 {
4014 union tgsi_exec_channel r[4];
4015 union tgsi_exec_channel value[4], value2[4];
4016 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4017 float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
4018 struct tgsi_buffer_params params;
4019 int i, j;
4020 uint unit, chan;
4021 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4022
4023 unit = fetch_sampler_unit(mach, inst, 0);
4024
4025 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4026 params.unit = unit;
4027 params.writemask = inst->Dst[0].Register.WriteMask;
4028
4029 IFETCH(&r[0], 1, TGSI_CHAN_X);
4030
4031 for (i = 0; i < 4; i++) {
4032 FETCH(&value[i], 2, TGSI_CHAN_X + i);
4033 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4034 FETCH(&value2[i], 3, TGSI_CHAN_X + i);
4035 }
4036
4037 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4038 rgba[0][j] = value[0].f[j];
4039 rgba[1][j] = value[1].f[j];
4040 rgba[2][j] = value[2].f[j];
4041 rgba[3][j] = value[3].f[j];
4042 }
4043 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4044 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4045 rgba2[0][j] = value2[0].f[j];
4046 rgba2[1][j] = value2[1].f[j];
4047 rgba2[2][j] = value2[2].f[j];
4048 rgba2[3][j] = value2[3].f[j];
4049 }
4050 }
4051
4052 mach->Buffer->op(mach->Buffer, &params, inst->Instruction.Opcode,
4053 r[0].i,
4054 rgba, rgba2);
4055
4056 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
4057 r[0].f[j] = rgba[0][j];
4058 r[1].f[j] = rgba[1][j];
4059 r[2].f[j] = rgba[2][j];
4060 r[3].f[j] = rgba[3][j];
4061 }
4062 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4063 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4064 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
4065 }
4066 }
4067 }
4068
4069 static void
4070 exec_atomop(struct tgsi_exec_machine *mach,
4071 const struct tgsi_full_instruction *inst)
4072 {
4073 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4074 exec_atomop_img(mach, inst);
4075 else
4076 exec_atomop_buf(mach, inst);
4077 }
4078
4079 static void
4080 exec_resq_img(struct tgsi_exec_machine *mach,
4081 const struct tgsi_full_instruction *inst)
4082 {
4083 int result[4];
4084 union tgsi_exec_channel r[4];
4085 uint unit;
4086 int i, chan, j;
4087 struct tgsi_image_params params;
4088 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4089
4090 unit = fetch_sampler_unit(mach, inst, 0);
4091
4092 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4093 params.unit = unit;
4094 params.tgsi_tex_instr = inst->Memory.Texture;
4095 params.format = inst->Memory.Format;
4096
4097 mach->Image->get_dims(mach->Image, &params, result);
4098
4099 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4100 for (j = 0; j < 4; j++) {
4101 r[j].i[i] = result[j];
4102 }
4103 }
4104
4105 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4106 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4107 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4108 TGSI_EXEC_DATA_INT);
4109 }
4110 }
4111 }
4112
4113 static void
4114 exec_resq_buf(struct tgsi_exec_machine *mach,
4115 const struct tgsi_full_instruction *inst)
4116 {
4117 int result;
4118 union tgsi_exec_channel r[4];
4119 uint unit;
4120 int i, chan;
4121 struct tgsi_buffer_params params;
4122 int kilmask = mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
4123
4124 unit = fetch_sampler_unit(mach, inst, 0);
4125
4126 params.execmask = mach->ExecMask & mach->NonHelperMask & ~kilmask;
4127 params.unit = unit;
4128
4129 mach->Buffer->get_dims(mach->Buffer, &params, &result);
4130
4131 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
4132 r[0].i[i] = result;
4133 }
4134
4135 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4136 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4137 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
4138 TGSI_EXEC_DATA_INT);
4139 }
4140 }
4141 }
4142
4143 static void
4144 exec_resq(struct tgsi_exec_machine *mach,
4145 const struct tgsi_full_instruction *inst)
4146 {
4147 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
4148 exec_resq_img(mach, inst);
4149 else
4150 exec_resq_buf(mach, inst);
4151 }
4152
4153 static void
4154 micro_i2f(union tgsi_exec_channel *dst,
4155 const union tgsi_exec_channel *src)
4156 {
4157 dst->f[0] = (float)src->i[0];
4158 dst->f[1] = (float)src->i[1];
4159 dst->f[2] = (float)src->i[2];
4160 dst->f[3] = (float)src->i[3];
4161 }
4162
4163 static void
4164 micro_not(union tgsi_exec_channel *dst,
4165 const union tgsi_exec_channel *src)
4166 {
4167 dst->u[0] = ~src->u[0];
4168 dst->u[1] = ~src->u[1];
4169 dst->u[2] = ~src->u[2];
4170 dst->u[3] = ~src->u[3];
4171 }
4172
4173 static void
4174 micro_shl(union tgsi_exec_channel *dst,
4175 const union tgsi_exec_channel *src0,
4176 const union tgsi_exec_channel *src1)
4177 {
4178 unsigned masked_count;
4179 masked_count = src1->u[0] & 0x1f;
4180 dst->u[0] = src0->u[0] << masked_count;
4181 masked_count = src1->u[1] & 0x1f;
4182 dst->u[1] = src0->u[1] << masked_count;
4183 masked_count = src1->u[2] & 0x1f;
4184 dst->u[2] = src0->u[2] << masked_count;
4185 masked_count = src1->u[3] & 0x1f;
4186 dst->u[3] = src0->u[3] << masked_count;
4187 }
4188
4189 static void
4190 micro_and(union tgsi_exec_channel *dst,
4191 const union tgsi_exec_channel *src0,
4192 const union tgsi_exec_channel *src1)
4193 {
4194 dst->u[0] = src0->u[0] & src1->u[0];
4195 dst->u[1] = src0->u[1] & src1->u[1];
4196 dst->u[2] = src0->u[2] & src1->u[2];
4197 dst->u[3] = src0->u[3] & src1->u[3];
4198 }
4199
4200 static void
4201 micro_or(union tgsi_exec_channel *dst,
4202 const union tgsi_exec_channel *src0,
4203 const union tgsi_exec_channel *src1)
4204 {
4205 dst->u[0] = src0->u[0] | src1->u[0];
4206 dst->u[1] = src0->u[1] | src1->u[1];
4207 dst->u[2] = src0->u[2] | src1->u[2];
4208 dst->u[3] = src0->u[3] | src1->u[3];
4209 }
4210
4211 static void
4212 micro_xor(union tgsi_exec_channel *dst,
4213 const union tgsi_exec_channel *src0,
4214 const union tgsi_exec_channel *src1)
4215 {
4216 dst->u[0] = src0->u[0] ^ src1->u[0];
4217 dst->u[1] = src0->u[1] ^ src1->u[1];
4218 dst->u[2] = src0->u[2] ^ src1->u[2];
4219 dst->u[3] = src0->u[3] ^ src1->u[3];
4220 }
4221
4222 static void
4223 micro_mod(union tgsi_exec_channel *dst,
4224 const union tgsi_exec_channel *src0,
4225 const union tgsi_exec_channel *src1)
4226 {
4227 dst->i[0] = src0->i[0] % src1->i[0];
4228 dst->i[1] = src0->i[1] % src1->i[1];
4229 dst->i[2] = src0->i[2] % src1->i[2];
4230 dst->i[3] = src0->i[3] % src1->i[3];
4231 }
4232
4233 static void
4234 micro_f2i(union tgsi_exec_channel *dst,
4235 const union tgsi_exec_channel *src)
4236 {
4237 dst->i[0] = (int)src->f[0];
4238 dst->i[1] = (int)src->f[1];
4239 dst->i[2] = (int)src->f[2];
4240 dst->i[3] = (int)src->f[3];
4241 }
4242
4243 static void
4244 micro_fseq(union tgsi_exec_channel *dst,
4245 const union tgsi_exec_channel *src0,
4246 const union tgsi_exec_channel *src1)
4247 {
4248 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
4249 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
4250 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
4251 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
4252 }
4253
4254 static void
4255 micro_fsge(union tgsi_exec_channel *dst,
4256 const union tgsi_exec_channel *src0,
4257 const union tgsi_exec_channel *src1)
4258 {
4259 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
4260 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
4261 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
4262 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
4263 }
4264
4265 static void
4266 micro_fslt(union tgsi_exec_channel *dst,
4267 const union tgsi_exec_channel *src0,
4268 const union tgsi_exec_channel *src1)
4269 {
4270 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
4271 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
4272 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
4273 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
4274 }
4275
4276 static void
4277 micro_fsne(union tgsi_exec_channel *dst,
4278 const union tgsi_exec_channel *src0,
4279 const union tgsi_exec_channel *src1)
4280 {
4281 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
4282 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
4283 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
4284 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
4285 }
4286
4287 static void
4288 micro_idiv(union tgsi_exec_channel *dst,
4289 const union tgsi_exec_channel *src0,
4290 const union tgsi_exec_channel *src1)
4291 {
4292 dst->i[0] = src1->i[0] ? src0->i[0] / src1->i[0] : 0;
4293 dst->i[1] = src1->i[1] ? src0->i[1] / src1->i[1] : 0;
4294 dst->i[2] = src1->i[2] ? src0->i[2] / src1->i[2] : 0;
4295 dst->i[3] = src1->i[3] ? src0->i[3] / src1->i[3] : 0;
4296 }
4297
4298 static void
4299 micro_imax(union tgsi_exec_channel *dst,
4300 const union tgsi_exec_channel *src0,
4301 const union tgsi_exec_channel *src1)
4302 {
4303 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
4304 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
4305 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
4306 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
4307 }
4308
4309 static void
4310 micro_imin(union tgsi_exec_channel *dst,
4311 const union tgsi_exec_channel *src0,
4312 const union tgsi_exec_channel *src1)
4313 {
4314 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
4315 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
4316 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
4317 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
4318 }
4319
4320 static void
4321 micro_isge(union tgsi_exec_channel *dst,
4322 const union tgsi_exec_channel *src0,
4323 const union tgsi_exec_channel *src1)
4324 {
4325 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
4326 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
4327 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
4328 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
4329 }
4330
4331 static void
4332 micro_ishr(union tgsi_exec_channel *dst,
4333 const union tgsi_exec_channel *src0,
4334 const union tgsi_exec_channel *src1)
4335 {
4336 unsigned masked_count;
4337 masked_count = src1->i[0] & 0x1f;
4338 dst->i[0] = src0->i[0] >> masked_count;
4339 masked_count = src1->i[1] & 0x1f;
4340 dst->i[1] = src0->i[1] >> masked_count;
4341 masked_count = src1->i[2] & 0x1f;
4342 dst->i[2] = src0->i[2] >> masked_count;
4343 masked_count = src1->i[3] & 0x1f;
4344 dst->i[3] = src0->i[3] >> masked_count;
4345 }
4346
4347 static void
4348 micro_islt(union tgsi_exec_channel *dst,
4349 const union tgsi_exec_channel *src0,
4350 const union tgsi_exec_channel *src1)
4351 {
4352 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
4353 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
4354 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
4355 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
4356 }
4357
4358 static void
4359 micro_f2u(union tgsi_exec_channel *dst,
4360 const union tgsi_exec_channel *src)
4361 {
4362 dst->u[0] = (uint)src->f[0];
4363 dst->u[1] = (uint)src->f[1];
4364 dst->u[2] = (uint)src->f[2];
4365 dst->u[3] = (uint)src->f[3];
4366 }
4367
4368 static void
4369 micro_u2f(union tgsi_exec_channel *dst,
4370 const union tgsi_exec_channel *src)
4371 {
4372 dst->f[0] = (float)src->u[0];
4373 dst->f[1] = (float)src->u[1];
4374 dst->f[2] = (float)src->u[2];
4375 dst->f[3] = (float)src->u[3];
4376 }
4377
4378 static void
4379 micro_uadd(union tgsi_exec_channel *dst,
4380 const union tgsi_exec_channel *src0,
4381 const union tgsi_exec_channel *src1)
4382 {
4383 dst->u[0] = src0->u[0] + src1->u[0];
4384 dst->u[1] = src0->u[1] + src1->u[1];
4385 dst->u[2] = src0->u[2] + src1->u[2];
4386 dst->u[3] = src0->u[3] + src1->u[3];
4387 }
4388
4389 static void
4390 micro_udiv(union tgsi_exec_channel *dst,
4391 const union tgsi_exec_channel *src0,
4392 const union tgsi_exec_channel *src1)
4393 {
4394 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
4395 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
4396 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
4397 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
4398 }
4399
4400 static void
4401 micro_umad(union tgsi_exec_channel *dst,
4402 const union tgsi_exec_channel *src0,
4403 const union tgsi_exec_channel *src1,
4404 const union tgsi_exec_channel *src2)
4405 {
4406 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
4407 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
4408 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
4409 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
4410 }
4411
4412 static void
4413 micro_umax(union tgsi_exec_channel *dst,
4414 const union tgsi_exec_channel *src0,
4415 const union tgsi_exec_channel *src1)
4416 {
4417 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
4418 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
4419 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
4420 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
4421 }
4422
4423 static void
4424 micro_umin(union tgsi_exec_channel *dst,
4425 const union tgsi_exec_channel *src0,
4426 const union tgsi_exec_channel *src1)
4427 {
4428 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
4429 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
4430 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
4431 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
4432 }
4433
4434 static void
4435 micro_umod(union tgsi_exec_channel *dst,
4436 const union tgsi_exec_channel *src0,
4437 const union tgsi_exec_channel *src1)
4438 {
4439 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
4440 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
4441 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
4442 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
4443 }
4444
4445 static void
4446 micro_umul(union tgsi_exec_channel *dst,
4447 const union tgsi_exec_channel *src0,
4448 const union tgsi_exec_channel *src1)
4449 {
4450 dst->u[0] = src0->u[0] * src1->u[0];
4451 dst->u[1] = src0->u[1] * src1->u[1];
4452 dst->u[2] = src0->u[2] * src1->u[2];
4453 dst->u[3] = src0->u[3] * src1->u[3];
4454 }
4455
4456 static void
4457 micro_imul_hi(union tgsi_exec_channel *dst,
4458 const union tgsi_exec_channel *src0,
4459 const union tgsi_exec_channel *src1)
4460 {
4461 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4462 dst->i[0] = I64M(src0->i[0], src1->i[0]);
4463 dst->i[1] = I64M(src0->i[1], src1->i[1]);
4464 dst->i[2] = I64M(src0->i[2], src1->i[2]);
4465 dst->i[3] = I64M(src0->i[3], src1->i[3]);
4466 #undef I64M
4467 }
4468
4469 static void
4470 micro_umul_hi(union tgsi_exec_channel *dst,
4471 const union tgsi_exec_channel *src0,
4472 const union tgsi_exec_channel *src1)
4473 {
4474 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4475 dst->u[0] = U64M(src0->u[0], src1->u[0]);
4476 dst->u[1] = U64M(src0->u[1], src1->u[1]);
4477 dst->u[2] = U64M(src0->u[2], src1->u[2]);
4478 dst->u[3] = U64M(src0->u[3], src1->u[3]);
4479 #undef U64M
4480 }
4481
4482 static void
4483 micro_useq(union tgsi_exec_channel *dst,
4484 const union tgsi_exec_channel *src0,
4485 const union tgsi_exec_channel *src1)
4486 {
4487 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
4488 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
4489 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
4490 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
4491 }
4492
4493 static void
4494 micro_usge(union tgsi_exec_channel *dst,
4495 const union tgsi_exec_channel *src0,
4496 const union tgsi_exec_channel *src1)
4497 {
4498 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
4499 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
4500 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
4501 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
4502 }
4503
4504 static void
4505 micro_ushr(union tgsi_exec_channel *dst,
4506 const union tgsi_exec_channel *src0,
4507 const union tgsi_exec_channel *src1)
4508 {
4509 unsigned masked_count;
4510 masked_count = src1->u[0] & 0x1f;
4511 dst->u[0] = src0->u[0] >> masked_count;
4512 masked_count = src1->u[1] & 0x1f;
4513 dst->u[1] = src0->u[1] >> masked_count;
4514 masked_count = src1->u[2] & 0x1f;
4515 dst->u[2] = src0->u[2] >> masked_count;
4516 masked_count = src1->u[3] & 0x1f;
4517 dst->u[3] = src0->u[3] >> masked_count;
4518 }
4519
4520 static void
4521 micro_uslt(union tgsi_exec_channel *dst,
4522 const union tgsi_exec_channel *src0,
4523 const union tgsi_exec_channel *src1)
4524 {
4525 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
4526 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
4527 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
4528 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
4529 }
4530
4531 static void
4532 micro_usne(union tgsi_exec_channel *dst,
4533 const union tgsi_exec_channel *src0,
4534 const union tgsi_exec_channel *src1)
4535 {
4536 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
4537 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
4538 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
4539 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
4540 }
4541
4542 static void
4543 micro_uarl(union tgsi_exec_channel *dst,
4544 const union tgsi_exec_channel *src)
4545 {
4546 dst->i[0] = src->u[0];
4547 dst->i[1] = src->u[1];
4548 dst->i[2] = src->u[2];
4549 dst->i[3] = src->u[3];
4550 }
4551
4552 static void
4553 micro_ucmp(union tgsi_exec_channel *dst,
4554 const union tgsi_exec_channel *src0,
4555 const union tgsi_exec_channel *src1,
4556 const union tgsi_exec_channel *src2)
4557 {
4558 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
4559 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
4560 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
4561 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
4562 }
4563
4564 /**
4565 * Signed bitfield extract (i.e. sign-extend the extracted bits)
4566 */
4567 static void
4568 micro_ibfe(union tgsi_exec_channel *dst,
4569 const union tgsi_exec_channel *src0,
4570 const union tgsi_exec_channel *src1,
4571 const union tgsi_exec_channel *src2)
4572 {
4573 int i;
4574 for (i = 0; i < 4; i++) {
4575 int width = src2->i[i] & 0x1f;
4576 int offset = src1->i[i] & 0x1f;
4577 if (width == 0)
4578 dst->i[i] = 0;
4579 else if (width + offset < 32)
4580 dst->i[i] = (src0->i[i] << (32 - width - offset)) >> (32 - width);
4581 else
4582 dst->i[i] = src0->i[i] >> offset;
4583 }
4584 }
4585
4586 /**
4587 * Unsigned bitfield extract
4588 */
4589 static void
4590 micro_ubfe(union tgsi_exec_channel *dst,
4591 const union tgsi_exec_channel *src0,
4592 const union tgsi_exec_channel *src1,
4593 const union tgsi_exec_channel *src2)
4594 {
4595 int i;
4596 for (i = 0; i < 4; i++) {
4597 int width = src2->u[i] & 0x1f;
4598 int offset = src1->u[i] & 0x1f;
4599 if (width == 0)
4600 dst->u[i] = 0;
4601 else if (width + offset < 32)
4602 dst->u[i] = (src0->u[i] << (32 - width - offset)) >> (32 - width);
4603 else
4604 dst->u[i] = src0->u[i] >> offset;
4605 }
4606 }
4607
4608 /**
4609 * Bitfield insert: copy low bits from src1 into a region of src0.
4610 */
4611 static void
4612 micro_bfi(union tgsi_exec_channel *dst,
4613 const union tgsi_exec_channel *src0,
4614 const union tgsi_exec_channel *src1,
4615 const union tgsi_exec_channel *src2,
4616 const union tgsi_exec_channel *src3)
4617 {
4618 int i;
4619 for (i = 0; i < 4; i++) {
4620 int width = src3->u[i] & 0x1f;
4621 int offset = src2->u[i] & 0x1f;
4622 int bitmask = ((1 << width) - 1) << offset;
4623 dst->u[i] = ((src1->u[i] << offset) & bitmask) | (src0->u[i] & ~bitmask);
4624 }
4625 }
4626
4627 static void
4628 micro_brev(union tgsi_exec_channel *dst,
4629 const union tgsi_exec_channel *src)
4630 {
4631 dst->u[0] = util_bitreverse(src->u[0]);
4632 dst->u[1] = util_bitreverse(src->u[1]);
4633 dst->u[2] = util_bitreverse(src->u[2]);
4634 dst->u[3] = util_bitreverse(src->u[3]);
4635 }
4636
4637 static void
4638 micro_popc(union tgsi_exec_channel *dst,
4639 const union tgsi_exec_channel *src)
4640 {
4641 dst->u[0] = util_bitcount(src->u[0]);
4642 dst->u[1] = util_bitcount(src->u[1]);
4643 dst->u[2] = util_bitcount(src->u[2]);
4644 dst->u[3] = util_bitcount(src->u[3]);
4645 }
4646
4647 static void
4648 micro_lsb(union tgsi_exec_channel *dst,
4649 const union tgsi_exec_channel *src)
4650 {
4651 dst->i[0] = ffs(src->u[0]) - 1;
4652 dst->i[1] = ffs(src->u[1]) - 1;
4653 dst->i[2] = ffs(src->u[2]) - 1;
4654 dst->i[3] = ffs(src->u[3]) - 1;
4655 }
4656
4657 static void
4658 micro_imsb(union tgsi_exec_channel *dst,
4659 const union tgsi_exec_channel *src)
4660 {
4661 dst->i[0] = util_last_bit_signed(src->i[0]) - 1;
4662 dst->i[1] = util_last_bit_signed(src->i[1]) - 1;
4663 dst->i[2] = util_last_bit_signed(src->i[2]) - 1;
4664 dst->i[3] = util_last_bit_signed(src->i[3]) - 1;
4665 }
4666
4667 static void
4668 micro_umsb(union tgsi_exec_channel *dst,
4669 const union tgsi_exec_channel *src)
4670 {
4671 dst->i[0] = util_last_bit(src->u[0]) - 1;
4672 dst->i[1] = util_last_bit(src->u[1]) - 1;
4673 dst->i[2] = util_last_bit(src->u[2]) - 1;
4674 dst->i[3] = util_last_bit(src->u[3]) - 1;
4675 }
4676
4677 static void
4678 exec_instruction(
4679 struct tgsi_exec_machine *mach,
4680 const struct tgsi_full_instruction *inst,
4681 int *pc )
4682 {
4683 union tgsi_exec_channel r[10];
4684
4685 (*pc)++;
4686
4687 switch (inst->Instruction.Opcode) {
4688 case TGSI_OPCODE_ARL:
4689 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4690 break;
4691
4692 case TGSI_OPCODE_MOV:
4693 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4694 break;
4695
4696 case TGSI_OPCODE_LIT:
4697 exec_lit(mach, inst);
4698 break;
4699
4700 case TGSI_OPCODE_RCP:
4701 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4702 break;
4703
4704 case TGSI_OPCODE_RSQ:
4705 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4706 break;
4707
4708 case TGSI_OPCODE_EXP:
4709 exec_exp(mach, inst);
4710 break;
4711
4712 case TGSI_OPCODE_LOG:
4713 exec_log(mach, inst);
4714 break;
4715
4716 case TGSI_OPCODE_MUL:
4717 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4718 break;
4719
4720 case TGSI_OPCODE_ADD:
4721 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4722 break;
4723
4724 case TGSI_OPCODE_DP3:
4725 exec_dp3(mach, inst);
4726 break;
4727
4728 case TGSI_OPCODE_DP4:
4729 exec_dp4(mach, inst);
4730 break;
4731
4732 case TGSI_OPCODE_DST:
4733 exec_dst(mach, inst);
4734 break;
4735
4736 case TGSI_OPCODE_MIN:
4737 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4738 break;
4739
4740 case TGSI_OPCODE_MAX:
4741 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4742 break;
4743
4744 case TGSI_OPCODE_SLT:
4745 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4746 break;
4747
4748 case TGSI_OPCODE_SGE:
4749 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4750 break;
4751
4752 case TGSI_OPCODE_MAD:
4753 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4754 break;
4755
4756 case TGSI_OPCODE_SUB:
4757 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4758 break;
4759
4760 case TGSI_OPCODE_LRP:
4761 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4762 break;
4763
4764 case TGSI_OPCODE_SQRT:
4765 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4766 break;
4767
4768 case TGSI_OPCODE_DP2A:
4769 exec_dp2a(mach, inst);
4770 break;
4771
4772 case TGSI_OPCODE_FRC:
4773 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4774 break;
4775
4776 case TGSI_OPCODE_CLAMP:
4777 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4778 break;
4779
4780 case TGSI_OPCODE_FLR:
4781 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4782 break;
4783
4784 case TGSI_OPCODE_ROUND:
4785 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4786 break;
4787
4788 case TGSI_OPCODE_EX2:
4789 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4790 break;
4791
4792 case TGSI_OPCODE_LG2:
4793 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4794 break;
4795
4796 case TGSI_OPCODE_POW:
4797 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4798 break;
4799
4800 case TGSI_OPCODE_XPD:
4801 exec_xpd(mach, inst);
4802 break;
4803
4804 case TGSI_OPCODE_ABS:
4805 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4806 break;
4807
4808 case TGSI_OPCODE_DPH:
4809 exec_dph(mach, inst);
4810 break;
4811
4812 case TGSI_OPCODE_COS:
4813 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4814 break;
4815
4816 case TGSI_OPCODE_DDX:
4817 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4818 break;
4819
4820 case TGSI_OPCODE_DDY:
4821 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4822 break;
4823
4824 case TGSI_OPCODE_KILL:
4825 exec_kill (mach, inst);
4826 break;
4827
4828 case TGSI_OPCODE_KILL_IF:
4829 exec_kill_if (mach, inst);
4830 break;
4831
4832 case TGSI_OPCODE_PK2H:
4833 exec_pk2h(mach, inst);
4834 break;
4835
4836 case TGSI_OPCODE_PK2US:
4837 assert (0);
4838 break;
4839
4840 case TGSI_OPCODE_PK4B:
4841 assert (0);
4842 break;
4843
4844 case TGSI_OPCODE_PK4UB:
4845 assert (0);
4846 break;
4847
4848 case TGSI_OPCODE_SEQ:
4849 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4850 break;
4851
4852 case TGSI_OPCODE_SGT:
4853 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4854 break;
4855
4856 case TGSI_OPCODE_SIN:
4857 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4858 break;
4859
4860 case TGSI_OPCODE_SLE:
4861 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4862 break;
4863
4864 case TGSI_OPCODE_SNE:
4865 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4866 break;
4867
4868 case TGSI_OPCODE_TEX:
4869 /* simple texture lookup */
4870 /* src[0] = texcoord */
4871 /* src[1] = sampler unit */
4872 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
4873 break;
4874
4875 case TGSI_OPCODE_TXB:
4876 /* Texture lookup with lod bias */
4877 /* src[0] = texcoord (src[0].w = LOD bias) */
4878 /* src[1] = sampler unit */
4879 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
4880 break;
4881
4882 case TGSI_OPCODE_TXD:
4883 /* Texture lookup with explict partial derivatives */
4884 /* src[0] = texcoord */
4885 /* src[1] = d[strq]/dx */
4886 /* src[2] = d[strq]/dy */
4887 /* src[3] = sampler unit */
4888 exec_txd(mach, inst);
4889 break;
4890
4891 case TGSI_OPCODE_TXL:
4892 /* Texture lookup with explit LOD */
4893 /* src[0] = texcoord (src[0].w = LOD) */
4894 /* src[1] = sampler unit */
4895 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
4896 break;
4897
4898 case TGSI_OPCODE_TXP:
4899 /* Texture lookup with projection */
4900 /* src[0] = texcoord (src[0].w = projection) */
4901 /* src[1] = sampler unit */
4902 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
4903 break;
4904
4905 case TGSI_OPCODE_TG4:
4906 /* src[0] = texcoord */
4907 /* src[1] = component */
4908 /* src[2] = sampler unit */
4909 exec_tex(mach, inst, TEX_MODIFIER_GATHER, 2);
4910 break;
4911
4912 case TGSI_OPCODE_LODQ:
4913 /* src[0] = texcoord */
4914 /* src[1] = sampler unit */
4915 exec_lodq(mach, inst);
4916 break;
4917
4918 case TGSI_OPCODE_UP2H:
4919 exec_up2h(mach, inst);
4920 break;
4921
4922 case TGSI_OPCODE_UP2US:
4923 assert (0);
4924 break;
4925
4926 case TGSI_OPCODE_UP4B:
4927 assert (0);
4928 break;
4929
4930 case TGSI_OPCODE_UP4UB:
4931 assert (0);
4932 break;
4933
4934 case TGSI_OPCODE_ARR:
4935 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4936 break;
4937
4938 case TGSI_OPCODE_CAL:
4939 /* skip the call if no execution channels are enabled */
4940 if (mach->ExecMask) {
4941 /* do the call */
4942
4943 /* First, record the depths of the execution stacks.
4944 * This is important for deeply nested/looped return statements.
4945 * We have to unwind the stacks by the correct amount. For a
4946 * real code generator, we could determine the number of entries
4947 * to pop off each stack with simple static analysis and avoid
4948 * implementing this data structure at run time.
4949 */
4950 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
4951 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
4952 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
4953 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
4954 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
4955 /* note that PC was already incremented above */
4956 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
4957
4958 mach->CallStackTop++;
4959
4960 /* Second, push the Cond, Loop, Cont, Func stacks */
4961 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
4962 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4963 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4964 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
4965 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4966 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
4967
4968 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
4969 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4970 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4971 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
4972 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4973 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
4974
4975 /* Finally, jump to the subroutine. The label is a pointer
4976 * (an instruction number) to the BGNSUB instruction.
4977 */
4978 *pc = inst->Label.Label;
4979 assert(mach->Instructions[*pc].Instruction.Opcode
4980 == TGSI_OPCODE_BGNSUB);
4981 }
4982 break;
4983
4984 case TGSI_OPCODE_RET:
4985 mach->FuncMask &= ~mach->ExecMask;
4986 UPDATE_EXEC_MASK(mach);
4987
4988 if (mach->FuncMask == 0x0) {
4989 /* really return now (otherwise, keep executing */
4990
4991 if (mach->CallStackTop == 0) {
4992 /* returning from main() */
4993 mach->CondStackTop = 0;
4994 mach->LoopStackTop = 0;
4995 *pc = -1;
4996 return;
4997 }
4998
4999 assert(mach->CallStackTop > 0);
5000 mach->CallStackTop--;
5001
5002 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5003 mach->CondMask = mach->CondStack[mach->CondStackTop];
5004
5005 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5006 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5007
5008 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5009 mach->ContMask = mach->ContStack[mach->ContStackTop];
5010
5011 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5012 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5013
5014 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5015 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5016
5017 assert(mach->FuncStackTop > 0);
5018 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5019
5020 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5021
5022 UPDATE_EXEC_MASK(mach);
5023 }
5024 break;
5025
5026 case TGSI_OPCODE_SSG:
5027 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5028 break;
5029
5030 case TGSI_OPCODE_CMP:
5031 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5032 break;
5033
5034 case TGSI_OPCODE_SCS:
5035 exec_scs(mach, inst);
5036 break;
5037
5038 case TGSI_OPCODE_DIV:
5039 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5040 break;
5041
5042 case TGSI_OPCODE_DP2:
5043 exec_dp2(mach, inst);
5044 break;
5045
5046 case TGSI_OPCODE_IF:
5047 /* push CondMask */
5048 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5049 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5050 FETCH( &r[0], 0, TGSI_CHAN_X );
5051 /* update CondMask */
5052 if( ! r[0].f[0] ) {
5053 mach->CondMask &= ~0x1;
5054 }
5055 if( ! r[0].f[1] ) {
5056 mach->CondMask &= ~0x2;
5057 }
5058 if( ! r[0].f[2] ) {
5059 mach->CondMask &= ~0x4;
5060 }
5061 if( ! r[0].f[3] ) {
5062 mach->CondMask &= ~0x8;
5063 }
5064 UPDATE_EXEC_MASK(mach);
5065 /* Todo: If CondMask==0, jump to ELSE */
5066 break;
5067
5068 case TGSI_OPCODE_UIF:
5069 /* push CondMask */
5070 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
5071 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
5072 IFETCH( &r[0], 0, TGSI_CHAN_X );
5073 /* update CondMask */
5074 if( ! r[0].u[0] ) {
5075 mach->CondMask &= ~0x1;
5076 }
5077 if( ! r[0].u[1] ) {
5078 mach->CondMask &= ~0x2;
5079 }
5080 if( ! r[0].u[2] ) {
5081 mach->CondMask &= ~0x4;
5082 }
5083 if( ! r[0].u[3] ) {
5084 mach->CondMask &= ~0x8;
5085 }
5086 UPDATE_EXEC_MASK(mach);
5087 /* Todo: If CondMask==0, jump to ELSE */
5088 break;
5089
5090 case TGSI_OPCODE_ELSE:
5091 /* invert CondMask wrt previous mask */
5092 {
5093 uint prevMask;
5094 assert(mach->CondStackTop > 0);
5095 prevMask = mach->CondStack[mach->CondStackTop - 1];
5096 mach->CondMask = ~mach->CondMask & prevMask;
5097 UPDATE_EXEC_MASK(mach);
5098 /* Todo: If CondMask==0, jump to ENDIF */
5099 }
5100 break;
5101
5102 case TGSI_OPCODE_ENDIF:
5103 /* pop CondMask */
5104 assert(mach->CondStackTop > 0);
5105 mach->CondMask = mach->CondStack[--mach->CondStackTop];
5106 UPDATE_EXEC_MASK(mach);
5107 break;
5108
5109 case TGSI_OPCODE_END:
5110 /* make sure we end primitives which haven't
5111 * been explicitly emitted */
5112 conditional_emit_primitive(mach);
5113 /* halt execution */
5114 *pc = -1;
5115 break;
5116
5117 case TGSI_OPCODE_PUSHA:
5118 assert (0);
5119 break;
5120
5121 case TGSI_OPCODE_POPA:
5122 assert (0);
5123 break;
5124
5125 case TGSI_OPCODE_CEIL:
5126 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5127 break;
5128
5129 case TGSI_OPCODE_I2F:
5130 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
5131 break;
5132
5133 case TGSI_OPCODE_NOT:
5134 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5135 break;
5136
5137 case TGSI_OPCODE_TRUNC:
5138 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
5139 break;
5140
5141 case TGSI_OPCODE_SHL:
5142 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5143 break;
5144
5145 case TGSI_OPCODE_AND:
5146 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5147 break;
5148
5149 case TGSI_OPCODE_OR:
5150 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5151 break;
5152
5153 case TGSI_OPCODE_MOD:
5154 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5155 break;
5156
5157 case TGSI_OPCODE_XOR:
5158 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5159 break;
5160
5161 case TGSI_OPCODE_SAD:
5162 assert (0);
5163 break;
5164
5165 case TGSI_OPCODE_TXF:
5166 exec_txf(mach, inst);
5167 break;
5168
5169 case TGSI_OPCODE_TXQ:
5170 exec_txq(mach, inst);
5171 break;
5172
5173 case TGSI_OPCODE_EMIT:
5174 emit_vertex(mach);
5175 break;
5176
5177 case TGSI_OPCODE_ENDPRIM:
5178 emit_primitive(mach);
5179 break;
5180
5181 case TGSI_OPCODE_BGNLOOP:
5182 /* push LoopMask and ContMasks */
5183 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5184 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5185 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
5186 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
5187
5188 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
5189 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
5190 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
5191 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
5192 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
5193 break;
5194
5195 case TGSI_OPCODE_ENDLOOP:
5196 /* Restore ContMask, but don't pop */
5197 assert(mach->ContStackTop > 0);
5198 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
5199 UPDATE_EXEC_MASK(mach);
5200 if (mach->ExecMask) {
5201 /* repeat loop: jump to instruction just past BGNLOOP */
5202 assert(mach->LoopLabelStackTop > 0);
5203 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
5204 }
5205 else {
5206 /* exit loop: pop LoopMask */
5207 assert(mach->LoopStackTop > 0);
5208 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
5209 /* pop ContMask */
5210 assert(mach->ContStackTop > 0);
5211 mach->ContMask = mach->ContStack[--mach->ContStackTop];
5212 assert(mach->LoopLabelStackTop > 0);
5213 --mach->LoopLabelStackTop;
5214
5215 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
5216 }
5217 UPDATE_EXEC_MASK(mach);
5218 break;
5219
5220 case TGSI_OPCODE_BRK:
5221 exec_break(mach);
5222 break;
5223
5224 case TGSI_OPCODE_CONT:
5225 /* turn off cont channels for each enabled exec channel */
5226 mach->ContMask &= ~mach->ExecMask;
5227 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5228 UPDATE_EXEC_MASK(mach);
5229 break;
5230
5231 case TGSI_OPCODE_BGNSUB:
5232 /* no-op */
5233 break;
5234
5235 case TGSI_OPCODE_ENDSUB:
5236 /*
5237 * XXX: This really should be a no-op. We should never reach this opcode.
5238 */
5239
5240 assert(mach->CallStackTop > 0);
5241 mach->CallStackTop--;
5242
5243 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
5244 mach->CondMask = mach->CondStack[mach->CondStackTop];
5245
5246 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
5247 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
5248
5249 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
5250 mach->ContMask = mach->ContStack[mach->ContStackTop];
5251
5252 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
5253 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
5254
5255 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
5256 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
5257
5258 assert(mach->FuncStackTop > 0);
5259 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
5260
5261 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
5262
5263 UPDATE_EXEC_MASK(mach);
5264 break;
5265
5266 case TGSI_OPCODE_NOP:
5267 break;
5268
5269 case TGSI_OPCODE_BREAKC:
5270 IFETCH(&r[0], 0, TGSI_CHAN_X);
5271 /* update CondMask */
5272 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
5273 mach->LoopMask &= ~0x1;
5274 }
5275 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
5276 mach->LoopMask &= ~0x2;
5277 }
5278 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
5279 mach->LoopMask &= ~0x4;
5280 }
5281 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
5282 mach->LoopMask &= ~0x8;
5283 }
5284 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5285 UPDATE_EXEC_MASK(mach);
5286 break;
5287
5288 case TGSI_OPCODE_F2I:
5289 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
5290 break;
5291
5292 case TGSI_OPCODE_FSEQ:
5293 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5294 break;
5295
5296 case TGSI_OPCODE_FSGE:
5297 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5298 break;
5299
5300 case TGSI_OPCODE_FSLT:
5301 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5302 break;
5303
5304 case TGSI_OPCODE_FSNE:
5305 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5306 break;
5307
5308 case TGSI_OPCODE_IDIV:
5309 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5310 break;
5311
5312 case TGSI_OPCODE_IMAX:
5313 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5314 break;
5315
5316 case TGSI_OPCODE_IMIN:
5317 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5318 break;
5319
5320 case TGSI_OPCODE_INEG:
5321 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5322 break;
5323
5324 case TGSI_OPCODE_ISGE:
5325 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5326 break;
5327
5328 case TGSI_OPCODE_ISHR:
5329 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5330 break;
5331
5332 case TGSI_OPCODE_ISLT:
5333 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5334 break;
5335
5336 case TGSI_OPCODE_F2U:
5337 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
5338 break;
5339
5340 case TGSI_OPCODE_U2F:
5341 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
5342 break;
5343
5344 case TGSI_OPCODE_UADD:
5345 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5346 break;
5347
5348 case TGSI_OPCODE_UDIV:
5349 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5350 break;
5351
5352 case TGSI_OPCODE_UMAD:
5353 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5354 break;
5355
5356 case TGSI_OPCODE_UMAX:
5357 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5358 break;
5359
5360 case TGSI_OPCODE_UMIN:
5361 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5362 break;
5363
5364 case TGSI_OPCODE_UMOD:
5365 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5366 break;
5367
5368 case TGSI_OPCODE_UMUL:
5369 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5370 break;
5371
5372 case TGSI_OPCODE_IMUL_HI:
5373 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5374 break;
5375
5376 case TGSI_OPCODE_UMUL_HI:
5377 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5378 break;
5379
5380 case TGSI_OPCODE_USEQ:
5381 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5382 break;
5383
5384 case TGSI_OPCODE_USGE:
5385 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5386 break;
5387
5388 case TGSI_OPCODE_USHR:
5389 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5390 break;
5391
5392 case TGSI_OPCODE_USLT:
5393 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5394 break;
5395
5396 case TGSI_OPCODE_USNE:
5397 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5398 break;
5399
5400 case TGSI_OPCODE_SWITCH:
5401 exec_switch(mach, inst);
5402 break;
5403
5404 case TGSI_OPCODE_CASE:
5405 exec_case(mach, inst);
5406 break;
5407
5408 case TGSI_OPCODE_DEFAULT:
5409 exec_default(mach);
5410 break;
5411
5412 case TGSI_OPCODE_ENDSWITCH:
5413 exec_endswitch(mach);
5414 break;
5415
5416 case TGSI_OPCODE_SAMPLE_I:
5417 exec_txf(mach, inst);
5418 break;
5419
5420 case TGSI_OPCODE_SAMPLE_I_MS:
5421 exec_txf(mach, inst);
5422 break;
5423
5424 case TGSI_OPCODE_SAMPLE:
5425 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
5426 break;
5427
5428 case TGSI_OPCODE_SAMPLE_B:
5429 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
5430 break;
5431
5432 case TGSI_OPCODE_SAMPLE_C:
5433 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
5434 break;
5435
5436 case TGSI_OPCODE_SAMPLE_C_LZ:
5437 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
5438 break;
5439
5440 case TGSI_OPCODE_SAMPLE_D:
5441 exec_sample_d(mach, inst);
5442 break;
5443
5444 case TGSI_OPCODE_SAMPLE_L:
5445 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
5446 break;
5447
5448 case TGSI_OPCODE_GATHER4:
5449 assert(0);
5450 break;
5451
5452 case TGSI_OPCODE_SVIEWINFO:
5453 exec_txq(mach, inst);
5454 break;
5455
5456 case TGSI_OPCODE_SAMPLE_POS:
5457 assert(0);
5458 break;
5459
5460 case TGSI_OPCODE_SAMPLE_INFO:
5461 assert(0);
5462 break;
5463
5464 case TGSI_OPCODE_UARL:
5465 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5466 break;
5467
5468 case TGSI_OPCODE_UCMP:
5469 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5470 break;
5471
5472 case TGSI_OPCODE_IABS:
5473 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5474 break;
5475
5476 case TGSI_OPCODE_ISSG:
5477 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5478 break;
5479
5480 case TGSI_OPCODE_TEX2:
5481 /* simple texture lookup */
5482 /* src[0] = texcoord */
5483 /* src[1] = compare */
5484 /* src[2] = sampler unit */
5485 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
5486 break;
5487 case TGSI_OPCODE_TXB2:
5488 /* simple texture lookup */
5489 /* src[0] = texcoord */
5490 /* src[1] = bias */
5491 /* src[2] = sampler unit */
5492 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
5493 break;
5494 case TGSI_OPCODE_TXL2:
5495 /* simple texture lookup */
5496 /* src[0] = texcoord */
5497 /* src[1] = lod */
5498 /* src[2] = sampler unit */
5499 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
5500 break;
5501
5502 case TGSI_OPCODE_IBFE:
5503 exec_vector_trinary(mach, inst, micro_ibfe, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5504 break;
5505 case TGSI_OPCODE_UBFE:
5506 exec_vector_trinary(mach, inst, micro_ubfe, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5507 break;
5508 case TGSI_OPCODE_BFI:
5509 exec_vector_quaternary(mach, inst, micro_bfi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5510 break;
5511 case TGSI_OPCODE_BREV:
5512 exec_vector_unary(mach, inst, micro_brev, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5513 break;
5514 case TGSI_OPCODE_POPC:
5515 exec_vector_unary(mach, inst, micro_popc, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
5516 break;
5517 case TGSI_OPCODE_LSB:
5518 exec_vector_unary(mach, inst, micro_lsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5519 break;
5520 case TGSI_OPCODE_IMSB:
5521 exec_vector_unary(mach, inst, micro_imsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
5522 break;
5523 case TGSI_OPCODE_UMSB:
5524 exec_vector_unary(mach, inst, micro_umsb, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
5525 break;
5526
5527 case TGSI_OPCODE_F2D:
5528 exec_f2d(mach, inst);
5529 break;
5530
5531 case TGSI_OPCODE_D2F:
5532 exec_d2f(mach, inst);
5533 break;
5534
5535 case TGSI_OPCODE_DABS:
5536 exec_double_unary(mach, inst, micro_dabs);
5537 break;
5538
5539 case TGSI_OPCODE_DNEG:
5540 exec_double_unary(mach, inst, micro_dneg);
5541 break;
5542
5543 case TGSI_OPCODE_DADD:
5544 exec_double_binary(mach, inst, micro_dadd, TGSI_EXEC_DATA_DOUBLE);
5545 break;
5546
5547 case TGSI_OPCODE_DMUL:
5548 exec_double_binary(mach, inst, micro_dmul, TGSI_EXEC_DATA_DOUBLE);
5549 break;
5550
5551 case TGSI_OPCODE_DMAX:
5552 exec_double_binary(mach, inst, micro_dmax, TGSI_EXEC_DATA_DOUBLE);
5553 break;
5554
5555 case TGSI_OPCODE_DMIN:
5556 exec_double_binary(mach, inst, micro_dmin, TGSI_EXEC_DATA_DOUBLE);
5557 break;
5558
5559 case TGSI_OPCODE_DSLT:
5560 exec_double_binary(mach, inst, micro_dslt, TGSI_EXEC_DATA_UINT);
5561 break;
5562
5563 case TGSI_OPCODE_DSGE:
5564 exec_double_binary(mach, inst, micro_dsge, TGSI_EXEC_DATA_UINT);
5565 break;
5566
5567 case TGSI_OPCODE_DSEQ:
5568 exec_double_binary(mach, inst, micro_dseq, TGSI_EXEC_DATA_UINT);
5569 break;
5570
5571 case TGSI_OPCODE_DSNE:
5572 exec_double_binary(mach, inst, micro_dsne, TGSI_EXEC_DATA_UINT);
5573 break;
5574
5575 case TGSI_OPCODE_DRCP:
5576 exec_double_unary(mach, inst, micro_drcp);
5577 break;
5578
5579 case TGSI_OPCODE_DSQRT:
5580 exec_double_unary(mach, inst, micro_dsqrt);
5581 break;
5582
5583 case TGSI_OPCODE_DRSQ:
5584 exec_double_unary(mach, inst, micro_drsq);
5585 break;
5586
5587 case TGSI_OPCODE_DMAD:
5588 exec_double_trinary(mach, inst, micro_dmad);
5589 break;
5590
5591 case TGSI_OPCODE_DFRAC:
5592 exec_double_unary(mach, inst, micro_dfrac);
5593 break;
5594
5595 case TGSI_OPCODE_DLDEXP:
5596 exec_dldexp(mach, inst);
5597 break;
5598
5599 case TGSI_OPCODE_DFRACEXP:
5600 exec_dfracexp(mach, inst);
5601 break;
5602
5603 case TGSI_OPCODE_I2D:
5604 exec_i2d(mach, inst);
5605 break;
5606
5607 case TGSI_OPCODE_D2I:
5608 exec_d2i(mach, inst);
5609 break;
5610
5611 case TGSI_OPCODE_U2D:
5612 exec_u2d(mach, inst);
5613 break;
5614
5615 case TGSI_OPCODE_D2U:
5616 exec_d2u(mach, inst);
5617 break;
5618
5619 case TGSI_OPCODE_LOAD:
5620 exec_load(mach, inst);
5621 break;
5622
5623 case TGSI_OPCODE_STORE:
5624 exec_store(mach, inst);
5625 break;
5626
5627 case TGSI_OPCODE_ATOMUADD:
5628 case TGSI_OPCODE_ATOMXCHG:
5629 case TGSI_OPCODE_ATOMCAS:
5630 case TGSI_OPCODE_ATOMAND:
5631 case TGSI_OPCODE_ATOMOR:
5632 case TGSI_OPCODE_ATOMXOR:
5633 case TGSI_OPCODE_ATOMUMIN:
5634 case TGSI_OPCODE_ATOMUMAX:
5635 case TGSI_OPCODE_ATOMIMIN:
5636 case TGSI_OPCODE_ATOMIMAX:
5637 exec_atomop(mach, inst);
5638 break;
5639
5640 case TGSI_OPCODE_RESQ:
5641 exec_resq(mach, inst);
5642 break;
5643 case TGSI_OPCODE_BARRIER:
5644 case TGSI_OPCODE_MEMBAR:
5645 break;
5646 default:
5647 assert( 0 );
5648 }
5649 }
5650
5651
5652 /**
5653 * Run TGSI interpreter.
5654 * \return bitmask of "alive" quad components
5655 */
5656 uint
5657 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
5658 {
5659 uint i;
5660 int pc = 0;
5661 uint default_mask = 0xf;
5662
5663 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
5664 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
5665
5666 if (mach->ShaderType == PIPE_SHADER_GEOMETRY) {
5667 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
5668 mach->Primitives[0] = 0;
5669 /* GS runs on a single primitive for now */
5670 default_mask = 0x1;
5671 }
5672
5673 if (mach->NonHelperMask == 0)
5674 mach->NonHelperMask = default_mask;
5675 mach->CondMask = default_mask;
5676 mach->LoopMask = default_mask;
5677 mach->ContMask = default_mask;
5678 mach->FuncMask = default_mask;
5679 mach->ExecMask = default_mask;
5680
5681 mach->Switch.mask = default_mask;
5682
5683 assert(mach->CondStackTop == 0);
5684 assert(mach->LoopStackTop == 0);
5685 assert(mach->ContStackTop == 0);
5686 assert(mach->SwitchStackTop == 0);
5687 assert(mach->BreakStackTop == 0);
5688 assert(mach->CallStackTop == 0);
5689
5690
5691 /* execute declarations (interpolants) */
5692 for (i = 0; i < mach->NumDeclarations; i++) {
5693 exec_declaration( mach, mach->Declarations+i );
5694 }
5695
5696 {
5697 #if DEBUG_EXECUTION
5698 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
5699 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
5700 uint inst = 1;
5701
5702 memset(mach->Temps, 0, sizeof(temps));
5703 memset(mach->Outputs, 0, sizeof(outputs));
5704 memset(temps, 0, sizeof(temps));
5705 memset(outputs, 0, sizeof(outputs));
5706 #endif
5707
5708 /* execute instructions, until pc is set to -1 */
5709 while (pc != -1) {
5710
5711 #if DEBUG_EXECUTION
5712 uint i;
5713
5714 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
5715 #endif
5716
5717 assert(pc < (int) mach->NumInstructions);
5718 exec_instruction(mach, mach->Instructions + pc, &pc);
5719
5720 #if DEBUG_EXECUTION
5721 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
5722 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
5723 uint j;
5724
5725 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
5726 debug_printf("TEMP[%2u] = ", i);
5727 for (j = 0; j < 4; j++) {
5728 if (j > 0) {
5729 debug_printf(" ");
5730 }
5731 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5732 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
5733 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
5734 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
5735 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
5736 }
5737 }
5738 }
5739 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
5740 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
5741 uint j;
5742
5743 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
5744 debug_printf("OUT[%2u] = ", i);
5745 for (j = 0; j < 4; j++) {
5746 if (j > 0) {
5747 debug_printf(" ");
5748 }
5749 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
5750 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
5751 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
5752 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
5753 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
5754 }
5755 }
5756 }
5757 #endif
5758 }
5759 }
5760
5761 #if 0
5762 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
5763 if (mach->ShaderType == PIPE_SHADER_FRAGMENT) {
5764 /*
5765 * Scale back depth component.
5766 */
5767 for (i = 0; i < 4; i++)
5768 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
5769 }
5770 #endif
5771
5772 /* Strictly speaking, these assertions aren't really needed but they
5773 * can potentially catch some bugs in the control flow code.
5774 */
5775 assert(mach->CondStackTop == 0);
5776 assert(mach->LoopStackTop == 0);
5777 assert(mach->ContStackTop == 0);
5778 assert(mach->SwitchStackTop == 0);
5779 assert(mach->BreakStackTop == 0);
5780 assert(mach->CallStackTop == 0);
5781
5782 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];
5783 }