1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddy(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
231 micro_dmul(union tgsi_double_channel
*dst
,
232 const union tgsi_double_channel
*src
)
234 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
235 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
236 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
237 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
241 micro_dmax(union tgsi_double_channel
*dst
,
242 const union tgsi_double_channel
*src
)
244 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
245 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
246 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
247 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
251 micro_dmin(union tgsi_double_channel
*dst
,
252 const union tgsi_double_channel
*src
)
254 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
255 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
256 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
257 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
261 micro_dneg(union tgsi_double_channel
*dst
,
262 const union tgsi_double_channel
*src
)
264 dst
->d
[0] = -src
->d
[0];
265 dst
->d
[1] = -src
->d
[1];
266 dst
->d
[2] = -src
->d
[2];
267 dst
->d
[3] = -src
->d
[3];
271 micro_dslt(union tgsi_double_channel
*dst
,
272 const union tgsi_double_channel
*src
)
274 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
275 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
276 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
277 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
281 micro_dsne(union tgsi_double_channel
*dst
,
282 const union tgsi_double_channel
*src
)
284 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
285 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
286 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
287 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
291 micro_dsge(union tgsi_double_channel
*dst
,
292 const union tgsi_double_channel
*src
)
294 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
295 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
296 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
297 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
301 micro_dseq(union tgsi_double_channel
*dst
,
302 const union tgsi_double_channel
*src
)
304 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
305 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
306 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
307 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
311 micro_drcp(union tgsi_double_channel
*dst
,
312 const union tgsi_double_channel
*src
)
314 dst
->d
[0] = 1.0 / src
->d
[0];
315 dst
->d
[1] = 1.0 / src
->d
[1];
316 dst
->d
[2] = 1.0 / src
->d
[2];
317 dst
->d
[3] = 1.0 / src
->d
[3];
321 micro_dsqrt(union tgsi_double_channel
*dst
,
322 const union tgsi_double_channel
*src
)
324 dst
->d
[0] = sqrt(src
->d
[0]);
325 dst
->d
[1] = sqrt(src
->d
[1]);
326 dst
->d
[2] = sqrt(src
->d
[2]);
327 dst
->d
[3] = sqrt(src
->d
[3]);
331 micro_drsq(union tgsi_double_channel
*dst
,
332 const union tgsi_double_channel
*src
)
334 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
335 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
336 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
337 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
341 micro_dmad(union tgsi_double_channel
*dst
,
342 const union tgsi_double_channel
*src
)
344 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
345 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
346 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
347 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
351 micro_dfrac(union tgsi_double_channel
*dst
,
352 const union tgsi_double_channel
*src
)
354 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
355 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
356 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
357 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
361 micro_dldexp(union tgsi_double_channel
*dst
,
362 const union tgsi_double_channel
*src0
,
363 union tgsi_exec_channel
*src1
)
365 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
366 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
367 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
368 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
372 micro_dfracexp(union tgsi_double_channel
*dst
,
373 union tgsi_exec_channel
*dst_exp
,
374 const union tgsi_double_channel
*src
)
376 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
377 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
378 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
379 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
383 micro_exp2(union tgsi_exec_channel
*dst
,
384 const union tgsi_exec_channel
*src
)
387 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
388 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
389 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
390 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
395 union tgsi_exec_channel clamped
;
397 for (i
= 0; i
< 4; i
++) {
398 if (src
->f
[i
] > 127.99999f
) {
399 clamped
.f
[i
] = 127.99999f
;
400 } else if (src
->f
[i
] < -126.99999f
) {
401 clamped
.f
[i
] = -126.99999f
;
403 clamped
.f
[i
] = src
->f
[i
];
409 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
410 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
411 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
412 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
413 #endif /* FAST_MATH */
417 micro_f2d(union tgsi_double_channel
*dst
,
418 const union tgsi_exec_channel
*src
)
420 dst
->d
[0] = (double)src
->f
[0];
421 dst
->d
[1] = (double)src
->f
[1];
422 dst
->d
[2] = (double)src
->f
[2];
423 dst
->d
[3] = (double)src
->f
[3];
427 micro_flr(union tgsi_exec_channel
*dst
,
428 const union tgsi_exec_channel
*src
)
430 dst
->f
[0] = floorf(src
->f
[0]);
431 dst
->f
[1] = floorf(src
->f
[1]);
432 dst
->f
[2] = floorf(src
->f
[2]);
433 dst
->f
[3] = floorf(src
->f
[3]);
437 micro_frc(union tgsi_exec_channel
*dst
,
438 const union tgsi_exec_channel
*src
)
440 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
441 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
442 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
443 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
447 micro_i2d(union tgsi_double_channel
*dst
,
448 const union tgsi_exec_channel
*src
)
450 dst
->d
[0] = (double)src
->i
[0];
451 dst
->d
[1] = (double)src
->i
[1];
452 dst
->d
[2] = (double)src
->i
[2];
453 dst
->d
[3] = (double)src
->i
[3];
457 micro_iabs(union tgsi_exec_channel
*dst
,
458 const union tgsi_exec_channel
*src
)
460 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
461 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
462 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
463 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
467 micro_ineg(union tgsi_exec_channel
*dst
,
468 const union tgsi_exec_channel
*src
)
470 dst
->i
[0] = -src
->i
[0];
471 dst
->i
[1] = -src
->i
[1];
472 dst
->i
[2] = -src
->i
[2];
473 dst
->i
[3] = -src
->i
[3];
477 micro_lg2(union tgsi_exec_channel
*dst
,
478 const union tgsi_exec_channel
*src
)
481 dst
->f
[0] = util_fast_log2(src
->f
[0]);
482 dst
->f
[1] = util_fast_log2(src
->f
[1]);
483 dst
->f
[2] = util_fast_log2(src
->f
[2]);
484 dst
->f
[3] = util_fast_log2(src
->f
[3]);
486 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
487 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
488 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
489 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
494 micro_lrp(union tgsi_exec_channel
*dst
,
495 const union tgsi_exec_channel
*src0
,
496 const union tgsi_exec_channel
*src1
,
497 const union tgsi_exec_channel
*src2
)
499 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
500 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
501 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
502 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
506 micro_mad(union tgsi_exec_channel
*dst
,
507 const union tgsi_exec_channel
*src0
,
508 const union tgsi_exec_channel
*src1
,
509 const union tgsi_exec_channel
*src2
)
511 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
512 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
513 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
514 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
518 micro_mov(union tgsi_exec_channel
*dst
,
519 const union tgsi_exec_channel
*src
)
521 dst
->u
[0] = src
->u
[0];
522 dst
->u
[1] = src
->u
[1];
523 dst
->u
[2] = src
->u
[2];
524 dst
->u
[3] = src
->u
[3];
528 micro_rcp(union tgsi_exec_channel
*dst
,
529 const union tgsi_exec_channel
*src
)
531 #if 0 /* for debugging */
532 assert(src
->f
[0] != 0.0f
);
533 assert(src
->f
[1] != 0.0f
);
534 assert(src
->f
[2] != 0.0f
);
535 assert(src
->f
[3] != 0.0f
);
537 dst
->f
[0] = 1.0f
/ src
->f
[0];
538 dst
->f
[1] = 1.0f
/ src
->f
[1];
539 dst
->f
[2] = 1.0f
/ src
->f
[2];
540 dst
->f
[3] = 1.0f
/ src
->f
[3];
544 micro_rnd(union tgsi_exec_channel
*dst
,
545 const union tgsi_exec_channel
*src
)
547 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
548 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
549 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
550 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
554 micro_rsq(union tgsi_exec_channel
*dst
,
555 const union tgsi_exec_channel
*src
)
557 #if 0 /* for debugging */
558 assert(src
->f
[0] != 0.0f
);
559 assert(src
->f
[1] != 0.0f
);
560 assert(src
->f
[2] != 0.0f
);
561 assert(src
->f
[3] != 0.0f
);
563 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
564 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
565 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
566 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
570 micro_sqrt(union tgsi_exec_channel
*dst
,
571 const union tgsi_exec_channel
*src
)
573 dst
->f
[0] = sqrtf(src
->f
[0]);
574 dst
->f
[1] = sqrtf(src
->f
[1]);
575 dst
->f
[2] = sqrtf(src
->f
[2]);
576 dst
->f
[3] = sqrtf(src
->f
[3]);
580 micro_seq(union tgsi_exec_channel
*dst
,
581 const union tgsi_exec_channel
*src0
,
582 const union tgsi_exec_channel
*src1
)
584 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
585 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
586 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
587 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
591 micro_sge(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src0
,
593 const union tgsi_exec_channel
*src1
)
595 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
596 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
597 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
598 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
602 micro_sgn(union tgsi_exec_channel
*dst
,
603 const union tgsi_exec_channel
*src
)
605 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
612 micro_isgn(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src
)
615 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
616 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
617 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
618 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
622 micro_sgt(union tgsi_exec_channel
*dst
,
623 const union tgsi_exec_channel
*src0
,
624 const union tgsi_exec_channel
*src1
)
626 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
627 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
628 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
629 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
633 micro_sin(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->f
[0] = sinf(src
->f
[0]);
637 dst
->f
[1] = sinf(src
->f
[1]);
638 dst
->f
[2] = sinf(src
->f
[2]);
639 dst
->f
[3] = sinf(src
->f
[3]);
643 micro_sle(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_slt(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src0
,
656 const union tgsi_exec_channel
*src1
)
658 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
659 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
660 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
661 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
665 micro_sne(union tgsi_exec_channel
*dst
,
666 const union tgsi_exec_channel
*src0
,
667 const union tgsi_exec_channel
*src1
)
669 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
670 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
671 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
672 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
676 micro_trunc(union tgsi_exec_channel
*dst
,
677 const union tgsi_exec_channel
*src
)
679 dst
->f
[0] = truncf(src
->f
[0]);
680 dst
->f
[1] = truncf(src
->f
[1]);
681 dst
->f
[2] = truncf(src
->f
[2]);
682 dst
->f
[3] = truncf(src
->f
[3]);
686 micro_u2d(union tgsi_double_channel
*dst
,
687 const union tgsi_exec_channel
*src
)
689 dst
->d
[0] = (double)src
->u
[0];
690 dst
->d
[1] = (double)src
->u
[1];
691 dst
->d
[2] = (double)src
->u
[2];
692 dst
->d
[3] = (double)src
->u
[3];
696 micro_i64abs(union tgsi_double_channel
*dst
,
697 const union tgsi_double_channel
*src
)
699 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
700 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
701 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
702 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
706 micro_i64sgn(union tgsi_double_channel
*dst
,
707 const union tgsi_double_channel
*src
)
709 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
710 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
711 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
712 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
716 micro_i64neg(union tgsi_double_channel
*dst
,
717 const union tgsi_double_channel
*src
)
719 dst
->i64
[0] = -src
->i64
[0];
720 dst
->i64
[1] = -src
->i64
[1];
721 dst
->i64
[2] = -src
->i64
[2];
722 dst
->i64
[3] = -src
->i64
[3];
726 micro_u64seq(union tgsi_double_channel
*dst
,
727 const union tgsi_double_channel
*src
)
729 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
730 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
731 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
732 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
736 micro_u64sne(union tgsi_double_channel
*dst
,
737 const union tgsi_double_channel
*src
)
739 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
740 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
741 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
742 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
746 micro_i64slt(union tgsi_double_channel
*dst
,
747 const union tgsi_double_channel
*src
)
749 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
750 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
751 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
752 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
756 micro_u64slt(union tgsi_double_channel
*dst
,
757 const union tgsi_double_channel
*src
)
759 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
760 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
761 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
762 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
766 micro_i64sge(union tgsi_double_channel
*dst
,
767 const union tgsi_double_channel
*src
)
769 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
770 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
771 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
772 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
776 micro_u64sge(union tgsi_double_channel
*dst
,
777 const union tgsi_double_channel
*src
)
779 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
780 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
781 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
782 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
786 micro_u64max(union tgsi_double_channel
*dst
,
787 const union tgsi_double_channel
*src
)
789 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
790 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
791 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
792 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
796 micro_i64max(union tgsi_double_channel
*dst
,
797 const union tgsi_double_channel
*src
)
799 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
800 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
801 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
802 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
806 micro_u64min(union tgsi_double_channel
*dst
,
807 const union tgsi_double_channel
*src
)
809 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
810 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
811 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
812 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
816 micro_i64min(union tgsi_double_channel
*dst
,
817 const union tgsi_double_channel
*src
)
819 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
820 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
821 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
822 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
826 micro_u64add(union tgsi_double_channel
*dst
,
827 const union tgsi_double_channel
*src
)
829 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
830 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
831 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
832 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
836 micro_u64mul(union tgsi_double_channel
*dst
,
837 const union tgsi_double_channel
*src
)
839 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
840 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
841 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
842 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
846 micro_u64div(union tgsi_double_channel
*dst
,
847 const union tgsi_double_channel
*src
)
849 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] / src
[1].u64
[0] : ~0ull;
850 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] / src
[1].u64
[1] : ~0ull;
851 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] / src
[1].u64
[2] : ~0ull;
852 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] / src
[1].u64
[3] : ~0ull;
856 micro_i64div(union tgsi_double_channel
*dst
,
857 const union tgsi_double_channel
*src
)
859 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] / src
[1].i64
[0] : 0;
860 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] / src
[1].i64
[1] : 0;
861 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] / src
[1].i64
[2] : 0;
862 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] / src
[1].i64
[3] : 0;
866 micro_u64mod(union tgsi_double_channel
*dst
,
867 const union tgsi_double_channel
*src
)
869 dst
->u64
[0] = src
[1].u64
[0] ? src
[0].u64
[0] % src
[1].u64
[0] : ~0ull;
870 dst
->u64
[1] = src
[1].u64
[1] ? src
[0].u64
[1] % src
[1].u64
[1] : ~0ull;
871 dst
->u64
[2] = src
[1].u64
[2] ? src
[0].u64
[2] % src
[1].u64
[2] : ~0ull;
872 dst
->u64
[3] = src
[1].u64
[3] ? src
[0].u64
[3] % src
[1].u64
[3] : ~0ull;
876 micro_i64mod(union tgsi_double_channel
*dst
,
877 const union tgsi_double_channel
*src
)
879 dst
->i64
[0] = src
[1].i64
[0] ? src
[0].i64
[0] % src
[1].i64
[0] : ~0ll;
880 dst
->i64
[1] = src
[1].i64
[1] ? src
[0].i64
[1] % src
[1].i64
[1] : ~0ll;
881 dst
->i64
[2] = src
[1].i64
[2] ? src
[0].i64
[2] % src
[1].i64
[2] : ~0ll;
882 dst
->i64
[3] = src
[1].i64
[3] ? src
[0].i64
[3] % src
[1].i64
[3] : ~0ll;
886 micro_u64shl(union tgsi_double_channel
*dst
,
887 const union tgsi_double_channel
*src0
,
888 union tgsi_exec_channel
*src1
)
890 unsigned masked_count
;
891 masked_count
= src1
->u
[0] & 0x3f;
892 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
893 masked_count
= src1
->u
[1] & 0x3f;
894 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
895 masked_count
= src1
->u
[2] & 0x3f;
896 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
897 masked_count
= src1
->u
[3] & 0x3f;
898 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
902 micro_i64shr(union tgsi_double_channel
*dst
,
903 const union tgsi_double_channel
*src0
,
904 union tgsi_exec_channel
*src1
)
906 unsigned masked_count
;
907 masked_count
= src1
->u
[0] & 0x3f;
908 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
909 masked_count
= src1
->u
[1] & 0x3f;
910 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
911 masked_count
= src1
->u
[2] & 0x3f;
912 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
913 masked_count
= src1
->u
[3] & 0x3f;
914 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
918 micro_u64shr(union tgsi_double_channel
*dst
,
919 const union tgsi_double_channel
*src0
,
920 union tgsi_exec_channel
*src1
)
922 unsigned masked_count
;
923 masked_count
= src1
->u
[0] & 0x3f;
924 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
925 masked_count
= src1
->u
[1] & 0x3f;
926 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
927 masked_count
= src1
->u
[2] & 0x3f;
928 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
929 masked_count
= src1
->u
[3] & 0x3f;
930 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
933 enum tgsi_exec_datatype
{
934 TGSI_EXEC_DATA_FLOAT
,
937 TGSI_EXEC_DATA_DOUBLE
,
938 TGSI_EXEC_DATA_INT64
,
939 TGSI_EXEC_DATA_UINT64
,
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
951 #define TEMP_PRIMITIVE_S1_I TGSI_EXEC_TEMP_PRIMITIVE_S1_I
952 #define TEMP_PRIMITIVE_S1_C TGSI_EXEC_TEMP_PRIMITIVE_S1_C
953 #define TEMP_PRIMITIVE_S2_I TGSI_EXEC_TEMP_PRIMITIVE_S2_I
954 #define TEMP_PRIMITIVE_S2_C TGSI_EXEC_TEMP_PRIMITIVE_S2_C
955 #define TEMP_PRIMITIVE_S3_I TGSI_EXEC_TEMP_PRIMITIVE_S3_I
956 #define TEMP_PRIMITIVE_S3_C TGSI_EXEC_TEMP_PRIMITIVE_S3_C
958 static const struct {
961 } temp_prim_idxs
[] = {
962 { TEMP_PRIMITIVE_I
, TEMP_PRIMITIVE_C
},
963 { TEMP_PRIMITIVE_S1_I
, TEMP_PRIMITIVE_S1_C
},
964 { TEMP_PRIMITIVE_S2_I
, TEMP_PRIMITIVE_S2_C
},
965 { TEMP_PRIMITIVE_S3_I
, TEMP_PRIMITIVE_S3_C
},
968 /** The execution mask depends on the conditional mask and the loop mask */
969 #define UPDATE_EXEC_MASK(MACH) \
970 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
973 static const union tgsi_exec_channel ZeroVec
=
974 { { 0.0, 0.0, 0.0, 0.0 } };
976 static const union tgsi_exec_channel OneVec
= {
977 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
980 static const union tgsi_exec_channel P128Vec
= {
981 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
984 static const union tgsi_exec_channel M128Vec
= {
985 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
990 * Assert that none of the float values in 'chan' are infinite or NaN.
991 * NaN and Inf may occur normally during program execution and should
992 * not lead to crashes, etc. But when debugging, it's helpful to catch
996 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
998 assert(!util_is_inf_or_nan((chan
)->f
[0]));
999 assert(!util_is_inf_or_nan((chan
)->f
[1]));
1000 assert(!util_is_inf_or_nan((chan
)->f
[2]));
1001 assert(!util_is_inf_or_nan((chan
)->f
[3]));
1007 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
1009 debug_printf("%s = {%f, %f, %f, %f}\n",
1010 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1017 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1019 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1021 debug_printf("Temp[%u] =\n", index
);
1022 for (i
= 0; i
< 4; i
++) {
1023 debug_printf(" %c: { %f, %f, %f, %f }\n",
1035 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1038 const unsigned *buf_sizes
)
1042 for (i
= 0; i
< num_bufs
; i
++) {
1043 mach
->Consts
[i
] = bufs
[i
];
1044 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1050 * Check if there's a potential src/dst register data dependency when
1051 * using SOA execution.
1054 * This would expand into:
1059 * The second instruction will have the wrong value for t0 if executed as-is.
1062 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1066 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1067 if (writemask
== TGSI_WRITEMASK_X
||
1068 writemask
== TGSI_WRITEMASK_Y
||
1069 writemask
== TGSI_WRITEMASK_Z
||
1070 writemask
== TGSI_WRITEMASK_W
||
1071 writemask
== TGSI_WRITEMASK_NONE
) {
1072 /* no chance of data dependency */
1076 /* loop over src regs */
1077 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1078 if ((inst
->Src
[i
].Register
.File
==
1079 inst
->Dst
[0].Register
.File
) &&
1080 ((inst
->Src
[i
].Register
.Index
==
1081 inst
->Dst
[0].Register
.Index
) ||
1082 inst
->Src
[i
].Register
.Indirect
||
1083 inst
->Dst
[0].Register
.Indirect
)) {
1084 /* loop over dest channels */
1085 uint channelsWritten
= 0x0;
1086 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1087 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1088 /* check if we're reading a channel that's been written */
1089 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1090 if (channelsWritten
& (1 << swizzle
)) {
1094 channelsWritten
|= (1 << chan
);
1104 * Initialize machine state by expanding tokens to full instructions,
1105 * allocating temporary storage, setting up constants, etc.
1106 * After this, we can call tgsi_exec_machine_run() many times.
1109 tgsi_exec_machine_bind_shader(
1110 struct tgsi_exec_machine
*mach
,
1111 const struct tgsi_token
*tokens
,
1112 struct tgsi_sampler
*sampler
,
1113 struct tgsi_image
*image
,
1114 struct tgsi_buffer
*buffer
)
1117 struct tgsi_parse_context parse
;
1118 struct tgsi_full_instruction
*instructions
;
1119 struct tgsi_full_declaration
*declarations
;
1120 uint maxInstructions
= 10, numInstructions
= 0;
1121 uint maxDeclarations
= 10, numDeclarations
= 0;
1124 tgsi_dump(tokens
, 0);
1130 mach
->Tokens
= tokens
;
1131 mach
->Sampler
= sampler
;
1132 mach
->Image
= image
;
1133 mach
->Buffer
= buffer
;
1136 /* unbind and free all */
1137 FREE(mach
->Declarations
);
1138 mach
->Declarations
= NULL
;
1139 mach
->NumDeclarations
= 0;
1141 FREE(mach
->Instructions
);
1142 mach
->Instructions
= NULL
;
1143 mach
->NumInstructions
= 0;
1148 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1149 if (k
!= TGSI_PARSE_OK
) {
1150 debug_printf( "Problem parsing!\n" );
1155 mach
->NumOutputs
= 0;
1157 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1158 mach
->SysSemanticToIndex
[k
] = -1;
1160 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1161 !mach
->UsedGeometryShader
) {
1162 struct tgsi_exec_vector
*inputs
;
1163 struct tgsi_exec_vector
*outputs
;
1165 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1166 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1172 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1173 TGSI_MAX_TOTAL_VERTICES
, 16);
1180 align_free(mach
->Inputs
);
1181 align_free(mach
->Outputs
);
1183 mach
->Inputs
= inputs
;
1184 mach
->Outputs
= outputs
;
1185 mach
->UsedGeometryShader
= TRUE
;
1188 declarations
= (struct tgsi_full_declaration
*)
1189 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1191 if (!declarations
) {
1195 instructions
= (struct tgsi_full_instruction
*)
1196 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1198 if (!instructions
) {
1199 FREE( declarations
);
1203 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1206 tgsi_parse_token( &parse
);
1207 switch( parse
.FullToken
.Token
.Type
) {
1208 case TGSI_TOKEN_TYPE_DECLARATION
:
1209 /* save expanded declaration */
1210 if (numDeclarations
== maxDeclarations
) {
1211 declarations
= REALLOC(declarations
,
1213 * sizeof(struct tgsi_full_declaration
),
1214 (maxDeclarations
+ 10)
1215 * sizeof(struct tgsi_full_declaration
));
1216 maxDeclarations
+= 10;
1218 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1220 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1221 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1226 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1227 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1228 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1231 memcpy(declarations
+ numDeclarations
,
1232 &parse
.FullToken
.FullDeclaration
,
1233 sizeof(declarations
[0]));
1237 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1239 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1240 assert( size
<= 4 );
1241 if (mach
->ImmLimit
>= mach
->ImmsReserved
) {
1242 unsigned newReserved
= mach
->ImmsReserved
? 2 * mach
->ImmsReserved
: 128;
1243 float4
*imms
= REALLOC(mach
->Imms
, mach
->ImmsReserved
, newReserved
* sizeof(float4
));
1245 mach
->ImmsReserved
= newReserved
;
1248 debug_printf("Unable to (re)allocate space for immidiate constants\n");
1253 for( i
= 0; i
< size
; i
++ ) {
1254 mach
->Imms
[mach
->ImmLimit
][i
] =
1255 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1257 mach
->ImmLimit
+= 1;
1261 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1263 /* save expanded instruction */
1264 if (numInstructions
== maxInstructions
) {
1265 instructions
= REALLOC(instructions
,
1267 * sizeof(struct tgsi_full_instruction
),
1268 (maxInstructions
+ 10)
1269 * sizeof(struct tgsi_full_instruction
));
1270 maxInstructions
+= 10;
1273 memcpy(instructions
+ numInstructions
,
1274 &parse
.FullToken
.FullInstruction
,
1275 sizeof(instructions
[0]));
1280 case TGSI_TOKEN_TYPE_PROPERTY
:
1281 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1282 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1283 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1292 tgsi_parse_free (&parse
);
1294 FREE(mach
->Declarations
);
1295 mach
->Declarations
= declarations
;
1296 mach
->NumDeclarations
= numDeclarations
;
1298 FREE(mach
->Instructions
);
1299 mach
->Instructions
= instructions
;
1300 mach
->NumInstructions
= numInstructions
;
1304 struct tgsi_exec_machine
*
1305 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1307 struct tgsi_exec_machine
*mach
;
1310 mach
= align_malloc( sizeof *mach
, 16 );
1314 memset(mach
, 0, sizeof(*mach
));
1316 mach
->ShaderType
= shader_type
;
1317 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1318 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1320 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1321 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1322 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1323 if (!mach
->Inputs
|| !mach
->Outputs
)
1327 if (shader_type
== PIPE_SHADER_FRAGMENT
) {
1328 mach
->InputSampleOffsetApply
= align_malloc(sizeof(apply_sample_offset_func
) * PIPE_MAX_SHADER_INPUTS
, 16);
1329 if (!mach
->InputSampleOffsetApply
)
1333 /* Setup constants needed by the SSE2 executor. */
1334 for( i
= 0; i
< 4; i
++ ) {
1335 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1336 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1337 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1338 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1339 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1340 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1341 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1342 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1343 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1344 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1348 /* silence warnings */
1357 align_free(mach
->InputSampleOffsetApply
);
1358 align_free(mach
->Inputs
);
1359 align_free(mach
->Outputs
);
1367 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1370 FREE(mach
->Instructions
);
1371 FREE(mach
->Declarations
);
1374 align_free(mach
->InputSampleOffsetApply
);
1375 align_free(mach
->Inputs
);
1376 align_free(mach
->Outputs
);
1383 micro_add(union tgsi_exec_channel
*dst
,
1384 const union tgsi_exec_channel
*src0
,
1385 const union tgsi_exec_channel
*src1
)
1387 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1388 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1389 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1390 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1395 union tgsi_exec_channel
*dst
,
1396 const union tgsi_exec_channel
*src0
,
1397 const union tgsi_exec_channel
*src1
)
1399 if (src1
->f
[0] != 0) {
1400 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1402 if (src1
->f
[1] != 0) {
1403 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1405 if (src1
->f
[2] != 0) {
1406 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1408 if (src1
->f
[3] != 0) {
1409 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1415 union tgsi_exec_channel
*dst
,
1416 const union tgsi_exec_channel
*src0
,
1417 const union tgsi_exec_channel
*src1
,
1418 const union tgsi_exec_channel
*src2
,
1419 const union tgsi_exec_channel
*src3
)
1421 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1422 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1423 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1424 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1428 micro_max(union tgsi_exec_channel
*dst
,
1429 const union tgsi_exec_channel
*src0
,
1430 const union tgsi_exec_channel
*src1
)
1432 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1433 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1434 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1435 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1439 micro_min(union tgsi_exec_channel
*dst
,
1440 const union tgsi_exec_channel
*src0
,
1441 const union tgsi_exec_channel
*src1
)
1443 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1444 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1445 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1446 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1450 micro_mul(union tgsi_exec_channel
*dst
,
1451 const union tgsi_exec_channel
*src0
,
1452 const union tgsi_exec_channel
*src1
)
1454 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1455 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1456 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1457 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1462 union tgsi_exec_channel
*dst
,
1463 const union tgsi_exec_channel
*src
)
1465 dst
->f
[0] = -src
->f
[0];
1466 dst
->f
[1] = -src
->f
[1];
1467 dst
->f
[2] = -src
->f
[2];
1468 dst
->f
[3] = -src
->f
[3];
1473 union tgsi_exec_channel
*dst
,
1474 const union tgsi_exec_channel
*src0
,
1475 const union tgsi_exec_channel
*src1
)
1478 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1479 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1480 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1481 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1483 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1484 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1485 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1486 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1491 micro_ldexp(union tgsi_exec_channel
*dst
,
1492 const union tgsi_exec_channel
*src0
,
1493 const union tgsi_exec_channel
*src1
)
1495 dst
->f
[0] = ldexpf(src0
->f
[0], src1
->i
[0]);
1496 dst
->f
[1] = ldexpf(src0
->f
[1], src1
->i
[1]);
1497 dst
->f
[2] = ldexpf(src0
->f
[2], src1
->i
[2]);
1498 dst
->f
[3] = ldexpf(src0
->f
[3], src1
->i
[3]);
1502 micro_sub(union tgsi_exec_channel
*dst
,
1503 const union tgsi_exec_channel
*src0
,
1504 const union tgsi_exec_channel
*src1
)
1506 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1507 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1508 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1509 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1513 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1516 const union tgsi_exec_channel
*index
,
1517 const union tgsi_exec_channel
*index2D
,
1518 union tgsi_exec_channel
*chan
)
1522 assert(swizzle
< 4);
1525 case TGSI_FILE_CONSTANT
:
1526 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1527 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1528 assert(mach
->Consts
[index2D
->i
[i
]]);
1530 if (index
->i
[i
] < 0) {
1533 /* NOTE: copying the const value as a uint instead of float */
1534 const uint constbuf
= index2D
->i
[i
];
1535 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1536 const int pos
= index
->i
[i
] * 4 + swizzle
;
1537 /* const buffer bounds check */
1538 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1540 /* Debug: print warning */
1541 static int count
= 0;
1543 debug_printf("TGSI Exec: const buffer index %d"
1544 " out of bounds\n", pos
);
1549 chan
->u
[i
] = buf
[pos
];
1554 case TGSI_FILE_INPUT
:
1555 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1557 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1558 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1559 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1560 index2D->i[i], index->i[i]);
1562 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1564 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1565 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1569 case TGSI_FILE_SYSTEM_VALUE
:
1570 /* XXX no swizzling at this point. Will be needed if we put
1571 * gl_FragCoord, for example, in a sys value register.
1573 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1574 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1578 case TGSI_FILE_TEMPORARY
:
1579 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1580 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1581 assert(index2D
->i
[i
] == 0);
1583 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1587 case TGSI_FILE_IMMEDIATE
:
1588 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1589 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1590 assert(index2D
->i
[i
] == 0);
1592 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1596 case TGSI_FILE_ADDRESS
:
1597 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1598 assert(index
->i
[i
] >= 0);
1599 assert(index2D
->i
[i
] == 0);
1601 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1605 case TGSI_FILE_OUTPUT
:
1606 /* vertex/fragment output vars can be read too */
1607 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1608 assert(index
->i
[i
] >= 0);
1609 assert(index2D
->i
[i
] == 0);
1611 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1617 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1624 get_index_registers(const struct tgsi_exec_machine
*mach
,
1625 const struct tgsi_full_src_register
*reg
,
1626 union tgsi_exec_channel
*index
,
1627 union tgsi_exec_channel
*index2D
)
1631 /* We start with a direct index into a register file.
1635 * file = Register.File
1636 * [1] = Register.Index
1641 index
->i
[3] = reg
->Register
.Index
;
1643 /* There is an extra source register that indirectly subscripts
1644 * a register file. The direct index now becomes an offset
1645 * that is being added to the indirect register.
1649 * ind = Indirect.File
1650 * [2] = Indirect.Index
1651 * .x = Indirect.SwizzleX
1653 if (reg
->Register
.Indirect
) {
1654 union tgsi_exec_channel index2
;
1655 union tgsi_exec_channel indir_index
;
1656 const uint execmask
= mach
->ExecMask
;
1659 /* which address register (always zero now) */
1663 index2
.i
[3] = reg
->Indirect
.Index
;
1664 /* get current value of address register[swizzle] */
1665 swizzle
= reg
->Indirect
.Swizzle
;
1666 fetch_src_file_channel(mach
,
1673 /* add value of address register to the offset */
1674 index
->i
[0] += indir_index
.i
[0];
1675 index
->i
[1] += indir_index
.i
[1];
1676 index
->i
[2] += indir_index
.i
[2];
1677 index
->i
[3] += indir_index
.i
[3];
1679 /* for disabled execution channels, zero-out the index to
1680 * avoid using a potential garbage value.
1682 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1683 if ((execmask
& (1 << i
)) == 0)
1688 /* There is an extra source register that is a second
1689 * subscript to a register file. Effectively it means that
1690 * the register file is actually a 2D array of registers.
1694 * [3] = Dimension.Index
1696 if (reg
->Register
.Dimension
) {
1700 index2D
->i
[3] = reg
->Dimension
.Index
;
1702 /* Again, the second subscript index can be addressed indirectly
1703 * identically to the first one.
1704 * Nothing stops us from indirectly addressing the indirect register,
1705 * but there is no need for that, so we won't exercise it.
1707 * file[ind[4].y+3][1],
1709 * ind = DimIndirect.File
1710 * [4] = DimIndirect.Index
1711 * .y = DimIndirect.SwizzleX
1713 if (reg
->Dimension
.Indirect
) {
1714 union tgsi_exec_channel index2
;
1715 union tgsi_exec_channel indir_index
;
1716 const uint execmask
= mach
->ExecMask
;
1722 index2
.i
[3] = reg
->DimIndirect
.Index
;
1724 swizzle
= reg
->DimIndirect
.Swizzle
;
1725 fetch_src_file_channel(mach
,
1726 reg
->DimIndirect
.File
,
1732 index2D
->i
[0] += indir_index
.i
[0];
1733 index2D
->i
[1] += indir_index
.i
[1];
1734 index2D
->i
[2] += indir_index
.i
[2];
1735 index2D
->i
[3] += indir_index
.i
[3];
1737 /* for disabled execution channels, zero-out the index to
1738 * avoid using a potential garbage value.
1740 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1741 if ((execmask
& (1 << i
)) == 0) {
1747 /* If by any chance there was a need for a 3D array of register
1748 * files, we would have to check whether Dimension is followed
1749 * by a dimension register and continue the saga.
1761 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1762 union tgsi_exec_channel
*chan
,
1763 const struct tgsi_full_src_register
*reg
,
1764 const uint chan_index
)
1766 union tgsi_exec_channel index
;
1767 union tgsi_exec_channel index2D
;
1770 get_index_registers(mach
, reg
, &index
, &index2D
);
1773 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1774 fetch_src_file_channel(mach
,
1783 fetch_source(const struct tgsi_exec_machine
*mach
,
1784 union tgsi_exec_channel
*chan
,
1785 const struct tgsi_full_src_register
*reg
,
1786 const uint chan_index
,
1787 enum tgsi_exec_datatype src_datatype
)
1789 fetch_source_d(mach
, chan
, reg
, chan_index
);
1791 if (reg
->Register
.Absolute
) {
1792 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1793 micro_abs(chan
, chan
);
1795 micro_iabs(chan
, chan
);
1799 if (reg
->Register
.Negate
) {
1800 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1801 micro_neg(chan
, chan
);
1803 micro_ineg(chan
, chan
);
1808 static union tgsi_exec_channel
*
1809 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1810 const union tgsi_exec_channel
*chan
,
1811 const struct tgsi_full_dst_register
*reg
,
1813 enum tgsi_exec_datatype dst_datatype
)
1815 static union tgsi_exec_channel null
;
1816 union tgsi_exec_channel
*dst
;
1817 union tgsi_exec_channel index2D
;
1818 int offset
= 0; /* indirection offset */
1822 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1823 check_inf_or_nan(chan
);
1826 /* There is an extra source register that indirectly subscripts
1827 * a register file. The direct index now becomes an offset
1828 * that is being added to the indirect register.
1832 * ind = Indirect.File
1833 * [2] = Indirect.Index
1834 * .x = Indirect.SwizzleX
1836 if (reg
->Register
.Indirect
) {
1837 union tgsi_exec_channel index
;
1838 union tgsi_exec_channel indir_index
;
1841 /* which address register (always zero for now) */
1845 index
.i
[3] = reg
->Indirect
.Index
;
1847 /* get current value of address register[swizzle] */
1848 swizzle
= reg
->Indirect
.Swizzle
;
1850 /* fetch values from the address/indirection register */
1851 fetch_src_file_channel(mach
,
1858 /* save indirection offset */
1859 offset
= indir_index
.i
[0];
1862 /* There is an extra source register that is a second
1863 * subscript to a register file. Effectively it means that
1864 * the register file is actually a 2D array of registers.
1868 * [3] = Dimension.Index
1870 if (reg
->Register
.Dimension
) {
1874 index2D
.i
[3] = reg
->Dimension
.Index
;
1876 /* Again, the second subscript index can be addressed indirectly
1877 * identically to the first one.
1878 * Nothing stops us from indirectly addressing the indirect register,
1879 * but there is no need for that, so we won't exercise it.
1881 * file[ind[4].y+3][1],
1883 * ind = DimIndirect.File
1884 * [4] = DimIndirect.Index
1885 * .y = DimIndirect.SwizzleX
1887 if (reg
->Dimension
.Indirect
) {
1888 union tgsi_exec_channel index2
;
1889 union tgsi_exec_channel indir_index
;
1890 const uint execmask
= mach
->ExecMask
;
1897 index2
.i
[3] = reg
->DimIndirect
.Index
;
1899 swizzle
= reg
->DimIndirect
.Swizzle
;
1900 fetch_src_file_channel(mach
,
1901 reg
->DimIndirect
.File
,
1907 index2D
.i
[0] += indir_index
.i
[0];
1908 index2D
.i
[1] += indir_index
.i
[1];
1909 index2D
.i
[2] += indir_index
.i
[2];
1910 index2D
.i
[3] += indir_index
.i
[3];
1912 /* for disabled execution channels, zero-out the index to
1913 * avoid using a potential garbage value.
1915 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1916 if ((execmask
& (1 << i
)) == 0) {
1922 /* If by any chance there was a need for a 3D array of register
1923 * files, we would have to check whether Dimension is followed
1924 * by a dimension register and continue the saga.
1933 switch (reg
->Register
.File
) {
1934 case TGSI_FILE_NULL
:
1938 case TGSI_FILE_OUTPUT
:
1939 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1940 + reg
->Register
.Index
;
1941 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1943 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1944 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1945 reg
->Register
.Index
);
1946 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1947 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1948 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1949 if (execmask
& (1 << i
))
1950 debug_printf("%f, ", chan
->f
[i
]);
1951 debug_printf(")\n");
1956 case TGSI_FILE_TEMPORARY
:
1957 index
= reg
->Register
.Index
;
1958 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1959 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1962 case TGSI_FILE_ADDRESS
:
1963 index
= reg
->Register
.Index
;
1964 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1976 store_dest_double(struct tgsi_exec_machine
*mach
,
1977 const union tgsi_exec_channel
*chan
,
1978 const struct tgsi_full_dst_register
*reg
,
1980 enum tgsi_exec_datatype dst_datatype
)
1982 union tgsi_exec_channel
*dst
;
1983 const uint execmask
= mach
->ExecMask
;
1986 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
1991 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1992 if (execmask
& (1 << i
))
1993 dst
->i
[i
] = chan
->i
[i
];
1997 store_dest(struct tgsi_exec_machine
*mach
,
1998 const union tgsi_exec_channel
*chan
,
1999 const struct tgsi_full_dst_register
*reg
,
2000 const struct tgsi_full_instruction
*inst
,
2002 enum tgsi_exec_datatype dst_datatype
)
2004 union tgsi_exec_channel
*dst
;
2005 const uint execmask
= mach
->ExecMask
;
2008 dst
= store_dest_dstret(mach
, chan
, reg
, chan_index
, dst_datatype
);
2012 if (!inst
->Instruction
.Saturate
) {
2013 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2014 if (execmask
& (1 << i
))
2015 dst
->i
[i
] = chan
->i
[i
];
2018 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2019 if (execmask
& (1 << i
)) {
2020 if (chan
->f
[i
] < 0.0f
)
2022 else if (chan
->f
[i
] > 1.0f
)
2025 dst
->i
[i
] = chan
->i
[i
];
2030 #define FETCH(VAL,INDEX,CHAN)\
2031 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
2033 #define IFETCH(VAL,INDEX,CHAN)\
2034 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
2038 * Execute ARB-style KIL which is predicated by a src register.
2039 * Kill fragment if any of the four values is less than zero.
2042 exec_kill_if(struct tgsi_exec_machine
*mach
,
2043 const struct tgsi_full_instruction
*inst
)
2047 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2048 union tgsi_exec_channel r
[1];
2050 /* This mask stores component bits that were already tested. */
2053 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2058 /* unswizzle channel */
2059 swizzle
= tgsi_util_get_full_src_register_swizzle (
2063 /* check if the component has not been already tested */
2064 if (uniquemask
& (1 << swizzle
))
2066 uniquemask
|= 1 << swizzle
;
2068 FETCH(&r
[0], 0, chan_index
);
2069 for (i
= 0; i
< 4; i
++)
2070 if (r
[0].f
[i
] < 0.0f
)
2074 /* restrict to fragments currently executing */
2075 kilmask
&= mach
->ExecMask
;
2077 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2081 * Unconditional fragment kill/discard.
2084 exec_kill(struct tgsi_exec_machine
*mach
)
2086 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2088 /* kill fragment for all fragments currently executing */
2089 kilmask
= mach
->ExecMask
;
2090 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2094 emit_vertex(struct tgsi_exec_machine
*mach
,
2095 const struct tgsi_full_instruction
*inst
)
2097 union tgsi_exec_channel r
[1];
2099 unsigned *prim_count
;
2100 /* FIXME: check for exec mask correctly
2102 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2103 if ((mach->ExecMask & (1 << i)))
2105 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2106 stream_id
= r
[0].u
[0];
2107 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2108 if (mach
->ExecMask
) {
2109 if (mach
->Primitives
[stream_id
][*prim_count
] >= mach
->MaxOutputVertices
)
2112 if (mach
->Primitives
[stream_id
][*prim_count
] == 0)
2113 mach
->PrimitiveOffsets
[stream_id
][*prim_count
] = mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0];
2114 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2115 mach
->Primitives
[stream_id
][*prim_count
]++;
2120 emit_primitive(struct tgsi_exec_machine
*mach
,
2121 const struct tgsi_full_instruction
*inst
)
2123 unsigned *prim_count
;
2124 union tgsi_exec_channel r
[1];
2125 unsigned stream_id
= 0;
2126 /* FIXME: check for exec mask correctly
2128 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2129 if ((mach->ExecMask & (1 << i)))
2132 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2133 stream_id
= r
[0].u
[0];
2135 prim_count
= &mach
->Temps
[temp_prim_idxs
[stream_id
].idx
].xyzw
[temp_prim_idxs
[stream_id
].chan
].u
[0];
2136 if (mach
->ExecMask
) {
2138 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2139 mach
->Primitives
[stream_id
][*prim_count
] = 0;
2144 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2146 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2148 mach
->Primitives
[0][mach
->Temps
[temp_prim_idxs
[0].idx
].xyzw
[temp_prim_idxs
[0].chan
].u
[0]];
2149 if (emitted_verts
) {
2150 emit_primitive(mach
, NULL
);
2157 * Fetch four texture samples using STR texture coordinates.
2160 fetch_texel( struct tgsi_sampler
*sampler
,
2161 const unsigned sview_idx
,
2162 const unsigned sampler_idx
,
2163 const union tgsi_exec_channel
*s
,
2164 const union tgsi_exec_channel
*t
,
2165 const union tgsi_exec_channel
*p
,
2166 const union tgsi_exec_channel
*c0
,
2167 const union tgsi_exec_channel
*c1
,
2168 float derivs
[3][2][TGSI_QUAD_SIZE
],
2169 const int8_t offset
[3],
2170 enum tgsi_sampler_control control
,
2171 union tgsi_exec_channel
*r
,
2172 union tgsi_exec_channel
*g
,
2173 union tgsi_exec_channel
*b
,
2174 union tgsi_exec_channel
*a
)
2177 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2179 /* FIXME: handle explicit derivs, offsets */
2180 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2181 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2183 for (j
= 0; j
< 4; j
++) {
2184 r
->f
[j
] = rgba
[0][j
];
2185 g
->f
[j
] = rgba
[1][j
];
2186 b
->f
[j
] = rgba
[2][j
];
2187 a
->f
[j
] = rgba
[3][j
];
2192 #define TEX_MODIFIER_NONE 0
2193 #define TEX_MODIFIER_PROJECTED 1
2194 #define TEX_MODIFIER_LOD_BIAS 2
2195 #define TEX_MODIFIER_EXPLICIT_LOD 3
2196 #define TEX_MODIFIER_LEVEL_ZERO 4
2197 #define TEX_MODIFIER_GATHER 5
2200 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2203 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2204 const struct tgsi_full_instruction
*inst
,
2207 if (inst
->Texture
.NumOffsets
== 1) {
2208 union tgsi_exec_channel index
;
2209 union tgsi_exec_channel offset
[3];
2210 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2211 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2212 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2213 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2214 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2215 fetch_src_file_channel(mach
, inst
->TexOffsets
[0].File
,
2216 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2217 offsets
[0] = offset
[0].i
[0];
2218 offsets
[1] = offset
[1].i
[0];
2219 offsets
[2] = offset
[2].i
[0];
2221 assert(inst
->Texture
.NumOffsets
== 0);
2222 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2228 * Fetch dx and dy values for one channel (s, t or r).
2229 * Put dx values into one float array, dy values into another.
2232 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2233 const struct tgsi_full_instruction
*inst
,
2236 float derivs
[2][TGSI_QUAD_SIZE
])
2238 union tgsi_exec_channel d
;
2239 FETCH(&d
, regdsrcx
, chan
);
2240 derivs
[0][0] = d
.f
[0];
2241 derivs
[0][1] = d
.f
[1];
2242 derivs
[0][2] = d
.f
[2];
2243 derivs
[0][3] = d
.f
[3];
2244 FETCH(&d
, regdsrcx
+ 1, chan
);
2245 derivs
[1][0] = d
.f
[0];
2246 derivs
[1][1] = d
.f
[1];
2247 derivs
[1][2] = d
.f
[2];
2248 derivs
[1][3] = d
.f
[3];
2252 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2253 const struct tgsi_full_instruction
*inst
,
2258 if (inst
->Src
[sampler
].Register
.Indirect
) {
2259 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2260 union tgsi_exec_channel indir_index
, index2
;
2261 const uint execmask
= mach
->ExecMask
;
2265 index2
.i
[3] = reg
->Indirect
.Index
;
2267 fetch_src_file_channel(mach
,
2269 reg
->Indirect
.Swizzle
,
2273 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2274 if (execmask
& (1 << i
)) {
2275 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2281 unit
= inst
->Src
[sampler
].Register
.Index
;
2287 * execute a texture instruction.
2289 * modifier is used to control the channel routing for the
2290 * instruction variants like proj, lod, and texture with lod bias.
2291 * sampler indicates which src register the sampler is contained in.
2294 exec_tex(struct tgsi_exec_machine
*mach
,
2295 const struct tgsi_full_instruction
*inst
,
2296 uint modifier
, uint sampler
)
2298 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2299 union tgsi_exec_channel r
[5];
2300 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2304 int dim
, shadow_ref
, i
;
2306 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2307 /* always fetch all 3 offsets, overkill but keeps code simple */
2308 fetch_texel_offsets(mach
, inst
, offsets
);
2310 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2311 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2313 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2314 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2317 if (shadow_ref
>= 0)
2318 assert(shadow_ref
>= dim
&& shadow_ref
< (int)ARRAY_SIZE(args
));
2320 /* fetch modifier to the last argument */
2321 if (modifier
!= TEX_MODIFIER_NONE
) {
2322 const int last
= ARRAY_SIZE(args
) - 1;
2324 /* fetch modifier from src0.w or src1.x */
2326 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2327 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2330 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2333 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2334 args
[last
] = &r
[last
];
2338 args
[last
] = &ZeroVec
;
2341 /* point unused arguments to zero vector */
2342 for (i
= dim
; i
< last
; i
++)
2345 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2346 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2347 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2348 control
= TGSI_SAMPLER_LOD_BIAS
;
2349 else if (modifier
== TEX_MODIFIER_GATHER
)
2350 control
= TGSI_SAMPLER_GATHER
;
2353 for (i
= dim
; i
< (int)ARRAY_SIZE(args
); i
++)
2357 /* fetch coordinates */
2358 for (i
= 0; i
< dim
; i
++) {
2359 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2362 micro_div(&r
[i
], &r
[i
], proj
);
2367 /* fetch reference value */
2368 if (shadow_ref
>= 0) {
2369 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2372 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2374 args
[shadow_ref
] = &r
[shadow_ref
];
2377 fetch_texel(mach
->Sampler
, unit
, unit
,
2378 args
[0], args
[1], args
[2], args
[3], args
[4],
2379 NULL
, offsets
, control
,
2380 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2383 debug_printf("fetch r: %g %g %g %g\n",
2384 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2385 debug_printf("fetch g: %g %g %g %g\n",
2386 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2387 debug_printf("fetch b: %g %g %g %g\n",
2388 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2389 debug_printf("fetch a: %g %g %g %g\n",
2390 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2393 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2394 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2395 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2401 exec_lodq(struct tgsi_exec_machine
*mach
,
2402 const struct tgsi_full_instruction
*inst
)
2404 uint resource_unit
, sampler_unit
;
2407 union tgsi_exec_channel coords
[4];
2408 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2409 union tgsi_exec_channel r
[2];
2411 resource_unit
= fetch_sampler_unit(mach
, inst
, 1);
2412 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2413 uint target
= mach
->SamplerViews
[resource_unit
].Resource
;
2414 dim
= tgsi_util_get_texture_coord_dim(target
);
2415 sampler_unit
= fetch_sampler_unit(mach
, inst
, 2);
2417 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2418 sampler_unit
= resource_unit
;
2420 assert(dim
<= ARRAY_SIZE(coords
));
2421 /* fetch coordinates */
2422 for (i
= 0; i
< dim
; i
++) {
2423 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2424 args
[i
] = &coords
[i
];
2426 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2429 mach
->Sampler
->query_lod(mach
->Sampler
, resource_unit
, sampler_unit
,
2434 TGSI_SAMPLER_LOD_NONE
,
2438 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2439 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2440 TGSI_EXEC_DATA_FLOAT
);
2442 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2443 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2444 TGSI_EXEC_DATA_FLOAT
);
2446 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LOD
) {
2447 unsigned char swizzles
[4];
2449 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2450 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2451 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2452 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2454 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2455 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2456 if (swizzles
[chan
] >= 2) {
2457 store_dest(mach
, &ZeroVec
,
2458 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2460 store_dest(mach
, &r
[swizzles
[chan
]],
2461 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2466 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2467 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2468 TGSI_EXEC_DATA_FLOAT
);
2470 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2471 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2472 TGSI_EXEC_DATA_FLOAT
);
2478 exec_txd(struct tgsi_exec_machine
*mach
,
2479 const struct tgsi_full_instruction
*inst
)
2481 union tgsi_exec_channel r
[4];
2482 float derivs
[3][2][TGSI_QUAD_SIZE
];
2487 unit
= fetch_sampler_unit(mach
, inst
, 3);
2488 /* always fetch all 3 offsets, overkill but keeps code simple */
2489 fetch_texel_offsets(mach
, inst
, offsets
);
2491 switch (inst
->Texture
.Texture
) {
2492 case TGSI_TEXTURE_1D
:
2493 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2495 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2497 fetch_texel(mach
->Sampler
, unit
, unit
,
2498 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2499 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2500 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2503 case TGSI_TEXTURE_SHADOW1D
:
2504 case TGSI_TEXTURE_1D_ARRAY
:
2505 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2506 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2507 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2508 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2509 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2511 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2513 fetch_texel(mach
->Sampler
, unit
, unit
,
2514 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2515 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2516 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2519 case TGSI_TEXTURE_2D
:
2520 case TGSI_TEXTURE_RECT
:
2521 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2522 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2524 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2525 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2527 fetch_texel(mach
->Sampler
, unit
, unit
,
2528 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2529 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2530 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2534 case TGSI_TEXTURE_SHADOW2D
:
2535 case TGSI_TEXTURE_SHADOWRECT
:
2536 case TGSI_TEXTURE_2D_ARRAY
:
2537 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2538 /* only SHADOW2D_ARRAY actually needs W */
2539 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2540 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2541 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2542 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2544 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2545 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2547 fetch_texel(mach
->Sampler
, unit
, unit
,
2548 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2549 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2550 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2553 case TGSI_TEXTURE_3D
:
2554 case TGSI_TEXTURE_CUBE
:
2555 case TGSI_TEXTURE_CUBE_ARRAY
:
2556 case TGSI_TEXTURE_SHADOWCUBE
:
2557 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2558 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2559 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2560 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2561 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2563 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2564 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2565 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2567 fetch_texel(mach
->Sampler
, unit
, unit
,
2568 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2569 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2570 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2577 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2578 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2579 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2586 exec_txf(struct tgsi_exec_machine
*mach
,
2587 const struct tgsi_full_instruction
*inst
)
2589 union tgsi_exec_channel r
[4];
2592 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2597 unit
= fetch_sampler_unit(mach
, inst
, 1);
2598 /* always fetch all 3 offsets, overkill but keeps code simple */
2599 fetch_texel_offsets(mach
, inst
, offsets
);
2601 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2603 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2604 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2605 target
= mach
->SamplerViews
[unit
].Resource
;
2608 target
= inst
->Texture
.Texture
;
2611 case TGSI_TEXTURE_3D
:
2612 case TGSI_TEXTURE_2D_ARRAY
:
2613 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2614 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2615 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2617 case TGSI_TEXTURE_2D
:
2618 case TGSI_TEXTURE_RECT
:
2619 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2620 case TGSI_TEXTURE_SHADOW2D
:
2621 case TGSI_TEXTURE_SHADOWRECT
:
2622 case TGSI_TEXTURE_1D_ARRAY
:
2623 case TGSI_TEXTURE_2D_MSAA
:
2624 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2626 case TGSI_TEXTURE_BUFFER
:
2627 case TGSI_TEXTURE_1D
:
2628 case TGSI_TEXTURE_SHADOW1D
:
2629 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2636 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2639 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2640 r
[0].f
[j
] = rgba
[0][j
];
2641 r
[1].f
[j
] = rgba
[1][j
];
2642 r
[2].f
[j
] = rgba
[2][j
];
2643 r
[3].f
[j
] = rgba
[3][j
];
2646 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2647 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2648 unsigned char swizzles
[4];
2649 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2650 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2651 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2652 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2654 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2655 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2656 store_dest(mach
, &r
[swizzles
[chan
]],
2657 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2662 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2663 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2664 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2671 exec_txq(struct tgsi_exec_machine
*mach
,
2672 const struct tgsi_full_instruction
*inst
)
2675 union tgsi_exec_channel r
[4], src
;
2680 unit
= fetch_sampler_unit(mach
, inst
, 1);
2682 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2684 /* XXX: This interface can't return per-pixel values */
2685 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2687 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2688 for (j
= 0; j
< 4; j
++) {
2689 r
[j
].i
[i
] = result
[j
];
2693 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2694 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2695 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2696 TGSI_EXEC_DATA_INT
);
2702 exec_sample(struct tgsi_exec_machine
*mach
,
2703 const struct tgsi_full_instruction
*inst
,
2704 uint modifier
, boolean compare
)
2706 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2707 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2708 union tgsi_exec_channel r
[5], c1
;
2709 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2710 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2712 unsigned char swizzles
[4];
2715 /* always fetch all 3 offsets, overkill but keeps code simple */
2716 fetch_texel_offsets(mach
, inst
, offsets
);
2718 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2720 if (modifier
!= TEX_MODIFIER_NONE
) {
2721 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2722 FETCH(&c1
, 3, TGSI_CHAN_X
);
2724 control
= TGSI_SAMPLER_LOD_BIAS
;
2726 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2727 FETCH(&c1
, 3, TGSI_CHAN_X
);
2729 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2731 else if (modifier
== TEX_MODIFIER_GATHER
) {
2732 control
= TGSI_SAMPLER_GATHER
;
2735 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2736 control
= TGSI_SAMPLER_LOD_ZERO
;
2740 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2742 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2743 case TGSI_TEXTURE_1D
:
2745 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2746 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2747 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2748 NULL
, offsets
, control
,
2749 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2752 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2753 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2754 NULL
, offsets
, control
,
2755 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2759 case TGSI_TEXTURE_1D_ARRAY
:
2760 case TGSI_TEXTURE_2D
:
2761 case TGSI_TEXTURE_RECT
:
2762 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2764 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2765 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2766 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2767 NULL
, offsets
, control
,
2768 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2771 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2772 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2773 NULL
, offsets
, control
,
2774 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2778 case TGSI_TEXTURE_2D_ARRAY
:
2779 case TGSI_TEXTURE_3D
:
2780 case TGSI_TEXTURE_CUBE
:
2781 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2782 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2784 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2785 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2786 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2787 NULL
, offsets
, control
,
2788 &r
[0], &r
[1], &r
[2], &r
[3]);
2791 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2792 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2793 NULL
, offsets
, control
,
2794 &r
[0], &r
[1], &r
[2], &r
[3]);
2798 case TGSI_TEXTURE_CUBE_ARRAY
:
2799 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2800 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2801 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2803 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2804 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2805 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2806 NULL
, offsets
, control
,
2807 &r
[0], &r
[1], &r
[2], &r
[3]);
2810 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2811 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2812 NULL
, offsets
, control
,
2813 &r
[0], &r
[1], &r
[2], &r
[3]);
2822 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2823 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2824 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2825 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2827 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2828 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2829 store_dest(mach
, &r
[swizzles
[chan
]],
2830 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2836 exec_sample_d(struct tgsi_exec_machine
*mach
,
2837 const struct tgsi_full_instruction
*inst
)
2839 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2840 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2841 union tgsi_exec_channel r
[4];
2842 float derivs
[3][2][TGSI_QUAD_SIZE
];
2844 unsigned char swizzles
[4];
2847 /* always fetch all 3 offsets, overkill but keeps code simple */
2848 fetch_texel_offsets(mach
, inst
, offsets
);
2850 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2852 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2853 case TGSI_TEXTURE_1D
:
2854 case TGSI_TEXTURE_1D_ARRAY
:
2855 /* only 1D array actually needs Y */
2856 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2858 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2860 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2861 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2862 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2863 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2866 case TGSI_TEXTURE_2D
:
2867 case TGSI_TEXTURE_RECT
:
2868 case TGSI_TEXTURE_2D_ARRAY
:
2869 /* only 2D array actually needs Z */
2870 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2871 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2873 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2874 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2876 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2877 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2878 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2879 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2882 case TGSI_TEXTURE_3D
:
2883 case TGSI_TEXTURE_CUBE
:
2884 case TGSI_TEXTURE_CUBE_ARRAY
:
2885 /* only cube array actually needs W */
2886 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2887 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2888 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2890 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2891 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2892 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2894 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2895 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2896 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2897 &r
[0], &r
[1], &r
[2], &r
[3]);
2904 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2905 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2906 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2907 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2909 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2910 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2911 store_dest(mach
, &r
[swizzles
[chan
]],
2912 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2919 * Evaluate a constant-valued coefficient at the position of the
2924 struct tgsi_exec_machine
*mach
,
2930 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2931 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2936 interp_constant_offset(
2937 UNUSED
const struct tgsi_exec_machine
*mach
,
2938 UNUSED
unsigned attrib
,
2939 UNUSED
unsigned chan
,
2942 UNUSED
union tgsi_exec_channel
*out_chan
)
2947 * Evaluate a linear-valued coefficient at the position of the
2951 interp_linear_offset(
2952 const struct tgsi_exec_machine
*mach
,
2957 union tgsi_exec_channel
*out_chan
)
2959 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2960 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2961 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
2962 out_chan
->f
[0] += delta
;
2963 out_chan
->f
[1] += delta
;
2964 out_chan
->f
[2] += delta
;
2965 out_chan
->f
[3] += delta
;
2969 eval_linear_coef(struct tgsi_exec_machine
*mach
,
2973 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2974 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2975 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2976 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2977 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2979 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2980 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2981 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2982 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2986 * Evaluate a perspective-valued coefficient at the position of the
2991 interp_perspective_offset(
2992 const struct tgsi_exec_machine
*mach
,
2997 union tgsi_exec_channel
*out_chan
)
2999 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
3000 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
3001 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
3002 const float delta
= ofs_x
* dadx
+ ofs_y
* dady
;
3003 out_chan
->f
[0] += delta
/ w
[0];
3004 out_chan
->f
[1] += delta
/ w
[1];
3005 out_chan
->f
[2] += delta
/ w
[2];
3006 out_chan
->f
[3] += delta
/ w
[3];
3010 eval_perspective_coef(
3011 struct tgsi_exec_machine
*mach
,
3015 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
3016 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
3017 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
3018 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
3019 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
3020 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
3021 /* divide by W here */
3022 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
3023 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
3024 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
3025 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
3029 typedef void (* eval_coef_func
)(
3030 struct tgsi_exec_machine
*mach
,
3035 exec_declaration(struct tgsi_exec_machine
*mach
,
3036 const struct tgsi_full_declaration
*decl
)
3038 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
3039 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
3043 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
3044 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
3045 uint first
, last
, mask
;
3047 first
= decl
->Range
.First
;
3048 last
= decl
->Range
.Last
;
3049 mask
= decl
->Declaration
.UsageMask
;
3051 /* XXX we could remove this special-case code since
3052 * mach->InterpCoefs[first].a0 should already have the
3053 * front/back-face value. But we should first update the
3054 * ureg code to emit the right UsageMask value (WRITEMASK_X).
3055 * Then, we could remove the tgsi_exec_machine::Face field.
3057 /* XXX make FACE a system value */
3058 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
3061 assert(decl
->Semantic
.Index
== 0);
3062 assert(first
== last
);
3064 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3065 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
3068 eval_coef_func eval
;
3069 apply_sample_offset_func interp
;
3072 switch (decl
->Interp
.Interpolate
) {
3073 case TGSI_INTERPOLATE_CONSTANT
:
3074 eval
= eval_constant_coef
;
3075 interp
= interp_constant_offset
;
3078 case TGSI_INTERPOLATE_LINEAR
:
3079 eval
= eval_linear_coef
;
3080 interp
= interp_linear_offset
;
3083 case TGSI_INTERPOLATE_PERSPECTIVE
:
3084 eval
= eval_perspective_coef
;
3085 interp
= interp_perspective_offset
;
3088 case TGSI_INTERPOLATE_COLOR
:
3089 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
3097 for (i
= first
; i
<= last
; i
++)
3098 mach
->InputSampleOffsetApply
[i
] = interp
;
3100 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3101 if (mask
& (1 << j
)) {
3102 for (i
= first
; i
<= last
; i
++) {
3109 if (DEBUG_EXECUTION
) {
3111 for (i
= first
; i
<= last
; ++i
) {
3112 debug_printf("IN[%2u] = ", i
);
3113 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3117 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3118 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3119 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3120 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3121 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3130 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3131 const union tgsi_exec_channel
*src
);
3134 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3135 const struct tgsi_full_instruction
*inst
,
3137 enum tgsi_exec_datatype dst_datatype
,
3138 enum tgsi_exec_datatype src_datatype
)
3141 union tgsi_exec_channel src
;
3142 union tgsi_exec_channel dst
;
3144 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3146 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3147 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3148 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3154 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3155 const struct tgsi_full_instruction
*inst
,
3157 enum tgsi_exec_datatype dst_datatype
,
3158 enum tgsi_exec_datatype src_datatype
)
3161 struct tgsi_exec_vector dst
;
3163 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3164 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3165 union tgsi_exec_channel src
;
3167 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3168 op(&dst
.xyzw
[chan
], &src
);
3171 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3172 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3173 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3178 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3179 const union tgsi_exec_channel
*src0
,
3180 const union tgsi_exec_channel
*src1
);
3183 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3184 const struct tgsi_full_instruction
*inst
,
3186 enum tgsi_exec_datatype dst_datatype
,
3187 enum tgsi_exec_datatype src_datatype
)
3190 union tgsi_exec_channel src
[2];
3191 union tgsi_exec_channel dst
;
3193 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3194 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3195 op(&dst
, &src
[0], &src
[1]);
3196 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3197 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3198 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3204 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3205 const struct tgsi_full_instruction
*inst
,
3207 enum tgsi_exec_datatype dst_datatype
,
3208 enum tgsi_exec_datatype src_datatype
)
3211 struct tgsi_exec_vector dst
;
3213 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3214 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3215 union tgsi_exec_channel src
[2];
3217 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3218 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3219 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3222 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3223 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3224 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3229 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3230 const union tgsi_exec_channel
*src0
,
3231 const union tgsi_exec_channel
*src1
,
3232 const union tgsi_exec_channel
*src2
);
3235 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3236 const struct tgsi_full_instruction
*inst
,
3237 micro_trinary_op op
,
3238 enum tgsi_exec_datatype dst_datatype
,
3239 enum tgsi_exec_datatype src_datatype
)
3242 struct tgsi_exec_vector dst
;
3244 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3245 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3246 union tgsi_exec_channel src
[3];
3248 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3249 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3250 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3251 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3254 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3255 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3256 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3261 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3262 const union tgsi_exec_channel
*src0
,
3263 const union tgsi_exec_channel
*src1
,
3264 const union tgsi_exec_channel
*src2
,
3265 const union tgsi_exec_channel
*src3
);
3268 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3269 const struct tgsi_full_instruction
*inst
,
3270 micro_quaternary_op op
,
3271 enum tgsi_exec_datatype dst_datatype
,
3272 enum tgsi_exec_datatype src_datatype
)
3275 struct tgsi_exec_vector dst
;
3277 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3278 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3279 union tgsi_exec_channel src
[4];
3281 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3282 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3283 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3284 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3285 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3288 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3289 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3290 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3296 exec_dp3(struct tgsi_exec_machine
*mach
,
3297 const struct tgsi_full_instruction
*inst
)
3300 union tgsi_exec_channel arg
[3];
3302 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3303 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3304 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3306 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3307 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3308 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3309 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3312 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3313 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3314 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3320 exec_dp4(struct tgsi_exec_machine
*mach
,
3321 const struct tgsi_full_instruction
*inst
)
3324 union tgsi_exec_channel arg
[3];
3326 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3327 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3328 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3330 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3331 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3332 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3333 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3336 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3337 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3338 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3344 exec_dp2(struct tgsi_exec_machine
*mach
,
3345 const struct tgsi_full_instruction
*inst
)
3348 union tgsi_exec_channel arg
[3];
3350 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3351 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3352 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3354 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3355 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3356 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3358 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3359 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3360 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3366 exec_pk2h(struct tgsi_exec_machine
*mach
,
3367 const struct tgsi_full_instruction
*inst
)
3370 union tgsi_exec_channel arg
[2], dst
;
3372 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3373 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3374 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3375 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3376 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3378 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3379 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3380 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3386 exec_up2h(struct tgsi_exec_machine
*mach
,
3387 const struct tgsi_full_instruction
*inst
)
3390 union tgsi_exec_channel arg
, dst
[2];
3392 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3393 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3394 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3395 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3397 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3398 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3399 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3405 micro_ucmp(union tgsi_exec_channel
*dst
,
3406 const union tgsi_exec_channel
*src0
,
3407 const union tgsi_exec_channel
*src1
,
3408 const union tgsi_exec_channel
*src2
)
3410 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3411 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3412 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3413 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3417 exec_ucmp(struct tgsi_exec_machine
*mach
,
3418 const struct tgsi_full_instruction
*inst
)
3421 struct tgsi_exec_vector dst
;
3423 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3424 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3425 union tgsi_exec_channel src
[3];
3427 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3428 TGSI_EXEC_DATA_UINT
);
3429 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3430 TGSI_EXEC_DATA_FLOAT
);
3431 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3432 TGSI_EXEC_DATA_FLOAT
);
3433 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3436 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3437 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3438 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3439 TGSI_EXEC_DATA_FLOAT
);
3445 exec_dst(struct tgsi_exec_machine
*mach
,
3446 const struct tgsi_full_instruction
*inst
)
3448 union tgsi_exec_channel r
[2];
3449 union tgsi_exec_channel d
[4];
3451 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3452 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3453 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3454 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3456 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3457 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3459 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3460 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3463 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3464 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3466 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3467 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3469 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3470 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3472 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3473 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3478 exec_log(struct tgsi_exec_machine
*mach
,
3479 const struct tgsi_full_instruction
*inst
)
3481 union tgsi_exec_channel r
[3];
3483 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3484 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3485 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3486 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3487 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3488 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3490 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3491 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3492 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3493 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3495 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3496 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3498 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3499 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3504 exec_exp(struct tgsi_exec_machine
*mach
,
3505 const struct tgsi_full_instruction
*inst
)
3507 union tgsi_exec_channel r
[3];
3509 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3510 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3511 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3512 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3513 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3515 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3516 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3517 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3519 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3520 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3521 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3523 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3524 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3529 exec_lit(struct tgsi_exec_machine
*mach
,
3530 const struct tgsi_full_instruction
*inst
)
3532 union tgsi_exec_channel r
[3];
3533 union tgsi_exec_channel d
[3];
3535 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3536 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3537 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3538 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3539 micro_max(&r
[1], &r
[1], &ZeroVec
);
3541 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3542 micro_min(&r
[2], &r
[2], &P128Vec
);
3543 micro_max(&r
[2], &r
[2], &M128Vec
);
3544 micro_pow(&r
[1], &r
[1], &r
[2]);
3545 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3546 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3548 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3549 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3550 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3553 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3554 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3557 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3558 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3563 exec_break(struct tgsi_exec_machine
*mach
)
3565 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3566 /* turn off loop channels for each enabled exec channel */
3567 mach
->LoopMask
&= ~mach
->ExecMask
;
3568 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3569 UPDATE_EXEC_MASK(mach
);
3571 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3573 mach
->Switch
.mask
= 0x0;
3575 UPDATE_EXEC_MASK(mach
);
3580 exec_switch(struct tgsi_exec_machine
*mach
,
3581 const struct tgsi_full_instruction
*inst
)
3583 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3584 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3586 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3587 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3588 mach
->Switch
.mask
= 0x0;
3589 mach
->Switch
.defaultMask
= 0x0;
3591 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3592 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3594 UPDATE_EXEC_MASK(mach
);
3598 exec_case(struct tgsi_exec_machine
*mach
,
3599 const struct tgsi_full_instruction
*inst
)
3601 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3602 union tgsi_exec_channel src
;
3605 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3607 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3610 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3613 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3616 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3620 mach
->Switch
.defaultMask
|= mask
;
3622 mach
->Switch
.mask
|= mask
& prevMask
;
3624 UPDATE_EXEC_MASK(mach
);
3627 /* FIXME: this will only work if default is last */
3629 exec_default(struct tgsi_exec_machine
*mach
)
3631 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3633 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3635 UPDATE_EXEC_MASK(mach
);
3639 exec_endswitch(struct tgsi_exec_machine
*mach
)
3641 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3642 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3644 UPDATE_EXEC_MASK(mach
);
3647 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3648 const union tgsi_double_channel
*src
);
3650 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3651 const union tgsi_double_channel
*src0
,
3652 union tgsi_exec_channel
*src1
);
3654 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3655 const union tgsi_exec_channel
*src
);
3657 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3658 const union tgsi_double_channel
*src
);
3661 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3662 union tgsi_double_channel
*chan
,
3663 const struct tgsi_full_src_register
*reg
,
3667 union tgsi_exec_channel src
[2];
3670 fetch_source_d(mach
, &src
[0], reg
, chan_0
);
3671 fetch_source_d(mach
, &src
[1], reg
, chan_1
);
3673 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3674 chan
->u
[i
][0] = src
[0].u
[i
];
3675 chan
->u
[i
][1] = src
[1].u
[i
];
3677 if (reg
->Register
.Absolute
) {
3678 micro_dabs(chan
, chan
);
3680 if (reg
->Register
.Negate
) {
3681 micro_dneg(chan
, chan
);
3686 store_double_channel(struct tgsi_exec_machine
*mach
,
3687 const union tgsi_double_channel
*chan
,
3688 const struct tgsi_full_dst_register
*reg
,
3689 const struct tgsi_full_instruction
*inst
,
3693 union tgsi_exec_channel dst
[2];
3695 union tgsi_double_channel temp
;
3696 const uint execmask
= mach
->ExecMask
;
3698 if (!inst
->Instruction
.Saturate
) {
3699 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3700 if (execmask
& (1 << i
)) {
3701 dst
[0].u
[i
] = chan
->u
[i
][0];
3702 dst
[1].u
[i
] = chan
->u
[i
][1];
3706 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3707 if (execmask
& (1 << i
)) {
3708 if (chan
->d
[i
] < 0.0)
3710 else if (chan
->d
[i
] > 1.0)
3713 temp
.d
[i
] = chan
->d
[i
];
3715 dst
[0].u
[i
] = temp
.u
[i
][0];
3716 dst
[1].u
[i
] = temp
.u
[i
][1];
3720 store_dest_double(mach
, &dst
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3721 if (chan_1
!= (unsigned)-1)
3722 store_dest_double(mach
, &dst
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3726 exec_double_unary(struct tgsi_exec_machine
*mach
,
3727 const struct tgsi_full_instruction
*inst
,
3730 union tgsi_double_channel src
;
3731 union tgsi_double_channel dst
;
3733 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3734 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3736 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3738 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3739 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3741 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3746 exec_double_binary(struct tgsi_exec_machine
*mach
,
3747 const struct tgsi_full_instruction
*inst
,
3749 enum tgsi_exec_datatype dst_datatype
)
3751 union tgsi_double_channel src
[2];
3752 union tgsi_double_channel dst
;
3753 int first_dest_chan
, second_dest_chan
;
3756 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3757 /* these are & because of the way DSLT etc store their destinations */
3758 if (wmask
& TGSI_WRITEMASK_XY
) {
3759 first_dest_chan
= TGSI_CHAN_X
;
3760 second_dest_chan
= TGSI_CHAN_Y
;
3761 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3762 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3763 second_dest_chan
= -1;
3766 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3767 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3769 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3772 if (wmask
& TGSI_WRITEMASK_ZW
) {
3773 first_dest_chan
= TGSI_CHAN_Z
;
3774 second_dest_chan
= TGSI_CHAN_W
;
3775 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3776 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3777 second_dest_chan
= -1;
3780 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3781 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3783 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3788 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3789 const struct tgsi_full_instruction
*inst
,
3792 union tgsi_double_channel src
[3];
3793 union tgsi_double_channel dst
;
3795 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3796 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3797 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3798 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3800 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3802 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3803 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3804 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3805 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3807 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3812 exec_dldexp(struct tgsi_exec_machine
*mach
,
3813 const struct tgsi_full_instruction
*inst
)
3815 union tgsi_double_channel src0
;
3816 union tgsi_exec_channel src1
;
3817 union tgsi_double_channel dst
;
3820 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3821 if (wmask
& TGSI_WRITEMASK_XY
) {
3822 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3823 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3824 micro_dldexp(&dst
, &src0
, &src1
);
3825 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3828 if (wmask
& TGSI_WRITEMASK_ZW
) {
3829 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3830 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3831 micro_dldexp(&dst
, &src0
, &src1
);
3832 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3837 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3838 const struct tgsi_full_instruction
*inst
)
3840 union tgsi_double_channel src
;
3841 union tgsi_double_channel dst
;
3842 union tgsi_exec_channel dst_exp
;
3844 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3845 micro_dfracexp(&dst
, &dst_exp
, &src
);
3846 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)
3847 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3848 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)
3849 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3850 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3851 if (inst
->Dst
[1].Register
.WriteMask
& (1 << chan
))
3852 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, chan
, TGSI_EXEC_DATA_INT
);
3857 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3858 const struct tgsi_full_instruction
*inst
,
3861 union tgsi_double_channel src0
;
3862 union tgsi_exec_channel src1
;
3863 union tgsi_double_channel dst
;
3866 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3867 if (wmask
& TGSI_WRITEMASK_XY
) {
3868 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3869 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3870 op(&dst
, &src0
, &src1
);
3871 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3874 if (wmask
& TGSI_WRITEMASK_ZW
) {
3875 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3876 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3877 op(&dst
, &src0
, &src1
);
3878 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3883 get_image_coord_dim(unsigned tgsi_tex
)
3887 case TGSI_TEXTURE_BUFFER
:
3888 case TGSI_TEXTURE_1D
:
3891 case TGSI_TEXTURE_2D
:
3892 case TGSI_TEXTURE_RECT
:
3893 case TGSI_TEXTURE_1D_ARRAY
:
3894 case TGSI_TEXTURE_2D_MSAA
:
3897 case TGSI_TEXTURE_3D
:
3898 case TGSI_TEXTURE_CUBE
:
3899 case TGSI_TEXTURE_2D_ARRAY
:
3900 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3901 case TGSI_TEXTURE_CUBE_ARRAY
:
3905 assert(!"unknown texture target");
3914 get_image_coord_sample(unsigned tgsi_tex
)
3918 case TGSI_TEXTURE_2D_MSAA
:
3921 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3931 exec_load_img(struct tgsi_exec_machine
*mach
,
3932 const struct tgsi_full_instruction
*inst
)
3934 union tgsi_exec_channel r
[4], sample_r
;
3940 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3941 struct tgsi_image_params params
;
3942 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3944 unit
= fetch_sampler_unit(mach
, inst
, 0);
3945 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3946 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3949 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3951 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3952 params
.format
= inst
->Memory
.Format
;
3954 for (i
= 0; i
< dim
; i
++) {
3955 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3959 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3961 mach
->Image
->load(mach
->Image
, ¶ms
,
3962 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3964 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3965 r
[0].f
[j
] = rgba
[0][j
];
3966 r
[1].f
[j
] = rgba
[1][j
];
3967 r
[2].f
[j
] = rgba
[2][j
];
3968 r
[3].f
[j
] = rgba
[3][j
];
3970 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3971 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3972 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3978 exec_load_buf(struct tgsi_exec_machine
*mach
,
3979 const struct tgsi_full_instruction
*inst
)
3981 union tgsi_exec_channel r
[4];
3985 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3986 struct tgsi_buffer_params params
;
3987 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3989 unit
= fetch_sampler_unit(mach
, inst
, 0);
3991 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3993 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
3995 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
3997 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3998 r
[0].f
[j
] = rgba
[0][j
];
3999 r
[1].f
[j
] = rgba
[1][j
];
4000 r
[2].f
[j
] = rgba
[2][j
];
4001 r
[3].f
[j
] = rgba
[3][j
];
4003 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4004 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4005 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4011 exec_load_mem(struct tgsi_exec_machine
*mach
,
4012 const struct tgsi_full_instruction
*inst
)
4014 union tgsi_exec_channel r
[4];
4016 char *ptr
= mach
->LocalMem
;
4020 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4021 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4027 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4028 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4029 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4030 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
4035 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4036 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4037 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4043 exec_load(struct tgsi_exec_machine
*mach
,
4044 const struct tgsi_full_instruction
*inst
)
4046 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4047 exec_load_img(mach
, inst
);
4048 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4049 exec_load_buf(mach
, inst
);
4050 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4051 exec_load_mem(mach
, inst
);
4055 fetch_store_img_unit(struct tgsi_exec_machine
*mach
,
4056 const struct tgsi_full_dst_register
*dst
)
4060 if (dst
->Register
.Indirect
) {
4061 union tgsi_exec_channel indir_index
, index2
;
4062 const uint execmask
= mach
->ExecMask
;
4066 index2
.i
[3] = dst
->Indirect
.Index
;
4068 fetch_src_file_channel(mach
,
4070 dst
->Indirect
.Swizzle
,
4074 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4075 if (execmask
& (1 << i
)) {
4076 unit
= dst
->Register
.Index
+ indir_index
.i
[i
];
4081 unit
= dst
->Register
.Index
;
4087 exec_store_img(struct tgsi_exec_machine
*mach
,
4088 const struct tgsi_full_instruction
*inst
)
4090 union tgsi_exec_channel r
[3], sample_r
;
4091 union tgsi_exec_channel value
[4];
4092 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4093 struct tgsi_image_params params
;
4098 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4099 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4100 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4101 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4104 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4106 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4107 params
.format
= inst
->Memory
.Format
;
4109 for (i
= 0; i
< dim
; i
++) {
4110 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
4113 for (i
= 0; i
< 4; i
++) {
4114 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4117 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4119 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4120 rgba
[0][j
] = value
[0].f
[j
];
4121 rgba
[1][j
] = value
[1].f
[j
];
4122 rgba
[2][j
] = value
[2].f
[j
];
4123 rgba
[3][j
] = value
[3].f
[j
];
4126 mach
->Image
->store(mach
->Image
, ¶ms
,
4127 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4132 exec_store_buf(struct tgsi_exec_machine
*mach
,
4133 const struct tgsi_full_instruction
*inst
)
4135 union tgsi_exec_channel r
[3];
4136 union tgsi_exec_channel value
[4];
4137 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4138 struct tgsi_buffer_params params
;
4141 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4143 unit
= fetch_store_img_unit(mach
, &inst
->Dst
[0]);
4145 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4147 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4149 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4150 for (i
= 0; i
< 4; i
++) {
4151 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4154 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4155 rgba
[0][j
] = value
[0].f
[j
];
4156 rgba
[1][j
] = value
[1].f
[j
];
4157 rgba
[2][j
] = value
[2].f
[j
];
4158 rgba
[3][j
] = value
[3].f
[j
];
4161 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4167 exec_store_mem(struct tgsi_exec_machine
*mach
,
4168 const struct tgsi_full_instruction
*inst
)
4170 union tgsi_exec_channel r
[3];
4171 union tgsi_exec_channel value
[4];
4173 char *ptr
= mach
->LocalMem
;
4174 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4175 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4177 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4179 for (i
= 0; i
< 4; i
++) {
4180 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4183 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4187 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4188 if (execmask
& (1 << i
)) {
4189 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4190 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4191 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4199 exec_store(struct tgsi_exec_machine
*mach
,
4200 const struct tgsi_full_instruction
*inst
)
4202 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4203 exec_store_img(mach
, inst
);
4204 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4205 exec_store_buf(mach
, inst
);
4206 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4207 exec_store_mem(mach
, inst
);
4211 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4212 const struct tgsi_full_instruction
*inst
)
4214 union tgsi_exec_channel r
[4], sample_r
;
4215 union tgsi_exec_channel value
[4], value2
[4];
4216 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4217 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4218 struct tgsi_image_params params
;
4223 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4224 unit
= fetch_sampler_unit(mach
, inst
, 0);
4225 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4226 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4229 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4231 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4232 params
.format
= inst
->Memory
.Format
;
4234 for (i
= 0; i
< dim
; i
++) {
4235 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4238 for (i
= 0; i
< 4; i
++) {
4239 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4240 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4241 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4244 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4246 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4247 rgba
[0][j
] = value
[0].f
[j
];
4248 rgba
[1][j
] = value
[1].f
[j
];
4249 rgba
[2][j
] = value
[2].f
[j
];
4250 rgba
[3][j
] = value
[3].f
[j
];
4252 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4253 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4254 rgba2
[0][j
] = value2
[0].f
[j
];
4255 rgba2
[1][j
] = value2
[1].f
[j
];
4256 rgba2
[2][j
] = value2
[2].f
[j
];
4257 rgba2
[3][j
] = value2
[3].f
[j
];
4261 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4262 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4265 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4266 r
[0].f
[j
] = rgba
[0][j
];
4267 r
[1].f
[j
] = rgba
[1][j
];
4268 r
[2].f
[j
] = rgba
[2][j
];
4269 r
[3].f
[j
] = rgba
[3][j
];
4271 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4272 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4273 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4279 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4280 const struct tgsi_full_instruction
*inst
)
4282 union tgsi_exec_channel r
[4];
4283 union tgsi_exec_channel value
[4], value2
[4];
4284 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4285 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4286 struct tgsi_buffer_params params
;
4289 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4291 unit
= fetch_sampler_unit(mach
, inst
, 0);
4293 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4295 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4297 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4299 for (i
= 0; i
< 4; i
++) {
4300 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4301 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4302 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4305 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4306 rgba
[0][j
] = value
[0].f
[j
];
4307 rgba
[1][j
] = value
[1].f
[j
];
4308 rgba
[2][j
] = value
[2].f
[j
];
4309 rgba
[3][j
] = value
[3].f
[j
];
4311 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4312 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4313 rgba2
[0][j
] = value2
[0].f
[j
];
4314 rgba2
[1][j
] = value2
[1].f
[j
];
4315 rgba2
[2][j
] = value2
[2].f
[j
];
4316 rgba2
[3][j
] = value2
[3].f
[j
];
4320 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4324 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4325 r
[0].f
[j
] = rgba
[0][j
];
4326 r
[1].f
[j
] = rgba
[1][j
];
4327 r
[2].f
[j
] = rgba
[2][j
];
4328 r
[3].f
[j
] = rgba
[3][j
];
4330 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4331 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4332 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4338 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4339 const struct tgsi_full_instruction
*inst
)
4341 union tgsi_exec_channel r
[4];
4342 union tgsi_exec_channel value
[4], value2
[4];
4343 char *ptr
= mach
->LocalMem
;
4347 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4348 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4349 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4351 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4356 for (i
= 0; i
< 4; i
++) {
4357 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4358 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4359 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4362 memcpy(&r
[0].u
[0], ptr
, 4);
4364 switch (inst
->Instruction
.Opcode
) {
4365 case TGSI_OPCODE_ATOMUADD
:
4366 val
+= value
[0].u
[0];
4368 case TGSI_OPCODE_ATOMXOR
:
4369 val
^= value
[0].u
[0];
4371 case TGSI_OPCODE_ATOMOR
:
4372 val
|= value
[0].u
[0];
4374 case TGSI_OPCODE_ATOMAND
:
4375 val
&= value
[0].u
[0];
4377 case TGSI_OPCODE_ATOMUMIN
:
4378 val
= MIN2(val
, value
[0].u
[0]);
4380 case TGSI_OPCODE_ATOMUMAX
:
4381 val
= MAX2(val
, value
[0].u
[0]);
4383 case TGSI_OPCODE_ATOMIMIN
:
4384 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4386 case TGSI_OPCODE_ATOMIMAX
:
4387 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4389 case TGSI_OPCODE_ATOMXCHG
:
4390 val
= value
[0].i
[0];
4392 case TGSI_OPCODE_ATOMCAS
:
4393 if (val
== value
[0].u
[0])
4394 val
= value2
[0].u
[0];
4396 case TGSI_OPCODE_ATOMFADD
:
4397 val
= fui(r
[0].f
[0] + value
[0].f
[0]);
4402 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4403 if (execmask
& (1 << i
))
4404 memcpy(ptr
, &val
, 4);
4406 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4407 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4408 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4414 exec_atomop(struct tgsi_exec_machine
*mach
,
4415 const struct tgsi_full_instruction
*inst
)
4417 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4418 exec_atomop_img(mach
, inst
);
4419 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4420 exec_atomop_buf(mach
, inst
);
4421 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4422 exec_atomop_mem(mach
, inst
);
4426 exec_resq_img(struct tgsi_exec_machine
*mach
,
4427 const struct tgsi_full_instruction
*inst
)
4430 union tgsi_exec_channel r
[4];
4433 struct tgsi_image_params params
;
4434 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4436 unit
= fetch_sampler_unit(mach
, inst
, 0);
4438 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4440 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4441 params
.format
= inst
->Memory
.Format
;
4443 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4445 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4446 for (j
= 0; j
< 4; j
++) {
4447 r
[j
].i
[i
] = result
[j
];
4451 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4452 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4453 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4454 TGSI_EXEC_DATA_INT
);
4460 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4461 const struct tgsi_full_instruction
*inst
)
4464 union tgsi_exec_channel r
[4];
4467 struct tgsi_buffer_params params
;
4468 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4470 unit
= fetch_sampler_unit(mach
, inst
, 0);
4472 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4475 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4477 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4481 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4482 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4483 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4484 TGSI_EXEC_DATA_INT
);
4490 exec_resq(struct tgsi_exec_machine
*mach
,
4491 const struct tgsi_full_instruction
*inst
)
4493 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4494 exec_resq_img(mach
, inst
);
4496 exec_resq_buf(mach
, inst
);
4500 micro_f2u64(union tgsi_double_channel
*dst
,
4501 const union tgsi_exec_channel
*src
)
4503 dst
->u64
[0] = (uint64_t)src
->f
[0];
4504 dst
->u64
[1] = (uint64_t)src
->f
[1];
4505 dst
->u64
[2] = (uint64_t)src
->f
[2];
4506 dst
->u64
[3] = (uint64_t)src
->f
[3];
4510 micro_f2i64(union tgsi_double_channel
*dst
,
4511 const union tgsi_exec_channel
*src
)
4513 dst
->i64
[0] = (int64_t)src
->f
[0];
4514 dst
->i64
[1] = (int64_t)src
->f
[1];
4515 dst
->i64
[2] = (int64_t)src
->f
[2];
4516 dst
->i64
[3] = (int64_t)src
->f
[3];
4520 micro_u2i64(union tgsi_double_channel
*dst
,
4521 const union tgsi_exec_channel
*src
)
4523 dst
->u64
[0] = (uint64_t)src
->u
[0];
4524 dst
->u64
[1] = (uint64_t)src
->u
[1];
4525 dst
->u64
[2] = (uint64_t)src
->u
[2];
4526 dst
->u64
[3] = (uint64_t)src
->u
[3];
4530 micro_i2i64(union tgsi_double_channel
*dst
,
4531 const union tgsi_exec_channel
*src
)
4533 dst
->i64
[0] = (int64_t)src
->i
[0];
4534 dst
->i64
[1] = (int64_t)src
->i
[1];
4535 dst
->i64
[2] = (int64_t)src
->i
[2];
4536 dst
->i64
[3] = (int64_t)src
->i
[3];
4540 micro_d2u64(union tgsi_double_channel
*dst
,
4541 const union tgsi_double_channel
*src
)
4543 dst
->u64
[0] = (uint64_t)src
->d
[0];
4544 dst
->u64
[1] = (uint64_t)src
->d
[1];
4545 dst
->u64
[2] = (uint64_t)src
->d
[2];
4546 dst
->u64
[3] = (uint64_t)src
->d
[3];
4550 micro_d2i64(union tgsi_double_channel
*dst
,
4551 const union tgsi_double_channel
*src
)
4553 dst
->i64
[0] = (int64_t)src
->d
[0];
4554 dst
->i64
[1] = (int64_t)src
->d
[1];
4555 dst
->i64
[2] = (int64_t)src
->d
[2];
4556 dst
->i64
[3] = (int64_t)src
->d
[3];
4560 micro_u642d(union tgsi_double_channel
*dst
,
4561 const union tgsi_double_channel
*src
)
4563 dst
->d
[0] = (double)src
->u64
[0];
4564 dst
->d
[1] = (double)src
->u64
[1];
4565 dst
->d
[2] = (double)src
->u64
[2];
4566 dst
->d
[3] = (double)src
->u64
[3];
4570 micro_i642d(union tgsi_double_channel
*dst
,
4571 const union tgsi_double_channel
*src
)
4573 dst
->d
[0] = (double)src
->i64
[0];
4574 dst
->d
[1] = (double)src
->i64
[1];
4575 dst
->d
[2] = (double)src
->i64
[2];
4576 dst
->d
[3] = (double)src
->i64
[3];
4580 micro_u642f(union tgsi_exec_channel
*dst
,
4581 const union tgsi_double_channel
*src
)
4583 dst
->f
[0] = (float)src
->u64
[0];
4584 dst
->f
[1] = (float)src
->u64
[1];
4585 dst
->f
[2] = (float)src
->u64
[2];
4586 dst
->f
[3] = (float)src
->u64
[3];
4590 micro_i642f(union tgsi_exec_channel
*dst
,
4591 const union tgsi_double_channel
*src
)
4593 dst
->f
[0] = (float)src
->i64
[0];
4594 dst
->f
[1] = (float)src
->i64
[1];
4595 dst
->f
[2] = (float)src
->i64
[2];
4596 dst
->f
[3] = (float)src
->i64
[3];
4600 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4601 const struct tgsi_full_instruction
*inst
,
4603 enum tgsi_exec_datatype src_datatype
)
4605 union tgsi_exec_channel src
;
4606 union tgsi_double_channel dst
;
4608 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4609 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4611 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4613 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4614 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4616 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4621 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4622 const struct tgsi_full_instruction
*inst
,
4624 enum tgsi_exec_datatype dst_datatype
)
4626 union tgsi_double_channel src
;
4627 union tgsi_exec_channel dst
;
4628 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4631 for (i
= 0; i
< 2; i
++) {
4634 wm
&= ~(1 << (bit
- 1));
4636 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4638 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4640 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4646 micro_i2f(union tgsi_exec_channel
*dst
,
4647 const union tgsi_exec_channel
*src
)
4649 dst
->f
[0] = (float)src
->i
[0];
4650 dst
->f
[1] = (float)src
->i
[1];
4651 dst
->f
[2] = (float)src
->i
[2];
4652 dst
->f
[3] = (float)src
->i
[3];
4656 micro_not(union tgsi_exec_channel
*dst
,
4657 const union tgsi_exec_channel
*src
)
4659 dst
->u
[0] = ~src
->u
[0];
4660 dst
->u
[1] = ~src
->u
[1];
4661 dst
->u
[2] = ~src
->u
[2];
4662 dst
->u
[3] = ~src
->u
[3];
4666 micro_shl(union tgsi_exec_channel
*dst
,
4667 const union tgsi_exec_channel
*src0
,
4668 const union tgsi_exec_channel
*src1
)
4670 unsigned masked_count
;
4671 masked_count
= src1
->u
[0] & 0x1f;
4672 dst
->u
[0] = src0
->u
[0] << masked_count
;
4673 masked_count
= src1
->u
[1] & 0x1f;
4674 dst
->u
[1] = src0
->u
[1] << masked_count
;
4675 masked_count
= src1
->u
[2] & 0x1f;
4676 dst
->u
[2] = src0
->u
[2] << masked_count
;
4677 masked_count
= src1
->u
[3] & 0x1f;
4678 dst
->u
[3] = src0
->u
[3] << masked_count
;
4682 micro_and(union tgsi_exec_channel
*dst
,
4683 const union tgsi_exec_channel
*src0
,
4684 const union tgsi_exec_channel
*src1
)
4686 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4687 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4688 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4689 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4693 micro_or(union tgsi_exec_channel
*dst
,
4694 const union tgsi_exec_channel
*src0
,
4695 const union tgsi_exec_channel
*src1
)
4697 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4698 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4699 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4700 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4704 micro_xor(union tgsi_exec_channel
*dst
,
4705 const union tgsi_exec_channel
*src0
,
4706 const union tgsi_exec_channel
*src1
)
4708 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4709 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4710 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4711 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4715 micro_mod(union tgsi_exec_channel
*dst
,
4716 const union tgsi_exec_channel
*src0
,
4717 const union tgsi_exec_channel
*src1
)
4719 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] % src1
->i
[0] : ~0;
4720 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] % src1
->i
[1] : ~0;
4721 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] % src1
->i
[2] : ~0;
4722 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] % src1
->i
[3] : ~0;
4726 micro_f2i(union tgsi_exec_channel
*dst
,
4727 const union tgsi_exec_channel
*src
)
4729 dst
->i
[0] = (int)src
->f
[0];
4730 dst
->i
[1] = (int)src
->f
[1];
4731 dst
->i
[2] = (int)src
->f
[2];
4732 dst
->i
[3] = (int)src
->f
[3];
4736 micro_fseq(union tgsi_exec_channel
*dst
,
4737 const union tgsi_exec_channel
*src0
,
4738 const union tgsi_exec_channel
*src1
)
4740 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4741 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4742 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4743 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4747 micro_fsge(union tgsi_exec_channel
*dst
,
4748 const union tgsi_exec_channel
*src0
,
4749 const union tgsi_exec_channel
*src1
)
4751 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4752 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4753 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4754 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4758 micro_fslt(union tgsi_exec_channel
*dst
,
4759 const union tgsi_exec_channel
*src0
,
4760 const union tgsi_exec_channel
*src1
)
4762 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4763 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4764 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4765 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4769 micro_fsne(union tgsi_exec_channel
*dst
,
4770 const union tgsi_exec_channel
*src0
,
4771 const union tgsi_exec_channel
*src1
)
4773 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4774 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4775 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4776 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4780 micro_idiv(union tgsi_exec_channel
*dst
,
4781 const union tgsi_exec_channel
*src0
,
4782 const union tgsi_exec_channel
*src1
)
4784 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4785 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4786 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4787 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4791 micro_imax(union tgsi_exec_channel
*dst
,
4792 const union tgsi_exec_channel
*src0
,
4793 const union tgsi_exec_channel
*src1
)
4795 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4796 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4797 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4798 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4802 micro_imin(union tgsi_exec_channel
*dst
,
4803 const union tgsi_exec_channel
*src0
,
4804 const union tgsi_exec_channel
*src1
)
4806 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4807 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4808 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4809 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4813 micro_isge(union tgsi_exec_channel
*dst
,
4814 const union tgsi_exec_channel
*src0
,
4815 const union tgsi_exec_channel
*src1
)
4817 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4818 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4819 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4820 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4824 micro_ishr(union tgsi_exec_channel
*dst
,
4825 const union tgsi_exec_channel
*src0
,
4826 const union tgsi_exec_channel
*src1
)
4828 unsigned masked_count
;
4829 masked_count
= src1
->i
[0] & 0x1f;
4830 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4831 masked_count
= src1
->i
[1] & 0x1f;
4832 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4833 masked_count
= src1
->i
[2] & 0x1f;
4834 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4835 masked_count
= src1
->i
[3] & 0x1f;
4836 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4840 micro_islt(union tgsi_exec_channel
*dst
,
4841 const union tgsi_exec_channel
*src0
,
4842 const union tgsi_exec_channel
*src1
)
4844 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4845 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4846 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4847 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4851 micro_f2u(union tgsi_exec_channel
*dst
,
4852 const union tgsi_exec_channel
*src
)
4854 dst
->u
[0] = (uint
)src
->f
[0];
4855 dst
->u
[1] = (uint
)src
->f
[1];
4856 dst
->u
[2] = (uint
)src
->f
[2];
4857 dst
->u
[3] = (uint
)src
->f
[3];
4861 micro_u2f(union tgsi_exec_channel
*dst
,
4862 const union tgsi_exec_channel
*src
)
4864 dst
->f
[0] = (float)src
->u
[0];
4865 dst
->f
[1] = (float)src
->u
[1];
4866 dst
->f
[2] = (float)src
->u
[2];
4867 dst
->f
[3] = (float)src
->u
[3];
4871 micro_uadd(union tgsi_exec_channel
*dst
,
4872 const union tgsi_exec_channel
*src0
,
4873 const union tgsi_exec_channel
*src1
)
4875 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4876 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4877 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4878 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4882 micro_udiv(union tgsi_exec_channel
*dst
,
4883 const union tgsi_exec_channel
*src0
,
4884 const union tgsi_exec_channel
*src1
)
4886 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4887 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4888 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4889 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4893 micro_umad(union tgsi_exec_channel
*dst
,
4894 const union tgsi_exec_channel
*src0
,
4895 const union tgsi_exec_channel
*src1
,
4896 const union tgsi_exec_channel
*src2
)
4898 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4899 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4900 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4901 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4905 micro_umax(union tgsi_exec_channel
*dst
,
4906 const union tgsi_exec_channel
*src0
,
4907 const union tgsi_exec_channel
*src1
)
4909 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4910 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4911 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4912 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4916 micro_umin(union tgsi_exec_channel
*dst
,
4917 const union tgsi_exec_channel
*src0
,
4918 const union tgsi_exec_channel
*src1
)
4920 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4921 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4922 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4923 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4927 micro_umod(union tgsi_exec_channel
*dst
,
4928 const union tgsi_exec_channel
*src0
,
4929 const union tgsi_exec_channel
*src1
)
4931 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4932 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4933 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4934 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4938 micro_umul(union tgsi_exec_channel
*dst
,
4939 const union tgsi_exec_channel
*src0
,
4940 const union tgsi_exec_channel
*src1
)
4942 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4943 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4944 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4945 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4949 micro_imul_hi(union tgsi_exec_channel
*dst
,
4950 const union tgsi_exec_channel
*src0
,
4951 const union tgsi_exec_channel
*src1
)
4953 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4954 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4955 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4956 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4957 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4962 micro_umul_hi(union tgsi_exec_channel
*dst
,
4963 const union tgsi_exec_channel
*src0
,
4964 const union tgsi_exec_channel
*src1
)
4966 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4967 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4968 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4969 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4970 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4975 micro_useq(union tgsi_exec_channel
*dst
,
4976 const union tgsi_exec_channel
*src0
,
4977 const union tgsi_exec_channel
*src1
)
4979 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4980 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4981 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4982 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4986 micro_usge(union tgsi_exec_channel
*dst
,
4987 const union tgsi_exec_channel
*src0
,
4988 const union tgsi_exec_channel
*src1
)
4990 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4991 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4992 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4993 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4997 micro_ushr(union tgsi_exec_channel
*dst
,
4998 const union tgsi_exec_channel
*src0
,
4999 const union tgsi_exec_channel
*src1
)
5001 unsigned masked_count
;
5002 masked_count
= src1
->u
[0] & 0x1f;
5003 dst
->u
[0] = src0
->u
[0] >> masked_count
;
5004 masked_count
= src1
->u
[1] & 0x1f;
5005 dst
->u
[1] = src0
->u
[1] >> masked_count
;
5006 masked_count
= src1
->u
[2] & 0x1f;
5007 dst
->u
[2] = src0
->u
[2] >> masked_count
;
5008 masked_count
= src1
->u
[3] & 0x1f;
5009 dst
->u
[3] = src0
->u
[3] >> masked_count
;
5013 micro_uslt(union tgsi_exec_channel
*dst
,
5014 const union tgsi_exec_channel
*src0
,
5015 const union tgsi_exec_channel
*src1
)
5017 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
5018 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
5019 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
5020 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
5024 micro_usne(union tgsi_exec_channel
*dst
,
5025 const union tgsi_exec_channel
*src0
,
5026 const union tgsi_exec_channel
*src1
)
5028 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
5029 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
5030 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
5031 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
5035 micro_uarl(union tgsi_exec_channel
*dst
,
5036 const union tgsi_exec_channel
*src
)
5038 dst
->i
[0] = src
->u
[0];
5039 dst
->i
[1] = src
->u
[1];
5040 dst
->i
[2] = src
->u
[2];
5041 dst
->i
[3] = src
->u
[3];
5045 * Signed bitfield extract (i.e. sign-extend the extracted bits)
5048 micro_ibfe(union tgsi_exec_channel
*dst
,
5049 const union tgsi_exec_channel
*src0
,
5050 const union tgsi_exec_channel
*src1
,
5051 const union tgsi_exec_channel
*src2
)
5054 for (i
= 0; i
< 4; i
++) {
5055 int width
= src2
->i
[i
];
5056 int offset
= src1
->i
[i
] & 0x1f;
5057 if (width
== 32 && offset
== 0) {
5058 dst
->i
[i
] = src0
->i
[i
];
5064 else if (width
+ offset
< 32)
5065 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
5067 dst
->i
[i
] = src0
->i
[i
] >> offset
;
5072 * Unsigned bitfield extract
5075 micro_ubfe(union tgsi_exec_channel
*dst
,
5076 const union tgsi_exec_channel
*src0
,
5077 const union tgsi_exec_channel
*src1
,
5078 const union tgsi_exec_channel
*src2
)
5081 for (i
= 0; i
< 4; i
++) {
5082 int width
= src2
->u
[i
];
5083 int offset
= src1
->u
[i
] & 0x1f;
5084 if (width
== 32 && offset
== 0) {
5085 dst
->u
[i
] = src0
->u
[i
];
5091 else if (width
+ offset
< 32)
5092 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
5094 dst
->u
[i
] = src0
->u
[i
] >> offset
;
5099 * Bitfield insert: copy low bits from src1 into a region of src0.
5102 micro_bfi(union tgsi_exec_channel
*dst
,
5103 const union tgsi_exec_channel
*src0
,
5104 const union tgsi_exec_channel
*src1
,
5105 const union tgsi_exec_channel
*src2
,
5106 const union tgsi_exec_channel
*src3
)
5109 for (i
= 0; i
< 4; i
++) {
5110 int width
= src3
->u
[i
];
5111 int offset
= src2
->u
[i
] & 0x1f;
5113 dst
->u
[i
] = src1
->u
[i
];
5115 int bitmask
= ((1 << width
) - 1) << offset
;
5116 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
5122 micro_brev(union tgsi_exec_channel
*dst
,
5123 const union tgsi_exec_channel
*src
)
5125 dst
->u
[0] = util_bitreverse(src
->u
[0]);
5126 dst
->u
[1] = util_bitreverse(src
->u
[1]);
5127 dst
->u
[2] = util_bitreverse(src
->u
[2]);
5128 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5132 micro_popc(union tgsi_exec_channel
*dst
,
5133 const union tgsi_exec_channel
*src
)
5135 dst
->u
[0] = util_bitcount(src
->u
[0]);
5136 dst
->u
[1] = util_bitcount(src
->u
[1]);
5137 dst
->u
[2] = util_bitcount(src
->u
[2]);
5138 dst
->u
[3] = util_bitcount(src
->u
[3]);
5142 micro_lsb(union tgsi_exec_channel
*dst
,
5143 const union tgsi_exec_channel
*src
)
5145 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5146 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5147 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5148 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5152 micro_imsb(union tgsi_exec_channel
*dst
,
5153 const union tgsi_exec_channel
*src
)
5155 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5156 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5157 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5158 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5162 micro_umsb(union tgsi_exec_channel
*dst
,
5163 const union tgsi_exec_channel
*src
)
5165 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5166 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5167 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5168 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5172 * Execute a TGSI instruction.
5173 * Returns TRUE if a barrier instruction is hit,
5178 struct tgsi_exec_machine
*mach
,
5179 const struct tgsi_full_instruction
*inst
,
5182 union tgsi_exec_channel r
[10];
5186 switch (inst
->Instruction
.Opcode
) {
5187 case TGSI_OPCODE_ARL
:
5188 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5191 case TGSI_OPCODE_MOV
:
5192 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5195 case TGSI_OPCODE_LIT
:
5196 exec_lit(mach
, inst
);
5199 case TGSI_OPCODE_RCP
:
5200 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5203 case TGSI_OPCODE_RSQ
:
5204 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5207 case TGSI_OPCODE_EXP
:
5208 exec_exp(mach
, inst
);
5211 case TGSI_OPCODE_LOG
:
5212 exec_log(mach
, inst
);
5215 case TGSI_OPCODE_MUL
:
5216 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5219 case TGSI_OPCODE_ADD
:
5220 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5223 case TGSI_OPCODE_DP3
:
5224 exec_dp3(mach
, inst
);
5227 case TGSI_OPCODE_DP4
:
5228 exec_dp4(mach
, inst
);
5231 case TGSI_OPCODE_DST
:
5232 exec_dst(mach
, inst
);
5235 case TGSI_OPCODE_MIN
:
5236 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5239 case TGSI_OPCODE_MAX
:
5240 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5243 case TGSI_OPCODE_SLT
:
5244 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5247 case TGSI_OPCODE_SGE
:
5248 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5251 case TGSI_OPCODE_MAD
:
5252 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5255 case TGSI_OPCODE_LRP
:
5256 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5259 case TGSI_OPCODE_SQRT
:
5260 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5263 case TGSI_OPCODE_FRC
:
5264 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5267 case TGSI_OPCODE_FLR
:
5268 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5271 case TGSI_OPCODE_ROUND
:
5272 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5275 case TGSI_OPCODE_EX2
:
5276 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5279 case TGSI_OPCODE_LG2
:
5280 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5283 case TGSI_OPCODE_POW
:
5284 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5287 case TGSI_OPCODE_LDEXP
:
5288 exec_vector_binary(mach
, inst
, micro_ldexp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5291 case TGSI_OPCODE_COS
:
5292 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5295 case TGSI_OPCODE_DDX
:
5296 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5299 case TGSI_OPCODE_DDY
:
5300 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5303 case TGSI_OPCODE_KILL
:
5307 case TGSI_OPCODE_KILL_IF
:
5308 exec_kill_if (mach
, inst
);
5311 case TGSI_OPCODE_PK2H
:
5312 exec_pk2h(mach
, inst
);
5315 case TGSI_OPCODE_PK2US
:
5319 case TGSI_OPCODE_PK4B
:
5323 case TGSI_OPCODE_PK4UB
:
5327 case TGSI_OPCODE_SEQ
:
5328 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5331 case TGSI_OPCODE_SGT
:
5332 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5335 case TGSI_OPCODE_SIN
:
5336 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5339 case TGSI_OPCODE_SLE
:
5340 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5343 case TGSI_OPCODE_SNE
:
5344 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5347 case TGSI_OPCODE_TEX
:
5348 /* simple texture lookup */
5349 /* src[0] = texcoord */
5350 /* src[1] = sampler unit */
5351 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5354 case TGSI_OPCODE_TXB
:
5355 /* Texture lookup with lod bias */
5356 /* src[0] = texcoord (src[0].w = LOD bias) */
5357 /* src[1] = sampler unit */
5358 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5361 case TGSI_OPCODE_TXD
:
5362 /* Texture lookup with explict partial derivatives */
5363 /* src[0] = texcoord */
5364 /* src[1] = d[strq]/dx */
5365 /* src[2] = d[strq]/dy */
5366 /* src[3] = sampler unit */
5367 exec_txd(mach
, inst
);
5370 case TGSI_OPCODE_TXL
:
5371 /* Texture lookup with explit LOD */
5372 /* src[0] = texcoord (src[0].w = LOD) */
5373 /* src[1] = sampler unit */
5374 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5377 case TGSI_OPCODE_TXP
:
5378 /* Texture lookup with projection */
5379 /* src[0] = texcoord (src[0].w = projection) */
5380 /* src[1] = sampler unit */
5381 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5384 case TGSI_OPCODE_TG4
:
5385 /* src[0] = texcoord */
5386 /* src[1] = component */
5387 /* src[2] = sampler unit */
5388 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5391 case TGSI_OPCODE_LODQ
:
5392 /* src[0] = texcoord */
5393 /* src[1] = sampler unit */
5394 exec_lodq(mach
, inst
);
5397 case TGSI_OPCODE_UP2H
:
5398 exec_up2h(mach
, inst
);
5401 case TGSI_OPCODE_UP2US
:
5405 case TGSI_OPCODE_UP4B
:
5409 case TGSI_OPCODE_UP4UB
:
5413 case TGSI_OPCODE_ARR
:
5414 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5417 case TGSI_OPCODE_CAL
:
5418 /* skip the call if no execution channels are enabled */
5419 if (mach
->ExecMask
) {
5422 /* First, record the depths of the execution stacks.
5423 * This is important for deeply nested/looped return statements.
5424 * We have to unwind the stacks by the correct amount. For a
5425 * real code generator, we could determine the number of entries
5426 * to pop off each stack with simple static analysis and avoid
5427 * implementing this data structure at run time.
5429 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5430 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5431 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5432 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5433 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5434 /* note that PC was already incremented above */
5435 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5437 mach
->CallStackTop
++;
5439 /* Second, push the Cond, Loop, Cont, Func stacks */
5440 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5441 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5442 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5443 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5444 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5445 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5447 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5448 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5449 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5450 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5451 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5452 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5454 /* Finally, jump to the subroutine. The label is a pointer
5455 * (an instruction number) to the BGNSUB instruction.
5457 *pc
= inst
->Label
.Label
;
5458 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5459 == TGSI_OPCODE_BGNSUB
);
5463 case TGSI_OPCODE_RET
:
5464 mach
->FuncMask
&= ~mach
->ExecMask
;
5465 UPDATE_EXEC_MASK(mach
);
5467 if (mach
->FuncMask
== 0x0) {
5468 /* really return now (otherwise, keep executing */
5470 if (mach
->CallStackTop
== 0) {
5471 /* returning from main() */
5472 mach
->CondStackTop
= 0;
5473 mach
->LoopStackTop
= 0;
5474 mach
->ContStackTop
= 0;
5475 mach
->LoopLabelStackTop
= 0;
5476 mach
->SwitchStackTop
= 0;
5477 mach
->BreakStackTop
= 0;
5482 assert(mach
->CallStackTop
> 0);
5483 mach
->CallStackTop
--;
5485 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5486 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5488 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5489 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5491 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5492 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5494 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5495 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5497 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5498 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5500 assert(mach
->FuncStackTop
> 0);
5501 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5503 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5505 UPDATE_EXEC_MASK(mach
);
5509 case TGSI_OPCODE_SSG
:
5510 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5513 case TGSI_OPCODE_CMP
:
5514 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5517 case TGSI_OPCODE_DIV
:
5518 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5521 case TGSI_OPCODE_DP2
:
5522 exec_dp2(mach
, inst
);
5525 case TGSI_OPCODE_IF
:
5527 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5528 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5529 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5530 /* update CondMask */
5532 mach
->CondMask
&= ~0x1;
5535 mach
->CondMask
&= ~0x2;
5538 mach
->CondMask
&= ~0x4;
5541 mach
->CondMask
&= ~0x8;
5543 UPDATE_EXEC_MASK(mach
);
5544 /* Todo: If CondMask==0, jump to ELSE */
5547 case TGSI_OPCODE_UIF
:
5549 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5550 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5551 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5552 /* update CondMask */
5554 mach
->CondMask
&= ~0x1;
5557 mach
->CondMask
&= ~0x2;
5560 mach
->CondMask
&= ~0x4;
5563 mach
->CondMask
&= ~0x8;
5565 UPDATE_EXEC_MASK(mach
);
5566 /* Todo: If CondMask==0, jump to ELSE */
5569 case TGSI_OPCODE_ELSE
:
5570 /* invert CondMask wrt previous mask */
5573 assert(mach
->CondStackTop
> 0);
5574 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5575 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5576 UPDATE_EXEC_MASK(mach
);
5577 /* Todo: If CondMask==0, jump to ENDIF */
5581 case TGSI_OPCODE_ENDIF
:
5583 assert(mach
->CondStackTop
> 0);
5584 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5585 UPDATE_EXEC_MASK(mach
);
5588 case TGSI_OPCODE_END
:
5589 /* make sure we end primitives which haven't
5590 * been explicitly emitted */
5591 conditional_emit_primitive(mach
);
5592 /* halt execution */
5596 case TGSI_OPCODE_CEIL
:
5597 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5600 case TGSI_OPCODE_I2F
:
5601 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5604 case TGSI_OPCODE_NOT
:
5605 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5608 case TGSI_OPCODE_TRUNC
:
5609 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5612 case TGSI_OPCODE_SHL
:
5613 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5616 case TGSI_OPCODE_AND
:
5617 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5620 case TGSI_OPCODE_OR
:
5621 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5624 case TGSI_OPCODE_MOD
:
5625 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5628 case TGSI_OPCODE_XOR
:
5629 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5632 case TGSI_OPCODE_TXF
:
5633 exec_txf(mach
, inst
);
5636 case TGSI_OPCODE_TXQ
:
5637 exec_txq(mach
, inst
);
5640 case TGSI_OPCODE_EMIT
:
5641 emit_vertex(mach
, inst
);
5644 case TGSI_OPCODE_ENDPRIM
:
5645 emit_primitive(mach
, inst
);
5648 case TGSI_OPCODE_BGNLOOP
:
5649 /* push LoopMask and ContMasks */
5650 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5651 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5652 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5653 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5655 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5656 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5657 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5658 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5659 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5662 case TGSI_OPCODE_ENDLOOP
:
5663 /* Restore ContMask, but don't pop */
5664 assert(mach
->ContStackTop
> 0);
5665 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5666 UPDATE_EXEC_MASK(mach
);
5667 if (mach
->ExecMask
) {
5668 /* repeat loop: jump to instruction just past BGNLOOP */
5669 assert(mach
->LoopLabelStackTop
> 0);
5670 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5673 /* exit loop: pop LoopMask */
5674 assert(mach
->LoopStackTop
> 0);
5675 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5677 assert(mach
->ContStackTop
> 0);
5678 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5679 assert(mach
->LoopLabelStackTop
> 0);
5680 --mach
->LoopLabelStackTop
;
5682 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5684 UPDATE_EXEC_MASK(mach
);
5687 case TGSI_OPCODE_BRK
:
5691 case TGSI_OPCODE_CONT
:
5692 /* turn off cont channels for each enabled exec channel */
5693 mach
->ContMask
&= ~mach
->ExecMask
;
5694 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5695 UPDATE_EXEC_MASK(mach
);
5698 case TGSI_OPCODE_BGNSUB
:
5702 case TGSI_OPCODE_ENDSUB
:
5704 * XXX: This really should be a no-op. We should never reach this opcode.
5707 assert(mach
->CallStackTop
> 0);
5708 mach
->CallStackTop
--;
5710 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5711 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5713 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5714 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5716 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5717 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5719 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5720 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5722 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5723 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5725 assert(mach
->FuncStackTop
> 0);
5726 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5728 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5730 UPDATE_EXEC_MASK(mach
);
5733 case TGSI_OPCODE_NOP
:
5736 case TGSI_OPCODE_F2I
:
5737 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5740 case TGSI_OPCODE_FSEQ
:
5741 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5744 case TGSI_OPCODE_FSGE
:
5745 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5748 case TGSI_OPCODE_FSLT
:
5749 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5752 case TGSI_OPCODE_FSNE
:
5753 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5756 case TGSI_OPCODE_IDIV
:
5757 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5760 case TGSI_OPCODE_IMAX
:
5761 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5764 case TGSI_OPCODE_IMIN
:
5765 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5768 case TGSI_OPCODE_INEG
:
5769 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5772 case TGSI_OPCODE_ISGE
:
5773 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5776 case TGSI_OPCODE_ISHR
:
5777 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5780 case TGSI_OPCODE_ISLT
:
5781 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5784 case TGSI_OPCODE_F2U
:
5785 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5788 case TGSI_OPCODE_U2F
:
5789 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5792 case TGSI_OPCODE_UADD
:
5793 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5796 case TGSI_OPCODE_UDIV
:
5797 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5800 case TGSI_OPCODE_UMAD
:
5801 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5804 case TGSI_OPCODE_UMAX
:
5805 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5808 case TGSI_OPCODE_UMIN
:
5809 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5812 case TGSI_OPCODE_UMOD
:
5813 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5816 case TGSI_OPCODE_UMUL
:
5817 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5820 case TGSI_OPCODE_IMUL_HI
:
5821 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5824 case TGSI_OPCODE_UMUL_HI
:
5825 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5828 case TGSI_OPCODE_USEQ
:
5829 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5832 case TGSI_OPCODE_USGE
:
5833 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5836 case TGSI_OPCODE_USHR
:
5837 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5840 case TGSI_OPCODE_USLT
:
5841 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5844 case TGSI_OPCODE_USNE
:
5845 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5848 case TGSI_OPCODE_SWITCH
:
5849 exec_switch(mach
, inst
);
5852 case TGSI_OPCODE_CASE
:
5853 exec_case(mach
, inst
);
5856 case TGSI_OPCODE_DEFAULT
:
5860 case TGSI_OPCODE_ENDSWITCH
:
5861 exec_endswitch(mach
);
5864 case TGSI_OPCODE_SAMPLE_I
:
5865 exec_txf(mach
, inst
);
5868 case TGSI_OPCODE_SAMPLE_I_MS
:
5869 exec_txf(mach
, inst
);
5872 case TGSI_OPCODE_SAMPLE
:
5873 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5876 case TGSI_OPCODE_SAMPLE_B
:
5877 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5880 case TGSI_OPCODE_SAMPLE_C
:
5881 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5884 case TGSI_OPCODE_SAMPLE_C_LZ
:
5885 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5888 case TGSI_OPCODE_SAMPLE_D
:
5889 exec_sample_d(mach
, inst
);
5892 case TGSI_OPCODE_SAMPLE_L
:
5893 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5896 case TGSI_OPCODE_GATHER4
:
5897 exec_sample(mach
, inst
, TEX_MODIFIER_GATHER
, FALSE
);
5900 case TGSI_OPCODE_SVIEWINFO
:
5901 exec_txq(mach
, inst
);
5904 case TGSI_OPCODE_SAMPLE_POS
:
5908 case TGSI_OPCODE_SAMPLE_INFO
:
5912 case TGSI_OPCODE_LOD
:
5913 exec_lodq(mach
, inst
);
5916 case TGSI_OPCODE_UARL
:
5917 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5920 case TGSI_OPCODE_UCMP
:
5921 exec_ucmp(mach
, inst
);
5924 case TGSI_OPCODE_IABS
:
5925 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5928 case TGSI_OPCODE_ISSG
:
5929 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5932 case TGSI_OPCODE_TEX2
:
5933 /* simple texture lookup */
5934 /* src[0] = texcoord */
5935 /* src[1] = compare */
5936 /* src[2] = sampler unit */
5937 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5939 case TGSI_OPCODE_TXB2
:
5940 /* simple texture lookup */
5941 /* src[0] = texcoord */
5943 /* src[2] = sampler unit */
5944 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5946 case TGSI_OPCODE_TXL2
:
5947 /* simple texture lookup */
5948 /* src[0] = texcoord */
5950 /* src[2] = sampler unit */
5951 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5954 case TGSI_OPCODE_IBFE
:
5955 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5957 case TGSI_OPCODE_UBFE
:
5958 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5960 case TGSI_OPCODE_BFI
:
5961 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5963 case TGSI_OPCODE_BREV
:
5964 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5966 case TGSI_OPCODE_POPC
:
5967 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5969 case TGSI_OPCODE_LSB
:
5970 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5972 case TGSI_OPCODE_IMSB
:
5973 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5975 case TGSI_OPCODE_UMSB
:
5976 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5979 case TGSI_OPCODE_F2D
:
5980 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
5983 case TGSI_OPCODE_D2F
:
5984 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
5987 case TGSI_OPCODE_DABS
:
5988 exec_double_unary(mach
, inst
, micro_dabs
);
5991 case TGSI_OPCODE_DNEG
:
5992 exec_double_unary(mach
, inst
, micro_dneg
);
5995 case TGSI_OPCODE_DADD
:
5996 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
5999 case TGSI_OPCODE_DDIV
:
6000 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
6003 case TGSI_OPCODE_DMUL
:
6004 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
6007 case TGSI_OPCODE_DMAX
:
6008 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
6011 case TGSI_OPCODE_DMIN
:
6012 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
6015 case TGSI_OPCODE_DSLT
:
6016 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
6019 case TGSI_OPCODE_DSGE
:
6020 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
6023 case TGSI_OPCODE_DSEQ
:
6024 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
6027 case TGSI_OPCODE_DSNE
:
6028 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
6031 case TGSI_OPCODE_DRCP
:
6032 exec_double_unary(mach
, inst
, micro_drcp
);
6035 case TGSI_OPCODE_DSQRT
:
6036 exec_double_unary(mach
, inst
, micro_dsqrt
);
6039 case TGSI_OPCODE_DRSQ
:
6040 exec_double_unary(mach
, inst
, micro_drsq
);
6043 case TGSI_OPCODE_DMAD
:
6044 exec_double_trinary(mach
, inst
, micro_dmad
);
6047 case TGSI_OPCODE_DFRAC
:
6048 exec_double_unary(mach
, inst
, micro_dfrac
);
6051 case TGSI_OPCODE_DLDEXP
:
6052 exec_dldexp(mach
, inst
);
6055 case TGSI_OPCODE_DFRACEXP
:
6056 exec_dfracexp(mach
, inst
);
6059 case TGSI_OPCODE_I2D
:
6060 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
6063 case TGSI_OPCODE_D2I
:
6064 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
6067 case TGSI_OPCODE_U2D
:
6068 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
6071 case TGSI_OPCODE_D2U
:
6072 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
6075 case TGSI_OPCODE_LOAD
:
6076 exec_load(mach
, inst
);
6079 case TGSI_OPCODE_STORE
:
6080 exec_store(mach
, inst
);
6083 case TGSI_OPCODE_ATOMUADD
:
6084 case TGSI_OPCODE_ATOMXCHG
:
6085 case TGSI_OPCODE_ATOMCAS
:
6086 case TGSI_OPCODE_ATOMAND
:
6087 case TGSI_OPCODE_ATOMOR
:
6088 case TGSI_OPCODE_ATOMXOR
:
6089 case TGSI_OPCODE_ATOMUMIN
:
6090 case TGSI_OPCODE_ATOMUMAX
:
6091 case TGSI_OPCODE_ATOMIMIN
:
6092 case TGSI_OPCODE_ATOMIMAX
:
6093 case TGSI_OPCODE_ATOMFADD
:
6094 exec_atomop(mach
, inst
);
6097 case TGSI_OPCODE_RESQ
:
6098 exec_resq(mach
, inst
);
6100 case TGSI_OPCODE_BARRIER
:
6101 case TGSI_OPCODE_MEMBAR
:
6105 case TGSI_OPCODE_I64ABS
:
6106 exec_double_unary(mach
, inst
, micro_i64abs
);
6109 case TGSI_OPCODE_I64SSG
:
6110 exec_double_unary(mach
, inst
, micro_i64sgn
);
6113 case TGSI_OPCODE_I64NEG
:
6114 exec_double_unary(mach
, inst
, micro_i64neg
);
6117 case TGSI_OPCODE_U64SEQ
:
6118 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6121 case TGSI_OPCODE_U64SNE
:
6122 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6125 case TGSI_OPCODE_I64SLT
:
6126 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6128 case TGSI_OPCODE_U64SLT
:
6129 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6132 case TGSI_OPCODE_I64SGE
:
6133 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6135 case TGSI_OPCODE_U64SGE
:
6136 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6139 case TGSI_OPCODE_I64MIN
:
6140 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6142 case TGSI_OPCODE_U64MIN
:
6143 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6145 case TGSI_OPCODE_I64MAX
:
6146 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6148 case TGSI_OPCODE_U64MAX
:
6149 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6151 case TGSI_OPCODE_U64ADD
:
6152 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6154 case TGSI_OPCODE_U64MUL
:
6155 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6157 case TGSI_OPCODE_U64SHL
:
6158 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6160 case TGSI_OPCODE_I64SHR
:
6161 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6163 case TGSI_OPCODE_U64SHR
:
6164 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6166 case TGSI_OPCODE_U64DIV
:
6167 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6169 case TGSI_OPCODE_I64DIV
:
6170 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6172 case TGSI_OPCODE_U64MOD
:
6173 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6175 case TGSI_OPCODE_I64MOD
:
6176 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6179 case TGSI_OPCODE_F2U64
:
6180 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6183 case TGSI_OPCODE_F2I64
:
6184 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6187 case TGSI_OPCODE_U2I64
:
6188 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6190 case TGSI_OPCODE_I2I64
:
6191 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6194 case TGSI_OPCODE_D2U64
:
6195 exec_double_unary(mach
, inst
, micro_d2u64
);
6198 case TGSI_OPCODE_D2I64
:
6199 exec_double_unary(mach
, inst
, micro_d2i64
);
6202 case TGSI_OPCODE_U642F
:
6203 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6205 case TGSI_OPCODE_I642F
:
6206 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6209 case TGSI_OPCODE_U642D
:
6210 exec_double_unary(mach
, inst
, micro_u642d
);
6212 case TGSI_OPCODE_I642D
:
6213 exec_double_unary(mach
, inst
, micro_i642d
);
6223 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6225 uint default_mask
= 0xf;
6227 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6228 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6230 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6231 for (unsigned i
= 0; i
< TGSI_MAX_VERTEX_STREAMS
; i
++) {
6232 mach
->Temps
[temp_prim_idxs
[i
].idx
].xyzw
[temp_prim_idxs
[i
].chan
].u
[0] = 0;
6233 mach
->Primitives
[i
][0] = 0;
6235 /* GS runs on a single primitive for now */
6239 if (mach
->NonHelperMask
== 0)
6240 mach
->NonHelperMask
= default_mask
;
6241 mach
->CondMask
= default_mask
;
6242 mach
->LoopMask
= default_mask
;
6243 mach
->ContMask
= default_mask
;
6244 mach
->FuncMask
= default_mask
;
6245 mach
->ExecMask
= default_mask
;
6247 mach
->Switch
.mask
= default_mask
;
6249 assert(mach
->CondStackTop
== 0);
6250 assert(mach
->LoopStackTop
== 0);
6251 assert(mach
->ContStackTop
== 0);
6252 assert(mach
->SwitchStackTop
== 0);
6253 assert(mach
->BreakStackTop
== 0);
6254 assert(mach
->CallStackTop
== 0);
6258 * Run TGSI interpreter.
6259 * \return bitmask of "alive" quad components
6262 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6266 mach
->pc
= start_pc
;
6269 tgsi_exec_machine_setup_masks(mach
);
6271 /* execute declarations (interpolants) */
6272 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6273 exec_declaration( mach
, mach
->Declarations
+i
);
6279 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6280 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6284 memset(mach
->Temps
, 0, sizeof(temps
));
6286 memset(mach
->Outputs
, 0, sizeof(outputs
));
6287 memset(temps
, 0, sizeof(temps
));
6288 memset(outputs
, 0, sizeof(outputs
));
6292 /* execute instructions, until pc is set to -1 */
6293 while (mach
->pc
!= -1) {
6294 boolean barrier_hit
;
6298 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6301 assert(mach
->pc
< (int) mach
->NumInstructions
);
6302 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6304 /* for compute shaders if we hit a barrier return now for later rescheduling */
6305 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6309 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6310 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6313 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6314 debug_printf("TEMP[%2u] = ", i
);
6315 for (j
= 0; j
< 4; j
++) {
6319 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6320 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6321 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6322 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6323 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6327 if (mach
->Outputs
) {
6328 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6329 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6332 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6333 debug_printf("OUT[%2u] = ", i
);
6334 for (j
= 0; j
< 4; j
++) {
6338 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6339 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6340 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6341 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6342 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6352 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6353 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6355 * Scale back depth component.
6357 for (i
= 0; i
< 4; i
++)
6358 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6362 /* Strictly speaking, these assertions aren't really needed but they
6363 * can potentially catch some bugs in the control flow code.
6365 assert(mach
->CondStackTop
== 0);
6366 assert(mach
->LoopStackTop
== 0);
6367 assert(mach
->ContStackTop
== 0);
6368 assert(mach
->SwitchStackTop
== 0);
6369 assert(mach
->BreakStackTop
== 0);
6370 assert(mach
->CallStackTop
== 0);
6372 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];