1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_half.h"
62 #include "util/u_memory.h"
63 #include "util/u_math.h"
64 #include "util/rounding.h"
67 #define DEBUG_EXECUTION 0
72 #define TILE_TOP_LEFT 0
73 #define TILE_TOP_RIGHT 1
74 #define TILE_BOTTOM_LEFT 2
75 #define TILE_BOTTOM_RIGHT 3
77 union tgsi_double_channel
{
78 double d
[TGSI_QUAD_SIZE
];
79 unsigned u
[TGSI_QUAD_SIZE
][2];
80 uint64_t u64
[TGSI_QUAD_SIZE
];
81 int64_t i64
[TGSI_QUAD_SIZE
];
84 struct tgsi_double_vector
{
85 union tgsi_double_channel xy
;
86 union tgsi_double_channel zw
;
90 micro_abs(union tgsi_exec_channel
*dst
,
91 const union tgsi_exec_channel
*src
)
93 dst
->f
[0] = fabsf(src
->f
[0]);
94 dst
->f
[1] = fabsf(src
->f
[1]);
95 dst
->f
[2] = fabsf(src
->f
[2]);
96 dst
->f
[3] = fabsf(src
->f
[3]);
100 micro_arl(union tgsi_exec_channel
*dst
,
101 const union tgsi_exec_channel
*src
)
103 dst
->i
[0] = (int)floorf(src
->f
[0]);
104 dst
->i
[1] = (int)floorf(src
->f
[1]);
105 dst
->i
[2] = (int)floorf(src
->f
[2]);
106 dst
->i
[3] = (int)floorf(src
->f
[3]);
110 micro_arr(union tgsi_exec_channel
*dst
,
111 const union tgsi_exec_channel
*src
)
113 dst
->i
[0] = (int)floorf(src
->f
[0] + 0.5f
);
114 dst
->i
[1] = (int)floorf(src
->f
[1] + 0.5f
);
115 dst
->i
[2] = (int)floorf(src
->f
[2] + 0.5f
);
116 dst
->i
[3] = (int)floorf(src
->f
[3] + 0.5f
);
120 micro_ceil(union tgsi_exec_channel
*dst
,
121 const union tgsi_exec_channel
*src
)
123 dst
->f
[0] = ceilf(src
->f
[0]);
124 dst
->f
[1] = ceilf(src
->f
[1]);
125 dst
->f
[2] = ceilf(src
->f
[2]);
126 dst
->f
[3] = ceilf(src
->f
[3]);
130 micro_cmp(union tgsi_exec_channel
*dst
,
131 const union tgsi_exec_channel
*src0
,
132 const union tgsi_exec_channel
*src1
,
133 const union tgsi_exec_channel
*src2
)
135 dst
->f
[0] = src0
->f
[0] < 0.0f
? src1
->f
[0] : src2
->f
[0];
136 dst
->f
[1] = src0
->f
[1] < 0.0f
? src1
->f
[1] : src2
->f
[1];
137 dst
->f
[2] = src0
->f
[2] < 0.0f
? src1
->f
[2] : src2
->f
[2];
138 dst
->f
[3] = src0
->f
[3] < 0.0f
? src1
->f
[3] : src2
->f
[3];
142 micro_cos(union tgsi_exec_channel
*dst
,
143 const union tgsi_exec_channel
*src
)
145 dst
->f
[0] = cosf(src
->f
[0]);
146 dst
->f
[1] = cosf(src
->f
[1]);
147 dst
->f
[2] = cosf(src
->f
[2]);
148 dst
->f
[3] = cosf(src
->f
[3]);
152 micro_d2f(union tgsi_exec_channel
*dst
,
153 const union tgsi_double_channel
*src
)
155 dst
->f
[0] = (float)src
->d
[0];
156 dst
->f
[1] = (float)src
->d
[1];
157 dst
->f
[2] = (float)src
->d
[2];
158 dst
->f
[3] = (float)src
->d
[3];
162 micro_d2i(union tgsi_exec_channel
*dst
,
163 const union tgsi_double_channel
*src
)
165 dst
->i
[0] = (int)src
->d
[0];
166 dst
->i
[1] = (int)src
->d
[1];
167 dst
->i
[2] = (int)src
->d
[2];
168 dst
->i
[3] = (int)src
->d
[3];
172 micro_d2u(union tgsi_exec_channel
*dst
,
173 const union tgsi_double_channel
*src
)
175 dst
->u
[0] = (unsigned)src
->d
[0];
176 dst
->u
[1] = (unsigned)src
->d
[1];
177 dst
->u
[2] = (unsigned)src
->d
[2];
178 dst
->u
[3] = (unsigned)src
->d
[3];
181 micro_dabs(union tgsi_double_channel
*dst
,
182 const union tgsi_double_channel
*src
)
184 dst
->d
[0] = src
->d
[0] >= 0.0 ? src
->d
[0] : -src
->d
[0];
185 dst
->d
[1] = src
->d
[1] >= 0.0 ? src
->d
[1] : -src
->d
[1];
186 dst
->d
[2] = src
->d
[2] >= 0.0 ? src
->d
[2] : -src
->d
[2];
187 dst
->d
[3] = src
->d
[3] >= 0.0 ? src
->d
[3] : -src
->d
[3];
191 micro_dadd(union tgsi_double_channel
*dst
,
192 const union tgsi_double_channel
*src
)
194 dst
->d
[0] = src
[0].d
[0] + src
[1].d
[0];
195 dst
->d
[1] = src
[0].d
[1] + src
[1].d
[1];
196 dst
->d
[2] = src
[0].d
[2] + src
[1].d
[2];
197 dst
->d
[3] = src
[0].d
[3] + src
[1].d
[3];
201 micro_ddiv(union tgsi_double_channel
*dst
,
202 const union tgsi_double_channel
*src
)
204 dst
->d
[0] = src
[0].d
[0] / src
[1].d
[0];
205 dst
->d
[1] = src
[0].d
[1] / src
[1].d
[1];
206 dst
->d
[2] = src
[0].d
[2] / src
[1].d
[2];
207 dst
->d
[3] = src
[0].d
[3] / src
[1].d
[3];
211 micro_ddx(union tgsi_exec_channel
*dst
,
212 const union tgsi_exec_channel
*src
)
217 dst
->f
[3] = src
->f
[TILE_BOTTOM_RIGHT
] - src
->f
[TILE_BOTTOM_LEFT
];
221 micro_ddy(union tgsi_exec_channel
*dst
,
222 const union tgsi_exec_channel
*src
)
227 dst
->f
[3] = src
->f
[TILE_BOTTOM_LEFT
] - src
->f
[TILE_TOP_LEFT
];
231 micro_dmul(union tgsi_double_channel
*dst
,
232 const union tgsi_double_channel
*src
)
234 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0];
235 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1];
236 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2];
237 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3];
241 micro_dmax(union tgsi_double_channel
*dst
,
242 const union tgsi_double_channel
*src
)
244 dst
->d
[0] = src
[0].d
[0] > src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
245 dst
->d
[1] = src
[0].d
[1] > src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
246 dst
->d
[2] = src
[0].d
[2] > src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
247 dst
->d
[3] = src
[0].d
[3] > src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
251 micro_dmin(union tgsi_double_channel
*dst
,
252 const union tgsi_double_channel
*src
)
254 dst
->d
[0] = src
[0].d
[0] < src
[1].d
[0] ? src
[0].d
[0] : src
[1].d
[0];
255 dst
->d
[1] = src
[0].d
[1] < src
[1].d
[1] ? src
[0].d
[1] : src
[1].d
[1];
256 dst
->d
[2] = src
[0].d
[2] < src
[1].d
[2] ? src
[0].d
[2] : src
[1].d
[2];
257 dst
->d
[3] = src
[0].d
[3] < src
[1].d
[3] ? src
[0].d
[3] : src
[1].d
[3];
261 micro_dneg(union tgsi_double_channel
*dst
,
262 const union tgsi_double_channel
*src
)
264 dst
->d
[0] = -src
->d
[0];
265 dst
->d
[1] = -src
->d
[1];
266 dst
->d
[2] = -src
->d
[2];
267 dst
->d
[3] = -src
->d
[3];
271 micro_dslt(union tgsi_double_channel
*dst
,
272 const union tgsi_double_channel
*src
)
274 dst
->u
[0][0] = src
[0].d
[0] < src
[1].d
[0] ? ~0U : 0U;
275 dst
->u
[1][0] = src
[0].d
[1] < src
[1].d
[1] ? ~0U : 0U;
276 dst
->u
[2][0] = src
[0].d
[2] < src
[1].d
[2] ? ~0U : 0U;
277 dst
->u
[3][0] = src
[0].d
[3] < src
[1].d
[3] ? ~0U : 0U;
281 micro_dsne(union tgsi_double_channel
*dst
,
282 const union tgsi_double_channel
*src
)
284 dst
->u
[0][0] = src
[0].d
[0] != src
[1].d
[0] ? ~0U : 0U;
285 dst
->u
[1][0] = src
[0].d
[1] != src
[1].d
[1] ? ~0U : 0U;
286 dst
->u
[2][0] = src
[0].d
[2] != src
[1].d
[2] ? ~0U : 0U;
287 dst
->u
[3][0] = src
[0].d
[3] != src
[1].d
[3] ? ~0U : 0U;
291 micro_dsge(union tgsi_double_channel
*dst
,
292 const union tgsi_double_channel
*src
)
294 dst
->u
[0][0] = src
[0].d
[0] >= src
[1].d
[0] ? ~0U : 0U;
295 dst
->u
[1][0] = src
[0].d
[1] >= src
[1].d
[1] ? ~0U : 0U;
296 dst
->u
[2][0] = src
[0].d
[2] >= src
[1].d
[2] ? ~0U : 0U;
297 dst
->u
[3][0] = src
[0].d
[3] >= src
[1].d
[3] ? ~0U : 0U;
301 micro_dseq(union tgsi_double_channel
*dst
,
302 const union tgsi_double_channel
*src
)
304 dst
->u
[0][0] = src
[0].d
[0] == src
[1].d
[0] ? ~0U : 0U;
305 dst
->u
[1][0] = src
[0].d
[1] == src
[1].d
[1] ? ~0U : 0U;
306 dst
->u
[2][0] = src
[0].d
[2] == src
[1].d
[2] ? ~0U : 0U;
307 dst
->u
[3][0] = src
[0].d
[3] == src
[1].d
[3] ? ~0U : 0U;
311 micro_drcp(union tgsi_double_channel
*dst
,
312 const union tgsi_double_channel
*src
)
314 dst
->d
[0] = 1.0 / src
->d
[0];
315 dst
->d
[1] = 1.0 / src
->d
[1];
316 dst
->d
[2] = 1.0 / src
->d
[2];
317 dst
->d
[3] = 1.0 / src
->d
[3];
321 micro_dsqrt(union tgsi_double_channel
*dst
,
322 const union tgsi_double_channel
*src
)
324 dst
->d
[0] = sqrt(src
->d
[0]);
325 dst
->d
[1] = sqrt(src
->d
[1]);
326 dst
->d
[2] = sqrt(src
->d
[2]);
327 dst
->d
[3] = sqrt(src
->d
[3]);
331 micro_drsq(union tgsi_double_channel
*dst
,
332 const union tgsi_double_channel
*src
)
334 dst
->d
[0] = 1.0 / sqrt(src
->d
[0]);
335 dst
->d
[1] = 1.0 / sqrt(src
->d
[1]);
336 dst
->d
[2] = 1.0 / sqrt(src
->d
[2]);
337 dst
->d
[3] = 1.0 / sqrt(src
->d
[3]);
341 micro_dmad(union tgsi_double_channel
*dst
,
342 const union tgsi_double_channel
*src
)
344 dst
->d
[0] = src
[0].d
[0] * src
[1].d
[0] + src
[2].d
[0];
345 dst
->d
[1] = src
[0].d
[1] * src
[1].d
[1] + src
[2].d
[1];
346 dst
->d
[2] = src
[0].d
[2] * src
[1].d
[2] + src
[2].d
[2];
347 dst
->d
[3] = src
[0].d
[3] * src
[1].d
[3] + src
[2].d
[3];
351 micro_dfrac(union tgsi_double_channel
*dst
,
352 const union tgsi_double_channel
*src
)
354 dst
->d
[0] = src
->d
[0] - floor(src
->d
[0]);
355 dst
->d
[1] = src
->d
[1] - floor(src
->d
[1]);
356 dst
->d
[2] = src
->d
[2] - floor(src
->d
[2]);
357 dst
->d
[3] = src
->d
[3] - floor(src
->d
[3]);
361 micro_dldexp(union tgsi_double_channel
*dst
,
362 const union tgsi_double_channel
*src0
,
363 union tgsi_exec_channel
*src1
)
365 dst
->d
[0] = ldexp(src0
->d
[0], src1
->i
[0]);
366 dst
->d
[1] = ldexp(src0
->d
[1], src1
->i
[1]);
367 dst
->d
[2] = ldexp(src0
->d
[2], src1
->i
[2]);
368 dst
->d
[3] = ldexp(src0
->d
[3], src1
->i
[3]);
372 micro_dfracexp(union tgsi_double_channel
*dst
,
373 union tgsi_exec_channel
*dst_exp
,
374 const union tgsi_double_channel
*src
)
376 dst
->d
[0] = frexp(src
->d
[0], &dst_exp
->i
[0]);
377 dst
->d
[1] = frexp(src
->d
[1], &dst_exp
->i
[1]);
378 dst
->d
[2] = frexp(src
->d
[2], &dst_exp
->i
[2]);
379 dst
->d
[3] = frexp(src
->d
[3], &dst_exp
->i
[3]);
383 micro_exp2(union tgsi_exec_channel
*dst
,
384 const union tgsi_exec_channel
*src
)
387 dst
->f
[0] = util_fast_exp2(src
->f
[0]);
388 dst
->f
[1] = util_fast_exp2(src
->f
[1]);
389 dst
->f
[2] = util_fast_exp2(src
->f
[2]);
390 dst
->f
[3] = util_fast_exp2(src
->f
[3]);
393 /* Inf is okay for this instruction, so clamp it to silence assertions. */
395 union tgsi_exec_channel clamped
;
397 for (i
= 0; i
< 4; i
++) {
398 if (src
->f
[i
] > 127.99999f
) {
399 clamped
.f
[i
] = 127.99999f
;
400 } else if (src
->f
[i
] < -126.99999f
) {
401 clamped
.f
[i
] = -126.99999f
;
403 clamped
.f
[i
] = src
->f
[i
];
409 dst
->f
[0] = powf(2.0f
, src
->f
[0]);
410 dst
->f
[1] = powf(2.0f
, src
->f
[1]);
411 dst
->f
[2] = powf(2.0f
, src
->f
[2]);
412 dst
->f
[3] = powf(2.0f
, src
->f
[3]);
413 #endif /* FAST_MATH */
417 micro_f2d(union tgsi_double_channel
*dst
,
418 const union tgsi_exec_channel
*src
)
420 dst
->d
[0] = (double)src
->f
[0];
421 dst
->d
[1] = (double)src
->f
[1];
422 dst
->d
[2] = (double)src
->f
[2];
423 dst
->d
[3] = (double)src
->f
[3];
427 micro_flr(union tgsi_exec_channel
*dst
,
428 const union tgsi_exec_channel
*src
)
430 dst
->f
[0] = floorf(src
->f
[0]);
431 dst
->f
[1] = floorf(src
->f
[1]);
432 dst
->f
[2] = floorf(src
->f
[2]);
433 dst
->f
[3] = floorf(src
->f
[3]);
437 micro_frc(union tgsi_exec_channel
*dst
,
438 const union tgsi_exec_channel
*src
)
440 dst
->f
[0] = src
->f
[0] - floorf(src
->f
[0]);
441 dst
->f
[1] = src
->f
[1] - floorf(src
->f
[1]);
442 dst
->f
[2] = src
->f
[2] - floorf(src
->f
[2]);
443 dst
->f
[3] = src
->f
[3] - floorf(src
->f
[3]);
447 micro_i2d(union tgsi_double_channel
*dst
,
448 const union tgsi_exec_channel
*src
)
450 dst
->d
[0] = (double)src
->i
[0];
451 dst
->d
[1] = (double)src
->i
[1];
452 dst
->d
[2] = (double)src
->i
[2];
453 dst
->d
[3] = (double)src
->i
[3];
457 micro_iabs(union tgsi_exec_channel
*dst
,
458 const union tgsi_exec_channel
*src
)
460 dst
->i
[0] = src
->i
[0] >= 0 ? src
->i
[0] : -src
->i
[0];
461 dst
->i
[1] = src
->i
[1] >= 0 ? src
->i
[1] : -src
->i
[1];
462 dst
->i
[2] = src
->i
[2] >= 0 ? src
->i
[2] : -src
->i
[2];
463 dst
->i
[3] = src
->i
[3] >= 0 ? src
->i
[3] : -src
->i
[3];
467 micro_ineg(union tgsi_exec_channel
*dst
,
468 const union tgsi_exec_channel
*src
)
470 dst
->i
[0] = -src
->i
[0];
471 dst
->i
[1] = -src
->i
[1];
472 dst
->i
[2] = -src
->i
[2];
473 dst
->i
[3] = -src
->i
[3];
477 micro_lg2(union tgsi_exec_channel
*dst
,
478 const union tgsi_exec_channel
*src
)
481 dst
->f
[0] = util_fast_log2(src
->f
[0]);
482 dst
->f
[1] = util_fast_log2(src
->f
[1]);
483 dst
->f
[2] = util_fast_log2(src
->f
[2]);
484 dst
->f
[3] = util_fast_log2(src
->f
[3]);
486 dst
->f
[0] = logf(src
->f
[0]) * 1.442695f
;
487 dst
->f
[1] = logf(src
->f
[1]) * 1.442695f
;
488 dst
->f
[2] = logf(src
->f
[2]) * 1.442695f
;
489 dst
->f
[3] = logf(src
->f
[3]) * 1.442695f
;
494 micro_lrp(union tgsi_exec_channel
*dst
,
495 const union tgsi_exec_channel
*src0
,
496 const union tgsi_exec_channel
*src1
,
497 const union tgsi_exec_channel
*src2
)
499 dst
->f
[0] = src0
->f
[0] * (src1
->f
[0] - src2
->f
[0]) + src2
->f
[0];
500 dst
->f
[1] = src0
->f
[1] * (src1
->f
[1] - src2
->f
[1]) + src2
->f
[1];
501 dst
->f
[2] = src0
->f
[2] * (src1
->f
[2] - src2
->f
[2]) + src2
->f
[2];
502 dst
->f
[3] = src0
->f
[3] * (src1
->f
[3] - src2
->f
[3]) + src2
->f
[3];
506 micro_mad(union tgsi_exec_channel
*dst
,
507 const union tgsi_exec_channel
*src0
,
508 const union tgsi_exec_channel
*src1
,
509 const union tgsi_exec_channel
*src2
)
511 dst
->f
[0] = src0
->f
[0] * src1
->f
[0] + src2
->f
[0];
512 dst
->f
[1] = src0
->f
[1] * src1
->f
[1] + src2
->f
[1];
513 dst
->f
[2] = src0
->f
[2] * src1
->f
[2] + src2
->f
[2];
514 dst
->f
[3] = src0
->f
[3] * src1
->f
[3] + src2
->f
[3];
518 micro_mov(union tgsi_exec_channel
*dst
,
519 const union tgsi_exec_channel
*src
)
521 dst
->u
[0] = src
->u
[0];
522 dst
->u
[1] = src
->u
[1];
523 dst
->u
[2] = src
->u
[2];
524 dst
->u
[3] = src
->u
[3];
528 micro_rcp(union tgsi_exec_channel
*dst
,
529 const union tgsi_exec_channel
*src
)
531 #if 0 /* for debugging */
532 assert(src
->f
[0] != 0.0f
);
533 assert(src
->f
[1] != 0.0f
);
534 assert(src
->f
[2] != 0.0f
);
535 assert(src
->f
[3] != 0.0f
);
537 dst
->f
[0] = 1.0f
/ src
->f
[0];
538 dst
->f
[1] = 1.0f
/ src
->f
[1];
539 dst
->f
[2] = 1.0f
/ src
->f
[2];
540 dst
->f
[3] = 1.0f
/ src
->f
[3];
544 micro_rnd(union tgsi_exec_channel
*dst
,
545 const union tgsi_exec_channel
*src
)
547 dst
->f
[0] = _mesa_roundevenf(src
->f
[0]);
548 dst
->f
[1] = _mesa_roundevenf(src
->f
[1]);
549 dst
->f
[2] = _mesa_roundevenf(src
->f
[2]);
550 dst
->f
[3] = _mesa_roundevenf(src
->f
[3]);
554 micro_rsq(union tgsi_exec_channel
*dst
,
555 const union tgsi_exec_channel
*src
)
557 #if 0 /* for debugging */
558 assert(src
->f
[0] != 0.0f
);
559 assert(src
->f
[1] != 0.0f
);
560 assert(src
->f
[2] != 0.0f
);
561 assert(src
->f
[3] != 0.0f
);
563 dst
->f
[0] = 1.0f
/ sqrtf(src
->f
[0]);
564 dst
->f
[1] = 1.0f
/ sqrtf(src
->f
[1]);
565 dst
->f
[2] = 1.0f
/ sqrtf(src
->f
[2]);
566 dst
->f
[3] = 1.0f
/ sqrtf(src
->f
[3]);
570 micro_sqrt(union tgsi_exec_channel
*dst
,
571 const union tgsi_exec_channel
*src
)
573 dst
->f
[0] = sqrtf(src
->f
[0]);
574 dst
->f
[1] = sqrtf(src
->f
[1]);
575 dst
->f
[2] = sqrtf(src
->f
[2]);
576 dst
->f
[3] = sqrtf(src
->f
[3]);
580 micro_seq(union tgsi_exec_channel
*dst
,
581 const union tgsi_exec_channel
*src0
,
582 const union tgsi_exec_channel
*src1
)
584 dst
->f
[0] = src0
->f
[0] == src1
->f
[0] ? 1.0f
: 0.0f
;
585 dst
->f
[1] = src0
->f
[1] == src1
->f
[1] ? 1.0f
: 0.0f
;
586 dst
->f
[2] = src0
->f
[2] == src1
->f
[2] ? 1.0f
: 0.0f
;
587 dst
->f
[3] = src0
->f
[3] == src1
->f
[3] ? 1.0f
: 0.0f
;
591 micro_sge(union tgsi_exec_channel
*dst
,
592 const union tgsi_exec_channel
*src0
,
593 const union tgsi_exec_channel
*src1
)
595 dst
->f
[0] = src0
->f
[0] >= src1
->f
[0] ? 1.0f
: 0.0f
;
596 dst
->f
[1] = src0
->f
[1] >= src1
->f
[1] ? 1.0f
: 0.0f
;
597 dst
->f
[2] = src0
->f
[2] >= src1
->f
[2] ? 1.0f
: 0.0f
;
598 dst
->f
[3] = src0
->f
[3] >= src1
->f
[3] ? 1.0f
: 0.0f
;
602 micro_sgn(union tgsi_exec_channel
*dst
,
603 const union tgsi_exec_channel
*src
)
605 dst
->f
[0] = src
->f
[0] < 0.0f
? -1.0f
: src
->f
[0] > 0.0f
? 1.0f
: 0.0f
;
606 dst
->f
[1] = src
->f
[1] < 0.0f
? -1.0f
: src
->f
[1] > 0.0f
? 1.0f
: 0.0f
;
607 dst
->f
[2] = src
->f
[2] < 0.0f
? -1.0f
: src
->f
[2] > 0.0f
? 1.0f
: 0.0f
;
608 dst
->f
[3] = src
->f
[3] < 0.0f
? -1.0f
: src
->f
[3] > 0.0f
? 1.0f
: 0.0f
;
612 micro_isgn(union tgsi_exec_channel
*dst
,
613 const union tgsi_exec_channel
*src
)
615 dst
->i
[0] = src
->i
[0] < 0 ? -1 : src
->i
[0] > 0 ? 1 : 0;
616 dst
->i
[1] = src
->i
[1] < 0 ? -1 : src
->i
[1] > 0 ? 1 : 0;
617 dst
->i
[2] = src
->i
[2] < 0 ? -1 : src
->i
[2] > 0 ? 1 : 0;
618 dst
->i
[3] = src
->i
[3] < 0 ? -1 : src
->i
[3] > 0 ? 1 : 0;
622 micro_sgt(union tgsi_exec_channel
*dst
,
623 const union tgsi_exec_channel
*src0
,
624 const union tgsi_exec_channel
*src1
)
626 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? 1.0f
: 0.0f
;
627 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? 1.0f
: 0.0f
;
628 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? 1.0f
: 0.0f
;
629 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? 1.0f
: 0.0f
;
633 micro_sin(union tgsi_exec_channel
*dst
,
634 const union tgsi_exec_channel
*src
)
636 dst
->f
[0] = sinf(src
->f
[0]);
637 dst
->f
[1] = sinf(src
->f
[1]);
638 dst
->f
[2] = sinf(src
->f
[2]);
639 dst
->f
[3] = sinf(src
->f
[3]);
643 micro_sle(union tgsi_exec_channel
*dst
,
644 const union tgsi_exec_channel
*src0
,
645 const union tgsi_exec_channel
*src1
)
647 dst
->f
[0] = src0
->f
[0] <= src1
->f
[0] ? 1.0f
: 0.0f
;
648 dst
->f
[1] = src0
->f
[1] <= src1
->f
[1] ? 1.0f
: 0.0f
;
649 dst
->f
[2] = src0
->f
[2] <= src1
->f
[2] ? 1.0f
: 0.0f
;
650 dst
->f
[3] = src0
->f
[3] <= src1
->f
[3] ? 1.0f
: 0.0f
;
654 micro_slt(union tgsi_exec_channel
*dst
,
655 const union tgsi_exec_channel
*src0
,
656 const union tgsi_exec_channel
*src1
)
658 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? 1.0f
: 0.0f
;
659 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? 1.0f
: 0.0f
;
660 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? 1.0f
: 0.0f
;
661 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? 1.0f
: 0.0f
;
665 micro_sne(union tgsi_exec_channel
*dst
,
666 const union tgsi_exec_channel
*src0
,
667 const union tgsi_exec_channel
*src1
)
669 dst
->f
[0] = src0
->f
[0] != src1
->f
[0] ? 1.0f
: 0.0f
;
670 dst
->f
[1] = src0
->f
[1] != src1
->f
[1] ? 1.0f
: 0.0f
;
671 dst
->f
[2] = src0
->f
[2] != src1
->f
[2] ? 1.0f
: 0.0f
;
672 dst
->f
[3] = src0
->f
[3] != src1
->f
[3] ? 1.0f
: 0.0f
;
676 micro_trunc(union tgsi_exec_channel
*dst
,
677 const union tgsi_exec_channel
*src
)
679 dst
->f
[0] = truncf(src
->f
[0]);
680 dst
->f
[1] = truncf(src
->f
[1]);
681 dst
->f
[2] = truncf(src
->f
[2]);
682 dst
->f
[3] = truncf(src
->f
[3]);
686 micro_u2d(union tgsi_double_channel
*dst
,
687 const union tgsi_exec_channel
*src
)
689 dst
->d
[0] = (double)src
->u
[0];
690 dst
->d
[1] = (double)src
->u
[1];
691 dst
->d
[2] = (double)src
->u
[2];
692 dst
->d
[3] = (double)src
->u
[3];
696 micro_i64abs(union tgsi_double_channel
*dst
,
697 const union tgsi_double_channel
*src
)
699 dst
->i64
[0] = src
->i64
[0] >= 0.0 ? src
->i64
[0] : -src
->i64
[0];
700 dst
->i64
[1] = src
->i64
[1] >= 0.0 ? src
->i64
[1] : -src
->i64
[1];
701 dst
->i64
[2] = src
->i64
[2] >= 0.0 ? src
->i64
[2] : -src
->i64
[2];
702 dst
->i64
[3] = src
->i64
[3] >= 0.0 ? src
->i64
[3] : -src
->i64
[3];
706 micro_i64sgn(union tgsi_double_channel
*dst
,
707 const union tgsi_double_channel
*src
)
709 dst
->i64
[0] = src
->i64
[0] < 0 ? -1 : src
->i64
[0] > 0 ? 1 : 0;
710 dst
->i64
[1] = src
->i64
[1] < 0 ? -1 : src
->i64
[1] > 0 ? 1 : 0;
711 dst
->i64
[2] = src
->i64
[2] < 0 ? -1 : src
->i64
[2] > 0 ? 1 : 0;
712 dst
->i64
[3] = src
->i64
[3] < 0 ? -1 : src
->i64
[3] > 0 ? 1 : 0;
716 micro_i64neg(union tgsi_double_channel
*dst
,
717 const union tgsi_double_channel
*src
)
719 dst
->i64
[0] = -src
->i64
[0];
720 dst
->i64
[1] = -src
->i64
[1];
721 dst
->i64
[2] = -src
->i64
[2];
722 dst
->i64
[3] = -src
->i64
[3];
726 micro_u64seq(union tgsi_double_channel
*dst
,
727 const union tgsi_double_channel
*src
)
729 dst
->u
[0][0] = src
[0].u64
[0] == src
[1].u64
[0] ? ~0U : 0U;
730 dst
->u
[1][0] = src
[0].u64
[1] == src
[1].u64
[1] ? ~0U : 0U;
731 dst
->u
[2][0] = src
[0].u64
[2] == src
[1].u64
[2] ? ~0U : 0U;
732 dst
->u
[3][0] = src
[0].u64
[3] == src
[1].u64
[3] ? ~0U : 0U;
736 micro_u64sne(union tgsi_double_channel
*dst
,
737 const union tgsi_double_channel
*src
)
739 dst
->u
[0][0] = src
[0].u64
[0] != src
[1].u64
[0] ? ~0U : 0U;
740 dst
->u
[1][0] = src
[0].u64
[1] != src
[1].u64
[1] ? ~0U : 0U;
741 dst
->u
[2][0] = src
[0].u64
[2] != src
[1].u64
[2] ? ~0U : 0U;
742 dst
->u
[3][0] = src
[0].u64
[3] != src
[1].u64
[3] ? ~0U : 0U;
746 micro_i64slt(union tgsi_double_channel
*dst
,
747 const union tgsi_double_channel
*src
)
749 dst
->u
[0][0] = src
[0].i64
[0] < src
[1].i64
[0] ? ~0U : 0U;
750 dst
->u
[1][0] = src
[0].i64
[1] < src
[1].i64
[1] ? ~0U : 0U;
751 dst
->u
[2][0] = src
[0].i64
[2] < src
[1].i64
[2] ? ~0U : 0U;
752 dst
->u
[3][0] = src
[0].i64
[3] < src
[1].i64
[3] ? ~0U : 0U;
756 micro_u64slt(union tgsi_double_channel
*dst
,
757 const union tgsi_double_channel
*src
)
759 dst
->u
[0][0] = src
[0].u64
[0] < src
[1].u64
[0] ? ~0U : 0U;
760 dst
->u
[1][0] = src
[0].u64
[1] < src
[1].u64
[1] ? ~0U : 0U;
761 dst
->u
[2][0] = src
[0].u64
[2] < src
[1].u64
[2] ? ~0U : 0U;
762 dst
->u
[3][0] = src
[0].u64
[3] < src
[1].u64
[3] ? ~0U : 0U;
766 micro_i64sge(union tgsi_double_channel
*dst
,
767 const union tgsi_double_channel
*src
)
769 dst
->u
[0][0] = src
[0].i64
[0] >= src
[1].i64
[0] ? ~0U : 0U;
770 dst
->u
[1][0] = src
[0].i64
[1] >= src
[1].i64
[1] ? ~0U : 0U;
771 dst
->u
[2][0] = src
[0].i64
[2] >= src
[1].i64
[2] ? ~0U : 0U;
772 dst
->u
[3][0] = src
[0].i64
[3] >= src
[1].i64
[3] ? ~0U : 0U;
776 micro_u64sge(union tgsi_double_channel
*dst
,
777 const union tgsi_double_channel
*src
)
779 dst
->u
[0][0] = src
[0].u64
[0] >= src
[1].u64
[0] ? ~0U : 0U;
780 dst
->u
[1][0] = src
[0].u64
[1] >= src
[1].u64
[1] ? ~0U : 0U;
781 dst
->u
[2][0] = src
[0].u64
[2] >= src
[1].u64
[2] ? ~0U : 0U;
782 dst
->u
[3][0] = src
[0].u64
[3] >= src
[1].u64
[3] ? ~0U : 0U;
786 micro_u64max(union tgsi_double_channel
*dst
,
787 const union tgsi_double_channel
*src
)
789 dst
->u64
[0] = src
[0].u64
[0] > src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
790 dst
->u64
[1] = src
[0].u64
[1] > src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
791 dst
->u64
[2] = src
[0].u64
[2] > src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
792 dst
->u64
[3] = src
[0].u64
[3] > src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
796 micro_i64max(union tgsi_double_channel
*dst
,
797 const union tgsi_double_channel
*src
)
799 dst
->i64
[0] = src
[0].i64
[0] > src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
800 dst
->i64
[1] = src
[0].i64
[1] > src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
801 dst
->i64
[2] = src
[0].i64
[2] > src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
802 dst
->i64
[3] = src
[0].i64
[3] > src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
806 micro_u64min(union tgsi_double_channel
*dst
,
807 const union tgsi_double_channel
*src
)
809 dst
->u64
[0] = src
[0].u64
[0] < src
[1].u64
[0] ? src
[0].u64
[0] : src
[1].u64
[0];
810 dst
->u64
[1] = src
[0].u64
[1] < src
[1].u64
[1] ? src
[0].u64
[1] : src
[1].u64
[1];
811 dst
->u64
[2] = src
[0].u64
[2] < src
[1].u64
[2] ? src
[0].u64
[2] : src
[1].u64
[2];
812 dst
->u64
[3] = src
[0].u64
[3] < src
[1].u64
[3] ? src
[0].u64
[3] : src
[1].u64
[3];
816 micro_i64min(union tgsi_double_channel
*dst
,
817 const union tgsi_double_channel
*src
)
819 dst
->i64
[0] = src
[0].i64
[0] < src
[1].i64
[0] ? src
[0].i64
[0] : src
[1].i64
[0];
820 dst
->i64
[1] = src
[0].i64
[1] < src
[1].i64
[1] ? src
[0].i64
[1] : src
[1].i64
[1];
821 dst
->i64
[2] = src
[0].i64
[2] < src
[1].i64
[2] ? src
[0].i64
[2] : src
[1].i64
[2];
822 dst
->i64
[3] = src
[0].i64
[3] < src
[1].i64
[3] ? src
[0].i64
[3] : src
[1].i64
[3];
826 micro_u64add(union tgsi_double_channel
*dst
,
827 const union tgsi_double_channel
*src
)
829 dst
->u64
[0] = src
[0].u64
[0] + src
[1].u64
[0];
830 dst
->u64
[1] = src
[0].u64
[1] + src
[1].u64
[1];
831 dst
->u64
[2] = src
[0].u64
[2] + src
[1].u64
[2];
832 dst
->u64
[3] = src
[0].u64
[3] + src
[1].u64
[3];
836 micro_u64mul(union tgsi_double_channel
*dst
,
837 const union tgsi_double_channel
*src
)
839 dst
->u64
[0] = src
[0].u64
[0] * src
[1].u64
[0];
840 dst
->u64
[1] = src
[0].u64
[1] * src
[1].u64
[1];
841 dst
->u64
[2] = src
[0].u64
[2] * src
[1].u64
[2];
842 dst
->u64
[3] = src
[0].u64
[3] * src
[1].u64
[3];
846 micro_u64div(union tgsi_double_channel
*dst
,
847 const union tgsi_double_channel
*src
)
849 dst
->u64
[0] = src
[0].u64
[0] / src
[1].u64
[0];
850 dst
->u64
[1] = src
[0].u64
[1] / src
[1].u64
[1];
851 dst
->u64
[2] = src
[0].u64
[2] / src
[1].u64
[2];
852 dst
->u64
[3] = src
[0].u64
[3] / src
[1].u64
[3];
856 micro_i64div(union tgsi_double_channel
*dst
,
857 const union tgsi_double_channel
*src
)
859 dst
->i64
[0] = src
[0].i64
[0] / src
[1].i64
[0];
860 dst
->i64
[1] = src
[0].i64
[1] / src
[1].i64
[1];
861 dst
->i64
[2] = src
[0].i64
[2] / src
[1].i64
[2];
862 dst
->i64
[3] = src
[0].i64
[3] / src
[1].i64
[3];
866 micro_u64mod(union tgsi_double_channel
*dst
,
867 const union tgsi_double_channel
*src
)
869 dst
->u64
[0] = src
[0].u64
[0] % src
[1].u64
[0];
870 dst
->u64
[1] = src
[0].u64
[1] % src
[1].u64
[1];
871 dst
->u64
[2] = src
[0].u64
[2] % src
[1].u64
[2];
872 dst
->u64
[3] = src
[0].u64
[3] % src
[1].u64
[3];
876 micro_i64mod(union tgsi_double_channel
*dst
,
877 const union tgsi_double_channel
*src
)
879 dst
->i64
[0] = src
[0].i64
[0] % src
[1].i64
[0];
880 dst
->i64
[1] = src
[0].i64
[1] % src
[1].i64
[1];
881 dst
->i64
[2] = src
[0].i64
[2] % src
[1].i64
[2];
882 dst
->i64
[3] = src
[0].i64
[3] % src
[1].i64
[3];
886 micro_u64shl(union tgsi_double_channel
*dst
,
887 const union tgsi_double_channel
*src0
,
888 union tgsi_exec_channel
*src1
)
890 unsigned masked_count
;
891 masked_count
= src1
->u
[0] & 0x3f;
892 dst
->u64
[0] = src0
->u64
[0] << masked_count
;
893 masked_count
= src1
->u
[1] & 0x3f;
894 dst
->u64
[1] = src0
->u64
[1] << masked_count
;
895 masked_count
= src1
->u
[2] & 0x3f;
896 dst
->u64
[2] = src0
->u64
[2] << masked_count
;
897 masked_count
= src1
->u
[3] & 0x3f;
898 dst
->u64
[3] = src0
->u64
[3] << masked_count
;
902 micro_i64shr(union tgsi_double_channel
*dst
,
903 const union tgsi_double_channel
*src0
,
904 union tgsi_exec_channel
*src1
)
906 unsigned masked_count
;
907 masked_count
= src1
->u
[0] & 0x3f;
908 dst
->i64
[0] = src0
->i64
[0] >> masked_count
;
909 masked_count
= src1
->u
[1] & 0x3f;
910 dst
->i64
[1] = src0
->i64
[1] >> masked_count
;
911 masked_count
= src1
->u
[2] & 0x3f;
912 dst
->i64
[2] = src0
->i64
[2] >> masked_count
;
913 masked_count
= src1
->u
[3] & 0x3f;
914 dst
->i64
[3] = src0
->i64
[3] >> masked_count
;
918 micro_u64shr(union tgsi_double_channel
*dst
,
919 const union tgsi_double_channel
*src0
,
920 union tgsi_exec_channel
*src1
)
922 unsigned masked_count
;
923 masked_count
= src1
->u
[0] & 0x3f;
924 dst
->u64
[0] = src0
->u64
[0] >> masked_count
;
925 masked_count
= src1
->u
[1] & 0x3f;
926 dst
->u64
[1] = src0
->u64
[1] >> masked_count
;
927 masked_count
= src1
->u
[2] & 0x3f;
928 dst
->u64
[2] = src0
->u64
[2] >> masked_count
;
929 masked_count
= src1
->u
[3] & 0x3f;
930 dst
->u64
[3] = src0
->u64
[3] >> masked_count
;
933 enum tgsi_exec_datatype
{
934 TGSI_EXEC_DATA_FLOAT
,
937 TGSI_EXEC_DATA_DOUBLE
,
938 TGSI_EXEC_DATA_INT64
,
939 TGSI_EXEC_DATA_UINT64
,
943 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
945 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
946 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
947 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
948 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
949 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
950 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
953 /** The execution mask depends on the conditional mask and the loop mask */
954 #define UPDATE_EXEC_MASK(MACH) \
955 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
958 static const union tgsi_exec_channel ZeroVec
=
959 { { 0.0, 0.0, 0.0, 0.0 } };
961 static const union tgsi_exec_channel OneVec
= {
962 {1.0f
, 1.0f
, 1.0f
, 1.0f
}
965 static const union tgsi_exec_channel P128Vec
= {
966 {128.0f
, 128.0f
, 128.0f
, 128.0f
}
969 static const union tgsi_exec_channel M128Vec
= {
970 {-128.0f
, -128.0f
, -128.0f
, -128.0f
}
975 * Assert that none of the float values in 'chan' are infinite or NaN.
976 * NaN and Inf may occur normally during program execution and should
977 * not lead to crashes, etc. But when debugging, it's helpful to catch
981 check_inf_or_nan(const union tgsi_exec_channel
*chan
)
983 assert(!util_is_inf_or_nan((chan
)->f
[0]));
984 assert(!util_is_inf_or_nan((chan
)->f
[1]));
985 assert(!util_is_inf_or_nan((chan
)->f
[2]));
986 assert(!util_is_inf_or_nan((chan
)->f
[3]));
992 print_chan(const char *msg
, const union tgsi_exec_channel
*chan
)
994 debug_printf("%s = {%f, %f, %f, %f}\n",
995 msg
, chan
->f
[0], chan
->f
[1], chan
->f
[2], chan
->f
[3]);
1002 print_temp(const struct tgsi_exec_machine
*mach
, uint index
)
1004 const struct tgsi_exec_vector
*tmp
= &mach
->Temps
[index
];
1006 debug_printf("Temp[%u] =\n", index
);
1007 for (i
= 0; i
< 4; i
++) {
1008 debug_printf(" %c: { %f, %f, %f, %f }\n",
1020 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine
*mach
,
1023 const unsigned *buf_sizes
)
1027 for (i
= 0; i
< num_bufs
; i
++) {
1028 mach
->Consts
[i
] = bufs
[i
];
1029 mach
->ConstsSize
[i
] = buf_sizes
[i
];
1035 * Check if there's a potential src/dst register data dependency when
1036 * using SOA execution.
1039 * This would expand into:
1044 * The second instruction will have the wrong value for t0 if executed as-is.
1047 tgsi_check_soa_dependencies(const struct tgsi_full_instruction
*inst
)
1051 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
1052 if (writemask
== TGSI_WRITEMASK_X
||
1053 writemask
== TGSI_WRITEMASK_Y
||
1054 writemask
== TGSI_WRITEMASK_Z
||
1055 writemask
== TGSI_WRITEMASK_W
||
1056 writemask
== TGSI_WRITEMASK_NONE
) {
1057 /* no chance of data dependency */
1061 /* loop over src regs */
1062 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1063 if ((inst
->Src
[i
].Register
.File
==
1064 inst
->Dst
[0].Register
.File
) &&
1065 ((inst
->Src
[i
].Register
.Index
==
1066 inst
->Dst
[0].Register
.Index
) ||
1067 inst
->Src
[i
].Register
.Indirect
||
1068 inst
->Dst
[0].Register
.Indirect
)) {
1069 /* loop over dest channels */
1070 uint channelsWritten
= 0x0;
1071 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1072 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
1073 /* check if we're reading a channel that's been written */
1074 uint swizzle
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[i
], chan
);
1075 if (channelsWritten
& (1 << swizzle
)) {
1079 channelsWritten
|= (1 << chan
);
1089 * Initialize machine state by expanding tokens to full instructions,
1090 * allocating temporary storage, setting up constants, etc.
1091 * After this, we can call tgsi_exec_machine_run() many times.
1094 tgsi_exec_machine_bind_shader(
1095 struct tgsi_exec_machine
*mach
,
1096 const struct tgsi_token
*tokens
,
1097 struct tgsi_sampler
*sampler
,
1098 struct tgsi_image
*image
,
1099 struct tgsi_buffer
*buffer
)
1102 struct tgsi_parse_context parse
;
1103 struct tgsi_full_instruction
*instructions
;
1104 struct tgsi_full_declaration
*declarations
;
1105 uint maxInstructions
= 10, numInstructions
= 0;
1106 uint maxDeclarations
= 10, numDeclarations
= 0;
1109 tgsi_dump(tokens
, 0);
1115 mach
->Tokens
= tokens
;
1116 mach
->Sampler
= sampler
;
1117 mach
->Image
= image
;
1118 mach
->Buffer
= buffer
;
1121 /* unbind and free all */
1122 FREE(mach
->Declarations
);
1123 mach
->Declarations
= NULL
;
1124 mach
->NumDeclarations
= 0;
1126 FREE(mach
->Instructions
);
1127 mach
->Instructions
= NULL
;
1128 mach
->NumInstructions
= 0;
1133 k
= tgsi_parse_init (&parse
, mach
->Tokens
);
1134 if (k
!= TGSI_PARSE_OK
) {
1135 debug_printf( "Problem parsing!\n" );
1140 mach
->NumOutputs
= 0;
1142 for (k
= 0; k
< TGSI_SEMANTIC_COUNT
; k
++)
1143 mach
->SysSemanticToIndex
[k
] = -1;
1145 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
&&
1146 !mach
->UsedGeometryShader
) {
1147 struct tgsi_exec_vector
*inputs
;
1148 struct tgsi_exec_vector
*outputs
;
1150 inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1151 TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_SHADER_INPUTS
,
1157 outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) *
1158 TGSI_MAX_TOTAL_VERTICES
, 16);
1165 align_free(mach
->Inputs
);
1166 align_free(mach
->Outputs
);
1168 mach
->Inputs
= inputs
;
1169 mach
->Outputs
= outputs
;
1170 mach
->UsedGeometryShader
= TRUE
;
1173 declarations
= (struct tgsi_full_declaration
*)
1174 MALLOC( maxDeclarations
* sizeof(struct tgsi_full_declaration
) );
1176 if (!declarations
) {
1180 instructions
= (struct tgsi_full_instruction
*)
1181 MALLOC( maxInstructions
* sizeof(struct tgsi_full_instruction
) );
1183 if (!instructions
) {
1184 FREE( declarations
);
1188 while( !tgsi_parse_end_of_tokens( &parse
) ) {
1191 tgsi_parse_token( &parse
);
1192 switch( parse
.FullToken
.Token
.Type
) {
1193 case TGSI_TOKEN_TYPE_DECLARATION
:
1194 /* save expanded declaration */
1195 if (numDeclarations
== maxDeclarations
) {
1196 declarations
= REALLOC(declarations
,
1198 * sizeof(struct tgsi_full_declaration
),
1199 (maxDeclarations
+ 10)
1200 * sizeof(struct tgsi_full_declaration
));
1201 maxDeclarations
+= 10;
1203 if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_OUTPUT
) {
1205 for (reg
= parse
.FullToken
.FullDeclaration
.Range
.First
;
1206 reg
<= parse
.FullToken
.FullDeclaration
.Range
.Last
;
1211 else if (parse
.FullToken
.FullDeclaration
.Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1212 const struct tgsi_full_declaration
*decl
= &parse
.FullToken
.FullDeclaration
;
1213 mach
->SysSemanticToIndex
[decl
->Semantic
.Name
] = decl
->Range
.First
;
1216 memcpy(declarations
+ numDeclarations
,
1217 &parse
.FullToken
.FullDeclaration
,
1218 sizeof(declarations
[0]));
1222 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1224 uint size
= parse
.FullToken
.FullImmediate
.Immediate
.NrTokens
- 1;
1225 assert( size
<= 4 );
1226 assert( mach
->ImmLimit
+ 1 <= TGSI_EXEC_NUM_IMMEDIATES
);
1228 for( i
= 0; i
< size
; i
++ ) {
1229 mach
->Imms
[mach
->ImmLimit
][i
] =
1230 parse
.FullToken
.FullImmediate
.u
[i
].Float
;
1232 mach
->ImmLimit
+= 1;
1236 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1238 /* save expanded instruction */
1239 if (numInstructions
== maxInstructions
) {
1240 instructions
= REALLOC(instructions
,
1242 * sizeof(struct tgsi_full_instruction
),
1243 (maxInstructions
+ 10)
1244 * sizeof(struct tgsi_full_instruction
));
1245 maxInstructions
+= 10;
1248 memcpy(instructions
+ numInstructions
,
1249 &parse
.FullToken
.FullInstruction
,
1250 sizeof(instructions
[0]));
1255 case TGSI_TOKEN_TYPE_PROPERTY
:
1256 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
1257 if (parse
.FullToken
.FullProperty
.Property
.PropertyName
== TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
) {
1258 mach
->MaxOutputVertices
= parse
.FullToken
.FullProperty
.u
[0].Data
;
1267 tgsi_parse_free (&parse
);
1269 FREE(mach
->Declarations
);
1270 mach
->Declarations
= declarations
;
1271 mach
->NumDeclarations
= numDeclarations
;
1273 FREE(mach
->Instructions
);
1274 mach
->Instructions
= instructions
;
1275 mach
->NumInstructions
= numInstructions
;
1279 struct tgsi_exec_machine
*
1280 tgsi_exec_machine_create(enum pipe_shader_type shader_type
)
1282 struct tgsi_exec_machine
*mach
;
1285 mach
= align_malloc( sizeof *mach
, 16 );
1289 memset(mach
, 0, sizeof(*mach
));
1291 mach
->ShaderType
= shader_type
;
1292 mach
->Addrs
= &mach
->Temps
[TGSI_EXEC_TEMP_ADDR
];
1293 mach
->MaxGeometryShaderOutputs
= TGSI_MAX_TOTAL_VERTICES
;
1294 mach
->Predicates
= &mach
->Temps
[TGSI_EXEC_TEMP_P0
];
1296 if (shader_type
!= PIPE_SHADER_COMPUTE
) {
1297 mach
->Inputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_INPUTS
, 16);
1298 mach
->Outputs
= align_malloc(sizeof(struct tgsi_exec_vector
) * PIPE_MAX_SHADER_OUTPUTS
, 16);
1299 if (!mach
->Inputs
|| !mach
->Outputs
)
1303 /* Setup constants needed by the SSE2 executor. */
1304 for( i
= 0; i
< 4; i
++ ) {
1305 mach
->Temps
[TGSI_EXEC_TEMP_00000000_I
].xyzw
[TGSI_EXEC_TEMP_00000000_C
].u
[i
] = 0x00000000;
1306 mach
->Temps
[TGSI_EXEC_TEMP_7FFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_7FFFFFFF_C
].u
[i
] = 0x7FFFFFFF;
1307 mach
->Temps
[TGSI_EXEC_TEMP_80000000_I
].xyzw
[TGSI_EXEC_TEMP_80000000_C
].u
[i
] = 0x80000000;
1308 mach
->Temps
[TGSI_EXEC_TEMP_FFFFFFFF_I
].xyzw
[TGSI_EXEC_TEMP_FFFFFFFF_C
].u
[i
] = 0xFFFFFFFF; /* not used */
1309 mach
->Temps
[TGSI_EXEC_TEMP_ONE_I
].xyzw
[TGSI_EXEC_TEMP_ONE_C
].f
[i
] = 1.0f
;
1310 mach
->Temps
[TGSI_EXEC_TEMP_TWO_I
].xyzw
[TGSI_EXEC_TEMP_TWO_C
].f
[i
] = 2.0f
; /* not used */
1311 mach
->Temps
[TGSI_EXEC_TEMP_128_I
].xyzw
[TGSI_EXEC_TEMP_128_C
].f
[i
] = 128.0f
;
1312 mach
->Temps
[TGSI_EXEC_TEMP_MINUS_128_I
].xyzw
[TGSI_EXEC_TEMP_MINUS_128_C
].f
[i
] = -128.0f
;
1313 mach
->Temps
[TGSI_EXEC_TEMP_THREE_I
].xyzw
[TGSI_EXEC_TEMP_THREE_C
].f
[i
] = 3.0f
;
1314 mach
->Temps
[TGSI_EXEC_TEMP_HALF_I
].xyzw
[TGSI_EXEC_TEMP_HALF_C
].f
[i
] = 0.5f
;
1318 /* silence warnings */
1327 align_free(mach
->Inputs
);
1328 align_free(mach
->Outputs
);
1336 tgsi_exec_machine_destroy(struct tgsi_exec_machine
*mach
)
1339 FREE(mach
->Instructions
);
1340 FREE(mach
->Declarations
);
1342 align_free(mach
->Inputs
);
1343 align_free(mach
->Outputs
);
1350 micro_add(union tgsi_exec_channel
*dst
,
1351 const union tgsi_exec_channel
*src0
,
1352 const union tgsi_exec_channel
*src1
)
1354 dst
->f
[0] = src0
->f
[0] + src1
->f
[0];
1355 dst
->f
[1] = src0
->f
[1] + src1
->f
[1];
1356 dst
->f
[2] = src0
->f
[2] + src1
->f
[2];
1357 dst
->f
[3] = src0
->f
[3] + src1
->f
[3];
1362 union tgsi_exec_channel
*dst
,
1363 const union tgsi_exec_channel
*src0
,
1364 const union tgsi_exec_channel
*src1
)
1366 if (src1
->f
[0] != 0) {
1367 dst
->f
[0] = src0
->f
[0] / src1
->f
[0];
1369 if (src1
->f
[1] != 0) {
1370 dst
->f
[1] = src0
->f
[1] / src1
->f
[1];
1372 if (src1
->f
[2] != 0) {
1373 dst
->f
[2] = src0
->f
[2] / src1
->f
[2];
1375 if (src1
->f
[3] != 0) {
1376 dst
->f
[3] = src0
->f
[3] / src1
->f
[3];
1382 union tgsi_exec_channel
*dst
,
1383 const union tgsi_exec_channel
*src0
,
1384 const union tgsi_exec_channel
*src1
,
1385 const union tgsi_exec_channel
*src2
,
1386 const union tgsi_exec_channel
*src3
)
1388 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src2
->f
[0] : src3
->f
[0];
1389 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src2
->f
[1] : src3
->f
[1];
1390 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src2
->f
[2] : src3
->f
[2];
1391 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src2
->f
[3] : src3
->f
[3];
1395 micro_max(union tgsi_exec_channel
*dst
,
1396 const union tgsi_exec_channel
*src0
,
1397 const union tgsi_exec_channel
*src1
)
1399 dst
->f
[0] = src0
->f
[0] > src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1400 dst
->f
[1] = src0
->f
[1] > src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1401 dst
->f
[2] = src0
->f
[2] > src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1402 dst
->f
[3] = src0
->f
[3] > src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1406 micro_min(union tgsi_exec_channel
*dst
,
1407 const union tgsi_exec_channel
*src0
,
1408 const union tgsi_exec_channel
*src1
)
1410 dst
->f
[0] = src0
->f
[0] < src1
->f
[0] ? src0
->f
[0] : src1
->f
[0];
1411 dst
->f
[1] = src0
->f
[1] < src1
->f
[1] ? src0
->f
[1] : src1
->f
[1];
1412 dst
->f
[2] = src0
->f
[2] < src1
->f
[2] ? src0
->f
[2] : src1
->f
[2];
1413 dst
->f
[3] = src0
->f
[3] < src1
->f
[3] ? src0
->f
[3] : src1
->f
[3];
1417 micro_mul(union tgsi_exec_channel
*dst
,
1418 const union tgsi_exec_channel
*src0
,
1419 const union tgsi_exec_channel
*src1
)
1421 dst
->f
[0] = src0
->f
[0] * src1
->f
[0];
1422 dst
->f
[1] = src0
->f
[1] * src1
->f
[1];
1423 dst
->f
[2] = src0
->f
[2] * src1
->f
[2];
1424 dst
->f
[3] = src0
->f
[3] * src1
->f
[3];
1429 union tgsi_exec_channel
*dst
,
1430 const union tgsi_exec_channel
*src
)
1432 dst
->f
[0] = -src
->f
[0];
1433 dst
->f
[1] = -src
->f
[1];
1434 dst
->f
[2] = -src
->f
[2];
1435 dst
->f
[3] = -src
->f
[3];
1440 union tgsi_exec_channel
*dst
,
1441 const union tgsi_exec_channel
*src0
,
1442 const union tgsi_exec_channel
*src1
)
1445 dst
->f
[0] = util_fast_pow( src0
->f
[0], src1
->f
[0] );
1446 dst
->f
[1] = util_fast_pow( src0
->f
[1], src1
->f
[1] );
1447 dst
->f
[2] = util_fast_pow( src0
->f
[2], src1
->f
[2] );
1448 dst
->f
[3] = util_fast_pow( src0
->f
[3], src1
->f
[3] );
1450 dst
->f
[0] = powf( src0
->f
[0], src1
->f
[0] );
1451 dst
->f
[1] = powf( src0
->f
[1], src1
->f
[1] );
1452 dst
->f
[2] = powf( src0
->f
[2], src1
->f
[2] );
1453 dst
->f
[3] = powf( src0
->f
[3], src1
->f
[3] );
1458 micro_sub(union tgsi_exec_channel
*dst
,
1459 const union tgsi_exec_channel
*src0
,
1460 const union tgsi_exec_channel
*src1
)
1462 dst
->f
[0] = src0
->f
[0] - src1
->f
[0];
1463 dst
->f
[1] = src0
->f
[1] - src1
->f
[1];
1464 dst
->f
[2] = src0
->f
[2] - src1
->f
[2];
1465 dst
->f
[3] = src0
->f
[3] - src1
->f
[3];
1469 fetch_src_file_channel(const struct tgsi_exec_machine
*mach
,
1470 const uint chan_index
,
1473 const union tgsi_exec_channel
*index
,
1474 const union tgsi_exec_channel
*index2D
,
1475 union tgsi_exec_channel
*chan
)
1479 assert(swizzle
< 4);
1482 case TGSI_FILE_CONSTANT
:
1483 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1484 assert(index2D
->i
[i
] >= 0 && index2D
->i
[i
] < PIPE_MAX_CONSTANT_BUFFERS
);
1485 assert(mach
->Consts
[index2D
->i
[i
]]);
1487 if (index
->i
[i
] < 0) {
1490 /* NOTE: copying the const value as a uint instead of float */
1491 const uint constbuf
= index2D
->i
[i
];
1492 const uint
*buf
= (const uint
*)mach
->Consts
[constbuf
];
1493 const int pos
= index
->i
[i
] * 4 + swizzle
;
1494 /* const buffer bounds check */
1495 if (pos
< 0 || pos
>= (int) mach
->ConstsSize
[constbuf
]) {
1497 /* Debug: print warning */
1498 static int count
= 0;
1500 debug_printf("TGSI Exec: const buffer index %d"
1501 " out of bounds\n", pos
);
1506 chan
->u
[i
] = buf
[pos
];
1511 case TGSI_FILE_INPUT
:
1512 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1514 if (PIPE_SHADER_GEOMETRY == mach->ShaderType) {
1515 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1516 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1517 index2D->i[i], index->i[i]);
1519 int pos
= index2D
->i
[i
] * TGSI_EXEC_MAX_INPUT_ATTRIBS
+ index
->i
[i
];
1521 assert(pos
< TGSI_MAX_PRIM_VERTICES
* PIPE_MAX_ATTRIBS
);
1522 chan
->u
[i
] = mach
->Inputs
[pos
].xyzw
[swizzle
].u
[i
];
1526 case TGSI_FILE_SYSTEM_VALUE
:
1527 /* XXX no swizzling at this point. Will be needed if we put
1528 * gl_FragCoord, for example, in a sys value register.
1530 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1531 chan
->u
[i
] = mach
->SystemValue
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1535 case TGSI_FILE_TEMPORARY
:
1536 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1537 assert(index
->i
[i
] < TGSI_EXEC_NUM_TEMPS
);
1538 assert(index2D
->i
[i
] == 0);
1540 chan
->u
[i
] = mach
->Temps
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1544 case TGSI_FILE_IMMEDIATE
:
1545 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1546 assert(index
->i
[i
] >= 0 && index
->i
[i
] < (int)mach
->ImmLimit
);
1547 assert(index2D
->i
[i
] == 0);
1549 chan
->f
[i
] = mach
->Imms
[index
->i
[i
]][swizzle
];
1553 case TGSI_FILE_ADDRESS
:
1554 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1555 assert(index
->i
[i
] >= 0);
1556 assert(index2D
->i
[i
] == 0);
1558 chan
->u
[i
] = mach
->Addrs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1562 case TGSI_FILE_PREDICATE
:
1563 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1564 assert(index
->i
[i
] >= 0 && index
->i
[i
] < TGSI_EXEC_NUM_PREDS
);
1565 assert(index2D
->i
[i
] == 0);
1567 chan
->u
[i
] = mach
->Predicates
[0].xyzw
[swizzle
].u
[i
];
1571 case TGSI_FILE_OUTPUT
:
1572 /* vertex/fragment output vars can be read too */
1573 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1574 assert(index
->i
[i
] >= 0);
1575 assert(index2D
->i
[i
] == 0);
1577 chan
->u
[i
] = mach
->Outputs
[index
->i
[i
]].xyzw
[swizzle
].u
[i
];
1583 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1590 fetch_source_d(const struct tgsi_exec_machine
*mach
,
1591 union tgsi_exec_channel
*chan
,
1592 const struct tgsi_full_src_register
*reg
,
1593 const uint chan_index
,
1594 enum tgsi_exec_datatype src_datatype
)
1596 union tgsi_exec_channel index
;
1597 union tgsi_exec_channel index2D
;
1600 /* We start with a direct index into a register file.
1604 * file = Register.File
1605 * [1] = Register.Index
1610 index
.i
[3] = reg
->Register
.Index
;
1612 /* There is an extra source register that indirectly subscripts
1613 * a register file. The direct index now becomes an offset
1614 * that is being added to the indirect register.
1618 * ind = Indirect.File
1619 * [2] = Indirect.Index
1620 * .x = Indirect.SwizzleX
1622 if (reg
->Register
.Indirect
) {
1623 union tgsi_exec_channel index2
;
1624 union tgsi_exec_channel indir_index
;
1625 const uint execmask
= mach
->ExecMask
;
1628 /* which address register (always zero now) */
1632 index2
.i
[3] = reg
->Indirect
.Index
;
1633 /* get current value of address register[swizzle] */
1634 swizzle
= reg
->Indirect
.Swizzle
;
1635 fetch_src_file_channel(mach
,
1643 /* add value of address register to the offset */
1644 index
.i
[0] += indir_index
.i
[0];
1645 index
.i
[1] += indir_index
.i
[1];
1646 index
.i
[2] += indir_index
.i
[2];
1647 index
.i
[3] += indir_index
.i
[3];
1649 /* for disabled execution channels, zero-out the index to
1650 * avoid using a potential garbage value.
1652 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1653 if ((execmask
& (1 << i
)) == 0)
1658 /* There is an extra source register that is a second
1659 * subscript to a register file. Effectively it means that
1660 * the register file is actually a 2D array of registers.
1664 * [3] = Dimension.Index
1666 if (reg
->Register
.Dimension
) {
1670 index2D
.i
[3] = reg
->Dimension
.Index
;
1672 /* Again, the second subscript index can be addressed indirectly
1673 * identically to the first one.
1674 * Nothing stops us from indirectly addressing the indirect register,
1675 * but there is no need for that, so we won't exercise it.
1677 * file[ind[4].y+3][1],
1679 * ind = DimIndirect.File
1680 * [4] = DimIndirect.Index
1681 * .y = DimIndirect.SwizzleX
1683 if (reg
->Dimension
.Indirect
) {
1684 union tgsi_exec_channel index2
;
1685 union tgsi_exec_channel indir_index
;
1686 const uint execmask
= mach
->ExecMask
;
1692 index2
.i
[3] = reg
->DimIndirect
.Index
;
1694 swizzle
= reg
->DimIndirect
.Swizzle
;
1695 fetch_src_file_channel(mach
,
1697 reg
->DimIndirect
.File
,
1703 index2D
.i
[0] += indir_index
.i
[0];
1704 index2D
.i
[1] += indir_index
.i
[1];
1705 index2D
.i
[2] += indir_index
.i
[2];
1706 index2D
.i
[3] += indir_index
.i
[3];
1708 /* for disabled execution channels, zero-out the index to
1709 * avoid using a potential garbage value.
1711 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1712 if ((execmask
& (1 << i
)) == 0) {
1718 /* If by any chance there was a need for a 3D array of register
1719 * files, we would have to check whether Dimension is followed
1720 * by a dimension register and continue the saga.
1729 swizzle
= tgsi_util_get_full_src_register_swizzle( reg
, chan_index
);
1730 fetch_src_file_channel(mach
,
1740 fetch_source(const struct tgsi_exec_machine
*mach
,
1741 union tgsi_exec_channel
*chan
,
1742 const struct tgsi_full_src_register
*reg
,
1743 const uint chan_index
,
1744 enum tgsi_exec_datatype src_datatype
)
1746 fetch_source_d(mach
, chan
, reg
, chan_index
, src_datatype
);
1748 if (reg
->Register
.Absolute
) {
1749 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1750 micro_abs(chan
, chan
);
1752 micro_iabs(chan
, chan
);
1756 if (reg
->Register
.Negate
) {
1757 if (src_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1758 micro_neg(chan
, chan
);
1760 micro_ineg(chan
, chan
);
1765 static union tgsi_exec_channel
*
1766 store_dest_dstret(struct tgsi_exec_machine
*mach
,
1767 const union tgsi_exec_channel
*chan
,
1768 const struct tgsi_full_dst_register
*reg
,
1769 const struct tgsi_full_instruction
*inst
,
1771 enum tgsi_exec_datatype dst_datatype
)
1774 static union tgsi_exec_channel null
;
1775 union tgsi_exec_channel
*dst
;
1776 union tgsi_exec_channel index2D
;
1777 uint execmask
= mach
->ExecMask
;
1778 int offset
= 0; /* indirection offset */
1782 if (0 && dst_datatype
== TGSI_EXEC_DATA_FLOAT
) {
1783 check_inf_or_nan(chan
);
1786 /* There is an extra source register that indirectly subscripts
1787 * a register file. The direct index now becomes an offset
1788 * that is being added to the indirect register.
1792 * ind = Indirect.File
1793 * [2] = Indirect.Index
1794 * .x = Indirect.SwizzleX
1796 if (reg
->Register
.Indirect
) {
1797 union tgsi_exec_channel index
;
1798 union tgsi_exec_channel indir_index
;
1801 /* which address register (always zero for now) */
1805 index
.i
[3] = reg
->Indirect
.Index
;
1807 /* get current value of address register[swizzle] */
1808 swizzle
= reg
->Indirect
.Swizzle
;
1810 /* fetch values from the address/indirection register */
1811 fetch_src_file_channel(mach
,
1819 /* save indirection offset */
1820 offset
= indir_index
.i
[0];
1823 /* There is an extra source register that is a second
1824 * subscript to a register file. Effectively it means that
1825 * the register file is actually a 2D array of registers.
1829 * [3] = Dimension.Index
1831 if (reg
->Register
.Dimension
) {
1835 index2D
.i
[3] = reg
->Dimension
.Index
;
1837 /* Again, the second subscript index can be addressed indirectly
1838 * identically to the first one.
1839 * Nothing stops us from indirectly addressing the indirect register,
1840 * but there is no need for that, so we won't exercise it.
1842 * file[ind[4].y+3][1],
1844 * ind = DimIndirect.File
1845 * [4] = DimIndirect.Index
1846 * .y = DimIndirect.SwizzleX
1848 if (reg
->Dimension
.Indirect
) {
1849 union tgsi_exec_channel index2
;
1850 union tgsi_exec_channel indir_index
;
1851 const uint execmask
= mach
->ExecMask
;
1858 index2
.i
[3] = reg
->DimIndirect
.Index
;
1860 swizzle
= reg
->DimIndirect
.Swizzle
;
1861 fetch_src_file_channel(mach
,
1863 reg
->DimIndirect
.File
,
1869 index2D
.i
[0] += indir_index
.i
[0];
1870 index2D
.i
[1] += indir_index
.i
[1];
1871 index2D
.i
[2] += indir_index
.i
[2];
1872 index2D
.i
[3] += indir_index
.i
[3];
1874 /* for disabled execution channels, zero-out the index to
1875 * avoid using a potential garbage value.
1877 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1878 if ((execmask
& (1 << i
)) == 0) {
1884 /* If by any chance there was a need for a 3D array of register
1885 * files, we would have to check whether Dimension is followed
1886 * by a dimension register and continue the saga.
1895 switch (reg
->Register
.File
) {
1896 case TGSI_FILE_NULL
:
1900 case TGSI_FILE_OUTPUT
:
1901 index
= mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0]
1902 + reg
->Register
.Index
;
1903 dst
= &mach
->Outputs
[offset
+ index
].xyzw
[chan_index
];
1905 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1906 mach
->NumOutputs
, mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0],
1907 reg
->Register
.Index
);
1908 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
1909 debug_printf("STORING OUT[%d] mask(%d), = (", offset
+ index
, execmask
);
1910 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
1911 if (execmask
& (1 << i
))
1912 debug_printf("%f, ", chan
->f
[i
]);
1913 debug_printf(")\n");
1918 case TGSI_FILE_TEMPORARY
:
1919 index
= reg
->Register
.Index
;
1920 assert( index
< TGSI_EXEC_NUM_TEMPS
);
1921 dst
= &mach
->Temps
[offset
+ index
].xyzw
[chan_index
];
1924 case TGSI_FILE_ADDRESS
:
1925 index
= reg
->Register
.Index
;
1926 dst
= &mach
->Addrs
[index
].xyzw
[chan_index
];
1929 case TGSI_FILE_PREDICATE
:
1930 index
= reg
->Register
.Index
;
1931 assert(index
< TGSI_EXEC_NUM_PREDS
);
1932 dst
= &mach
->Predicates
[index
].xyzw
[chan_index
];
1940 if (inst
->Instruction
.Predicate
) {
1942 union tgsi_exec_channel
*pred
;
1944 switch (chan_index
) {
1946 swizzle
= inst
->Predicate
.SwizzleX
;
1949 swizzle
= inst
->Predicate
.SwizzleY
;
1952 swizzle
= inst
->Predicate
.SwizzleZ
;
1955 swizzle
= inst
->Predicate
.SwizzleW
;
1962 assert(inst
->Predicate
.Index
== 0);
1964 pred
= &mach
->Predicates
[inst
->Predicate
.Index
].xyzw
[swizzle
];
1966 if (inst
->Predicate
.Negate
) {
1967 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1969 execmask
&= ~(1 << i
);
1973 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
1975 execmask
&= ~(1 << i
);
1985 store_dest_double(struct tgsi_exec_machine
*mach
,
1986 const union tgsi_exec_channel
*chan
,
1987 const struct tgsi_full_dst_register
*reg
,
1988 const struct tgsi_full_instruction
*inst
,
1990 enum tgsi_exec_datatype dst_datatype
)
1992 union tgsi_exec_channel
*dst
;
1993 const uint execmask
= mach
->ExecMask
;
1996 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
2002 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2003 if (execmask
& (1 << i
))
2004 dst
->i
[i
] = chan
->i
[i
];
2008 store_dest(struct tgsi_exec_machine
*mach
,
2009 const union tgsi_exec_channel
*chan
,
2010 const struct tgsi_full_dst_register
*reg
,
2011 const struct tgsi_full_instruction
*inst
,
2013 enum tgsi_exec_datatype dst_datatype
)
2015 union tgsi_exec_channel
*dst
;
2016 const uint execmask
= mach
->ExecMask
;
2019 dst
= store_dest_dstret(mach
, chan
, reg
, inst
, chan_index
,
2024 if (!inst
->Instruction
.Saturate
) {
2025 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2026 if (execmask
& (1 << i
))
2027 dst
->i
[i
] = chan
->i
[i
];
2030 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
2031 if (execmask
& (1 << i
)) {
2032 if (chan
->f
[i
] < 0.0f
)
2034 else if (chan
->f
[i
] > 1.0f
)
2037 dst
->i
[i
] = chan
->i
[i
];
2042 #define FETCH(VAL,INDEX,CHAN)\
2043 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
2045 #define IFETCH(VAL,INDEX,CHAN)\
2046 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
2050 * Execute ARB-style KIL which is predicated by a src register.
2051 * Kill fragment if any of the four values is less than zero.
2054 exec_kill_if(struct tgsi_exec_machine
*mach
,
2055 const struct tgsi_full_instruction
*inst
)
2059 uint kilmask
= 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2060 union tgsi_exec_channel r
[1];
2062 /* This mask stores component bits that were already tested. */
2065 for (chan_index
= 0; chan_index
< 4; chan_index
++)
2070 /* unswizzle channel */
2071 swizzle
= tgsi_util_get_full_src_register_swizzle (
2075 /* check if the component has not been already tested */
2076 if (uniquemask
& (1 << swizzle
))
2078 uniquemask
|= 1 << swizzle
;
2080 FETCH(&r
[0], 0, chan_index
);
2081 for (i
= 0; i
< 4; i
++)
2082 if (r
[0].f
[i
] < 0.0f
)
2086 /* restrict to fragments currently executing */
2087 kilmask
&= mach
->ExecMask
;
2089 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2093 * Unconditional fragment kill/discard.
2096 exec_kill(struct tgsi_exec_machine
*mach
,
2097 const struct tgsi_full_instruction
*inst
)
2099 uint kilmask
; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
2101 /* kill fragment for all fragments currently executing */
2102 kilmask
= mach
->ExecMask
;
2103 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] |= kilmask
;
2107 emit_vertex(struct tgsi_exec_machine
*mach
)
2109 /* FIXME: check for exec mask correctly
2111 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2112 if ((mach->ExecMask & (1 << i)))
2114 if (mach
->ExecMask
) {
2115 if (mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]] >= mach
->MaxOutputVertices
)
2118 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] += mach
->NumOutputs
;
2119 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]]++;
2124 emit_primitive(struct tgsi_exec_machine
*mach
)
2126 unsigned *prim_count
= &mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0];
2127 /* FIXME: check for exec mask correctly
2129 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
2130 if ((mach->ExecMask & (1 << i)))
2132 if (mach
->ExecMask
) {
2134 debug_assert((*prim_count
* mach
->NumOutputs
) < mach
->MaxGeometryShaderOutputs
);
2135 mach
->Primitives
[*prim_count
] = 0;
2140 conditional_emit_primitive(struct tgsi_exec_machine
*mach
)
2142 if (PIPE_SHADER_GEOMETRY
== mach
->ShaderType
) {
2144 mach
->Primitives
[mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0]];
2145 if (emitted_verts
) {
2146 emit_primitive(mach
);
2153 * Fetch four texture samples using STR texture coordinates.
2156 fetch_texel( struct tgsi_sampler
*sampler
,
2157 const unsigned sview_idx
,
2158 const unsigned sampler_idx
,
2159 const union tgsi_exec_channel
*s
,
2160 const union tgsi_exec_channel
*t
,
2161 const union tgsi_exec_channel
*p
,
2162 const union tgsi_exec_channel
*c0
,
2163 const union tgsi_exec_channel
*c1
,
2164 float derivs
[3][2][TGSI_QUAD_SIZE
],
2165 const int8_t offset
[3],
2166 enum tgsi_sampler_control control
,
2167 union tgsi_exec_channel
*r
,
2168 union tgsi_exec_channel
*g
,
2169 union tgsi_exec_channel
*b
,
2170 union tgsi_exec_channel
*a
)
2173 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2175 /* FIXME: handle explicit derivs, offsets */
2176 sampler
->get_samples(sampler
, sview_idx
, sampler_idx
,
2177 s
->f
, t
->f
, p
->f
, c0
->f
, c1
->f
, derivs
, offset
, control
, rgba
);
2179 for (j
= 0; j
< 4; j
++) {
2180 r
->f
[j
] = rgba
[0][j
];
2181 g
->f
[j
] = rgba
[1][j
];
2182 b
->f
[j
] = rgba
[2][j
];
2183 a
->f
[j
] = rgba
[3][j
];
2188 #define TEX_MODIFIER_NONE 0
2189 #define TEX_MODIFIER_PROJECTED 1
2190 #define TEX_MODIFIER_LOD_BIAS 2
2191 #define TEX_MODIFIER_EXPLICIT_LOD 3
2192 #define TEX_MODIFIER_LEVEL_ZERO 4
2193 #define TEX_MODIFIER_GATHER 5
2196 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
2199 fetch_texel_offsets(struct tgsi_exec_machine
*mach
,
2200 const struct tgsi_full_instruction
*inst
,
2203 if (inst
->Texture
.NumOffsets
== 1) {
2204 union tgsi_exec_channel index
;
2205 union tgsi_exec_channel offset
[3];
2206 index
.i
[0] = index
.i
[1] = index
.i
[2] = index
.i
[3] = inst
->TexOffsets
[0].Index
;
2207 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2208 inst
->TexOffsets
[0].SwizzleX
, &index
, &ZeroVec
, &offset
[0]);
2209 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2210 inst
->TexOffsets
[0].SwizzleY
, &index
, &ZeroVec
, &offset
[1]);
2211 fetch_src_file_channel(mach
, 0, inst
->TexOffsets
[0].File
,
2212 inst
->TexOffsets
[0].SwizzleZ
, &index
, &ZeroVec
, &offset
[2]);
2213 offsets
[0] = offset
[0].i
[0];
2214 offsets
[1] = offset
[1].i
[0];
2215 offsets
[2] = offset
[2].i
[0];
2217 assert(inst
->Texture
.NumOffsets
== 0);
2218 offsets
[0] = offsets
[1] = offsets
[2] = 0;
2224 * Fetch dx and dy values for one channel (s, t or r).
2225 * Put dx values into one float array, dy values into another.
2228 fetch_assign_deriv_channel(struct tgsi_exec_machine
*mach
,
2229 const struct tgsi_full_instruction
*inst
,
2232 float derivs
[2][TGSI_QUAD_SIZE
])
2234 union tgsi_exec_channel d
;
2235 FETCH(&d
, regdsrcx
, chan
);
2236 derivs
[0][0] = d
.f
[0];
2237 derivs
[0][1] = d
.f
[1];
2238 derivs
[0][2] = d
.f
[2];
2239 derivs
[0][3] = d
.f
[3];
2240 FETCH(&d
, regdsrcx
+ 1, chan
);
2241 derivs
[1][0] = d
.f
[0];
2242 derivs
[1][1] = d
.f
[1];
2243 derivs
[1][2] = d
.f
[2];
2244 derivs
[1][3] = d
.f
[3];
2248 fetch_sampler_unit(struct tgsi_exec_machine
*mach
,
2249 const struct tgsi_full_instruction
*inst
,
2254 if (inst
->Src
[sampler
].Register
.Indirect
) {
2255 const struct tgsi_full_src_register
*reg
= &inst
->Src
[sampler
];
2256 union tgsi_exec_channel indir_index
, index2
;
2257 const uint execmask
= mach
->ExecMask
;
2261 index2
.i
[3] = reg
->Indirect
.Index
;
2263 fetch_src_file_channel(mach
,
2266 reg
->Indirect
.Swizzle
,
2270 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2271 if (execmask
& (1 << i
)) {
2272 unit
= inst
->Src
[sampler
].Register
.Index
+ indir_index
.i
[i
];
2278 unit
= inst
->Src
[sampler
].Register
.Index
;
2284 * execute a texture instruction.
2286 * modifier is used to control the channel routing for the
2287 * instruction variants like proj, lod, and texture with lod bias.
2288 * sampler indicates which src register the sampler is contained in.
2291 exec_tex(struct tgsi_exec_machine
*mach
,
2292 const struct tgsi_full_instruction
*inst
,
2293 uint modifier
, uint sampler
)
2295 const union tgsi_exec_channel
*args
[5], *proj
= NULL
;
2296 union tgsi_exec_channel r
[5];
2297 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2301 int dim
, shadow_ref
, i
;
2303 unit
= fetch_sampler_unit(mach
, inst
, sampler
);
2304 /* always fetch all 3 offsets, overkill but keeps code simple */
2305 fetch_texel_offsets(mach
, inst
, offsets
);
2307 assert(modifier
!= TEX_MODIFIER_LEVEL_ZERO
);
2308 assert(inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
);
2310 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2311 shadow_ref
= tgsi_util_get_shadow_ref_src_index(inst
->Texture
.Texture
);
2314 if (shadow_ref
>= 0)
2315 assert(shadow_ref
>= dim
&& shadow_ref
< ARRAY_SIZE(args
));
2317 /* fetch modifier to the last argument */
2318 if (modifier
!= TEX_MODIFIER_NONE
) {
2319 const int last
= ARRAY_SIZE(args
) - 1;
2321 /* fetch modifier from src0.w or src1.x */
2323 assert(dim
<= TGSI_CHAN_W
&& shadow_ref
!= TGSI_CHAN_W
);
2324 FETCH(&r
[last
], 0, TGSI_CHAN_W
);
2327 assert(shadow_ref
!= 4);
2328 FETCH(&r
[last
], 1, TGSI_CHAN_X
);
2331 if (modifier
!= TEX_MODIFIER_PROJECTED
) {
2332 args
[last
] = &r
[last
];
2336 args
[last
] = &ZeroVec
;
2339 /* point unused arguments to zero vector */
2340 for (i
= dim
; i
< last
; i
++)
2343 if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
)
2344 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2345 else if (modifier
== TEX_MODIFIER_LOD_BIAS
)
2346 control
= TGSI_SAMPLER_LOD_BIAS
;
2347 else if (modifier
== TEX_MODIFIER_GATHER
)
2348 control
= TGSI_SAMPLER_GATHER
;
2351 for (i
= dim
; i
< ARRAY_SIZE(args
); i
++)
2355 /* fetch coordinates */
2356 for (i
= 0; i
< dim
; i
++) {
2357 FETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
2360 micro_div(&r
[i
], &r
[i
], proj
);
2365 /* fetch reference value */
2366 if (shadow_ref
>= 0) {
2367 FETCH(&r
[shadow_ref
], shadow_ref
/ 4, TGSI_CHAN_X
+ (shadow_ref
% 4));
2370 micro_div(&r
[shadow_ref
], &r
[shadow_ref
], proj
);
2372 args
[shadow_ref
] = &r
[shadow_ref
];
2375 fetch_texel(mach
->Sampler
, unit
, unit
,
2376 args
[0], args
[1], args
[2], args
[3], args
[4],
2377 NULL
, offsets
, control
,
2378 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2381 debug_printf("fetch r: %g %g %g %g\n",
2382 r
[0].f
[0], r
[0].f
[1], r
[0].f
[2], r
[0].f
[3]);
2383 debug_printf("fetch g: %g %g %g %g\n",
2384 r
[1].f
[0], r
[1].f
[1], r
[1].f
[2], r
[1].f
[3]);
2385 debug_printf("fetch b: %g %g %g %g\n",
2386 r
[2].f
[0], r
[2].f
[1], r
[2].f
[2], r
[2].f
[3]);
2387 debug_printf("fetch a: %g %g %g %g\n",
2388 r
[3].f
[0], r
[3].f
[1], r
[3].f
[2], r
[3].f
[3]);
2391 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2392 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2393 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2399 exec_lodq(struct tgsi_exec_machine
*mach
,
2400 const struct tgsi_full_instruction
*inst
)
2405 union tgsi_exec_channel coords
[4];
2406 const union tgsi_exec_channel
*args
[ARRAY_SIZE(coords
)];
2407 union tgsi_exec_channel r
[2];
2409 unit
= fetch_sampler_unit(mach
, inst
, 1);
2410 dim
= tgsi_util_get_texture_coord_dim(inst
->Texture
.Texture
);
2411 assert(dim
<= ARRAY_SIZE(coords
));
2412 /* fetch coordinates */
2413 for (i
= 0; i
< dim
; i
++) {
2414 FETCH(&coords
[i
], 0, TGSI_CHAN_X
+ i
);
2415 args
[i
] = &coords
[i
];
2417 for (i
= dim
; i
< ARRAY_SIZE(coords
); i
++) {
2420 mach
->Sampler
->query_lod(mach
->Sampler
, unit
, unit
,
2425 TGSI_SAMPLER_LOD_NONE
,
2429 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
2430 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
,
2431 TGSI_EXEC_DATA_FLOAT
);
2433 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
2434 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
,
2435 TGSI_EXEC_DATA_FLOAT
);
2440 exec_txd(struct tgsi_exec_machine
*mach
,
2441 const struct tgsi_full_instruction
*inst
)
2443 union tgsi_exec_channel r
[4];
2444 float derivs
[3][2][TGSI_QUAD_SIZE
];
2449 unit
= fetch_sampler_unit(mach
, inst
, 3);
2450 /* always fetch all 3 offsets, overkill but keeps code simple */
2451 fetch_texel_offsets(mach
, inst
, offsets
);
2453 switch (inst
->Texture
.Texture
) {
2454 case TGSI_TEXTURE_1D
:
2455 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2457 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2459 fetch_texel(mach
->Sampler
, unit
, unit
,
2460 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2461 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2462 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2465 case TGSI_TEXTURE_SHADOW1D
:
2466 case TGSI_TEXTURE_1D_ARRAY
:
2467 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2468 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
2469 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2470 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2471 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2473 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2475 fetch_texel(mach
->Sampler
, unit
, unit
,
2476 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2477 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2478 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2481 case TGSI_TEXTURE_2D
:
2482 case TGSI_TEXTURE_RECT
:
2483 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2484 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2486 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2487 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2489 fetch_texel(mach
->Sampler
, unit
, unit
,
2490 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2491 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2492 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2496 case TGSI_TEXTURE_SHADOW2D
:
2497 case TGSI_TEXTURE_SHADOWRECT
:
2498 case TGSI_TEXTURE_2D_ARRAY
:
2499 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2500 /* only SHADOW2D_ARRAY actually needs W */
2501 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2502 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2503 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2504 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2506 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2507 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2509 fetch_texel(mach
->Sampler
, unit
, unit
,
2510 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2511 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2512 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2515 case TGSI_TEXTURE_3D
:
2516 case TGSI_TEXTURE_CUBE
:
2517 case TGSI_TEXTURE_CUBE_ARRAY
:
2518 case TGSI_TEXTURE_SHADOWCUBE
:
2519 /* only TEXTURE_CUBE_ARRAY and TEXTURE_SHADOWCUBE actually need W */
2520 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2521 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2522 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2523 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2525 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_X
, derivs
[0]);
2526 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Y
, derivs
[1]);
2527 fetch_assign_deriv_channel(mach
, inst
, 1, TGSI_CHAN_Z
, derivs
[2]);
2529 fetch_texel(mach
->Sampler
, unit
, unit
,
2530 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
, /* inputs */
2531 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2532 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2539 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2540 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2541 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2548 exec_txf(struct tgsi_exec_machine
*mach
,
2549 const struct tgsi_full_instruction
*inst
)
2551 union tgsi_exec_channel r
[4];
2554 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
2559 unit
= fetch_sampler_unit(mach
, inst
, 1);
2560 /* always fetch all 3 offsets, overkill but keeps code simple */
2561 fetch_texel_offsets(mach
, inst
, offsets
);
2563 IFETCH(&r
[3], 0, TGSI_CHAN_W
);
2565 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2566 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2567 target
= mach
->SamplerViews
[unit
].Resource
;
2570 target
= inst
->Texture
.Texture
;
2573 case TGSI_TEXTURE_3D
:
2574 case TGSI_TEXTURE_2D_ARRAY
:
2575 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2576 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2577 IFETCH(&r
[2], 0, TGSI_CHAN_Z
);
2579 case TGSI_TEXTURE_2D
:
2580 case TGSI_TEXTURE_RECT
:
2581 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2582 case TGSI_TEXTURE_SHADOW2D
:
2583 case TGSI_TEXTURE_SHADOWRECT
:
2584 case TGSI_TEXTURE_1D_ARRAY
:
2585 case TGSI_TEXTURE_2D_MSAA
:
2586 IFETCH(&r
[1], 0, TGSI_CHAN_Y
);
2588 case TGSI_TEXTURE_BUFFER
:
2589 case TGSI_TEXTURE_1D
:
2590 case TGSI_TEXTURE_SHADOW1D
:
2591 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
2598 mach
->Sampler
->get_texel(mach
->Sampler
, unit
, r
[0].i
, r
[1].i
, r
[2].i
, r
[3].i
,
2601 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
2602 r
[0].f
[j
] = rgba
[0][j
];
2603 r
[1].f
[j
] = rgba
[1][j
];
2604 r
[2].f
[j
] = rgba
[2][j
];
2605 r
[3].f
[j
] = rgba
[3][j
];
2608 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I
||
2609 inst
->Instruction
.Opcode
== TGSI_OPCODE_SAMPLE_I_MS
) {
2610 unsigned char swizzles
[4];
2611 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2612 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2613 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2614 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2616 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2617 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2618 store_dest(mach
, &r
[swizzles
[chan
]],
2619 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2624 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2625 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2626 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2633 exec_txq(struct tgsi_exec_machine
*mach
,
2634 const struct tgsi_full_instruction
*inst
)
2637 union tgsi_exec_channel r
[4], src
;
2642 unit
= fetch_sampler_unit(mach
, inst
, 1);
2644 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
2646 /* XXX: This interface can't return per-pixel values */
2647 mach
->Sampler
->get_dims(mach
->Sampler
, unit
, src
.i
[0], result
);
2649 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2650 for (j
= 0; j
< 4; j
++) {
2651 r
[j
].i
[i
] = result
[j
];
2655 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2656 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2657 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
2658 TGSI_EXEC_DATA_INT
);
2664 exec_sample(struct tgsi_exec_machine
*mach
,
2665 const struct tgsi_full_instruction
*inst
,
2666 uint modifier
, boolean compare
)
2668 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2669 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2670 union tgsi_exec_channel r
[5], c1
;
2671 const union tgsi_exec_channel
*lod
= &ZeroVec
;
2672 enum tgsi_sampler_control control
= TGSI_SAMPLER_LOD_NONE
;
2674 unsigned char swizzles
[4];
2677 /* always fetch all 3 offsets, overkill but keeps code simple */
2678 fetch_texel_offsets(mach
, inst
, offsets
);
2680 assert(modifier
!= TEX_MODIFIER_PROJECTED
);
2682 if (modifier
!= TEX_MODIFIER_NONE
) {
2683 if (modifier
== TEX_MODIFIER_LOD_BIAS
) {
2684 FETCH(&c1
, 3, TGSI_CHAN_X
);
2686 control
= TGSI_SAMPLER_LOD_BIAS
;
2688 else if (modifier
== TEX_MODIFIER_EXPLICIT_LOD
) {
2689 FETCH(&c1
, 3, TGSI_CHAN_X
);
2691 control
= TGSI_SAMPLER_LOD_EXPLICIT
;
2694 assert(modifier
== TEX_MODIFIER_LEVEL_ZERO
);
2695 control
= TGSI_SAMPLER_LOD_ZERO
;
2699 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2701 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2702 case TGSI_TEXTURE_1D
:
2704 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2705 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2706 &r
[0], &ZeroVec
, &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2707 NULL
, offsets
, control
,
2708 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2711 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2712 &r
[0], &ZeroVec
, &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2713 NULL
, offsets
, control
,
2714 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2718 case TGSI_TEXTURE_1D_ARRAY
:
2719 case TGSI_TEXTURE_2D
:
2720 case TGSI_TEXTURE_RECT
:
2721 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2723 FETCH(&r
[2], 3, TGSI_CHAN_X
);
2724 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2725 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
, /* S, T, P, C, LOD */
2726 NULL
, offsets
, control
,
2727 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2730 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2731 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, lod
, /* S, T, P, C, LOD */
2732 NULL
, offsets
, control
,
2733 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2737 case TGSI_TEXTURE_2D_ARRAY
:
2738 case TGSI_TEXTURE_3D
:
2739 case TGSI_TEXTURE_CUBE
:
2740 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2741 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2743 FETCH(&r
[3], 3, TGSI_CHAN_X
);
2744 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2745 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2746 NULL
, offsets
, control
,
2747 &r
[0], &r
[1], &r
[2], &r
[3]);
2750 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2751 &r
[0], &r
[1], &r
[2], &ZeroVec
, lod
,
2752 NULL
, offsets
, control
,
2753 &r
[0], &r
[1], &r
[2], &r
[3]);
2757 case TGSI_TEXTURE_CUBE_ARRAY
:
2758 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2759 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2760 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2762 FETCH(&r
[4], 3, TGSI_CHAN_X
);
2763 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2764 &r
[0], &r
[1], &r
[2], &r
[3], &r
[4],
2765 NULL
, offsets
, control
,
2766 &r
[0], &r
[1], &r
[2], &r
[3]);
2769 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2770 &r
[0], &r
[1], &r
[2], &r
[3], lod
,
2771 NULL
, offsets
, control
,
2772 &r
[0], &r
[1], &r
[2], &r
[3]);
2781 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2782 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2783 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2784 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2786 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2787 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2788 store_dest(mach
, &r
[swizzles
[chan
]],
2789 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2795 exec_sample_d(struct tgsi_exec_machine
*mach
,
2796 const struct tgsi_full_instruction
*inst
)
2798 const uint resource_unit
= inst
->Src
[1].Register
.Index
;
2799 const uint sampler_unit
= inst
->Src
[2].Register
.Index
;
2800 union tgsi_exec_channel r
[4];
2801 float derivs
[3][2][TGSI_QUAD_SIZE
];
2803 unsigned char swizzles
[4];
2806 /* always fetch all 3 offsets, overkill but keeps code simple */
2807 fetch_texel_offsets(mach
, inst
, offsets
);
2809 FETCH(&r
[0], 0, TGSI_CHAN_X
);
2811 switch (mach
->SamplerViews
[resource_unit
].Resource
) {
2812 case TGSI_TEXTURE_1D
:
2813 case TGSI_TEXTURE_1D_ARRAY
:
2814 /* only 1D array actually needs Y */
2815 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2817 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2819 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2820 &r
[0], &r
[1], &ZeroVec
, &ZeroVec
, &ZeroVec
, /* S, T, P, C, LOD */
2821 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2822 &r
[0], &r
[1], &r
[2], &r
[3]); /* R, G, B, A */
2825 case TGSI_TEXTURE_2D
:
2826 case TGSI_TEXTURE_RECT
:
2827 case TGSI_TEXTURE_2D_ARRAY
:
2828 /* only 2D array actually needs Z */
2829 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2830 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2832 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2833 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2835 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2836 &r
[0], &r
[1], &r
[2], &ZeroVec
, &ZeroVec
, /* inputs */
2837 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2838 &r
[0], &r
[1], &r
[2], &r
[3]); /* outputs */
2841 case TGSI_TEXTURE_3D
:
2842 case TGSI_TEXTURE_CUBE
:
2843 case TGSI_TEXTURE_CUBE_ARRAY
:
2844 /* only cube array actually needs W */
2845 FETCH(&r
[1], 0, TGSI_CHAN_Y
);
2846 FETCH(&r
[2], 0, TGSI_CHAN_Z
);
2847 FETCH(&r
[3], 0, TGSI_CHAN_W
);
2849 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_X
, derivs
[0]);
2850 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Y
, derivs
[1]);
2851 fetch_assign_deriv_channel(mach
, inst
, 3, TGSI_CHAN_Z
, derivs
[2]);
2853 fetch_texel(mach
->Sampler
, resource_unit
, sampler_unit
,
2854 &r
[0], &r
[1], &r
[2], &r
[3], &ZeroVec
,
2855 derivs
, offsets
, TGSI_SAMPLER_DERIVS_EXPLICIT
,
2856 &r
[0], &r
[1], &r
[2], &r
[3]);
2863 swizzles
[0] = inst
->Src
[1].Register
.SwizzleX
;
2864 swizzles
[1] = inst
->Src
[1].Register
.SwizzleY
;
2865 swizzles
[2] = inst
->Src
[1].Register
.SwizzleZ
;
2866 swizzles
[3] = inst
->Src
[1].Register
.SwizzleW
;
2868 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
2869 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
2870 store_dest(mach
, &r
[swizzles
[chan
]],
2871 &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
2878 * Evaluate a constant-valued coefficient at the position of the
2883 struct tgsi_exec_machine
*mach
,
2889 for( i
= 0; i
< TGSI_QUAD_SIZE
; i
++ ) {
2890 mach
->Inputs
[attrib
].xyzw
[chan
].f
[i
] = mach
->InterpCoefs
[attrib
].a0
[chan
];
2895 * Evaluate a linear-valued coefficient at the position of the
2900 struct tgsi_exec_machine
*mach
,
2904 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2905 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2906 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2907 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2908 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2909 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
;
2910 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = a0
+ dadx
;
2911 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = a0
+ dady
;
2912 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = a0
+ dadx
+ dady
;
2916 * Evaluate a perspective-valued coefficient at the position of the
2920 eval_perspective_coef(
2921 struct tgsi_exec_machine
*mach
,
2925 const float x
= mach
->QuadPos
.xyzw
[0].f
[0];
2926 const float y
= mach
->QuadPos
.xyzw
[1].f
[0];
2927 const float dadx
= mach
->InterpCoefs
[attrib
].dadx
[chan
];
2928 const float dady
= mach
->InterpCoefs
[attrib
].dady
[chan
];
2929 const float a0
= mach
->InterpCoefs
[attrib
].a0
[chan
] + dadx
* x
+ dady
* y
;
2930 const float *w
= mach
->QuadPos
.xyzw
[3].f
;
2931 /* divide by W here */
2932 mach
->Inputs
[attrib
].xyzw
[chan
].f
[0] = a0
/ w
[0];
2933 mach
->Inputs
[attrib
].xyzw
[chan
].f
[1] = (a0
+ dadx
) / w
[1];
2934 mach
->Inputs
[attrib
].xyzw
[chan
].f
[2] = (a0
+ dady
) / w
[2];
2935 mach
->Inputs
[attrib
].xyzw
[chan
].f
[3] = (a0
+ dadx
+ dady
) / w
[3];
2939 typedef void (* eval_coef_func
)(
2940 struct tgsi_exec_machine
*mach
,
2945 exec_declaration(struct tgsi_exec_machine
*mach
,
2946 const struct tgsi_full_declaration
*decl
)
2948 if (decl
->Declaration
.File
== TGSI_FILE_SAMPLER_VIEW
) {
2949 mach
->SamplerViews
[decl
->Range
.First
] = decl
->SamplerView
;
2953 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
2954 if (decl
->Declaration
.File
== TGSI_FILE_INPUT
) {
2955 uint first
, last
, mask
;
2957 first
= decl
->Range
.First
;
2958 last
= decl
->Range
.Last
;
2959 mask
= decl
->Declaration
.UsageMask
;
2961 /* XXX we could remove this special-case code since
2962 * mach->InterpCoefs[first].a0 should already have the
2963 * front/back-face value. But we should first update the
2964 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2965 * Then, we could remove the tgsi_exec_machine::Face field.
2967 /* XXX make FACE a system value */
2968 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FACE
) {
2971 assert(decl
->Semantic
.Index
== 0);
2972 assert(first
== last
);
2974 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
2975 mach
->Inputs
[first
].xyzw
[0].f
[i
] = mach
->Face
;
2978 eval_coef_func eval
;
2981 switch (decl
->Interp
.Interpolate
) {
2982 case TGSI_INTERPOLATE_CONSTANT
:
2983 eval
= eval_constant_coef
;
2986 case TGSI_INTERPOLATE_LINEAR
:
2987 eval
= eval_linear_coef
;
2990 case TGSI_INTERPOLATE_PERSPECTIVE
:
2991 eval
= eval_perspective_coef
;
2994 case TGSI_INTERPOLATE_COLOR
:
2995 eval
= mach
->flatshade_color
? eval_constant_coef
: eval_perspective_coef
;
3003 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3004 if (mask
& (1 << j
)) {
3005 for (i
= first
; i
<= last
; i
++) {
3012 if (DEBUG_EXECUTION
) {
3014 for (i
= first
; i
<= last
; ++i
) {
3015 debug_printf("IN[%2u] = ", i
);
3016 for (j
= 0; j
< TGSI_NUM_CHANNELS
; j
++) {
3020 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
3021 mach
->Inputs
[i
].xyzw
[0].f
[j
], mach
->Inputs
[i
].xyzw
[0].u
[j
],
3022 mach
->Inputs
[i
].xyzw
[1].f
[j
], mach
->Inputs
[i
].xyzw
[1].u
[j
],
3023 mach
->Inputs
[i
].xyzw
[2].f
[j
], mach
->Inputs
[i
].xyzw
[2].u
[j
],
3024 mach
->Inputs
[i
].xyzw
[3].f
[j
], mach
->Inputs
[i
].xyzw
[3].u
[j
]);
3033 typedef void (* micro_unary_op
)(union tgsi_exec_channel
*dst
,
3034 const union tgsi_exec_channel
*src
);
3037 exec_scalar_unary(struct tgsi_exec_machine
*mach
,
3038 const struct tgsi_full_instruction
*inst
,
3040 enum tgsi_exec_datatype dst_datatype
,
3041 enum tgsi_exec_datatype src_datatype
)
3044 union tgsi_exec_channel src
;
3045 union tgsi_exec_channel dst
;
3047 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3049 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3050 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3051 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3057 exec_vector_unary(struct tgsi_exec_machine
*mach
,
3058 const struct tgsi_full_instruction
*inst
,
3060 enum tgsi_exec_datatype dst_datatype
,
3061 enum tgsi_exec_datatype src_datatype
)
3064 struct tgsi_exec_vector dst
;
3066 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3067 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3068 union tgsi_exec_channel src
;
3070 fetch_source(mach
, &src
, &inst
->Src
[0], chan
, src_datatype
);
3071 op(&dst
.xyzw
[chan
], &src
);
3074 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3075 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3076 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3081 typedef void (* micro_binary_op
)(union tgsi_exec_channel
*dst
,
3082 const union tgsi_exec_channel
*src0
,
3083 const union tgsi_exec_channel
*src1
);
3086 exec_scalar_binary(struct tgsi_exec_machine
*mach
,
3087 const struct tgsi_full_instruction
*inst
,
3089 enum tgsi_exec_datatype dst_datatype
,
3090 enum tgsi_exec_datatype src_datatype
)
3093 union tgsi_exec_channel src
[2];
3094 union tgsi_exec_channel dst
;
3096 fetch_source(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
3097 fetch_source(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, src_datatype
);
3098 op(&dst
, &src
[0], &src
[1]);
3099 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3100 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3101 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3107 exec_vector_binary(struct tgsi_exec_machine
*mach
,
3108 const struct tgsi_full_instruction
*inst
,
3110 enum tgsi_exec_datatype dst_datatype
,
3111 enum tgsi_exec_datatype src_datatype
)
3114 struct tgsi_exec_vector dst
;
3116 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3117 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3118 union tgsi_exec_channel src
[2];
3120 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3121 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3122 op(&dst
.xyzw
[chan
], &src
[0], &src
[1]);
3125 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3126 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3127 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3132 typedef void (* micro_trinary_op
)(union tgsi_exec_channel
*dst
,
3133 const union tgsi_exec_channel
*src0
,
3134 const union tgsi_exec_channel
*src1
,
3135 const union tgsi_exec_channel
*src2
);
3138 exec_vector_trinary(struct tgsi_exec_machine
*mach
,
3139 const struct tgsi_full_instruction
*inst
,
3140 micro_trinary_op op
,
3141 enum tgsi_exec_datatype dst_datatype
,
3142 enum tgsi_exec_datatype src_datatype
)
3145 struct tgsi_exec_vector dst
;
3147 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3148 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3149 union tgsi_exec_channel src
[3];
3151 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3152 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3153 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3154 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3157 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3158 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3159 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3164 typedef void (* micro_quaternary_op
)(union tgsi_exec_channel
*dst
,
3165 const union tgsi_exec_channel
*src0
,
3166 const union tgsi_exec_channel
*src1
,
3167 const union tgsi_exec_channel
*src2
,
3168 const union tgsi_exec_channel
*src3
);
3171 exec_vector_quaternary(struct tgsi_exec_machine
*mach
,
3172 const struct tgsi_full_instruction
*inst
,
3173 micro_quaternary_op op
,
3174 enum tgsi_exec_datatype dst_datatype
,
3175 enum tgsi_exec_datatype src_datatype
)
3178 struct tgsi_exec_vector dst
;
3180 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3181 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3182 union tgsi_exec_channel src
[4];
3184 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
, src_datatype
);
3185 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
, src_datatype
);
3186 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
, src_datatype
);
3187 fetch_source(mach
, &src
[3], &inst
->Src
[3], chan
, src_datatype
);
3188 op(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2], &src
[3]);
3191 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3192 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3193 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
, dst_datatype
);
3199 exec_dp3(struct tgsi_exec_machine
*mach
,
3200 const struct tgsi_full_instruction
*inst
)
3203 union tgsi_exec_channel arg
[3];
3205 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3206 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3207 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3209 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_Z
; chan
++) {
3210 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3211 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3212 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3215 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3216 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3217 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3223 exec_dp4(struct tgsi_exec_machine
*mach
,
3224 const struct tgsi_full_instruction
*inst
)
3227 union tgsi_exec_channel arg
[3];
3229 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3230 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3231 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3233 for (chan
= TGSI_CHAN_Y
; chan
<= TGSI_CHAN_W
; chan
++) {
3234 fetch_source(mach
, &arg
[0], &inst
->Src
[0], chan
, TGSI_EXEC_DATA_FLOAT
);
3235 fetch_source(mach
, &arg
[1], &inst
->Src
[1], chan
, TGSI_EXEC_DATA_FLOAT
);
3236 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3239 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3240 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3241 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3247 exec_dp2a(struct tgsi_exec_machine
*mach
,
3248 const struct tgsi_full_instruction
*inst
)
3251 union tgsi_exec_channel arg
[3];
3253 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3254 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3255 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3257 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3258 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3259 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3261 fetch_source(mach
, &arg
[1], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3262 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3264 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3265 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3266 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3272 exec_dph(struct tgsi_exec_machine
*mach
,
3273 const struct tgsi_full_instruction
*inst
)
3276 union tgsi_exec_channel arg
[3];
3278 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3279 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3280 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3282 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3283 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3284 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3286 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3287 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3288 micro_mad(&arg
[0], &arg
[0], &arg
[1], &arg
[2]);
3290 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3291 micro_add(&arg
[0], &arg
[0], &arg
[1]);
3293 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3294 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3295 store_dest(mach
, &arg
[0], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3301 exec_dp2(struct tgsi_exec_machine
*mach
,
3302 const struct tgsi_full_instruction
*inst
)
3305 union tgsi_exec_channel arg
[3];
3307 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3308 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3309 micro_mul(&arg
[2], &arg
[0], &arg
[1]);
3311 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3312 fetch_source(mach
, &arg
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3313 micro_mad(&arg
[2], &arg
[0], &arg
[1], &arg
[2]);
3315 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3316 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3317 store_dest(mach
, &arg
[2], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3323 exec_pk2h(struct tgsi_exec_machine
*mach
,
3324 const struct tgsi_full_instruction
*inst
)
3327 union tgsi_exec_channel arg
[2], dst
;
3329 fetch_source(mach
, &arg
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3330 fetch_source(mach
, &arg
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3331 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3332 dst
.u
[chan
] = util_float_to_half(arg
[0].f
[chan
]) |
3333 (util_float_to_half(arg
[1].f
[chan
]) << 16);
3335 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3336 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3337 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_UINT
);
3343 exec_up2h(struct tgsi_exec_machine
*mach
,
3344 const struct tgsi_full_instruction
*inst
)
3347 union tgsi_exec_channel arg
, dst
[2];
3349 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3350 for (chan
= 0; chan
< TGSI_QUAD_SIZE
; chan
++) {
3351 dst
[0].f
[chan
] = util_half_to_float(arg
.u
[chan
] & 0xffff);
3352 dst
[1].f
[chan
] = util_half_to_float(arg
.u
[chan
] >> 16);
3354 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3355 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3356 store_dest(mach
, &dst
[chan
& 1], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
3362 micro_ucmp(union tgsi_exec_channel
*dst
,
3363 const union tgsi_exec_channel
*src0
,
3364 const union tgsi_exec_channel
*src1
,
3365 const union tgsi_exec_channel
*src2
)
3367 dst
->f
[0] = src0
->u
[0] ? src1
->f
[0] : src2
->f
[0];
3368 dst
->f
[1] = src0
->u
[1] ? src1
->f
[1] : src2
->f
[1];
3369 dst
->f
[2] = src0
->u
[2] ? src1
->f
[2] : src2
->f
[2];
3370 dst
->f
[3] = src0
->u
[3] ? src1
->f
[3] : src2
->f
[3];
3374 exec_ucmp(struct tgsi_exec_machine
*mach
,
3375 const struct tgsi_full_instruction
*inst
)
3378 struct tgsi_exec_vector dst
;
3380 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3381 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3382 union tgsi_exec_channel src
[3];
3384 fetch_source(mach
, &src
[0], &inst
->Src
[0], chan
,
3385 TGSI_EXEC_DATA_UINT
);
3386 fetch_source(mach
, &src
[1], &inst
->Src
[1], chan
,
3387 TGSI_EXEC_DATA_FLOAT
);
3388 fetch_source(mach
, &src
[2], &inst
->Src
[2], chan
,
3389 TGSI_EXEC_DATA_FLOAT
);
3390 micro_ucmp(&dst
.xyzw
[chan
], &src
[0], &src
[1], &src
[2]);
3393 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
3394 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
3395 store_dest(mach
, &dst
.xyzw
[chan
], &inst
->Dst
[0], inst
, chan
,
3396 TGSI_EXEC_DATA_FLOAT
);
3402 exec_scs(struct tgsi_exec_machine
*mach
,
3403 const struct tgsi_full_instruction
*inst
)
3405 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
3406 union tgsi_exec_channel arg
;
3407 union tgsi_exec_channel result
;
3409 fetch_source(mach
, &arg
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3411 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3412 micro_cos(&result
, &arg
);
3413 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3415 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3416 micro_sin(&result
, &arg
);
3417 store_dest(mach
, &result
, &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3420 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3421 store_dest(mach
, &ZeroVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3423 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3424 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3429 exec_xpd(struct tgsi_exec_machine
*mach
,
3430 const struct tgsi_full_instruction
*inst
)
3432 union tgsi_exec_channel r
[6];
3433 union tgsi_exec_channel d
[3];
3435 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3436 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3438 micro_mul(&r
[2], &r
[0], &r
[1]);
3440 fetch_source(mach
, &r
[3], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3441 fetch_source(mach
, &r
[4], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3443 micro_mul(&r
[5], &r
[3], &r
[4] );
3444 micro_sub(&d
[TGSI_CHAN_X
], &r
[2], &r
[5]);
3446 fetch_source(mach
, &r
[2], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3448 micro_mul(&r
[3], &r
[3], &r
[2]);
3450 fetch_source(mach
, &r
[5], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3452 micro_mul(&r
[1], &r
[1], &r
[5]);
3453 micro_sub(&d
[TGSI_CHAN_Y
], &r
[3], &r
[1]);
3455 micro_mul(&r
[5], &r
[5], &r
[4]);
3456 micro_mul(&r
[0], &r
[0], &r
[2]);
3457 micro_sub(&d
[TGSI_CHAN_Z
], &r
[5], &r
[0]);
3459 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3460 store_dest(mach
, &d
[TGSI_CHAN_X
], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3462 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3463 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3465 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3466 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3468 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3469 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3474 exec_dst(struct tgsi_exec_machine
*mach
,
3475 const struct tgsi_full_instruction
*inst
)
3477 union tgsi_exec_channel r
[2];
3478 union tgsi_exec_channel d
[4];
3480 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3481 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3482 fetch_source(mach
, &r
[1], &inst
->Src
[1], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3483 micro_mul(&d
[TGSI_CHAN_Y
], &r
[0], &r
[1]);
3485 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3486 fetch_source(mach
, &d
[TGSI_CHAN_Z
], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3488 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3489 fetch_source(mach
, &d
[TGSI_CHAN_W
], &inst
->Src
[1], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3492 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3493 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3495 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3496 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3498 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3499 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3501 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3502 store_dest(mach
, &d
[TGSI_CHAN_W
], &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3507 exec_log(struct tgsi_exec_machine
*mach
,
3508 const struct tgsi_full_instruction
*inst
)
3510 union tgsi_exec_channel r
[3];
3512 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3513 micro_abs(&r
[2], &r
[0]); /* r2 = abs(r0) */
3514 micro_lg2(&r
[1], &r
[2]); /* r1 = lg2(r2) */
3515 micro_flr(&r
[0], &r
[1]); /* r0 = floor(r1) */
3516 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3517 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3519 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3520 micro_exp2(&r
[0], &r
[0]); /* r0 = 2 ^ r0 */
3521 micro_div(&r
[0], &r
[2], &r
[0]); /* r0 = r2 / r0 */
3522 store_dest(mach
, &r
[0], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3524 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3525 store_dest(mach
, &r
[1], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3527 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3528 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3533 exec_exp(struct tgsi_exec_machine
*mach
,
3534 const struct tgsi_full_instruction
*inst
)
3536 union tgsi_exec_channel r
[3];
3538 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3539 micro_flr(&r
[1], &r
[0]); /* r1 = floor(r0) */
3540 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3541 micro_exp2(&r
[2], &r
[1]); /* r2 = 2 ^ r1 */
3542 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3544 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3545 micro_sub(&r
[2], &r
[0], &r
[1]); /* r2 = r0 - r1 */
3546 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3548 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3549 micro_exp2(&r
[2], &r
[0]); /* r2 = 2 ^ r0 */
3550 store_dest(mach
, &r
[2], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3552 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3553 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3558 exec_lit(struct tgsi_exec_machine
*mach
,
3559 const struct tgsi_full_instruction
*inst
)
3561 union tgsi_exec_channel r
[3];
3562 union tgsi_exec_channel d
[3];
3564 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_YZ
) {
3565 fetch_source(mach
, &r
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3566 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3567 fetch_source(mach
, &r
[1], &inst
->Src
[0], TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3568 micro_max(&r
[1], &r
[1], &ZeroVec
);
3570 fetch_source(mach
, &r
[2], &inst
->Src
[0], TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3571 micro_min(&r
[2], &r
[2], &P128Vec
);
3572 micro_max(&r
[2], &r
[2], &M128Vec
);
3573 micro_pow(&r
[1], &r
[1], &r
[2]);
3574 micro_lt(&d
[TGSI_CHAN_Z
], &ZeroVec
, &r
[0], &r
[1], &ZeroVec
);
3575 store_dest(mach
, &d
[TGSI_CHAN_Z
], &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_EXEC_DATA_FLOAT
);
3577 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3578 micro_max(&d
[TGSI_CHAN_Y
], &r
[0], &ZeroVec
);
3579 store_dest(mach
, &d
[TGSI_CHAN_Y
], &inst
->Dst
[0], inst
, TGSI_CHAN_Y
, TGSI_EXEC_DATA_FLOAT
);
3582 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3583 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_EXEC_DATA_FLOAT
);
3586 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3587 store_dest(mach
, &OneVec
, &inst
->Dst
[0], inst
, TGSI_CHAN_W
, TGSI_EXEC_DATA_FLOAT
);
3592 exec_break(struct tgsi_exec_machine
*mach
)
3594 if (mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_LOOP
) {
3595 /* turn off loop channels for each enabled exec channel */
3596 mach
->LoopMask
&= ~mach
->ExecMask
;
3597 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3598 UPDATE_EXEC_MASK(mach
);
3600 assert(mach
->BreakType
== TGSI_EXEC_BREAK_INSIDE_SWITCH
);
3602 mach
->Switch
.mask
= 0x0;
3604 UPDATE_EXEC_MASK(mach
);
3609 exec_switch(struct tgsi_exec_machine
*mach
,
3610 const struct tgsi_full_instruction
*inst
)
3612 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
3613 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
3615 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
3616 fetch_source(mach
, &mach
->Switch
.selector
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3617 mach
->Switch
.mask
= 0x0;
3618 mach
->Switch
.defaultMask
= 0x0;
3620 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
3621 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_SWITCH
;
3623 UPDATE_EXEC_MASK(mach
);
3627 exec_case(struct tgsi_exec_machine
*mach
,
3628 const struct tgsi_full_instruction
*inst
)
3630 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3631 union tgsi_exec_channel src
;
3634 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_EXEC_DATA_UINT
);
3636 if (mach
->Switch
.selector
.u
[0] == src
.u
[0]) {
3639 if (mach
->Switch
.selector
.u
[1] == src
.u
[1]) {
3642 if (mach
->Switch
.selector
.u
[2] == src
.u
[2]) {
3645 if (mach
->Switch
.selector
.u
[3] == src
.u
[3]) {
3649 mach
->Switch
.defaultMask
|= mask
;
3651 mach
->Switch
.mask
|= mask
& prevMask
;
3653 UPDATE_EXEC_MASK(mach
);
3656 /* FIXME: this will only work if default is last */
3658 exec_default(struct tgsi_exec_machine
*mach
)
3660 uint prevMask
= mach
->SwitchStack
[mach
->SwitchStackTop
- 1].mask
;
3662 mach
->Switch
.mask
|= ~mach
->Switch
.defaultMask
& prevMask
;
3664 UPDATE_EXEC_MASK(mach
);
3668 exec_endswitch(struct tgsi_exec_machine
*mach
)
3670 mach
->Switch
= mach
->SwitchStack
[--mach
->SwitchStackTop
];
3671 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
3673 UPDATE_EXEC_MASK(mach
);
3676 typedef void (* micro_dop
)(union tgsi_double_channel
*dst
,
3677 const union tgsi_double_channel
*src
);
3679 typedef void (* micro_dop_sop
)(union tgsi_double_channel
*dst
,
3680 const union tgsi_double_channel
*src0
,
3681 union tgsi_exec_channel
*src1
);
3683 typedef void (* micro_dop_s
)(union tgsi_double_channel
*dst
,
3684 const union tgsi_exec_channel
*src
);
3686 typedef void (* micro_sop_d
)(union tgsi_exec_channel
*dst
,
3687 const union tgsi_double_channel
*src
);
3690 fetch_double_channel(struct tgsi_exec_machine
*mach
,
3691 union tgsi_double_channel
*chan
,
3692 const struct tgsi_full_src_register
*reg
,
3696 union tgsi_exec_channel src
[2];
3699 fetch_source_d(mach
, &src
[0], reg
, chan_0
, TGSI_EXEC_DATA_UINT
);
3700 fetch_source_d(mach
, &src
[1], reg
, chan_1
, TGSI_EXEC_DATA_UINT
);
3702 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
3703 chan
->u
[i
][0] = src
[0].u
[i
];
3704 chan
->u
[i
][1] = src
[1].u
[i
];
3706 if (reg
->Register
.Absolute
) {
3707 micro_dabs(chan
, chan
);
3709 if (reg
->Register
.Negate
) {
3710 micro_dneg(chan
, chan
);
3715 store_double_channel(struct tgsi_exec_machine
*mach
,
3716 const union tgsi_double_channel
*chan
,
3717 const struct tgsi_full_dst_register
*reg
,
3718 const struct tgsi_full_instruction
*inst
,
3722 union tgsi_exec_channel dst
[2];
3724 union tgsi_double_channel temp
;
3725 const uint execmask
= mach
->ExecMask
;
3727 if (!inst
->Instruction
.Saturate
) {
3728 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3729 if (execmask
& (1 << i
)) {
3730 dst
[0].u
[i
] = chan
->u
[i
][0];
3731 dst
[1].u
[i
] = chan
->u
[i
][1];
3735 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
3736 if (execmask
& (1 << i
)) {
3737 if (chan
->d
[i
] < 0.0)
3739 else if (chan
->d
[i
] > 1.0)
3742 temp
.d
[i
] = chan
->d
[i
];
3744 dst
[0].u
[i
] = temp
.u
[i
][0];
3745 dst
[1].u
[i
] = temp
.u
[i
][1];
3749 store_dest_double(mach
, &dst
[0], reg
, inst
, chan_0
, TGSI_EXEC_DATA_UINT
);
3751 store_dest_double(mach
, &dst
[1], reg
, inst
, chan_1
, TGSI_EXEC_DATA_UINT
);
3755 exec_double_unary(struct tgsi_exec_machine
*mach
,
3756 const struct tgsi_full_instruction
*inst
,
3759 union tgsi_double_channel src
;
3760 union tgsi_double_channel dst
;
3762 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3763 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3765 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3767 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3768 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3770 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3775 exec_double_binary(struct tgsi_exec_machine
*mach
,
3776 const struct tgsi_full_instruction
*inst
,
3778 enum tgsi_exec_datatype dst_datatype
)
3780 union tgsi_double_channel src
[2];
3781 union tgsi_double_channel dst
;
3782 int first_dest_chan
, second_dest_chan
;
3785 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3786 /* these are & because of the way DSLT etc store their destinations */
3787 if (wmask
& TGSI_WRITEMASK_XY
) {
3788 first_dest_chan
= TGSI_CHAN_X
;
3789 second_dest_chan
= TGSI_CHAN_Y
;
3790 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3791 first_dest_chan
= (wmask
& TGSI_WRITEMASK_X
) ? TGSI_CHAN_X
: TGSI_CHAN_Y
;
3792 second_dest_chan
= -1;
3795 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3796 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3798 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3801 if (wmask
& TGSI_WRITEMASK_ZW
) {
3802 first_dest_chan
= TGSI_CHAN_Z
;
3803 second_dest_chan
= TGSI_CHAN_W
;
3804 if (dst_datatype
== TGSI_EXEC_DATA_UINT
) {
3805 first_dest_chan
= (wmask
& TGSI_WRITEMASK_Z
) ? TGSI_CHAN_Z
: TGSI_CHAN_W
;
3806 second_dest_chan
= -1;
3809 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3810 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3812 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, first_dest_chan
, second_dest_chan
);
3817 exec_double_trinary(struct tgsi_exec_machine
*mach
,
3818 const struct tgsi_full_instruction
*inst
,
3821 union tgsi_double_channel src
[3];
3822 union tgsi_double_channel dst
;
3824 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
3825 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3826 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3827 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3829 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3831 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
3832 fetch_double_channel(mach
, &src
[0], &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3833 fetch_double_channel(mach
, &src
[1], &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3834 fetch_double_channel(mach
, &src
[2], &inst
->Src
[2], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3836 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3841 exec_dldexp(struct tgsi_exec_machine
*mach
,
3842 const struct tgsi_full_instruction
*inst
)
3844 union tgsi_double_channel src0
;
3845 union tgsi_exec_channel src1
;
3846 union tgsi_double_channel dst
;
3849 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3850 if (wmask
& TGSI_WRITEMASK_XY
) {
3851 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3852 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3853 micro_dldexp(&dst
, &src0
, &src1
);
3854 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3857 if (wmask
& TGSI_WRITEMASK_ZW
) {
3858 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3859 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3860 micro_dldexp(&dst
, &src0
, &src1
);
3861 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3866 exec_dfracexp(struct tgsi_exec_machine
*mach
,
3867 const struct tgsi_full_instruction
*inst
)
3869 union tgsi_double_channel src
;
3870 union tgsi_double_channel dst
;
3871 union tgsi_exec_channel dst_exp
;
3873 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
)) {
3874 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3875 micro_dfracexp(&dst
, &dst_exp
, &src
);
3876 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3877 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3879 if (((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
)) {
3880 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3881 micro_dfracexp(&dst
, &dst_exp
, &src
);
3882 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3883 store_dest(mach
, &dst_exp
, &inst
->Dst
[1], inst
, ffs(inst
->Dst
[1].Register
.WriteMask
) - 1, TGSI_EXEC_DATA_INT
);
3888 exec_arg0_64_arg1_32(struct tgsi_exec_machine
*mach
,
3889 const struct tgsi_full_instruction
*inst
,
3892 union tgsi_double_channel src0
;
3893 union tgsi_exec_channel src1
;
3894 union tgsi_double_channel dst
;
3897 wmask
= inst
->Dst
[0].Register
.WriteMask
;
3898 if (wmask
& TGSI_WRITEMASK_XY
) {
3899 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
3900 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_X
, TGSI_EXEC_DATA_INT
);
3901 op(&dst
, &src0
, &src1
);
3902 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
3905 if (wmask
& TGSI_WRITEMASK_ZW
) {
3906 fetch_double_channel(mach
, &src0
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
3907 fetch_source(mach
, &src1
, &inst
->Src
[1], TGSI_CHAN_Z
, TGSI_EXEC_DATA_INT
);
3908 op(&dst
, &src0
, &src1
);
3909 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
3914 get_image_coord_dim(unsigned tgsi_tex
)
3918 case TGSI_TEXTURE_BUFFER
:
3919 case TGSI_TEXTURE_1D
:
3922 case TGSI_TEXTURE_2D
:
3923 case TGSI_TEXTURE_RECT
:
3924 case TGSI_TEXTURE_1D_ARRAY
:
3925 case TGSI_TEXTURE_2D_MSAA
:
3928 case TGSI_TEXTURE_3D
:
3929 case TGSI_TEXTURE_CUBE
:
3930 case TGSI_TEXTURE_2D_ARRAY
:
3931 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3932 case TGSI_TEXTURE_CUBE_ARRAY
:
3936 assert(!"unknown texture target");
3945 get_image_coord_sample(unsigned tgsi_tex
)
3949 case TGSI_TEXTURE_2D_MSAA
:
3952 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
3962 exec_load_img(struct tgsi_exec_machine
*mach
,
3963 const struct tgsi_full_instruction
*inst
)
3965 union tgsi_exec_channel r
[4], sample_r
;
3971 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
3972 struct tgsi_image_params params
;
3973 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
3975 unit
= fetch_sampler_unit(mach
, inst
, 0);
3976 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
3977 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
3980 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
3982 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
3983 params
.format
= inst
->Memory
.Format
;
3985 for (i
= 0; i
< dim
; i
++) {
3986 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
3990 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
3992 mach
->Image
->load(mach
->Image
, ¶ms
,
3993 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
3995 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
3996 r
[0].f
[j
] = rgba
[0][j
];
3997 r
[1].f
[j
] = rgba
[1][j
];
3998 r
[2].f
[j
] = rgba
[2][j
];
3999 r
[3].f
[j
] = rgba
[3][j
];
4001 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4002 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4003 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4009 exec_load_buf(struct tgsi_exec_machine
*mach
,
4010 const struct tgsi_full_instruction
*inst
)
4012 union tgsi_exec_channel r
[4];
4016 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4017 struct tgsi_buffer_params params
;
4018 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4020 unit
= fetch_sampler_unit(mach
, inst
, 0);
4022 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4024 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4026 mach
->Buffer
->load(mach
->Buffer
, ¶ms
,
4028 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4029 r
[0].f
[j
] = rgba
[0][j
];
4030 r
[1].f
[j
] = rgba
[1][j
];
4031 r
[2].f
[j
] = rgba
[2][j
];
4032 r
[3].f
[j
] = rgba
[3][j
];
4034 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4035 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4036 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4042 exec_load_mem(struct tgsi_exec_machine
*mach
,
4043 const struct tgsi_full_instruction
*inst
)
4045 union tgsi_exec_channel r
[4];
4047 char *ptr
= mach
->LocalMem
;
4051 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4052 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4058 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4059 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4060 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4061 memcpy(&r
[chan
].u
[j
], ptr
+ (4 * chan
), 4);
4066 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4067 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4068 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4074 exec_load(struct tgsi_exec_machine
*mach
,
4075 const struct tgsi_full_instruction
*inst
)
4077 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4078 exec_load_img(mach
, inst
);
4079 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4080 exec_load_buf(mach
, inst
);
4081 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4082 exec_load_mem(mach
, inst
);
4086 exec_store_img(struct tgsi_exec_machine
*mach
,
4087 const struct tgsi_full_instruction
*inst
)
4089 union tgsi_exec_channel r
[3], sample_r
;
4090 union tgsi_exec_channel value
[4];
4091 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4092 struct tgsi_image_params params
;
4097 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4098 unit
= inst
->Dst
[0].Register
.Index
;
4099 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4100 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4103 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4105 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4106 params
.format
= inst
->Memory
.Format
;
4108 for (i
= 0; i
< dim
; i
++) {
4109 IFETCH(&r
[i
], 0, TGSI_CHAN_X
+ i
);
4112 for (i
= 0; i
< 4; i
++) {
4113 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4116 IFETCH(&sample_r
, 0, TGSI_CHAN_X
+ sample
);
4118 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4119 rgba
[0][j
] = value
[0].f
[j
];
4120 rgba
[1][j
] = value
[1].f
[j
];
4121 rgba
[2][j
] = value
[2].f
[j
];
4122 rgba
[3][j
] = value
[3].f
[j
];
4125 mach
->Image
->store(mach
->Image
, ¶ms
,
4126 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4131 exec_store_buf(struct tgsi_exec_machine
*mach
,
4132 const struct tgsi_full_instruction
*inst
)
4134 union tgsi_exec_channel r
[3];
4135 union tgsi_exec_channel value
[4];
4136 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4137 struct tgsi_buffer_params params
;
4140 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4142 unit
= inst
->Dst
[0].Register
.Index
;
4144 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4146 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4148 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4149 for (i
= 0; i
< 4; i
++) {
4150 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4153 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4154 rgba
[0][j
] = value
[0].f
[j
];
4155 rgba
[1][j
] = value
[1].f
[j
];
4156 rgba
[2][j
] = value
[2].f
[j
];
4157 rgba
[3][j
] = value
[3].f
[j
];
4160 mach
->Buffer
->store(mach
->Buffer
, ¶ms
,
4166 exec_store_mem(struct tgsi_exec_machine
*mach
,
4167 const struct tgsi_full_instruction
*inst
)
4169 union tgsi_exec_channel r
[3];
4170 union tgsi_exec_channel value
[4];
4172 char *ptr
= mach
->LocalMem
;
4173 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4174 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4176 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
4178 for (i
= 0; i
< 4; i
++) {
4179 FETCH(&value
[i
], 1, TGSI_CHAN_X
+ i
);
4182 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4186 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4187 if (execmask
& (1 << i
)) {
4188 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4189 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4190 memcpy(ptr
+ (chan
* 4), &value
[chan
].u
[0], 4);
4198 exec_store(struct tgsi_exec_machine
*mach
,
4199 const struct tgsi_full_instruction
*inst
)
4201 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
)
4202 exec_store_img(mach
, inst
);
4203 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
4204 exec_store_buf(mach
, inst
);
4205 else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
)
4206 exec_store_mem(mach
, inst
);
4210 exec_atomop_img(struct tgsi_exec_machine
*mach
,
4211 const struct tgsi_full_instruction
*inst
)
4213 union tgsi_exec_channel r
[4], sample_r
;
4214 union tgsi_exec_channel value
[4], value2
[4];
4215 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4216 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4217 struct tgsi_image_params params
;
4222 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4223 unit
= fetch_sampler_unit(mach
, inst
, 0);
4224 dim
= get_image_coord_dim(inst
->Memory
.Texture
);
4225 sample
= get_image_coord_sample(inst
->Memory
.Texture
);
4228 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4230 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4231 params
.format
= inst
->Memory
.Format
;
4233 for (i
= 0; i
< dim
; i
++) {
4234 IFETCH(&r
[i
], 1, TGSI_CHAN_X
+ i
);
4237 for (i
= 0; i
< 4; i
++) {
4238 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4239 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4240 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4243 IFETCH(&sample_r
, 1, TGSI_CHAN_X
+ sample
);
4245 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4246 rgba
[0][j
] = value
[0].f
[j
];
4247 rgba
[1][j
] = value
[1].f
[j
];
4248 rgba
[2][j
] = value
[2].f
[j
];
4249 rgba
[3][j
] = value
[3].f
[j
];
4251 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4252 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4253 rgba2
[0][j
] = value2
[0].f
[j
];
4254 rgba2
[1][j
] = value2
[1].f
[j
];
4255 rgba2
[2][j
] = value2
[2].f
[j
];
4256 rgba2
[3][j
] = value2
[3].f
[j
];
4260 mach
->Image
->op(mach
->Image
, ¶ms
, inst
->Instruction
.Opcode
,
4261 r
[0].i
, r
[1].i
, r
[2].i
, sample_r
.i
,
4264 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4265 r
[0].f
[j
] = rgba
[0][j
];
4266 r
[1].f
[j
] = rgba
[1][j
];
4267 r
[2].f
[j
] = rgba
[2][j
];
4268 r
[3].f
[j
] = rgba
[3][j
];
4270 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4271 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4272 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4278 exec_atomop_buf(struct tgsi_exec_machine
*mach
,
4279 const struct tgsi_full_instruction
*inst
)
4281 union tgsi_exec_channel r
[4];
4282 union tgsi_exec_channel value
[4], value2
[4];
4283 float rgba
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4284 float rgba2
[TGSI_NUM_CHANNELS
][TGSI_QUAD_SIZE
];
4285 struct tgsi_buffer_params params
;
4288 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4290 unit
= fetch_sampler_unit(mach
, inst
, 0);
4292 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4294 params
.writemask
= inst
->Dst
[0].Register
.WriteMask
;
4296 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4298 for (i
= 0; i
< 4; i
++) {
4299 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4300 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4301 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4304 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4305 rgba
[0][j
] = value
[0].f
[j
];
4306 rgba
[1][j
] = value
[1].f
[j
];
4307 rgba
[2][j
] = value
[2].f
[j
];
4308 rgba
[3][j
] = value
[3].f
[j
];
4310 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
4311 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4312 rgba2
[0][j
] = value2
[0].f
[j
];
4313 rgba2
[1][j
] = value2
[1].f
[j
];
4314 rgba2
[2][j
] = value2
[2].f
[j
];
4315 rgba2
[3][j
] = value2
[3].f
[j
];
4319 mach
->Buffer
->op(mach
->Buffer
, ¶ms
, inst
->Instruction
.Opcode
,
4323 for (j
= 0; j
< TGSI_QUAD_SIZE
; j
++) {
4324 r
[0].f
[j
] = rgba
[0][j
];
4325 r
[1].f
[j
] = rgba
[1][j
];
4326 r
[2].f
[j
] = rgba
[2][j
];
4327 r
[3].f
[j
] = rgba
[3][j
];
4329 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4330 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4331 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4337 exec_atomop_mem(struct tgsi_exec_machine
*mach
,
4338 const struct tgsi_full_instruction
*inst
)
4340 union tgsi_exec_channel r
[4];
4341 union tgsi_exec_channel value
[4], value2
[4];
4342 char *ptr
= mach
->LocalMem
;
4346 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4347 int execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4348 IFETCH(&r
[0], 1, TGSI_CHAN_X
);
4350 if (r
[0].u
[0] >= mach
->LocalMemSize
)
4355 for (i
= 0; i
< 4; i
++) {
4356 FETCH(&value
[i
], 2, TGSI_CHAN_X
+ i
);
4357 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
4358 FETCH(&value2
[i
], 3, TGSI_CHAN_X
+ i
);
4361 memcpy(&r
[0].u
[0], ptr
, 4);
4363 switch (inst
->Instruction
.Opcode
) {
4364 case TGSI_OPCODE_ATOMUADD
:
4365 val
+= value
[0].u
[0];
4367 case TGSI_OPCODE_ATOMXOR
:
4368 val
^= value
[0].u
[0];
4370 case TGSI_OPCODE_ATOMOR
:
4371 val
|= value
[0].u
[0];
4373 case TGSI_OPCODE_ATOMAND
:
4374 val
&= value
[0].u
[0];
4376 case TGSI_OPCODE_ATOMUMIN
:
4377 val
= MIN2(val
, value
[0].u
[0]);
4379 case TGSI_OPCODE_ATOMUMAX
:
4380 val
= MAX2(val
, value
[0].u
[0]);
4382 case TGSI_OPCODE_ATOMIMIN
:
4383 val
= MIN2(r
[0].i
[0], value
[0].i
[0]);
4385 case TGSI_OPCODE_ATOMIMAX
:
4386 val
= MAX2(r
[0].i
[0], value
[0].i
[0]);
4388 case TGSI_OPCODE_ATOMXCHG
:
4389 val
= value
[0].i
[0];
4391 case TGSI_OPCODE_ATOMCAS
:
4392 if (val
== value
[0].u
[0])
4393 val
= value2
[0].u
[0];
4398 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++)
4399 if (execmask
& (1 << i
))
4400 memcpy(ptr
, &val
, 4);
4402 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4403 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4404 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
, TGSI_EXEC_DATA_FLOAT
);
4410 exec_atomop(struct tgsi_exec_machine
*mach
,
4411 const struct tgsi_full_instruction
*inst
)
4413 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4414 exec_atomop_img(mach
, inst
);
4415 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
4416 exec_atomop_buf(mach
, inst
);
4417 else if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
)
4418 exec_atomop_mem(mach
, inst
);
4422 exec_resq_img(struct tgsi_exec_machine
*mach
,
4423 const struct tgsi_full_instruction
*inst
)
4426 union tgsi_exec_channel r
[4];
4429 struct tgsi_image_params params
;
4430 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4432 unit
= fetch_sampler_unit(mach
, inst
, 0);
4434 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4436 params
.tgsi_tex_instr
= inst
->Memory
.Texture
;
4437 params
.format
= inst
->Memory
.Format
;
4439 mach
->Image
->get_dims(mach
->Image
, ¶ms
, result
);
4441 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4442 for (j
= 0; j
< 4; j
++) {
4443 r
[j
].i
[i
] = result
[j
];
4447 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4448 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4449 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4450 TGSI_EXEC_DATA_INT
);
4456 exec_resq_buf(struct tgsi_exec_machine
*mach
,
4457 const struct tgsi_full_instruction
*inst
)
4460 union tgsi_exec_channel r
[4];
4463 struct tgsi_buffer_params params
;
4464 int kilmask
= mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];
4466 unit
= fetch_sampler_unit(mach
, inst
, 0);
4468 params
.execmask
= mach
->ExecMask
& mach
->NonHelperMask
& ~kilmask
;
4471 mach
->Buffer
->get_dims(mach
->Buffer
, ¶ms
, &result
);
4473 for (i
= 0; i
< TGSI_QUAD_SIZE
; i
++) {
4477 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
4478 if (inst
->Dst
[0].Register
.WriteMask
& (1 << chan
)) {
4479 store_dest(mach
, &r
[chan
], &inst
->Dst
[0], inst
, chan
,
4480 TGSI_EXEC_DATA_INT
);
4486 exec_resq(struct tgsi_exec_machine
*mach
,
4487 const struct tgsi_full_instruction
*inst
)
4489 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
4490 exec_resq_img(mach
, inst
);
4492 exec_resq_buf(mach
, inst
);
4496 micro_f2u64(union tgsi_double_channel
*dst
,
4497 const union tgsi_exec_channel
*src
)
4499 dst
->u64
[0] = (uint64_t)src
->f
[0];
4500 dst
->u64
[1] = (uint64_t)src
->f
[1];
4501 dst
->u64
[2] = (uint64_t)src
->f
[2];
4502 dst
->u64
[3] = (uint64_t)src
->f
[3];
4506 micro_f2i64(union tgsi_double_channel
*dst
,
4507 const union tgsi_exec_channel
*src
)
4509 dst
->i64
[0] = (int64_t)src
->f
[0];
4510 dst
->i64
[1] = (int64_t)src
->f
[1];
4511 dst
->i64
[2] = (int64_t)src
->f
[2];
4512 dst
->i64
[3] = (int64_t)src
->f
[3];
4516 micro_u2i64(union tgsi_double_channel
*dst
,
4517 const union tgsi_exec_channel
*src
)
4519 dst
->u64
[0] = (uint64_t)src
->u
[0];
4520 dst
->u64
[1] = (uint64_t)src
->u
[1];
4521 dst
->u64
[2] = (uint64_t)src
->u
[2];
4522 dst
->u64
[3] = (uint64_t)src
->u
[3];
4526 micro_i2i64(union tgsi_double_channel
*dst
,
4527 const union tgsi_exec_channel
*src
)
4529 dst
->i64
[0] = (int64_t)src
->i
[0];
4530 dst
->i64
[1] = (int64_t)src
->i
[1];
4531 dst
->i64
[2] = (int64_t)src
->i
[2];
4532 dst
->i64
[3] = (int64_t)src
->i
[3];
4536 micro_d2u64(union tgsi_double_channel
*dst
,
4537 const union tgsi_double_channel
*src
)
4539 dst
->u64
[0] = (uint64_t)src
->d
[0];
4540 dst
->u64
[1] = (uint64_t)src
->d
[1];
4541 dst
->u64
[2] = (uint64_t)src
->d
[2];
4542 dst
->u64
[3] = (uint64_t)src
->d
[3];
4546 micro_d2i64(union tgsi_double_channel
*dst
,
4547 const union tgsi_double_channel
*src
)
4549 dst
->i64
[0] = (int64_t)src
->d
[0];
4550 dst
->i64
[1] = (int64_t)src
->d
[1];
4551 dst
->i64
[2] = (int64_t)src
->d
[2];
4552 dst
->i64
[3] = (int64_t)src
->d
[3];
4556 micro_u642d(union tgsi_double_channel
*dst
,
4557 const union tgsi_double_channel
*src
)
4559 dst
->d
[0] = (double)src
->u64
[0];
4560 dst
->d
[1] = (double)src
->u64
[1];
4561 dst
->d
[2] = (double)src
->u64
[2];
4562 dst
->d
[3] = (double)src
->u64
[3];
4566 micro_i642d(union tgsi_double_channel
*dst
,
4567 const union tgsi_double_channel
*src
)
4569 dst
->d
[0] = (double)src
->i64
[0];
4570 dst
->d
[1] = (double)src
->i64
[1];
4571 dst
->d
[2] = (double)src
->i64
[2];
4572 dst
->d
[3] = (double)src
->i64
[3];
4576 micro_u642f(union tgsi_exec_channel
*dst
,
4577 const union tgsi_double_channel
*src
)
4579 dst
->f
[0] = (float)src
->u64
[0];
4580 dst
->f
[1] = (float)src
->u64
[1];
4581 dst
->f
[2] = (float)src
->u64
[2];
4582 dst
->f
[3] = (float)src
->u64
[3];
4586 micro_i642f(union tgsi_exec_channel
*dst
,
4587 const union tgsi_double_channel
*src
)
4589 dst
->f
[0] = (float)src
->i64
[0];
4590 dst
->f
[1] = (float)src
->i64
[1];
4591 dst
->f
[2] = (float)src
->i64
[2];
4592 dst
->f
[3] = (float)src
->i64
[3];
4596 exec_t_2_64(struct tgsi_exec_machine
*mach
,
4597 const struct tgsi_full_instruction
*inst
,
4599 enum tgsi_exec_datatype src_datatype
)
4601 union tgsi_exec_channel src
;
4602 union tgsi_double_channel dst
;
4604 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) == TGSI_WRITEMASK_XY
) {
4605 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, src_datatype
);
4607 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_X
, TGSI_CHAN_Y
);
4609 if ((inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_ZW
) == TGSI_WRITEMASK_ZW
) {
4610 fetch_source(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Y
, src_datatype
);
4612 store_double_channel(mach
, &dst
, &inst
->Dst
[0], inst
, TGSI_CHAN_Z
, TGSI_CHAN_W
);
4617 exec_64_2_t(struct tgsi_exec_machine
*mach
,
4618 const struct tgsi_full_instruction
*inst
,
4620 enum tgsi_exec_datatype dst_datatype
)
4622 union tgsi_double_channel src
;
4623 union tgsi_exec_channel dst
;
4624 int wm
= inst
->Dst
[0].Register
.WriteMask
;
4627 for (i
= 0; i
< 2; i
++) {
4630 wm
&= ~(1 << (bit
- 1));
4632 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_X
, TGSI_CHAN_Y
);
4634 fetch_double_channel(mach
, &src
, &inst
->Src
[0], TGSI_CHAN_Z
, TGSI_CHAN_W
);
4636 store_dest(mach
, &dst
, &inst
->Dst
[0], inst
, bit
- 1, dst_datatype
);
4642 micro_i2f(union tgsi_exec_channel
*dst
,
4643 const union tgsi_exec_channel
*src
)
4645 dst
->f
[0] = (float)src
->i
[0];
4646 dst
->f
[1] = (float)src
->i
[1];
4647 dst
->f
[2] = (float)src
->i
[2];
4648 dst
->f
[3] = (float)src
->i
[3];
4652 micro_not(union tgsi_exec_channel
*dst
,
4653 const union tgsi_exec_channel
*src
)
4655 dst
->u
[0] = ~src
->u
[0];
4656 dst
->u
[1] = ~src
->u
[1];
4657 dst
->u
[2] = ~src
->u
[2];
4658 dst
->u
[3] = ~src
->u
[3];
4662 micro_shl(union tgsi_exec_channel
*dst
,
4663 const union tgsi_exec_channel
*src0
,
4664 const union tgsi_exec_channel
*src1
)
4666 unsigned masked_count
;
4667 masked_count
= src1
->u
[0] & 0x1f;
4668 dst
->u
[0] = src0
->u
[0] << masked_count
;
4669 masked_count
= src1
->u
[1] & 0x1f;
4670 dst
->u
[1] = src0
->u
[1] << masked_count
;
4671 masked_count
= src1
->u
[2] & 0x1f;
4672 dst
->u
[2] = src0
->u
[2] << masked_count
;
4673 masked_count
= src1
->u
[3] & 0x1f;
4674 dst
->u
[3] = src0
->u
[3] << masked_count
;
4678 micro_and(union tgsi_exec_channel
*dst
,
4679 const union tgsi_exec_channel
*src0
,
4680 const union tgsi_exec_channel
*src1
)
4682 dst
->u
[0] = src0
->u
[0] & src1
->u
[0];
4683 dst
->u
[1] = src0
->u
[1] & src1
->u
[1];
4684 dst
->u
[2] = src0
->u
[2] & src1
->u
[2];
4685 dst
->u
[3] = src0
->u
[3] & src1
->u
[3];
4689 micro_or(union tgsi_exec_channel
*dst
,
4690 const union tgsi_exec_channel
*src0
,
4691 const union tgsi_exec_channel
*src1
)
4693 dst
->u
[0] = src0
->u
[0] | src1
->u
[0];
4694 dst
->u
[1] = src0
->u
[1] | src1
->u
[1];
4695 dst
->u
[2] = src0
->u
[2] | src1
->u
[2];
4696 dst
->u
[3] = src0
->u
[3] | src1
->u
[3];
4700 micro_xor(union tgsi_exec_channel
*dst
,
4701 const union tgsi_exec_channel
*src0
,
4702 const union tgsi_exec_channel
*src1
)
4704 dst
->u
[0] = src0
->u
[0] ^ src1
->u
[0];
4705 dst
->u
[1] = src0
->u
[1] ^ src1
->u
[1];
4706 dst
->u
[2] = src0
->u
[2] ^ src1
->u
[2];
4707 dst
->u
[3] = src0
->u
[3] ^ src1
->u
[3];
4711 micro_mod(union tgsi_exec_channel
*dst
,
4712 const union tgsi_exec_channel
*src0
,
4713 const union tgsi_exec_channel
*src1
)
4715 dst
->i
[0] = src0
->i
[0] % src1
->i
[0];
4716 dst
->i
[1] = src0
->i
[1] % src1
->i
[1];
4717 dst
->i
[2] = src0
->i
[2] % src1
->i
[2];
4718 dst
->i
[3] = src0
->i
[3] % src1
->i
[3];
4722 micro_f2i(union tgsi_exec_channel
*dst
,
4723 const union tgsi_exec_channel
*src
)
4725 dst
->i
[0] = (int)src
->f
[0];
4726 dst
->i
[1] = (int)src
->f
[1];
4727 dst
->i
[2] = (int)src
->f
[2];
4728 dst
->i
[3] = (int)src
->f
[3];
4732 micro_fseq(union tgsi_exec_channel
*dst
,
4733 const union tgsi_exec_channel
*src0
,
4734 const union tgsi_exec_channel
*src1
)
4736 dst
->u
[0] = src0
->f
[0] == src1
->f
[0] ? ~0 : 0;
4737 dst
->u
[1] = src0
->f
[1] == src1
->f
[1] ? ~0 : 0;
4738 dst
->u
[2] = src0
->f
[2] == src1
->f
[2] ? ~0 : 0;
4739 dst
->u
[3] = src0
->f
[3] == src1
->f
[3] ? ~0 : 0;
4743 micro_fsge(union tgsi_exec_channel
*dst
,
4744 const union tgsi_exec_channel
*src0
,
4745 const union tgsi_exec_channel
*src1
)
4747 dst
->u
[0] = src0
->f
[0] >= src1
->f
[0] ? ~0 : 0;
4748 dst
->u
[1] = src0
->f
[1] >= src1
->f
[1] ? ~0 : 0;
4749 dst
->u
[2] = src0
->f
[2] >= src1
->f
[2] ? ~0 : 0;
4750 dst
->u
[3] = src0
->f
[3] >= src1
->f
[3] ? ~0 : 0;
4754 micro_fslt(union tgsi_exec_channel
*dst
,
4755 const union tgsi_exec_channel
*src0
,
4756 const union tgsi_exec_channel
*src1
)
4758 dst
->u
[0] = src0
->f
[0] < src1
->f
[0] ? ~0 : 0;
4759 dst
->u
[1] = src0
->f
[1] < src1
->f
[1] ? ~0 : 0;
4760 dst
->u
[2] = src0
->f
[2] < src1
->f
[2] ? ~0 : 0;
4761 dst
->u
[3] = src0
->f
[3] < src1
->f
[3] ? ~0 : 0;
4765 micro_fsne(union tgsi_exec_channel
*dst
,
4766 const union tgsi_exec_channel
*src0
,
4767 const union tgsi_exec_channel
*src1
)
4769 dst
->u
[0] = src0
->f
[0] != src1
->f
[0] ? ~0 : 0;
4770 dst
->u
[1] = src0
->f
[1] != src1
->f
[1] ? ~0 : 0;
4771 dst
->u
[2] = src0
->f
[2] != src1
->f
[2] ? ~0 : 0;
4772 dst
->u
[3] = src0
->f
[3] != src1
->f
[3] ? ~0 : 0;
4776 micro_idiv(union tgsi_exec_channel
*dst
,
4777 const union tgsi_exec_channel
*src0
,
4778 const union tgsi_exec_channel
*src1
)
4780 dst
->i
[0] = src1
->i
[0] ? src0
->i
[0] / src1
->i
[0] : 0;
4781 dst
->i
[1] = src1
->i
[1] ? src0
->i
[1] / src1
->i
[1] : 0;
4782 dst
->i
[2] = src1
->i
[2] ? src0
->i
[2] / src1
->i
[2] : 0;
4783 dst
->i
[3] = src1
->i
[3] ? src0
->i
[3] / src1
->i
[3] : 0;
4787 micro_imax(union tgsi_exec_channel
*dst
,
4788 const union tgsi_exec_channel
*src0
,
4789 const union tgsi_exec_channel
*src1
)
4791 dst
->i
[0] = src0
->i
[0] > src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4792 dst
->i
[1] = src0
->i
[1] > src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4793 dst
->i
[2] = src0
->i
[2] > src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4794 dst
->i
[3] = src0
->i
[3] > src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4798 micro_imin(union tgsi_exec_channel
*dst
,
4799 const union tgsi_exec_channel
*src0
,
4800 const union tgsi_exec_channel
*src1
)
4802 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? src0
->i
[0] : src1
->i
[0];
4803 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? src0
->i
[1] : src1
->i
[1];
4804 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? src0
->i
[2] : src1
->i
[2];
4805 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? src0
->i
[3] : src1
->i
[3];
4809 micro_isge(union tgsi_exec_channel
*dst
,
4810 const union tgsi_exec_channel
*src0
,
4811 const union tgsi_exec_channel
*src1
)
4813 dst
->i
[0] = src0
->i
[0] >= src1
->i
[0] ? -1 : 0;
4814 dst
->i
[1] = src0
->i
[1] >= src1
->i
[1] ? -1 : 0;
4815 dst
->i
[2] = src0
->i
[2] >= src1
->i
[2] ? -1 : 0;
4816 dst
->i
[3] = src0
->i
[3] >= src1
->i
[3] ? -1 : 0;
4820 micro_ishr(union tgsi_exec_channel
*dst
,
4821 const union tgsi_exec_channel
*src0
,
4822 const union tgsi_exec_channel
*src1
)
4824 unsigned masked_count
;
4825 masked_count
= src1
->i
[0] & 0x1f;
4826 dst
->i
[0] = src0
->i
[0] >> masked_count
;
4827 masked_count
= src1
->i
[1] & 0x1f;
4828 dst
->i
[1] = src0
->i
[1] >> masked_count
;
4829 masked_count
= src1
->i
[2] & 0x1f;
4830 dst
->i
[2] = src0
->i
[2] >> masked_count
;
4831 masked_count
= src1
->i
[3] & 0x1f;
4832 dst
->i
[3] = src0
->i
[3] >> masked_count
;
4836 micro_islt(union tgsi_exec_channel
*dst
,
4837 const union tgsi_exec_channel
*src0
,
4838 const union tgsi_exec_channel
*src1
)
4840 dst
->i
[0] = src0
->i
[0] < src1
->i
[0] ? -1 : 0;
4841 dst
->i
[1] = src0
->i
[1] < src1
->i
[1] ? -1 : 0;
4842 dst
->i
[2] = src0
->i
[2] < src1
->i
[2] ? -1 : 0;
4843 dst
->i
[3] = src0
->i
[3] < src1
->i
[3] ? -1 : 0;
4847 micro_f2u(union tgsi_exec_channel
*dst
,
4848 const union tgsi_exec_channel
*src
)
4850 dst
->u
[0] = (uint
)src
->f
[0];
4851 dst
->u
[1] = (uint
)src
->f
[1];
4852 dst
->u
[2] = (uint
)src
->f
[2];
4853 dst
->u
[3] = (uint
)src
->f
[3];
4857 micro_u2f(union tgsi_exec_channel
*dst
,
4858 const union tgsi_exec_channel
*src
)
4860 dst
->f
[0] = (float)src
->u
[0];
4861 dst
->f
[1] = (float)src
->u
[1];
4862 dst
->f
[2] = (float)src
->u
[2];
4863 dst
->f
[3] = (float)src
->u
[3];
4867 micro_uadd(union tgsi_exec_channel
*dst
,
4868 const union tgsi_exec_channel
*src0
,
4869 const union tgsi_exec_channel
*src1
)
4871 dst
->u
[0] = src0
->u
[0] + src1
->u
[0];
4872 dst
->u
[1] = src0
->u
[1] + src1
->u
[1];
4873 dst
->u
[2] = src0
->u
[2] + src1
->u
[2];
4874 dst
->u
[3] = src0
->u
[3] + src1
->u
[3];
4878 micro_udiv(union tgsi_exec_channel
*dst
,
4879 const union tgsi_exec_channel
*src0
,
4880 const union tgsi_exec_channel
*src1
)
4882 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] / src1
->u
[0] : ~0u;
4883 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] / src1
->u
[1] : ~0u;
4884 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] / src1
->u
[2] : ~0u;
4885 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] / src1
->u
[3] : ~0u;
4889 micro_umad(union tgsi_exec_channel
*dst
,
4890 const union tgsi_exec_channel
*src0
,
4891 const union tgsi_exec_channel
*src1
,
4892 const union tgsi_exec_channel
*src2
)
4894 dst
->u
[0] = src0
->u
[0] * src1
->u
[0] + src2
->u
[0];
4895 dst
->u
[1] = src0
->u
[1] * src1
->u
[1] + src2
->u
[1];
4896 dst
->u
[2] = src0
->u
[2] * src1
->u
[2] + src2
->u
[2];
4897 dst
->u
[3] = src0
->u
[3] * src1
->u
[3] + src2
->u
[3];
4901 micro_umax(union tgsi_exec_channel
*dst
,
4902 const union tgsi_exec_channel
*src0
,
4903 const union tgsi_exec_channel
*src1
)
4905 dst
->u
[0] = src0
->u
[0] > src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4906 dst
->u
[1] = src0
->u
[1] > src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4907 dst
->u
[2] = src0
->u
[2] > src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4908 dst
->u
[3] = src0
->u
[3] > src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4912 micro_umin(union tgsi_exec_channel
*dst
,
4913 const union tgsi_exec_channel
*src0
,
4914 const union tgsi_exec_channel
*src1
)
4916 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? src0
->u
[0] : src1
->u
[0];
4917 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? src0
->u
[1] : src1
->u
[1];
4918 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? src0
->u
[2] : src1
->u
[2];
4919 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? src0
->u
[3] : src1
->u
[3];
4923 micro_umod(union tgsi_exec_channel
*dst
,
4924 const union tgsi_exec_channel
*src0
,
4925 const union tgsi_exec_channel
*src1
)
4927 dst
->u
[0] = src1
->u
[0] ? src0
->u
[0] % src1
->u
[0] : ~0u;
4928 dst
->u
[1] = src1
->u
[1] ? src0
->u
[1] % src1
->u
[1] : ~0u;
4929 dst
->u
[2] = src1
->u
[2] ? src0
->u
[2] % src1
->u
[2] : ~0u;
4930 dst
->u
[3] = src1
->u
[3] ? src0
->u
[3] % src1
->u
[3] : ~0u;
4934 micro_umul(union tgsi_exec_channel
*dst
,
4935 const union tgsi_exec_channel
*src0
,
4936 const union tgsi_exec_channel
*src1
)
4938 dst
->u
[0] = src0
->u
[0] * src1
->u
[0];
4939 dst
->u
[1] = src0
->u
[1] * src1
->u
[1];
4940 dst
->u
[2] = src0
->u
[2] * src1
->u
[2];
4941 dst
->u
[3] = src0
->u
[3] * src1
->u
[3];
4945 micro_imul_hi(union tgsi_exec_channel
*dst
,
4946 const union tgsi_exec_channel
*src0
,
4947 const union tgsi_exec_channel
*src1
)
4949 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
4950 dst
->i
[0] = I64M(src0
->i
[0], src1
->i
[0]);
4951 dst
->i
[1] = I64M(src0
->i
[1], src1
->i
[1]);
4952 dst
->i
[2] = I64M(src0
->i
[2], src1
->i
[2]);
4953 dst
->i
[3] = I64M(src0
->i
[3], src1
->i
[3]);
4958 micro_umul_hi(union tgsi_exec_channel
*dst
,
4959 const union tgsi_exec_channel
*src0
,
4960 const union tgsi_exec_channel
*src1
)
4962 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
4963 dst
->u
[0] = U64M(src0
->u
[0], src1
->u
[0]);
4964 dst
->u
[1] = U64M(src0
->u
[1], src1
->u
[1]);
4965 dst
->u
[2] = U64M(src0
->u
[2], src1
->u
[2]);
4966 dst
->u
[3] = U64M(src0
->u
[3], src1
->u
[3]);
4971 micro_useq(union tgsi_exec_channel
*dst
,
4972 const union tgsi_exec_channel
*src0
,
4973 const union tgsi_exec_channel
*src1
)
4975 dst
->u
[0] = src0
->u
[0] == src1
->u
[0] ? ~0 : 0;
4976 dst
->u
[1] = src0
->u
[1] == src1
->u
[1] ? ~0 : 0;
4977 dst
->u
[2] = src0
->u
[2] == src1
->u
[2] ? ~0 : 0;
4978 dst
->u
[3] = src0
->u
[3] == src1
->u
[3] ? ~0 : 0;
4982 micro_usge(union tgsi_exec_channel
*dst
,
4983 const union tgsi_exec_channel
*src0
,
4984 const union tgsi_exec_channel
*src1
)
4986 dst
->u
[0] = src0
->u
[0] >= src1
->u
[0] ? ~0 : 0;
4987 dst
->u
[1] = src0
->u
[1] >= src1
->u
[1] ? ~0 : 0;
4988 dst
->u
[2] = src0
->u
[2] >= src1
->u
[2] ? ~0 : 0;
4989 dst
->u
[3] = src0
->u
[3] >= src1
->u
[3] ? ~0 : 0;
4993 micro_ushr(union tgsi_exec_channel
*dst
,
4994 const union tgsi_exec_channel
*src0
,
4995 const union tgsi_exec_channel
*src1
)
4997 unsigned masked_count
;
4998 masked_count
= src1
->u
[0] & 0x1f;
4999 dst
->u
[0] = src0
->u
[0] >> masked_count
;
5000 masked_count
= src1
->u
[1] & 0x1f;
5001 dst
->u
[1] = src0
->u
[1] >> masked_count
;
5002 masked_count
= src1
->u
[2] & 0x1f;
5003 dst
->u
[2] = src0
->u
[2] >> masked_count
;
5004 masked_count
= src1
->u
[3] & 0x1f;
5005 dst
->u
[3] = src0
->u
[3] >> masked_count
;
5009 micro_uslt(union tgsi_exec_channel
*dst
,
5010 const union tgsi_exec_channel
*src0
,
5011 const union tgsi_exec_channel
*src1
)
5013 dst
->u
[0] = src0
->u
[0] < src1
->u
[0] ? ~0 : 0;
5014 dst
->u
[1] = src0
->u
[1] < src1
->u
[1] ? ~0 : 0;
5015 dst
->u
[2] = src0
->u
[2] < src1
->u
[2] ? ~0 : 0;
5016 dst
->u
[3] = src0
->u
[3] < src1
->u
[3] ? ~0 : 0;
5020 micro_usne(union tgsi_exec_channel
*dst
,
5021 const union tgsi_exec_channel
*src0
,
5022 const union tgsi_exec_channel
*src1
)
5024 dst
->u
[0] = src0
->u
[0] != src1
->u
[0] ? ~0 : 0;
5025 dst
->u
[1] = src0
->u
[1] != src1
->u
[1] ? ~0 : 0;
5026 dst
->u
[2] = src0
->u
[2] != src1
->u
[2] ? ~0 : 0;
5027 dst
->u
[3] = src0
->u
[3] != src1
->u
[3] ? ~0 : 0;
5031 micro_uarl(union tgsi_exec_channel
*dst
,
5032 const union tgsi_exec_channel
*src
)
5034 dst
->i
[0] = src
->u
[0];
5035 dst
->i
[1] = src
->u
[1];
5036 dst
->i
[2] = src
->u
[2];
5037 dst
->i
[3] = src
->u
[3];
5041 * Signed bitfield extract (i.e. sign-extend the extracted bits)
5044 micro_ibfe(union tgsi_exec_channel
*dst
,
5045 const union tgsi_exec_channel
*src0
,
5046 const union tgsi_exec_channel
*src1
,
5047 const union tgsi_exec_channel
*src2
)
5050 for (i
= 0; i
< 4; i
++) {
5051 int width
= src2
->i
[i
] & 0x1f;
5052 int offset
= src1
->i
[i
] & 0x1f;
5055 else if (width
+ offset
< 32)
5056 dst
->i
[i
] = (src0
->i
[i
] << (32 - width
- offset
)) >> (32 - width
);
5058 dst
->i
[i
] = src0
->i
[i
] >> offset
;
5063 * Unsigned bitfield extract
5066 micro_ubfe(union tgsi_exec_channel
*dst
,
5067 const union tgsi_exec_channel
*src0
,
5068 const union tgsi_exec_channel
*src1
,
5069 const union tgsi_exec_channel
*src2
)
5072 for (i
= 0; i
< 4; i
++) {
5073 int width
= src2
->u
[i
] & 0x1f;
5074 int offset
= src1
->u
[i
] & 0x1f;
5077 else if (width
+ offset
< 32)
5078 dst
->u
[i
] = (src0
->u
[i
] << (32 - width
- offset
)) >> (32 - width
);
5080 dst
->u
[i
] = src0
->u
[i
] >> offset
;
5085 * Bitfield insert: copy low bits from src1 into a region of src0.
5088 micro_bfi(union tgsi_exec_channel
*dst
,
5089 const union tgsi_exec_channel
*src0
,
5090 const union tgsi_exec_channel
*src1
,
5091 const union tgsi_exec_channel
*src2
,
5092 const union tgsi_exec_channel
*src3
)
5095 for (i
= 0; i
< 4; i
++) {
5096 int width
= src3
->u
[i
] & 0x1f;
5097 int offset
= src2
->u
[i
] & 0x1f;
5098 int bitmask
= ((1 << width
) - 1) << offset
;
5099 dst
->u
[i
] = ((src1
->u
[i
] << offset
) & bitmask
) | (src0
->u
[i
] & ~bitmask
);
5104 micro_brev(union tgsi_exec_channel
*dst
,
5105 const union tgsi_exec_channel
*src
)
5107 dst
->u
[0] = util_bitreverse(src
->u
[0]);
5108 dst
->u
[1] = util_bitreverse(src
->u
[1]);
5109 dst
->u
[2] = util_bitreverse(src
->u
[2]);
5110 dst
->u
[3] = util_bitreverse(src
->u
[3]);
5114 micro_popc(union tgsi_exec_channel
*dst
,
5115 const union tgsi_exec_channel
*src
)
5117 dst
->u
[0] = util_bitcount(src
->u
[0]);
5118 dst
->u
[1] = util_bitcount(src
->u
[1]);
5119 dst
->u
[2] = util_bitcount(src
->u
[2]);
5120 dst
->u
[3] = util_bitcount(src
->u
[3]);
5124 micro_lsb(union tgsi_exec_channel
*dst
,
5125 const union tgsi_exec_channel
*src
)
5127 dst
->i
[0] = ffs(src
->u
[0]) - 1;
5128 dst
->i
[1] = ffs(src
->u
[1]) - 1;
5129 dst
->i
[2] = ffs(src
->u
[2]) - 1;
5130 dst
->i
[3] = ffs(src
->u
[3]) - 1;
5134 micro_imsb(union tgsi_exec_channel
*dst
,
5135 const union tgsi_exec_channel
*src
)
5137 dst
->i
[0] = util_last_bit_signed(src
->i
[0]) - 1;
5138 dst
->i
[1] = util_last_bit_signed(src
->i
[1]) - 1;
5139 dst
->i
[2] = util_last_bit_signed(src
->i
[2]) - 1;
5140 dst
->i
[3] = util_last_bit_signed(src
->i
[3]) - 1;
5144 micro_umsb(union tgsi_exec_channel
*dst
,
5145 const union tgsi_exec_channel
*src
)
5147 dst
->i
[0] = util_last_bit(src
->u
[0]) - 1;
5148 dst
->i
[1] = util_last_bit(src
->u
[1]) - 1;
5149 dst
->i
[2] = util_last_bit(src
->u
[2]) - 1;
5150 dst
->i
[3] = util_last_bit(src
->u
[3]) - 1;
5154 * Execute a TGSI instruction.
5155 * Returns TRUE if a barrier instruction is hit,
5160 struct tgsi_exec_machine
*mach
,
5161 const struct tgsi_full_instruction
*inst
,
5164 union tgsi_exec_channel r
[10];
5168 switch (inst
->Instruction
.Opcode
) {
5169 case TGSI_OPCODE_ARL
:
5170 exec_vector_unary(mach
, inst
, micro_arl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5173 case TGSI_OPCODE_MOV
:
5174 exec_vector_unary(mach
, inst
, micro_mov
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5177 case TGSI_OPCODE_LIT
:
5178 exec_lit(mach
, inst
);
5181 case TGSI_OPCODE_RCP
:
5182 exec_scalar_unary(mach
, inst
, micro_rcp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5185 case TGSI_OPCODE_RSQ
:
5186 exec_scalar_unary(mach
, inst
, micro_rsq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5189 case TGSI_OPCODE_EXP
:
5190 exec_exp(mach
, inst
);
5193 case TGSI_OPCODE_LOG
:
5194 exec_log(mach
, inst
);
5197 case TGSI_OPCODE_MUL
:
5198 exec_vector_binary(mach
, inst
, micro_mul
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5201 case TGSI_OPCODE_ADD
:
5202 exec_vector_binary(mach
, inst
, micro_add
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5205 case TGSI_OPCODE_DP3
:
5206 exec_dp3(mach
, inst
);
5209 case TGSI_OPCODE_DP4
:
5210 exec_dp4(mach
, inst
);
5213 case TGSI_OPCODE_DST
:
5214 exec_dst(mach
, inst
);
5217 case TGSI_OPCODE_MIN
:
5218 exec_vector_binary(mach
, inst
, micro_min
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5221 case TGSI_OPCODE_MAX
:
5222 exec_vector_binary(mach
, inst
, micro_max
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5225 case TGSI_OPCODE_SLT
:
5226 exec_vector_binary(mach
, inst
, micro_slt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5229 case TGSI_OPCODE_SGE
:
5230 exec_vector_binary(mach
, inst
, micro_sge
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5233 case TGSI_OPCODE_MAD
:
5234 exec_vector_trinary(mach
, inst
, micro_mad
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5237 case TGSI_OPCODE_LRP
:
5238 exec_vector_trinary(mach
, inst
, micro_lrp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5241 case TGSI_OPCODE_SQRT
:
5242 exec_scalar_unary(mach
, inst
, micro_sqrt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5245 case TGSI_OPCODE_DP2A
:
5246 exec_dp2a(mach
, inst
);
5249 case TGSI_OPCODE_FRC
:
5250 exec_vector_unary(mach
, inst
, micro_frc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5253 case TGSI_OPCODE_FLR
:
5254 exec_vector_unary(mach
, inst
, micro_flr
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5257 case TGSI_OPCODE_ROUND
:
5258 exec_vector_unary(mach
, inst
, micro_rnd
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5261 case TGSI_OPCODE_EX2
:
5262 exec_scalar_unary(mach
, inst
, micro_exp2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5265 case TGSI_OPCODE_LG2
:
5266 exec_scalar_unary(mach
, inst
, micro_lg2
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5269 case TGSI_OPCODE_POW
:
5270 exec_scalar_binary(mach
, inst
, micro_pow
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5273 case TGSI_OPCODE_XPD
:
5274 exec_xpd(mach
, inst
);
5277 case TGSI_OPCODE_DPH
:
5278 exec_dph(mach
, inst
);
5281 case TGSI_OPCODE_COS
:
5282 exec_scalar_unary(mach
, inst
, micro_cos
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5285 case TGSI_OPCODE_DDX
:
5286 exec_vector_unary(mach
, inst
, micro_ddx
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5289 case TGSI_OPCODE_DDY
:
5290 exec_vector_unary(mach
, inst
, micro_ddy
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5293 case TGSI_OPCODE_KILL
:
5294 exec_kill (mach
, inst
);
5297 case TGSI_OPCODE_KILL_IF
:
5298 exec_kill_if (mach
, inst
);
5301 case TGSI_OPCODE_PK2H
:
5302 exec_pk2h(mach
, inst
);
5305 case TGSI_OPCODE_PK2US
:
5309 case TGSI_OPCODE_PK4B
:
5313 case TGSI_OPCODE_PK4UB
:
5317 case TGSI_OPCODE_SEQ
:
5318 exec_vector_binary(mach
, inst
, micro_seq
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5321 case TGSI_OPCODE_SGT
:
5322 exec_vector_binary(mach
, inst
, micro_sgt
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5325 case TGSI_OPCODE_SIN
:
5326 exec_scalar_unary(mach
, inst
, micro_sin
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5329 case TGSI_OPCODE_SLE
:
5330 exec_vector_binary(mach
, inst
, micro_sle
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5333 case TGSI_OPCODE_SNE
:
5334 exec_vector_binary(mach
, inst
, micro_sne
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5337 case TGSI_OPCODE_TEX
:
5338 /* simple texture lookup */
5339 /* src[0] = texcoord */
5340 /* src[1] = sampler unit */
5341 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 1);
5344 case TGSI_OPCODE_TXB
:
5345 /* Texture lookup with lod bias */
5346 /* src[0] = texcoord (src[0].w = LOD bias) */
5347 /* src[1] = sampler unit */
5348 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 1);
5351 case TGSI_OPCODE_TXD
:
5352 /* Texture lookup with explict partial derivatives */
5353 /* src[0] = texcoord */
5354 /* src[1] = d[strq]/dx */
5355 /* src[2] = d[strq]/dy */
5356 /* src[3] = sampler unit */
5357 exec_txd(mach
, inst
);
5360 case TGSI_OPCODE_TXL
:
5361 /* Texture lookup with explit LOD */
5362 /* src[0] = texcoord (src[0].w = LOD) */
5363 /* src[1] = sampler unit */
5364 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 1);
5367 case TGSI_OPCODE_TXP
:
5368 /* Texture lookup with projection */
5369 /* src[0] = texcoord (src[0].w = projection) */
5370 /* src[1] = sampler unit */
5371 exec_tex(mach
, inst
, TEX_MODIFIER_PROJECTED
, 1);
5374 case TGSI_OPCODE_TG4
:
5375 /* src[0] = texcoord */
5376 /* src[1] = component */
5377 /* src[2] = sampler unit */
5378 exec_tex(mach
, inst
, TEX_MODIFIER_GATHER
, 2);
5381 case TGSI_OPCODE_LODQ
:
5382 /* src[0] = texcoord */
5383 /* src[1] = sampler unit */
5384 exec_lodq(mach
, inst
);
5387 case TGSI_OPCODE_UP2H
:
5388 exec_up2h(mach
, inst
);
5391 case TGSI_OPCODE_UP2US
:
5395 case TGSI_OPCODE_UP4B
:
5399 case TGSI_OPCODE_UP4UB
:
5403 case TGSI_OPCODE_ARR
:
5404 exec_vector_unary(mach
, inst
, micro_arr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5407 case TGSI_OPCODE_CAL
:
5408 /* skip the call if no execution channels are enabled */
5409 if (mach
->ExecMask
) {
5412 /* First, record the depths of the execution stacks.
5413 * This is important for deeply nested/looped return statements.
5414 * We have to unwind the stacks by the correct amount. For a
5415 * real code generator, we could determine the number of entries
5416 * to pop off each stack with simple static analysis and avoid
5417 * implementing this data structure at run time.
5419 mach
->CallStack
[mach
->CallStackTop
].CondStackTop
= mach
->CondStackTop
;
5420 mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
= mach
->LoopStackTop
;
5421 mach
->CallStack
[mach
->CallStackTop
].ContStackTop
= mach
->ContStackTop
;
5422 mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
= mach
->SwitchStackTop
;
5423 mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
= mach
->BreakStackTop
;
5424 /* note that PC was already incremented above */
5425 mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
= *pc
;
5427 mach
->CallStackTop
++;
5429 /* Second, push the Cond, Loop, Cont, Func stacks */
5430 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5431 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5432 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5433 assert(mach
->SwitchStackTop
< TGSI_EXEC_MAX_SWITCH_NESTING
);
5434 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5435 assert(mach
->FuncStackTop
< TGSI_EXEC_MAX_CALL_NESTING
);
5437 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5438 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5439 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5440 mach
->SwitchStack
[mach
->SwitchStackTop
++] = mach
->Switch
;
5441 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5442 mach
->FuncStack
[mach
->FuncStackTop
++] = mach
->FuncMask
;
5444 /* Finally, jump to the subroutine. The label is a pointer
5445 * (an instruction number) to the BGNSUB instruction.
5447 *pc
= inst
->Label
.Label
;
5448 assert(mach
->Instructions
[*pc
].Instruction
.Opcode
5449 == TGSI_OPCODE_BGNSUB
);
5453 case TGSI_OPCODE_RET
:
5454 mach
->FuncMask
&= ~mach
->ExecMask
;
5455 UPDATE_EXEC_MASK(mach
);
5457 if (mach
->FuncMask
== 0x0) {
5458 /* really return now (otherwise, keep executing */
5460 if (mach
->CallStackTop
== 0) {
5461 /* returning from main() */
5462 mach
->CondStackTop
= 0;
5463 mach
->LoopStackTop
= 0;
5464 mach
->ContStackTop
= 0;
5465 mach
->LoopLabelStackTop
= 0;
5466 mach
->SwitchStackTop
= 0;
5467 mach
->BreakStackTop
= 0;
5472 assert(mach
->CallStackTop
> 0);
5473 mach
->CallStackTop
--;
5475 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5476 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5478 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5479 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5481 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5482 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5484 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5485 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5487 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5488 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5490 assert(mach
->FuncStackTop
> 0);
5491 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5493 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5495 UPDATE_EXEC_MASK(mach
);
5499 case TGSI_OPCODE_SSG
:
5500 exec_vector_unary(mach
, inst
, micro_sgn
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5503 case TGSI_OPCODE_CMP
:
5504 exec_vector_trinary(mach
, inst
, micro_cmp
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5507 case TGSI_OPCODE_SCS
:
5508 exec_scs(mach
, inst
);
5511 case TGSI_OPCODE_DIV
:
5512 exec_vector_binary(mach
, inst
, micro_div
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5515 case TGSI_OPCODE_DP2
:
5516 exec_dp2(mach
, inst
);
5519 case TGSI_OPCODE_IF
:
5521 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5522 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5523 FETCH( &r
[0], 0, TGSI_CHAN_X
);
5524 /* update CondMask */
5526 mach
->CondMask
&= ~0x1;
5529 mach
->CondMask
&= ~0x2;
5532 mach
->CondMask
&= ~0x4;
5535 mach
->CondMask
&= ~0x8;
5537 UPDATE_EXEC_MASK(mach
);
5538 /* Todo: If CondMask==0, jump to ELSE */
5541 case TGSI_OPCODE_UIF
:
5543 assert(mach
->CondStackTop
< TGSI_EXEC_MAX_COND_NESTING
);
5544 mach
->CondStack
[mach
->CondStackTop
++] = mach
->CondMask
;
5545 IFETCH( &r
[0], 0, TGSI_CHAN_X
);
5546 /* update CondMask */
5548 mach
->CondMask
&= ~0x1;
5551 mach
->CondMask
&= ~0x2;
5554 mach
->CondMask
&= ~0x4;
5557 mach
->CondMask
&= ~0x8;
5559 UPDATE_EXEC_MASK(mach
);
5560 /* Todo: If CondMask==0, jump to ELSE */
5563 case TGSI_OPCODE_ELSE
:
5564 /* invert CondMask wrt previous mask */
5567 assert(mach
->CondStackTop
> 0);
5568 prevMask
= mach
->CondStack
[mach
->CondStackTop
- 1];
5569 mach
->CondMask
= ~mach
->CondMask
& prevMask
;
5570 UPDATE_EXEC_MASK(mach
);
5571 /* Todo: If CondMask==0, jump to ENDIF */
5575 case TGSI_OPCODE_ENDIF
:
5577 assert(mach
->CondStackTop
> 0);
5578 mach
->CondMask
= mach
->CondStack
[--mach
->CondStackTop
];
5579 UPDATE_EXEC_MASK(mach
);
5582 case TGSI_OPCODE_END
:
5583 /* make sure we end primitives which haven't
5584 * been explicitly emitted */
5585 conditional_emit_primitive(mach
);
5586 /* halt execution */
5590 case TGSI_OPCODE_PUSHA
:
5594 case TGSI_OPCODE_POPA
:
5598 case TGSI_OPCODE_CEIL
:
5599 exec_vector_unary(mach
, inst
, micro_ceil
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5602 case TGSI_OPCODE_I2F
:
5603 exec_vector_unary(mach
, inst
, micro_i2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_INT
);
5606 case TGSI_OPCODE_NOT
:
5607 exec_vector_unary(mach
, inst
, micro_not
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5610 case TGSI_OPCODE_TRUNC
:
5611 exec_vector_unary(mach
, inst
, micro_trunc
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_FLOAT
);
5614 case TGSI_OPCODE_SHL
:
5615 exec_vector_binary(mach
, inst
, micro_shl
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5618 case TGSI_OPCODE_AND
:
5619 exec_vector_binary(mach
, inst
, micro_and
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5622 case TGSI_OPCODE_OR
:
5623 exec_vector_binary(mach
, inst
, micro_or
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5626 case TGSI_OPCODE_MOD
:
5627 exec_vector_binary(mach
, inst
, micro_mod
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5630 case TGSI_OPCODE_XOR
:
5631 exec_vector_binary(mach
, inst
, micro_xor
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5634 case TGSI_OPCODE_SAD
:
5638 case TGSI_OPCODE_TXF
:
5639 exec_txf(mach
, inst
);
5642 case TGSI_OPCODE_TXQ
:
5643 exec_txq(mach
, inst
);
5646 case TGSI_OPCODE_EMIT
:
5650 case TGSI_OPCODE_ENDPRIM
:
5651 emit_primitive(mach
);
5654 case TGSI_OPCODE_BGNLOOP
:
5655 /* push LoopMask and ContMasks */
5656 assert(mach
->LoopStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5657 assert(mach
->ContStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5658 assert(mach
->LoopLabelStackTop
< TGSI_EXEC_MAX_LOOP_NESTING
);
5659 assert(mach
->BreakStackTop
< TGSI_EXEC_MAX_BREAK_STACK
);
5661 mach
->LoopStack
[mach
->LoopStackTop
++] = mach
->LoopMask
;
5662 mach
->ContStack
[mach
->ContStackTop
++] = mach
->ContMask
;
5663 mach
->LoopLabelStack
[mach
->LoopLabelStackTop
++] = *pc
- 1;
5664 mach
->BreakStack
[mach
->BreakStackTop
++] = mach
->BreakType
;
5665 mach
->BreakType
= TGSI_EXEC_BREAK_INSIDE_LOOP
;
5668 case TGSI_OPCODE_ENDLOOP
:
5669 /* Restore ContMask, but don't pop */
5670 assert(mach
->ContStackTop
> 0);
5671 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
- 1];
5672 UPDATE_EXEC_MASK(mach
);
5673 if (mach
->ExecMask
) {
5674 /* repeat loop: jump to instruction just past BGNLOOP */
5675 assert(mach
->LoopLabelStackTop
> 0);
5676 *pc
= mach
->LoopLabelStack
[mach
->LoopLabelStackTop
- 1] + 1;
5679 /* exit loop: pop LoopMask */
5680 assert(mach
->LoopStackTop
> 0);
5681 mach
->LoopMask
= mach
->LoopStack
[--mach
->LoopStackTop
];
5683 assert(mach
->ContStackTop
> 0);
5684 mach
->ContMask
= mach
->ContStack
[--mach
->ContStackTop
];
5685 assert(mach
->LoopLabelStackTop
> 0);
5686 --mach
->LoopLabelStackTop
;
5688 mach
->BreakType
= mach
->BreakStack
[--mach
->BreakStackTop
];
5690 UPDATE_EXEC_MASK(mach
);
5693 case TGSI_OPCODE_BRK
:
5697 case TGSI_OPCODE_CONT
:
5698 /* turn off cont channels for each enabled exec channel */
5699 mach
->ContMask
&= ~mach
->ExecMask
;
5700 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5701 UPDATE_EXEC_MASK(mach
);
5704 case TGSI_OPCODE_BGNSUB
:
5708 case TGSI_OPCODE_ENDSUB
:
5710 * XXX: This really should be a no-op. We should never reach this opcode.
5713 assert(mach
->CallStackTop
> 0);
5714 mach
->CallStackTop
--;
5716 mach
->CondStackTop
= mach
->CallStack
[mach
->CallStackTop
].CondStackTop
;
5717 mach
->CondMask
= mach
->CondStack
[mach
->CondStackTop
];
5719 mach
->LoopStackTop
= mach
->CallStack
[mach
->CallStackTop
].LoopStackTop
;
5720 mach
->LoopMask
= mach
->LoopStack
[mach
->LoopStackTop
];
5722 mach
->ContStackTop
= mach
->CallStack
[mach
->CallStackTop
].ContStackTop
;
5723 mach
->ContMask
= mach
->ContStack
[mach
->ContStackTop
];
5725 mach
->SwitchStackTop
= mach
->CallStack
[mach
->CallStackTop
].SwitchStackTop
;
5726 mach
->Switch
= mach
->SwitchStack
[mach
->SwitchStackTop
];
5728 mach
->BreakStackTop
= mach
->CallStack
[mach
->CallStackTop
].BreakStackTop
;
5729 mach
->BreakType
= mach
->BreakStack
[mach
->BreakStackTop
];
5731 assert(mach
->FuncStackTop
> 0);
5732 mach
->FuncMask
= mach
->FuncStack
[--mach
->FuncStackTop
];
5734 *pc
= mach
->CallStack
[mach
->CallStackTop
].ReturnAddr
;
5736 UPDATE_EXEC_MASK(mach
);
5739 case TGSI_OPCODE_NOP
:
5742 case TGSI_OPCODE_BREAKC
:
5743 IFETCH(&r
[0], 0, TGSI_CHAN_X
);
5744 /* update CondMask */
5745 if (r
[0].u
[0] && (mach
->ExecMask
& 0x1)) {
5746 mach
->LoopMask
&= ~0x1;
5748 if (r
[0].u
[1] && (mach
->ExecMask
& 0x2)) {
5749 mach
->LoopMask
&= ~0x2;
5751 if (r
[0].u
[2] && (mach
->ExecMask
& 0x4)) {
5752 mach
->LoopMask
&= ~0x4;
5754 if (r
[0].u
[3] && (mach
->ExecMask
& 0x8)) {
5755 mach
->LoopMask
&= ~0x8;
5757 /* Todo: if mach->LoopMask == 0, jump to end of loop */
5758 UPDATE_EXEC_MASK(mach
);
5761 case TGSI_OPCODE_F2I
:
5762 exec_vector_unary(mach
, inst
, micro_f2i
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_FLOAT
);
5765 case TGSI_OPCODE_FSEQ
:
5766 exec_vector_binary(mach
, inst
, micro_fseq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5769 case TGSI_OPCODE_FSGE
:
5770 exec_vector_binary(mach
, inst
, micro_fsge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5773 case TGSI_OPCODE_FSLT
:
5774 exec_vector_binary(mach
, inst
, micro_fslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5777 case TGSI_OPCODE_FSNE
:
5778 exec_vector_binary(mach
, inst
, micro_fsne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5781 case TGSI_OPCODE_IDIV
:
5782 exec_vector_binary(mach
, inst
, micro_idiv
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5785 case TGSI_OPCODE_IMAX
:
5786 exec_vector_binary(mach
, inst
, micro_imax
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5789 case TGSI_OPCODE_IMIN
:
5790 exec_vector_binary(mach
, inst
, micro_imin
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5793 case TGSI_OPCODE_INEG
:
5794 exec_vector_unary(mach
, inst
, micro_ineg
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5797 case TGSI_OPCODE_ISGE
:
5798 exec_vector_binary(mach
, inst
, micro_isge
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5801 case TGSI_OPCODE_ISHR
:
5802 exec_vector_binary(mach
, inst
, micro_ishr
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5805 case TGSI_OPCODE_ISLT
:
5806 exec_vector_binary(mach
, inst
, micro_islt
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5809 case TGSI_OPCODE_F2U
:
5810 exec_vector_unary(mach
, inst
, micro_f2u
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_FLOAT
);
5813 case TGSI_OPCODE_U2F
:
5814 exec_vector_unary(mach
, inst
, micro_u2f
, TGSI_EXEC_DATA_FLOAT
, TGSI_EXEC_DATA_UINT
);
5817 case TGSI_OPCODE_UADD
:
5818 exec_vector_binary(mach
, inst
, micro_uadd
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5821 case TGSI_OPCODE_UDIV
:
5822 exec_vector_binary(mach
, inst
, micro_udiv
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5825 case TGSI_OPCODE_UMAD
:
5826 exec_vector_trinary(mach
, inst
, micro_umad
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5829 case TGSI_OPCODE_UMAX
:
5830 exec_vector_binary(mach
, inst
, micro_umax
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5833 case TGSI_OPCODE_UMIN
:
5834 exec_vector_binary(mach
, inst
, micro_umin
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5837 case TGSI_OPCODE_UMOD
:
5838 exec_vector_binary(mach
, inst
, micro_umod
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5841 case TGSI_OPCODE_UMUL
:
5842 exec_vector_binary(mach
, inst
, micro_umul
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5845 case TGSI_OPCODE_IMUL_HI
:
5846 exec_vector_binary(mach
, inst
, micro_imul_hi
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5849 case TGSI_OPCODE_UMUL_HI
:
5850 exec_vector_binary(mach
, inst
, micro_umul_hi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5853 case TGSI_OPCODE_USEQ
:
5854 exec_vector_binary(mach
, inst
, micro_useq
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5857 case TGSI_OPCODE_USGE
:
5858 exec_vector_binary(mach
, inst
, micro_usge
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5861 case TGSI_OPCODE_USHR
:
5862 exec_vector_binary(mach
, inst
, micro_ushr
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5865 case TGSI_OPCODE_USLT
:
5866 exec_vector_binary(mach
, inst
, micro_uslt
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5869 case TGSI_OPCODE_USNE
:
5870 exec_vector_binary(mach
, inst
, micro_usne
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5873 case TGSI_OPCODE_SWITCH
:
5874 exec_switch(mach
, inst
);
5877 case TGSI_OPCODE_CASE
:
5878 exec_case(mach
, inst
);
5881 case TGSI_OPCODE_DEFAULT
:
5885 case TGSI_OPCODE_ENDSWITCH
:
5886 exec_endswitch(mach
);
5889 case TGSI_OPCODE_SAMPLE_I
:
5890 exec_txf(mach
, inst
);
5893 case TGSI_OPCODE_SAMPLE_I_MS
:
5894 exec_txf(mach
, inst
);
5897 case TGSI_OPCODE_SAMPLE
:
5898 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, FALSE
);
5901 case TGSI_OPCODE_SAMPLE_B
:
5902 exec_sample(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, FALSE
);
5905 case TGSI_OPCODE_SAMPLE_C
:
5906 exec_sample(mach
, inst
, TEX_MODIFIER_NONE
, TRUE
);
5909 case TGSI_OPCODE_SAMPLE_C_LZ
:
5910 exec_sample(mach
, inst
, TEX_MODIFIER_LEVEL_ZERO
, TRUE
);
5913 case TGSI_OPCODE_SAMPLE_D
:
5914 exec_sample_d(mach
, inst
);
5917 case TGSI_OPCODE_SAMPLE_L
:
5918 exec_sample(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, FALSE
);
5921 case TGSI_OPCODE_GATHER4
:
5925 case TGSI_OPCODE_SVIEWINFO
:
5926 exec_txq(mach
, inst
);
5929 case TGSI_OPCODE_SAMPLE_POS
:
5933 case TGSI_OPCODE_SAMPLE_INFO
:
5937 case TGSI_OPCODE_UARL
:
5938 exec_vector_unary(mach
, inst
, micro_uarl
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5941 case TGSI_OPCODE_UCMP
:
5942 exec_ucmp(mach
, inst
);
5945 case TGSI_OPCODE_IABS
:
5946 exec_vector_unary(mach
, inst
, micro_iabs
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5949 case TGSI_OPCODE_ISSG
:
5950 exec_vector_unary(mach
, inst
, micro_isgn
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5953 case TGSI_OPCODE_TEX2
:
5954 /* simple texture lookup */
5955 /* src[0] = texcoord */
5956 /* src[1] = compare */
5957 /* src[2] = sampler unit */
5958 exec_tex(mach
, inst
, TEX_MODIFIER_NONE
, 2);
5960 case TGSI_OPCODE_TXB2
:
5961 /* simple texture lookup */
5962 /* src[0] = texcoord */
5964 /* src[2] = sampler unit */
5965 exec_tex(mach
, inst
, TEX_MODIFIER_LOD_BIAS
, 2);
5967 case TGSI_OPCODE_TXL2
:
5968 /* simple texture lookup */
5969 /* src[0] = texcoord */
5971 /* src[2] = sampler unit */
5972 exec_tex(mach
, inst
, TEX_MODIFIER_EXPLICIT_LOD
, 2);
5975 case TGSI_OPCODE_IBFE
:
5976 exec_vector_trinary(mach
, inst
, micro_ibfe
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5978 case TGSI_OPCODE_UBFE
:
5979 exec_vector_trinary(mach
, inst
, micro_ubfe
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5981 case TGSI_OPCODE_BFI
:
5982 exec_vector_quaternary(mach
, inst
, micro_bfi
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5984 case TGSI_OPCODE_BREV
:
5985 exec_vector_unary(mach
, inst
, micro_brev
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5987 case TGSI_OPCODE_POPC
:
5988 exec_vector_unary(mach
, inst
, micro_popc
, TGSI_EXEC_DATA_UINT
, TGSI_EXEC_DATA_UINT
);
5990 case TGSI_OPCODE_LSB
:
5991 exec_vector_unary(mach
, inst
, micro_lsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
5993 case TGSI_OPCODE_IMSB
:
5994 exec_vector_unary(mach
, inst
, micro_imsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_INT
);
5996 case TGSI_OPCODE_UMSB
:
5997 exec_vector_unary(mach
, inst
, micro_umsb
, TGSI_EXEC_DATA_INT
, TGSI_EXEC_DATA_UINT
);
6000 case TGSI_OPCODE_F2D
:
6001 exec_t_2_64(mach
, inst
, micro_f2d
, TGSI_EXEC_DATA_FLOAT
);
6004 case TGSI_OPCODE_D2F
:
6005 exec_64_2_t(mach
, inst
, micro_d2f
, TGSI_EXEC_DATA_FLOAT
);
6008 case TGSI_OPCODE_DABS
:
6009 exec_double_unary(mach
, inst
, micro_dabs
);
6012 case TGSI_OPCODE_DNEG
:
6013 exec_double_unary(mach
, inst
, micro_dneg
);
6016 case TGSI_OPCODE_DADD
:
6017 exec_double_binary(mach
, inst
, micro_dadd
, TGSI_EXEC_DATA_DOUBLE
);
6020 case TGSI_OPCODE_DDIV
:
6021 exec_double_binary(mach
, inst
, micro_ddiv
, TGSI_EXEC_DATA_DOUBLE
);
6024 case TGSI_OPCODE_DMUL
:
6025 exec_double_binary(mach
, inst
, micro_dmul
, TGSI_EXEC_DATA_DOUBLE
);
6028 case TGSI_OPCODE_DMAX
:
6029 exec_double_binary(mach
, inst
, micro_dmax
, TGSI_EXEC_DATA_DOUBLE
);
6032 case TGSI_OPCODE_DMIN
:
6033 exec_double_binary(mach
, inst
, micro_dmin
, TGSI_EXEC_DATA_DOUBLE
);
6036 case TGSI_OPCODE_DSLT
:
6037 exec_double_binary(mach
, inst
, micro_dslt
, TGSI_EXEC_DATA_UINT
);
6040 case TGSI_OPCODE_DSGE
:
6041 exec_double_binary(mach
, inst
, micro_dsge
, TGSI_EXEC_DATA_UINT
);
6044 case TGSI_OPCODE_DSEQ
:
6045 exec_double_binary(mach
, inst
, micro_dseq
, TGSI_EXEC_DATA_UINT
);
6048 case TGSI_OPCODE_DSNE
:
6049 exec_double_binary(mach
, inst
, micro_dsne
, TGSI_EXEC_DATA_UINT
);
6052 case TGSI_OPCODE_DRCP
:
6053 exec_double_unary(mach
, inst
, micro_drcp
);
6056 case TGSI_OPCODE_DSQRT
:
6057 exec_double_unary(mach
, inst
, micro_dsqrt
);
6060 case TGSI_OPCODE_DRSQ
:
6061 exec_double_unary(mach
, inst
, micro_drsq
);
6064 case TGSI_OPCODE_DMAD
:
6065 exec_double_trinary(mach
, inst
, micro_dmad
);
6068 case TGSI_OPCODE_DFRAC
:
6069 exec_double_unary(mach
, inst
, micro_dfrac
);
6072 case TGSI_OPCODE_DLDEXP
:
6073 exec_dldexp(mach
, inst
);
6076 case TGSI_OPCODE_DFRACEXP
:
6077 exec_dfracexp(mach
, inst
);
6080 case TGSI_OPCODE_I2D
:
6081 exec_t_2_64(mach
, inst
, micro_i2d
, TGSI_EXEC_DATA_INT
);
6084 case TGSI_OPCODE_D2I
:
6085 exec_64_2_t(mach
, inst
, micro_d2i
, TGSI_EXEC_DATA_INT
);
6088 case TGSI_OPCODE_U2D
:
6089 exec_t_2_64(mach
, inst
, micro_u2d
, TGSI_EXEC_DATA_UINT
);
6092 case TGSI_OPCODE_D2U
:
6093 exec_64_2_t(mach
, inst
, micro_d2u
, TGSI_EXEC_DATA_INT
);
6096 case TGSI_OPCODE_LOAD
:
6097 exec_load(mach
, inst
);
6100 case TGSI_OPCODE_STORE
:
6101 exec_store(mach
, inst
);
6104 case TGSI_OPCODE_ATOMUADD
:
6105 case TGSI_OPCODE_ATOMXCHG
:
6106 case TGSI_OPCODE_ATOMCAS
:
6107 case TGSI_OPCODE_ATOMAND
:
6108 case TGSI_OPCODE_ATOMOR
:
6109 case TGSI_OPCODE_ATOMXOR
:
6110 case TGSI_OPCODE_ATOMUMIN
:
6111 case TGSI_OPCODE_ATOMUMAX
:
6112 case TGSI_OPCODE_ATOMIMIN
:
6113 case TGSI_OPCODE_ATOMIMAX
:
6114 exec_atomop(mach
, inst
);
6117 case TGSI_OPCODE_RESQ
:
6118 exec_resq(mach
, inst
);
6120 case TGSI_OPCODE_BARRIER
:
6121 case TGSI_OPCODE_MEMBAR
:
6125 case TGSI_OPCODE_I64ABS
:
6126 exec_double_unary(mach
, inst
, micro_i64abs
);
6129 case TGSI_OPCODE_I64SSG
:
6130 exec_double_unary(mach
, inst
, micro_i64sgn
);
6133 case TGSI_OPCODE_I64NEG
:
6134 exec_double_unary(mach
, inst
, micro_i64neg
);
6137 case TGSI_OPCODE_U64SEQ
:
6138 exec_double_binary(mach
, inst
, micro_u64seq
, TGSI_EXEC_DATA_UINT
);
6141 case TGSI_OPCODE_U64SNE
:
6142 exec_double_binary(mach
, inst
, micro_u64sne
, TGSI_EXEC_DATA_UINT
);
6145 case TGSI_OPCODE_I64SLT
:
6146 exec_double_binary(mach
, inst
, micro_i64slt
, TGSI_EXEC_DATA_UINT
);
6148 case TGSI_OPCODE_U64SLT
:
6149 exec_double_binary(mach
, inst
, micro_u64slt
, TGSI_EXEC_DATA_UINT
);
6152 case TGSI_OPCODE_I64SGE
:
6153 exec_double_binary(mach
, inst
, micro_i64sge
, TGSI_EXEC_DATA_UINT
);
6155 case TGSI_OPCODE_U64SGE
:
6156 exec_double_binary(mach
, inst
, micro_u64sge
, TGSI_EXEC_DATA_UINT
);
6159 case TGSI_OPCODE_I64MIN
:
6160 exec_double_binary(mach
, inst
, micro_i64min
, TGSI_EXEC_DATA_INT64
);
6162 case TGSI_OPCODE_U64MIN
:
6163 exec_double_binary(mach
, inst
, micro_u64min
, TGSI_EXEC_DATA_UINT64
);
6165 case TGSI_OPCODE_I64MAX
:
6166 exec_double_binary(mach
, inst
, micro_i64max
, TGSI_EXEC_DATA_INT64
);
6168 case TGSI_OPCODE_U64MAX
:
6169 exec_double_binary(mach
, inst
, micro_u64max
, TGSI_EXEC_DATA_UINT64
);
6171 case TGSI_OPCODE_U64ADD
:
6172 exec_double_binary(mach
, inst
, micro_u64add
, TGSI_EXEC_DATA_UINT64
);
6174 case TGSI_OPCODE_U64MUL
:
6175 exec_double_binary(mach
, inst
, micro_u64mul
, TGSI_EXEC_DATA_UINT64
);
6177 case TGSI_OPCODE_U64SHL
:
6178 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shl
);
6180 case TGSI_OPCODE_I64SHR
:
6181 exec_arg0_64_arg1_32(mach
, inst
, micro_i64shr
);
6183 case TGSI_OPCODE_U64SHR
:
6184 exec_arg0_64_arg1_32(mach
, inst
, micro_u64shr
);
6186 case TGSI_OPCODE_U64DIV
:
6187 exec_double_binary(mach
, inst
, micro_u64div
, TGSI_EXEC_DATA_UINT64
);
6189 case TGSI_OPCODE_I64DIV
:
6190 exec_double_binary(mach
, inst
, micro_i64div
, TGSI_EXEC_DATA_INT64
);
6192 case TGSI_OPCODE_U64MOD
:
6193 exec_double_binary(mach
, inst
, micro_u64mod
, TGSI_EXEC_DATA_UINT64
);
6195 case TGSI_OPCODE_I64MOD
:
6196 exec_double_binary(mach
, inst
, micro_i64mod
, TGSI_EXEC_DATA_INT64
);
6199 case TGSI_OPCODE_F2U64
:
6200 exec_t_2_64(mach
, inst
, micro_f2u64
, TGSI_EXEC_DATA_FLOAT
);
6203 case TGSI_OPCODE_F2I64
:
6204 exec_t_2_64(mach
, inst
, micro_f2i64
, TGSI_EXEC_DATA_FLOAT
);
6207 case TGSI_OPCODE_U2I64
:
6208 exec_t_2_64(mach
, inst
, micro_u2i64
, TGSI_EXEC_DATA_INT
);
6210 case TGSI_OPCODE_I2I64
:
6211 exec_t_2_64(mach
, inst
, micro_i2i64
, TGSI_EXEC_DATA_INT
);
6214 case TGSI_OPCODE_D2U64
:
6215 exec_double_unary(mach
, inst
, micro_d2u64
);
6218 case TGSI_OPCODE_D2I64
:
6219 exec_double_unary(mach
, inst
, micro_d2i64
);
6222 case TGSI_OPCODE_U642F
:
6223 exec_64_2_t(mach
, inst
, micro_u642f
, TGSI_EXEC_DATA_FLOAT
);
6225 case TGSI_OPCODE_I642F
:
6226 exec_64_2_t(mach
, inst
, micro_i642f
, TGSI_EXEC_DATA_FLOAT
);
6229 case TGSI_OPCODE_U642D
:
6230 exec_double_unary(mach
, inst
, micro_u642d
);
6232 case TGSI_OPCODE_I642D
:
6233 exec_double_unary(mach
, inst
, micro_i642d
);
6243 tgsi_exec_machine_setup_masks(struct tgsi_exec_machine
*mach
)
6245 uint default_mask
= 0xf;
6247 mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0] = 0;
6248 mach
->Temps
[TEMP_OUTPUT_I
].xyzw
[TEMP_OUTPUT_C
].u
[0] = 0;
6250 if (mach
->ShaderType
== PIPE_SHADER_GEOMETRY
) {
6251 mach
->Temps
[TEMP_PRIMITIVE_I
].xyzw
[TEMP_PRIMITIVE_C
].u
[0] = 0;
6252 mach
->Primitives
[0] = 0;
6253 /* GS runs on a single primitive for now */
6257 if (mach
->NonHelperMask
== 0)
6258 mach
->NonHelperMask
= default_mask
;
6259 mach
->CondMask
= default_mask
;
6260 mach
->LoopMask
= default_mask
;
6261 mach
->ContMask
= default_mask
;
6262 mach
->FuncMask
= default_mask
;
6263 mach
->ExecMask
= default_mask
;
6265 mach
->Switch
.mask
= default_mask
;
6267 assert(mach
->CondStackTop
== 0);
6268 assert(mach
->LoopStackTop
== 0);
6269 assert(mach
->ContStackTop
== 0);
6270 assert(mach
->SwitchStackTop
== 0);
6271 assert(mach
->BreakStackTop
== 0);
6272 assert(mach
->CallStackTop
== 0);
6276 * Run TGSI interpreter.
6277 * \return bitmask of "alive" quad components
6280 tgsi_exec_machine_run( struct tgsi_exec_machine
*mach
, int start_pc
)
6284 mach
->pc
= start_pc
;
6287 tgsi_exec_machine_setup_masks(mach
);
6289 /* execute declarations (interpolants) */
6290 for (i
= 0; i
< mach
->NumDeclarations
; i
++) {
6291 exec_declaration( mach
, mach
->Declarations
+i
);
6297 struct tgsi_exec_vector temps
[TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
];
6298 struct tgsi_exec_vector outputs
[PIPE_MAX_ATTRIBS
];
6302 memset(mach
->Temps
, 0, sizeof(temps
));
6304 memset(mach
->Outputs
, 0, sizeof(outputs
));
6305 memset(temps
, 0, sizeof(temps
));
6306 memset(outputs
, 0, sizeof(outputs
));
6310 /* execute instructions, until pc is set to -1 */
6311 while (mach
->pc
!= -1) {
6312 boolean barrier_hit
;
6316 tgsi_dump_instruction(&mach
->Instructions
[mach
->pc
], inst
++);
6319 assert(mach
->pc
< (int) mach
->NumInstructions
);
6320 barrier_hit
= exec_instruction(mach
, mach
->Instructions
+ mach
->pc
, &mach
->pc
);
6322 /* for compute shaders if we hit a barrier return now for later rescheduling */
6323 if (barrier_hit
&& mach
->ShaderType
== PIPE_SHADER_COMPUTE
)
6327 for (i
= 0; i
< TGSI_EXEC_NUM_TEMPS
+ TGSI_EXEC_NUM_TEMP_EXTRAS
; i
++) {
6328 if (memcmp(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]))) {
6331 memcpy(&temps
[i
], &mach
->Temps
[i
], sizeof(temps
[i
]));
6332 debug_printf("TEMP[%2u] = ", i
);
6333 for (j
= 0; j
< 4; j
++) {
6337 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6338 temps
[i
].xyzw
[0].f
[j
], temps
[i
].xyzw
[0].u
[j
],
6339 temps
[i
].xyzw
[1].f
[j
], temps
[i
].xyzw
[1].u
[j
],
6340 temps
[i
].xyzw
[2].f
[j
], temps
[i
].xyzw
[2].u
[j
],
6341 temps
[i
].xyzw
[3].f
[j
], temps
[i
].xyzw
[3].u
[j
]);
6345 if (mach
->Outputs
) {
6346 for (i
= 0; i
< PIPE_MAX_ATTRIBS
; i
++) {
6347 if (memcmp(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]))) {
6350 memcpy(&outputs
[i
], &mach
->Outputs
[i
], sizeof(outputs
[i
]));
6351 debug_printf("OUT[%2u] = ", i
);
6352 for (j
= 0; j
< 4; j
++) {
6356 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
6357 outputs
[i
].xyzw
[0].f
[j
], outputs
[i
].xyzw
[0].u
[j
],
6358 outputs
[i
].xyzw
[1].f
[j
], outputs
[i
].xyzw
[1].u
[j
],
6359 outputs
[i
].xyzw
[2].f
[j
], outputs
[i
].xyzw
[2].u
[j
],
6360 outputs
[i
].xyzw
[3].f
[j
], outputs
[i
].xyzw
[3].u
[j
]);
6370 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
6371 if (mach
->ShaderType
== PIPE_SHADER_FRAGMENT
) {
6373 * Scale back depth component.
6375 for (i
= 0; i
< 4; i
++)
6376 mach
->Outputs
[0].xyzw
[2].f
[i
] *= ctx
->DrawBuffer
->_DepthMaxF
;
6380 /* Strictly speaking, these assertions aren't really needed but they
6381 * can potentially catch some bugs in the control flow code.
6383 assert(mach
->CondStackTop
== 0);
6384 assert(mach
->LoopStackTop
== 0);
6385 assert(mach
->ContStackTop
== 0);
6386 assert(mach
->SwitchStackTop
== 0);
6387 assert(mach
->BreakStackTop
== 0);
6388 assert(mach
->CallStackTop
== 0);
6390 return ~mach
->Temps
[TEMP_KILMASK_I
].xyzw
[TEMP_KILMASK_C
].u
[0];