[g3dvl] move stuff from flush into own functions
[mesa.git] / src / gallium / auxiliary / tgsi / tgsi_exec.h
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 #ifndef TGSI_EXEC_H
30 #define TGSI_EXEC_H
31
32 #include "pipe/p_compiler.h"
33 #include "pipe/p_state.h"
34
35 #if defined __cplusplus
36 extern "C" {
37 #endif
38
39
40 #define NUM_CHANNELS 4 /* R,G,B,A */
41 #define QUAD_SIZE 4 /* 4 pixel/quad */
42
43
44 /**
45 * Registers may be treated as float, signed int or unsigned int.
46 */
47 union tgsi_exec_channel
48 {
49 float f[QUAD_SIZE];
50 int i[QUAD_SIZE];
51 unsigned u[QUAD_SIZE];
52 };
53
54 /**
55 * A vector[RGBA] of channels[4 pixels]
56 */
57 struct tgsi_exec_vector
58 {
59 union tgsi_exec_channel xyzw[NUM_CHANNELS];
60 };
61
62 /**
63 * For fragment programs, information for computing fragment input
64 * values from plane equation of the triangle/line.
65 */
66 struct tgsi_interp_coef
67 {
68 float a0[NUM_CHANNELS]; /* in an xyzw layout */
69 float dadx[NUM_CHANNELS];
70 float dady[NUM_CHANNELS];
71 };
72
73 enum tgsi_sampler_control {
74 tgsi_sampler_lod_bias,
75 tgsi_sampler_lod_explicit
76 };
77
78 /**
79 * Information for sampling textures, which must be implemented
80 * by code outside the TGSI executor.
81 */
82 struct tgsi_sampler
83 {
84 /** Get samples for four fragments in a quad */
85 void (*get_samples)(struct tgsi_sampler *sampler,
86 const float s[QUAD_SIZE],
87 const float t[QUAD_SIZE],
88 const float p[QUAD_SIZE],
89 const float c0[QUAD_SIZE],
90 enum tgsi_sampler_control control,
91 float rgba[NUM_CHANNELS][QUAD_SIZE]);
92 };
93
94 #define TGSI_EXEC_NUM_TEMPS 128
95 #define TGSI_EXEC_NUM_IMMEDIATES 256
96 #define TGSI_EXEC_NUM_TEMP_ARRAYS 8
97
98 /*
99 * Locations of various utility registers (_I = Index, _C = Channel)
100 */
101 #define TGSI_EXEC_TEMP_00000000_I (TGSI_EXEC_NUM_TEMPS + 0)
102 #define TGSI_EXEC_TEMP_00000000_C 0
103
104 #define TGSI_EXEC_TEMP_7FFFFFFF_I (TGSI_EXEC_NUM_TEMPS + 0)
105 #define TGSI_EXEC_TEMP_7FFFFFFF_C 1
106
107 #define TGSI_EXEC_TEMP_80000000_I (TGSI_EXEC_NUM_TEMPS + 0)
108 #define TGSI_EXEC_TEMP_80000000_C 2
109
110 #define TGSI_EXEC_TEMP_FFFFFFFF_I (TGSI_EXEC_NUM_TEMPS + 0)
111 #define TGSI_EXEC_TEMP_FFFFFFFF_C 3
112
113 #define TGSI_EXEC_TEMP_ONE_I (TGSI_EXEC_NUM_TEMPS + 1)
114 #define TGSI_EXEC_TEMP_ONE_C 0
115
116 #define TGSI_EXEC_TEMP_TWO_I (TGSI_EXEC_NUM_TEMPS + 1)
117 #define TGSI_EXEC_TEMP_TWO_C 1
118
119 #define TGSI_EXEC_TEMP_128_I (TGSI_EXEC_NUM_TEMPS + 1)
120 #define TGSI_EXEC_TEMP_128_C 2
121
122 #define TGSI_EXEC_TEMP_MINUS_128_I (TGSI_EXEC_NUM_TEMPS + 1)
123 #define TGSI_EXEC_TEMP_MINUS_128_C 3
124
125 #define TGSI_EXEC_TEMP_KILMASK_I (TGSI_EXEC_NUM_TEMPS + 2)
126 #define TGSI_EXEC_TEMP_KILMASK_C 0
127
128 #define TGSI_EXEC_TEMP_OUTPUT_I (TGSI_EXEC_NUM_TEMPS + 2)
129 #define TGSI_EXEC_TEMP_OUTPUT_C 1
130
131 #define TGSI_EXEC_TEMP_PRIMITIVE_I (TGSI_EXEC_NUM_TEMPS + 2)
132 #define TGSI_EXEC_TEMP_PRIMITIVE_C 2
133
134 /* NVIDIA condition code (CC) vector
135 */
136 #define TGSI_EXEC_CC_GT 0x01
137 #define TGSI_EXEC_CC_EQ 0x02
138 #define TGSI_EXEC_CC_LT 0x04
139 #define TGSI_EXEC_CC_UN 0x08
140
141 #define TGSI_EXEC_CC_X_MASK 0x000000ff
142 #define TGSI_EXEC_CC_X_SHIFT 0
143 #define TGSI_EXEC_CC_Y_MASK 0x0000ff00
144 #define TGSI_EXEC_CC_Y_SHIFT 8
145 #define TGSI_EXEC_CC_Z_MASK 0x00ff0000
146 #define TGSI_EXEC_CC_Z_SHIFT 16
147 #define TGSI_EXEC_CC_W_MASK 0xff000000
148 #define TGSI_EXEC_CC_W_SHIFT 24
149
150 #define TGSI_EXEC_TEMP_CC_I (TGSI_EXEC_NUM_TEMPS + 2)
151 #define TGSI_EXEC_TEMP_CC_C 3
152
153 #define TGSI_EXEC_TEMP_THREE_I (TGSI_EXEC_NUM_TEMPS + 3)
154 #define TGSI_EXEC_TEMP_THREE_C 0
155
156 #define TGSI_EXEC_TEMP_HALF_I (TGSI_EXEC_NUM_TEMPS + 3)
157 #define TGSI_EXEC_TEMP_HALF_C 1
158
159 /* execution mask, each value is either 0 or ~0 */
160 #define TGSI_EXEC_MASK_I (TGSI_EXEC_NUM_TEMPS + 3)
161 #define TGSI_EXEC_MASK_C 2
162
163 /* 4 register buffer for various purposes */
164 #define TGSI_EXEC_TEMP_R0 (TGSI_EXEC_NUM_TEMPS + 4)
165 #define TGSI_EXEC_NUM_TEMP_R 4
166
167 #define TGSI_EXEC_TEMP_ADDR (TGSI_EXEC_NUM_TEMPS + 8)
168 #define TGSI_EXEC_NUM_ADDRS 1
169
170 /* predicate register */
171 #define TGSI_EXEC_TEMP_P0 (TGSI_EXEC_NUM_TEMPS + 9)
172 #define TGSI_EXEC_NUM_PREDS 1
173
174 #define TGSI_EXEC_NUM_TEMP_EXTRAS 10
175
176
177
178 #define TGSI_EXEC_MAX_NESTING 32
179 #define TGSI_EXEC_MAX_COND_NESTING TGSI_EXEC_MAX_NESTING
180 #define TGSI_EXEC_MAX_LOOP_NESTING TGSI_EXEC_MAX_NESTING
181 #define TGSI_EXEC_MAX_SWITCH_NESTING TGSI_EXEC_MAX_NESTING
182 #define TGSI_EXEC_MAX_CALL_NESTING TGSI_EXEC_MAX_NESTING
183
184 /* The maximum number of input attributes per vertex. For 2D
185 * input register files, this is the stride between two 1D
186 * arrays.
187 */
188 #define TGSI_EXEC_MAX_INPUT_ATTRIBS 17
189
190 /* The maximum number of constant vectors per constant buffer.
191 */
192 #define TGSI_EXEC_MAX_CONST_BUFFER 4096
193
194 /* The maximum number of vertices per primitive */
195 #define TGSI_MAX_PRIM_VERTICES 6
196
197 /* The maximum number of primitives to be generated */
198 #define TGSI_MAX_PRIMITIVES 64
199
200 /* The maximum total number of vertices */
201 #define TGSI_MAX_TOTAL_VERTICES (TGSI_MAX_PRIM_VERTICES * TGSI_MAX_PRIMITIVES * PIPE_MAX_ATTRIBS)
202
203 /** function call/activation record */
204 struct tgsi_call_record
205 {
206 uint CondStackTop;
207 uint LoopStackTop;
208 uint ContStackTop;
209 int SwitchStackTop;
210 int BreakStackTop;
211 uint ReturnAddr;
212 };
213
214
215 /* Switch-case block state. */
216 struct tgsi_switch_record {
217 uint mask; /**< execution mask */
218 union tgsi_exec_channel selector; /**< a value case statements are compared to */
219 uint defaultMask; /**< non-execute mask for default case */
220 };
221
222
223 enum tgsi_break_type {
224 TGSI_EXEC_BREAK_INSIDE_LOOP,
225 TGSI_EXEC_BREAK_INSIDE_SWITCH
226 };
227
228
229 #define TGSI_EXEC_MAX_BREAK_STACK (TGSI_EXEC_MAX_LOOP_NESTING + TGSI_EXEC_MAX_SWITCH_NESTING)
230
231
232 /**
233 * Run-time virtual machine state for executing TGSI shader.
234 */
235 struct tgsi_exec_machine
236 {
237 /* Total = program temporaries + internal temporaries
238 */
239 struct tgsi_exec_vector Temps[TGSI_EXEC_NUM_TEMPS +
240 TGSI_EXEC_NUM_TEMP_EXTRAS];
241 struct tgsi_exec_vector TempArray[TGSI_EXEC_NUM_TEMP_ARRAYS][TGSI_EXEC_NUM_TEMPS];
242
243 float Imms[TGSI_EXEC_NUM_IMMEDIATES][4];
244
245 float ImmArray[TGSI_EXEC_NUM_IMMEDIATES][4];
246
247 struct tgsi_exec_vector Inputs[TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS];
248 struct tgsi_exec_vector Outputs[TGSI_MAX_TOTAL_VERTICES];
249
250 struct tgsi_exec_vector *Addrs;
251 struct tgsi_exec_vector *Predicates;
252
253 struct tgsi_sampler **Samplers;
254
255 unsigned ImmLimit;
256
257 const void *Consts[PIPE_MAX_CONSTANT_BUFFERS];
258 unsigned ConstsSize[PIPE_MAX_CONSTANT_BUFFERS];
259
260 const struct tgsi_token *Tokens; /**< Declarations, instructions */
261 unsigned Processor; /**< TGSI_PROCESSOR_x */
262
263 /* GEOMETRY processor only. */
264 unsigned *Primitives;
265 unsigned NumOutputs;
266 unsigned MaxGeometryShaderOutputs;
267
268 /* FRAGMENT processor only. */
269 const struct tgsi_interp_coef *InterpCoefs;
270 struct tgsi_exec_vector QuadPos;
271 float Face; /**< +1 if front facing, -1 if back facing */
272
273 /* Conditional execution masks */
274 uint CondMask; /**< For IF/ELSE/ENDIF */
275 uint LoopMask; /**< For BGNLOOP/ENDLOOP */
276 uint ContMask; /**< For loop CONT statements */
277 uint FuncMask; /**< For function calls */
278 uint ExecMask; /**< = CondMask & LoopMask */
279
280 /* Current switch-case state. */
281 struct tgsi_switch_record Switch;
282
283 /* Current break type. */
284 enum tgsi_break_type BreakType;
285
286 /** Condition mask stack (for nested conditionals) */
287 uint CondStack[TGSI_EXEC_MAX_COND_NESTING];
288 int CondStackTop;
289
290 /** Loop mask stack (for nested loops) */
291 uint LoopStack[TGSI_EXEC_MAX_LOOP_NESTING];
292 int LoopStackTop;
293
294 /** Loop label stack */
295 uint LoopLabelStack[TGSI_EXEC_MAX_LOOP_NESTING];
296 int LoopLabelStackTop;
297
298 /** Loop continue mask stack (see comments in tgsi_exec.c) */
299 uint ContStack[TGSI_EXEC_MAX_LOOP_NESTING];
300 int ContStackTop;
301
302 /** Switch case stack */
303 struct tgsi_switch_record SwitchStack[TGSI_EXEC_MAX_SWITCH_NESTING];
304 int SwitchStackTop;
305
306 enum tgsi_break_type BreakStack[TGSI_EXEC_MAX_BREAK_STACK];
307 int BreakStackTop;
308
309 /** Function execution mask stack (for executing subroutine code) */
310 uint FuncStack[TGSI_EXEC_MAX_CALL_NESTING];
311 int FuncStackTop;
312
313 /** Function call stack for saving/restoring the program counter */
314 struct tgsi_call_record CallStack[TGSI_EXEC_MAX_CALL_NESTING];
315 int CallStackTop;
316
317 struct tgsi_full_instruction *Instructions;
318 uint NumInstructions;
319
320 struct tgsi_full_declaration *Declarations;
321 uint NumDeclarations;
322
323 };
324
325 struct tgsi_exec_machine *
326 tgsi_exec_machine_create( void );
327
328 void
329 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach);
330
331
332 void
333 tgsi_exec_machine_bind_shader(
334 struct tgsi_exec_machine *mach,
335 const struct tgsi_token *tokens,
336 uint numSamplers,
337 struct tgsi_sampler **samplers);
338
339 uint
340 tgsi_exec_machine_run(
341 struct tgsi_exec_machine *mach );
342
343
344 void
345 tgsi_exec_machine_free_data(struct tgsi_exec_machine *mach);
346
347
348 boolean
349 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst);
350
351
352 static INLINE void
353 tgsi_set_kill_mask(struct tgsi_exec_machine *mach, unsigned mask)
354 {
355 mach->Temps[TGSI_EXEC_TEMP_KILMASK_I].xyzw[TGSI_EXEC_TEMP_KILMASK_C].u[0] =
356 mask;
357 }
358
359
360 /** Set execution mask values prior to executing the shader */
361 static INLINE void
362 tgsi_set_exec_mask(struct tgsi_exec_machine *mach,
363 boolean ch0, boolean ch1, boolean ch2, boolean ch3)
364 {
365 int *mask = mach->Temps[TGSI_EXEC_MASK_I].xyzw[TGSI_EXEC_MASK_C].i;
366 mask[0] = ch0 ? ~0 : 0;
367 mask[1] = ch1 ? ~0 : 0;
368 mask[2] = ch2 ? ~0 : 0;
369 mask[3] = ch3 ? ~0 : 0;
370 }
371
372
373 extern void
374 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
375 unsigned num_bufs,
376 const void **bufs,
377 const unsigned *buf_sizes);
378
379
380 static INLINE int
381 tgsi_exec_get_shader_param(enum pipe_shader_cap param)
382 {
383 switch(param) {
384 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
385 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
386 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
387 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
388 return INT_MAX;
389 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
390 return TGSI_EXEC_MAX_NESTING;
391 case PIPE_SHADER_CAP_MAX_INPUTS:
392 return TGSI_EXEC_MAX_INPUT_ATTRIBS;
393 case PIPE_SHADER_CAP_MAX_CONSTS:
394 return TGSI_EXEC_MAX_CONST_BUFFER;
395 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
396 return PIPE_MAX_CONSTANT_BUFFERS;
397 case PIPE_SHADER_CAP_MAX_TEMPS:
398 return TGSI_EXEC_NUM_TEMPS;
399 case PIPE_SHADER_CAP_MAX_ADDRS:
400 return TGSI_EXEC_NUM_ADDRS;
401 case PIPE_SHADER_CAP_MAX_PREDS:
402 return TGSI_EXEC_NUM_PREDS;
403 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
404 return 1;
405 default:
406 return 0;
407 }
408 }
409
410 #if defined __cplusplus
411 } /* extern "C" */
412 #endif
413
414 #endif /* TGSI_EXEC_H */