src/gallium/auxiliary/util/u_cpu_detect.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2008 Dennis Smit
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10  * license, and/or sell copies of the Software, and to permit persons to whom
  11  * the Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20  * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  23  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  **************************************************************************/
  26
  27 /**
  28  * @file
  29  * CPU feature detection.
  30  *
  31  * @author Dennis Smit
  32  * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
  33  */
  34
  35 #include "pipe/p_config.h"
  36
  37 #include "u_debug.h"
  38 #include "u_cpu_detect.h"
  39
  40 #if defined(PIPE_ARCH_PPC)
  41 #if defined(PIPE_OS_DARWIN)
  42 #include <sys/sysctl.h>
  43 #else
  44 #include <signal.h>
  45 #include <setjmp.h>
  46 #endif
  47 #endif
  48
  49 #if defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
  50 #include <sys/param.h>
  51 #include <sys/sysctl.h>
  52 #include <machine/cpu.h>
  53 #endif
  54
  55 #if defined(PIPE_OS_FREEBSD)
  56 #include <sys/types.h>
  57 #include <sys/sysctl.h>
  58 #endif
  59
  60 #if defined(PIPE_OS_LINUX)
  61 #include <signal.h>
  62 #endif
  63
  64 #ifdef PIPE_OS_UNIX
  65 #include <unistd.h>
  66 #endif
  67
  68 #if defined(PIPE_OS_WINDOWS)
  69 #include <windows.h>
  70 #if defined(MSVC)
  71 #include <intrin.h>
  72 #endif
  73 #endif
  74
  75
  76 struct util_cpu_caps util_cpu_caps;
  77
  78 static int has_cpuid(void);
  79
  80 #if defined(PIPE_ARCH_X86)
  81
  82 /* The sigill handlers */
  83 #if defined(PIPE_OS_LINUX) /*&& defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)*/
  84 static void
  85 sigill_handler_sse(int signal, struct sigcontext sc)
  86 {
  87    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
  88     * instructions are 3 bytes long.  We must increment the instruction
  89     * pointer manually to avoid repeated execution of the offending
  90     * instruction.
  91     *
  92     * If the SIGILL is caused by a divide-by-zero when unmasked
  93     * exceptions aren't supported, the SIMD FPU status and control
  94     * word will be restored at the end of the test, so we don't need
  95     * to worry about doing it here.  Besides, we may not be able to...
  96     */
  97    sc.eip += 3;
  98
  99    util_cpu_caps.has_sse=0;
 100 }
 101
 102 static void
 103 sigfpe_handler_sse(int signal, struct sigcontext sc)
 104 {
 105    if (sc.fpstate->magic != 0xffff) {
 106       /* Our signal context has the extended FPU state, so reset the
 107        * divide-by-zero exception mask and clear the divide-by-zero
 108        * exception bit.
 109        */
 110       sc.fpstate->mxcsr |= 0x00000200;
 111       sc.fpstate->mxcsr &= 0xfffffffb;
 112    } else {
 113       /* If we ever get here, we're completely hosed.
 114       */
 115    }
 116 }
 117 #endif /* PIPE_OS_LINUX && _POSIX_SOURCE && X86_FXSR_MAGIC */
 118
 119 #if defined(PIPE_OS_WINDOWS)
 120 static LONG CALLBACK
 121 win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 122 {
 123    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 124       ep->ContextRecord->Eip +=3;
 125       util_cpu_caps.has_sse=0;
 126       return EXCEPTION_CONTINUE_EXECUTION;
 127    }
 128    return EXCEPTION_CONTINUE_SEARCH;
 129 }
 130 #endif /* PIPE_OS_WINDOWS */
 131
 132 #endif /* PIPE_ARCH_X86 */
 133
 134
 135 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_DARWIN)
 136 static jmp_buf  __lv_powerpc_jmpbuf;
 137 static volatile sig_atomic_t __lv_powerpc_canjump = 0;
 138
 139 static void
 140 sigill_handler(int sig)
 141 {
 142    if (!__lv_powerpc_canjump) {
 143       signal (sig, SIG_DFL);
 144       raise (sig);
 145    }
 146
 147    __lv_powerpc_canjump = 0;
 148    longjmp(__lv_powerpc_jmpbuf, 1);
 149 }
 150 #endif
 151
 152 #if defined(PIPE_ARCH_PPC)
 153 static void
 154 check_os_altivec_support(void)
 155 {
 156 #if defined(PIPE_OS_DARWIN)
 157    int sels[2] = {CTL_HW, HW_VECTORUNIT};
 158    int has_vu = 0;
 159    int len = sizeof (has_vu);
 160    int err;
 161
 162    err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 163
 164    if (err == 0) {
 165       if (has_vu != 0) {
 166          util_cpu_caps.has_altivec = 1;
 167       }
 168    }
 169 #else /* !PIPE_OS_DARWIN */
 170    /* no Darwin, do it the brute-force way */
 171    /* this is borrowed from the libmpeg2 library */
 172    signal(SIGILL, sigill_handler);
 173    if (setjmp(__lv_powerpc_jmpbuf)) {
 174       signal(SIGILL, SIG_DFL);
 175    } else {
 176       __lv_powerpc_canjump = 1;
 177
 178       __asm __volatile
 179          ("mtspr 256, %0\n\t"
 180           "vand %%v0, %%v0, %%v0"
 181           :
 182           : "r" (-1));
 183
 184       signal(SIGILL, SIG_DFL);
 185       util_cpu_caps.has_altivec = 1;
 186    }
 187 #endif /* PIPE_OS_DARWIN */
 188 }
 189 #endif /* PIPE_ARCH_PPC */
 190
 191 /* If we're running on a processor that can do SSE, let's see if we
 192  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 193  * haven't been configured for a Pentium III but are running on one,
 194  * and RedHat patched 2.2 kernels that have broken exception handling
 195  * support for user space apps that do SSE.
 196  */
 197 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
 198 static void
 199 check_os_katmai_support(void)
 200 {
 201 #if defined(PIPE_ARCH_X86)
 202 #if defined(PIPE_OS_FREEBSD)
 203    int has_sse=0, ret;
 204    int len = sizeof (has_sse);
 205
 206    ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
 207    if (ret || !has_sse)
 208       util_cpu_caps.has_sse=0;
 209
 210 #elif defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
 211    int has_sse, has_sse2, ret, mib[2];
 212    int varlen;
 213
 214    mib[0] = CTL_MACHDEP;
 215    mib[1] = CPU_SSE;
 216    varlen = sizeof (has_sse);
 217
 218    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 219    if (ret < 0 || !has_sse) {
 220       util_cpu_caps.has_sse = 0;
 221    } else {
 222       util_cpu_caps.has_sse = 1;
 223    }
 224
 225    mib[1] = CPU_SSE2;
 226    varlen = sizeof (has_sse2);
 227    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 228    if (ret < 0 || !has_sse2) {
 229       util_cpu_caps.has_sse2 = 0;
 230    } else {
 231       util_cpu_caps.has_sse2 = 1;
 232    }
 233    util_cpu_caps.has_sse = 0; /* FIXME ?!?!? */
 234
 235 #elif defined(PIPE_OS_WINDOWS)
 236    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 237    if (util_cpu_caps.has_sse) {
 238       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 239 #if defined(PIPE_CC_GCC)
 240       __asm __volatile ("xorps %xmm0, %xmm0");
 241 #elif defined(PIPE_CC_MSVC)
 242       __asm {
 243           xorps xmm0, xmm0        /* executing SSE instruction */
 244       }
 245 #else
 246 #error Unsupported compiler
 247 #endif
 248       SetUnhandledExceptionFilter(exc_fil);
 249    }
 250 #elif defined(PIPE_OS_LINUX)
 251    struct sigaction saved_sigill;
 252    struct sigaction saved_sigfpe;
 253
 254    /* Save the original signal handlers.
 255    */
 256    sigaction(SIGILL, NULL, &saved_sigill);
 257    sigaction(SIGFPE, NULL, &saved_sigfpe);
 258
 259    signal(SIGILL, (void (*)(int))sigill_handler_sse);
 260    signal(SIGFPE, (void (*)(int))sigfpe_handler_sse);
 261
 262    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 263     * supports the extended FPU save and restore required for SSE.  If
 264     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 265     * doesn't support Streaming SIMD Exceptions, even if the processor
 266     * does.
 267     */
 268    if (util_cpu_caps.has_sse) {
 269       __asm __volatile ("xorps %xmm1, %xmm0");
 270    }
 271
 272    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 273     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 274     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 275     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 276     * as expected, we're okay but we need to clean up after it.
 277     *
 278     * Are we being too stringent in our requirement that the OS support
 279     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 280     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 281     * doesn't even support them.  We at least know the user-space SSE
 282     * support is good in kernels that do support unmasked exceptions,
 283     * and therefore to be safe I'm going to leave this test in here.
 284     */
 285    if (util_cpu_caps.has_sse) {
 286       /* test_os_katmai_exception_support(); */
 287    }
 288
 289    /* Restore the original signal handlers.
 290    */
 291    sigaction(SIGILL, &saved_sigill, NULL);
 292    sigaction(SIGFPE, &saved_sigfpe, NULL);
 293
 294 #else
 295    /* We can't use POSIX signal handling to test the availability of
 296     * SSE, so we disable it by default.
 297     */
 298    util_cpu_caps.has_sse = 0;
 299 #endif /* __linux__ */
 300 #endif
 301
 302 #if defined(PIPE_ARCH_X86_64)
 303    util_cpu_caps.has_sse = 1;
 304 #endif
 305 }
 306
 307
 308 static int has_cpuid(void)
 309 {
 310 #if defined(PIPE_ARCH_X86)
 311 #if defined(PIPE_OS_GCC)
 312    int a, c;
 313
 314    __asm __volatile
 315       ("pushf\n"
 316        "popl %0\n"
 317        "movl %0, %1\n"
 318        "xorl $0x200000, %0\n"
 319        "push %0\n"
 320        "popf\n"
 321        "pushf\n"
 322        "popl %0\n"
 323        : "=a" (a), "=c" (c)
 324        :
 325        : "cc");
 326
 327    return a != c;
 328 #else
 329    /* FIXME */
 330    return 1;
 331 #endif
 332 #elif defined(PIPE_ARCH_X86_64)
 333    return 1;
 334 #else
 335    return 0;
 336 #endif
 337 }
 338
 339
 340 /**
 341  * @sa cpuid.h included in gcc-4.3 onwards.
 342  * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
 343  */
 344 static INLINE void
 345 cpuid(uint32_t ax, uint32_t *p)
 346 {
 347 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
 348    __asm __volatile (
 349      "xchgl %%ebx, %1\n\t"
 350      "cpuid\n\t"
 351      "xchgl %%ebx, %1"
 352      : "=a" (p[0]),
 353        "=S" (p[1]),
 354        "=c" (p[2]),
 355        "=d" (p[3])
 356      : "0" (ax)
 357    );
 358 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
 359    __asm __volatile (
 360      "cpuid\n\t"
 361      : "=a" (p[0]),
 362        "=b" (p[1]),
 363        "=c" (p[2]),
 364        "=d" (p[3])
 365      : "0" (ax)
 366    );
 367 #elif defined(PIPE_CC_MSVC)
 368    __cpuid(p, ax);
 369 #else
 370    p[0] = 0;
 371    p[1] = 0;
 372    p[2] = 0;
 373    p[3] = 0;
 374 #endif
 375 }
 376 #endif /* X86 or X86_64 */
 377
 378 void
 379 util_cpu_detect(void)
 380 {
 381    static boolean util_cpu_detect_initialized = FALSE;
 382
 383    if(util_cpu_detect_initialized)
 384       return;
 385
 386    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 387
 388    /* Check for arch type */
 389 #if defined(PIPE_ARCH_MIPS)
 390    util_cpu_caps.arch = UTIL_CPU_ARCH_MIPS;
 391 #elif defined(PIPE_ARCH_ALPHA)
 392    util_cpu_caps.arch = UTIL_CPU_ARCH_ALPHA;
 393 #elif defined(PIPE_ARCH_SPARC)
 394    util_cpu_caps.arch = UTIL_CPU_ARCH_SPARC;
 395 #elif defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 396    util_cpu_caps.arch = UTIL_CPU_ARCH_X86;
 397    util_cpu_caps.little_endian = 1;
 398 #elif defined(PIPE_ARCH_PPC)
 399    util_cpu_caps.arch = UTIL_CPU_ARCH_POWERPC;
 400    util_cpu_caps.little_endian = 0;
 401 #else
 402    util_cpu_caps.arch = UTIL_CPU_ARCH_UNKNOWN;
 403 #endif
 404
 405    /* Count the number of CPUs in system */
 406 #if defined(PIPE_OS_WINDOWS)
 407    {
 408       SYSTEM_INFO system_info;
 409       GetSystemInfo(&system_info);
 410       util_cpu_caps.nr_cpus = system_info.dwNumberOfProcessors;
 411    }
 412 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
 413    util_cpu_caps.nr_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 414    if (util_cpu_caps.nr_cpus == -1)
 415       util_cpu_caps.nr_cpus = 1;
 416 #elif defined(PIPE_OS_BSD)
 417    {
 418       int mib[2], ncpu;
 419       int len;
 420
 421       mib[0] = CTL_HW;
 422       mib[1] = HW_NCPU;
 423
 424       len = sizeof (ncpu);
 425       sysctl(mib, 2, &ncpu, &len, NULL, 0);
 426       util_cpu_caps.nr_cpus = ncpu;
 427    }
 428 #else
 429    util_cpu_caps.nr_cpus = 1;
 430 #endif
 431
 432 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 433    if (has_cpuid()) {
 434       uint32_t regs[4];
 435       uint32_t regs2[4];
 436
 437       util_cpu_caps.cacheline = 32;
 438
 439       /* Get max cpuid level */
 440       cpuid(0x00000000, regs);
 441
 442       if (regs[0] >= 0x00000001) {
 443          unsigned int cacheline;
 444
 445          cpuid (0x00000001, regs2);
 446
 447          util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf;
 448          if (util_cpu_caps.x86_cpu_type == 0xf)
 449              util_cpu_caps.x86_cpu_type = 8 + ((regs2[0] >> 20) & 255); /* use extended family (P4, IA64) */
 450
 451          /* general feature flags */
 452          util_cpu_caps.has_tsc    = (regs2[3] & (1 << 8  )) >>  8; /* 0x0000010 */
 453          util_cpu_caps.has_mmx    = (regs2[3] & (1 << 23 )) >> 23; /* 0x0800000 */
 454          util_cpu_caps.has_sse    = (regs2[3] & (1 << 25 )) >> 25; /* 0x2000000 */
 455          util_cpu_caps.has_sse2   = (regs2[3] & (1 << 26 )) >> 26; /* 0x4000000 */
 456          util_cpu_caps.has_sse3   = (regs2[2] & (1));          /* 0x0000001 */
 457          util_cpu_caps.has_ssse3  = (regs2[2] & (1 << 9 )) >> 9;   /* 0x0000020 */
 458          util_cpu_caps.has_sse4_1 = (regs2[2] & (1 << 19)) >> 19;
 459          util_cpu_caps.has_mmx2   = util_cpu_caps.has_sse; /* SSE cpus supports mmxext too */
 460
 461          cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
 462          if (cacheline > 0)
 463             util_cpu_caps.cacheline = cacheline;
 464       }
 465
 466       cpuid(0x80000000, regs);
 467
 468       if (regs[0] >= 0x80000001) {
 469
 470          cpuid(0x80000001, regs2);
 471
 472          util_cpu_caps.has_mmx  |= (regs2[3] & (1 << 23 )) >> 23; /* 0x0800000 */
 473          util_cpu_caps.has_mmx2 |= (regs2[3] & (1 << 22 )) >> 22; /* 0x400000 */
 474          util_cpu_caps.has_3dnow    = (regs2[3] & (1 << 31 )) >> 31; /* 0x80000000 */
 475          util_cpu_caps.has_3dnow_ext = (regs2[3] & (1 << 30 )) >> 30;
 476       }
 477
 478       if (regs[0] >= 0x80000006) {
 479          cpuid(0x80000006, regs2);
 480          util_cpu_caps.cacheline = regs2[2] & 0xFF;
 481       }
 482
 483       if (util_cpu_caps.has_sse)
 484          check_os_katmai_support();
 485
 486       if (!util_cpu_caps.has_sse) {
 487          util_cpu_caps.has_sse2 = 0;
 488          util_cpu_caps.has_sse3 = 0;
 489          util_cpu_caps.has_ssse3 = 0;
 490          util_cpu_caps.has_sse4_1 = 0;
 491       }
 492    }
 493 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 494
 495 #if defined(PIPE_ARCH_PPC)
 496    check_os_altivec_support();
 497 #endif /* PIPE_ARCH_PPC */
 498
 499 #ifdef DEBUG
 500    debug_printf("util_cpu_caps.arch = %i\n", util_cpu_caps.arch);
 501    debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 502
 503    debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps.x86_cpu_type);
 504    debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 505
 506    debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
 507    debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
 508    debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
 509    debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps.has_sse);
 510    debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps.has_sse2);
 511    debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps.has_sse3);
 512    debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps.has_ssse3);
 513    debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps.has_sse4_1);
 514    debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps.has_3dnow);
 515    debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps.has_3dnow_ext);
 516    debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps.has_altivec);
 517 #endif
 518
 519    util_cpu_detect_initialized = TRUE;
 520 }