1 /**************************************************************************
3 * Copyright 2008 Dennis Smit
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 **************************************************************************/
29 * CPU feature detection.
32 * @author Based on the work of Eric Anholt <anholt@FreeBSD.org>
35 #include "pipe/p_config.h"
38 #include "u_cpu_detect.h"
39 #include "c11/threads.h"
41 #if defined(PIPE_ARCH_PPC)
42 #if defined(PIPE_OS_APPLE)
43 #include <sys/sysctl.h>
50 #if defined(PIPE_OS_NETBSD) || defined(PIPE_OS_OPENBSD)
51 #include <sys/param.h>
52 #include <sys/sysctl.h>
53 #include <machine/cpu.h>
56 #if defined(PIPE_OS_FREEBSD) || defined(PIPE_OS_DRAGONFLY)
57 #include <sys/types.h>
58 #include <sys/sysctl.h>
61 #if defined(PIPE_OS_LINUX)
71 #if defined(HAS_ANDROID_CPUFEATURES)
72 #include <cpu-features.h>
75 #if defined(PIPE_OS_WINDOWS)
77 #if defined(PIPE_CC_MSVC)
84 DEBUG_GET_ONCE_BOOL_OPTION(dump_cpu
, "GALLIUM_DUMP_CPU", FALSE
)
88 struct util_cpu_caps util_cpu_caps
;
90 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
91 static int has_cpuid(void);
95 #if defined(PIPE_ARCH_PPC) && !defined(PIPE_OS_APPLE)
96 static jmp_buf __lv_powerpc_jmpbuf
;
97 static volatile sig_atomic_t __lv_powerpc_canjump
= 0;
100 sigill_handler(int sig
)
102 if (!__lv_powerpc_canjump
) {
103 signal (sig
, SIG_DFL
);
107 __lv_powerpc_canjump
= 0;
108 longjmp(__lv_powerpc_jmpbuf
, 1);
112 #if defined(PIPE_ARCH_PPC)
114 check_os_altivec_support(void)
116 #if defined(PIPE_OS_APPLE)
117 int sels
[2] = {CTL_HW
, HW_VECTORUNIT
};
119 int len
= sizeof (has_vu
);
122 err
= sysctl(sels
, 2, &has_vu
, &len
, NULL
, 0);
126 util_cpu_caps
.has_altivec
= 1;
129 #else /* !PIPE_OS_APPLE */
130 /* not on Apple/Darwin, do it the brute-force way */
131 /* this is borrowed from the libmpeg2 library */
132 signal(SIGILL
, sigill_handler
);
133 if (setjmp(__lv_powerpc_jmpbuf
)) {
134 signal(SIGILL
, SIG_DFL
);
136 boolean enable_altivec
= TRUE
; /* Default: enable if available, and if not overridden */
137 boolean enable_vsx
= TRUE
;
139 /* Disabling Altivec code generation is not the same as disabling VSX code generation,
140 * which can be done simply by passing -mattr=-vsx to the LLVM compiler; cf.
141 * lp_build_create_jit_compiler_for_module().
142 * If you want to disable Altivec code generation, the best place to do it is here.
144 char *env_control
= getenv("GALLIVM_ALTIVEC"); /* 1=enable (default); 0=disable */
145 if (env_control
&& env_control
[0] == '0') {
146 enable_altivec
= FALSE
;
149 /* VSX instructions can be explicitly enabled/disabled via GALLIVM_VSX=1 or 0 */
150 char *env_vsx
= getenv("GALLIVM_VSX");
151 if (env_vsx
&& env_vsx
[0] == '0') {
154 if (enable_altivec
) {
155 __lv_powerpc_canjump
= 1;
159 "vand %%v0, %%v0, %%v0"
163 util_cpu_caps
.has_altivec
= 1;
166 __asm
__volatile("xxland %vs0, %vs0, %vs0");
167 util_cpu_caps
.has_vsx
= 1;
169 signal(SIGILL
, SIG_DFL
);
171 util_cpu_caps
.has_altivec
= 0;
174 #endif /* !PIPE_OS_APPLE */
176 #endif /* PIPE_ARCH_PPC */
179 #if defined(PIPE_ARCH_X86) || defined (PIPE_ARCH_X86_64)
180 static int has_cpuid(void)
182 #if defined(PIPE_ARCH_X86)
183 #if defined(PIPE_OS_GCC)
190 "xorl $0x200000, %0\n"
204 #elif defined(PIPE_ARCH_X86_64)
213 * @sa cpuid.h included in gcc-4.3 onwards.
214 * @sa http://msdn.microsoft.com/en-us/library/hskdteyh.aspx
217 cpuid(uint32_t ax
, uint32_t *p
)
219 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
221 "xchgl %%ebx, %1\n\t"
230 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
239 #elif defined(PIPE_CC_MSVC)
250 * @sa cpuid.h included in gcc-4.4 onwards.
251 * @sa http://msdn.microsoft.com/en-us/library/hskdteyh%28v=vs.90%29.aspx
254 cpuid_count(uint32_t ax
, uint32_t cx
, uint32_t *p
)
256 #if defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86)
258 "xchgl %%ebx, %1\n\t"
267 #elif defined(PIPE_CC_GCC) && defined(PIPE_ARCH_X86_64)
276 #elif defined(PIPE_CC_MSVC)
277 __cpuidex(p
, ax
, cx
);
287 static inline uint64_t xgetbv(void)
289 #if defined(PIPE_CC_GCC)
293 ".byte 0x0f, 0x01, 0xd0" // xgetbv isn't supported on gcc < 4.4
299 return ((uint64_t)edx
<< 32) | eax
;
300 #elif defined(PIPE_CC_MSVC) && defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
301 return _xgetbv(_XCR_XFEATURE_ENABLED_MASK
);
308 #if defined(PIPE_ARCH_X86)
309 PIPE_ALIGN_STACK
static inline boolean
sse2_has_daz(void)
314 uint32_t pad2
[128-8];
315 } PIPE_ALIGN_VAR(16) fxarea
;
317 fxarea
.mxcsr_mask
= 0;
318 #if defined(PIPE_CC_GCC)
319 __asm
__volatile ("fxsave %0" : "+m" (fxarea
));
320 #elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL)
323 fxarea
.mxcsr_mask
= 0;
325 return !!(fxarea
.mxcsr_mask
& (1 << 6));
329 #endif /* X86 or X86_64 */
331 #if defined(PIPE_ARCH_ARM)
333 check_os_arm_support(void)
336 * On Android, the cpufeatures library is preferred way of checking
337 * CPU capabilities. However, it is not available for standalone Mesa
338 * builds, i.e. when Android build system (Android.mk-based) is not
339 * used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
340 * have a separate macro that only gets enabled from respective Android.mk.
342 #if defined(HAS_ANDROID_CPUFEATURES)
343 AndroidCpuFamily cpu_family
= android_getCpuFamily();
344 uint64_t cpu_features
= android_getCpuFeatures();
346 if (cpu_family
== ANDROID_CPU_FAMILY_ARM
) {
347 if (cpu_features
& ANDROID_CPU_ARM_FEATURE_NEON
)
348 util_cpu_caps
.has_neon
= 1;
350 #elif defined(PIPE_OS_LINUX)
354 fd
= open("/proc/self/auxv", O_RDONLY
| O_CLOEXEC
);
356 while (read(fd
, &aux
, sizeof(Elf32_auxv_t
)) == sizeof(Elf32_auxv_t
)) {
357 if (aux
.a_type
== AT_HWCAP
) {
358 uint32_t hwcap
= aux
.a_un
.a_val
;
360 util_cpu_caps
.has_neon
= (hwcap
>> 12) & 1;
366 #endif /* PIPE_OS_LINUX */
368 #endif /* PIPE_ARCH_ARM */
371 util_cpu_detect_once(void)
373 memset(&util_cpu_caps
, 0, sizeof util_cpu_caps
);
375 /* Count the number of CPUs in system */
376 #if defined(PIPE_OS_WINDOWS)
378 SYSTEM_INFO system_info
;
379 GetSystemInfo(&system_info
);
380 util_cpu_caps
.nr_cpus
= system_info
.dwNumberOfProcessors
;
382 #elif defined(PIPE_OS_UNIX) && defined(_SC_NPROCESSORS_ONLN)
383 util_cpu_caps
.nr_cpus
= sysconf(_SC_NPROCESSORS_ONLN
);
384 if (util_cpu_caps
.nr_cpus
== ~0)
385 util_cpu_caps
.nr_cpus
= 1;
386 #elif defined(PIPE_OS_BSD)
395 sysctl(mib
, 2, &ncpu
, &len
, NULL
, 0);
396 util_cpu_caps
.nr_cpus
= ncpu
;
399 util_cpu_caps
.nr_cpus
= 1;
402 /* Make the fallback cacheline size nonzero so that it can be
403 * safely passed to align().
405 util_cpu_caps
.cacheline
= sizeof(void *);
407 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
412 util_cpu_caps
.cacheline
= 32;
414 /* Get max cpuid level */
415 cpuid(0x00000000, regs
);
417 if (regs
[0] >= 0x00000001) {
418 unsigned int cacheline
;
420 cpuid (0x00000001, regs2
);
422 util_cpu_caps
.x86_cpu_type
= (regs2
[0] >> 8) & 0xf;
423 /* Add "extended family". */
424 if (util_cpu_caps
.x86_cpu_type
== 0xf)
425 util_cpu_caps
.x86_cpu_type
+= ((regs2
[0] >> 20) & 0xff);
427 /* general feature flags */
428 util_cpu_caps
.has_tsc
= (regs2
[3] >> 4) & 1; /* 0x0000010 */
429 util_cpu_caps
.has_mmx
= (regs2
[3] >> 23) & 1; /* 0x0800000 */
430 util_cpu_caps
.has_sse
= (regs2
[3] >> 25) & 1; /* 0x2000000 */
431 util_cpu_caps
.has_sse2
= (regs2
[3] >> 26) & 1; /* 0x4000000 */
432 util_cpu_caps
.has_sse3
= (regs2
[2] >> 0) & 1; /* 0x0000001 */
433 util_cpu_caps
.has_ssse3
= (regs2
[2] >> 9) & 1; /* 0x0000020 */
434 util_cpu_caps
.has_sse4_1
= (regs2
[2] >> 19) & 1;
435 util_cpu_caps
.has_sse4_2
= (regs2
[2] >> 20) & 1;
436 util_cpu_caps
.has_popcnt
= (regs2
[2] >> 23) & 1;
437 util_cpu_caps
.has_avx
= ((regs2
[2] >> 28) & 1) && // AVX
438 ((regs2
[2] >> 27) & 1) && // OSXSAVE
439 ((xgetbv() & 6) == 6); // XMM & YMM
440 util_cpu_caps
.has_f16c
= ((regs2
[2] >> 29) & 1) && util_cpu_caps
.has_avx
;
441 util_cpu_caps
.has_fma
= ((regs2
[2] >> 12) & 1) && util_cpu_caps
.has_avx
;
442 util_cpu_caps
.has_mmx2
= util_cpu_caps
.has_sse
; /* SSE cpus supports mmxext too */
443 #if defined(PIPE_ARCH_X86_64)
444 util_cpu_caps
.has_daz
= 1;
446 util_cpu_caps
.has_daz
= util_cpu_caps
.has_sse3
||
447 (util_cpu_caps
.has_sse2
&& sse2_has_daz());
450 cacheline
= ((regs2
[1] >> 8) & 0xFF) * 8;
452 util_cpu_caps
.cacheline
= cacheline
;
454 if (util_cpu_caps
.has_avx
&& regs
[0] >= 0x00000007) {
456 cpuid_count(0x00000007, 0x00000000, regs7
);
457 util_cpu_caps
.has_avx2
= (regs7
[1] >> 5) & 1;
461 if (((regs2
[2] >> 27) & 1) && // OSXSAVE
462 (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS
463 ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS
465 cpuid_count(0x00000007, 0x00000000, regs3
);
466 util_cpu_caps
.has_avx512f
= (regs3
[1] >> 16) & 1;
467 util_cpu_caps
.has_avx512dq
= (regs3
[1] >> 17) & 1;
468 util_cpu_caps
.has_avx512ifma
= (regs3
[1] >> 21) & 1;
469 util_cpu_caps
.has_avx512pf
= (regs3
[1] >> 26) & 1;
470 util_cpu_caps
.has_avx512er
= (regs3
[1] >> 27) & 1;
471 util_cpu_caps
.has_avx512cd
= (regs3
[1] >> 28) & 1;
472 util_cpu_caps
.has_avx512bw
= (regs3
[1] >> 30) & 1;
473 util_cpu_caps
.has_avx512vl
= (regs3
[1] >> 31) & 1;
474 util_cpu_caps
.has_avx512vbmi
= (regs3
[2] >> 1) & 1;
477 if (regs
[1] == 0x756e6547 && regs
[2] == 0x6c65746e && regs
[3] == 0x49656e69) {
479 util_cpu_caps
.has_intel
= 1;
482 cpuid(0x80000000, regs
);
484 if (regs
[0] >= 0x80000001) {
486 cpuid(0x80000001, regs2
);
488 util_cpu_caps
.has_mmx
|= (regs2
[3] >> 23) & 1;
489 util_cpu_caps
.has_mmx2
|= (regs2
[3] >> 22) & 1;
490 util_cpu_caps
.has_3dnow
= (regs2
[3] >> 31) & 1;
491 util_cpu_caps
.has_3dnow_ext
= (regs2
[3] >> 30) & 1;
493 util_cpu_caps
.has_xop
= util_cpu_caps
.has_avx
&&
494 ((regs2
[2] >> 11) & 1);
497 if (regs
[0] >= 0x80000006) {
498 /* should we really do this if the clflush size above worked? */
499 unsigned int cacheline
;
500 cpuid(0x80000006, regs2
);
501 cacheline
= regs2
[2] & 0xFF;
503 util_cpu_caps
.cacheline
= cacheline
;
506 if (!util_cpu_caps
.has_sse
) {
507 util_cpu_caps
.has_sse2
= 0;
508 util_cpu_caps
.has_sse3
= 0;
509 util_cpu_caps
.has_ssse3
= 0;
510 util_cpu_caps
.has_sse4_1
= 0;
513 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
515 #if defined(PIPE_ARCH_ARM)
516 check_os_arm_support();
519 #if defined(PIPE_ARCH_PPC)
520 check_os_altivec_support();
521 #endif /* PIPE_ARCH_PPC */
524 if (debug_get_option_dump_cpu()) {
525 debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps
.nr_cpus
);
527 debug_printf("util_cpu_caps.x86_cpu_type = %u\n", util_cpu_caps
.x86_cpu_type
);
528 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps
.cacheline
);
530 debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps
.has_tsc
);
531 debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps
.has_mmx
);
532 debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps
.has_mmx2
);
533 debug_printf("util_cpu_caps.has_sse = %u\n", util_cpu_caps
.has_sse
);
534 debug_printf("util_cpu_caps.has_sse2 = %u\n", util_cpu_caps
.has_sse2
);
535 debug_printf("util_cpu_caps.has_sse3 = %u\n", util_cpu_caps
.has_sse3
);
536 debug_printf("util_cpu_caps.has_ssse3 = %u\n", util_cpu_caps
.has_ssse3
);
537 debug_printf("util_cpu_caps.has_sse4_1 = %u\n", util_cpu_caps
.has_sse4_1
);
538 debug_printf("util_cpu_caps.has_sse4_2 = %u\n", util_cpu_caps
.has_sse4_2
);
539 debug_printf("util_cpu_caps.has_avx = %u\n", util_cpu_caps
.has_avx
);
540 debug_printf("util_cpu_caps.has_avx2 = %u\n", util_cpu_caps
.has_avx2
);
541 debug_printf("util_cpu_caps.has_f16c = %u\n", util_cpu_caps
.has_f16c
);
542 debug_printf("util_cpu_caps.has_popcnt = %u\n", util_cpu_caps
.has_popcnt
);
543 debug_printf("util_cpu_caps.has_3dnow = %u\n", util_cpu_caps
.has_3dnow
);
544 debug_printf("util_cpu_caps.has_3dnow_ext = %u\n", util_cpu_caps
.has_3dnow_ext
);
545 debug_printf("util_cpu_caps.has_xop = %u\n", util_cpu_caps
.has_xop
);
546 debug_printf("util_cpu_caps.has_altivec = %u\n", util_cpu_caps
.has_altivec
);
547 debug_printf("util_cpu_caps.has_vsx = %u\n", util_cpu_caps
.has_vsx
);
548 debug_printf("util_cpu_caps.has_neon = %u\n", util_cpu_caps
.has_neon
);
549 debug_printf("util_cpu_caps.has_daz = %u\n", util_cpu_caps
.has_daz
);
550 debug_printf("util_cpu_caps.has_avx512f = %u\n", util_cpu_caps
.has_avx512f
);
551 debug_printf("util_cpu_caps.has_avx512dq = %u\n", util_cpu_caps
.has_avx512dq
);
552 debug_printf("util_cpu_caps.has_avx512ifma = %u\n", util_cpu_caps
.has_avx512ifma
);
553 debug_printf("util_cpu_caps.has_avx512pf = %u\n", util_cpu_caps
.has_avx512pf
);
554 debug_printf("util_cpu_caps.has_avx512er = %u\n", util_cpu_caps
.has_avx512er
);
555 debug_printf("util_cpu_caps.has_avx512cd = %u\n", util_cpu_caps
.has_avx512cd
);
556 debug_printf("util_cpu_caps.has_avx512bw = %u\n", util_cpu_caps
.has_avx512bw
);
557 debug_printf("util_cpu_caps.has_avx512vl = %u\n", util_cpu_caps
.has_avx512vl
);
558 debug_printf("util_cpu_caps.has_avx512vbmi = %u\n", util_cpu_caps
.has_avx512vbmi
);
563 static once_flag cpu_once_flag
= ONCE_FLAG_INIT
;
566 util_cpu_detect(void)
568 call_once(&cpu_once_flag
, util_cpu_detect_once
);