061c9af5247f7e426820aa7f62c8db5aa857a550
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_blend.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_blend.h"
28
29 #include "etnaviv_context.h"
30 #include "etnaviv_screen.h"
31 #include "etnaviv_translate.h"
32 #include "hw/common.xml.h"
33 #include "pipe/p_defines.h"
34 #include "util/u_memory.h"
35
36 void *
37 etna_blend_state_create(struct pipe_context *pctx,
38 const struct pipe_blend_state *so)
39 {
40 struct etna_context *ctx = etna_context(pctx);
41 const struct pipe_rt_blend_state *rt0 = &so->rt[0];
42 struct etna_blend_state *co = CALLOC_STRUCT(etna_blend_state);
43 bool alpha_enable, logicop_enable;
44
45 if (!co)
46 return NULL;
47
48 co->base = *so;
49
50 /* Enable blending if
51 * - blend enabled in blend state
52 * - NOT source factor is ONE and destination factor ZERO for both rgb and
53 * alpha (which would mean that blending is effectively disabled)
54 */
55 alpha_enable = rt0->blend_enable &&
56 !(rt0->rgb_src_factor == PIPE_BLENDFACTOR_ONE &&
57 rt0->rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
58 rt0->alpha_src_factor == PIPE_BLENDFACTOR_ONE &&
59 rt0->alpha_dst_factor == PIPE_BLENDFACTOR_ZERO);
60
61 /* Enable separate alpha if
62 * - Blending enabled (see above)
63 * - NOT source factor is equal to destination factor for both rgb abd
64 * alpha (which would effectively that mean alpha is not separate)
65 */
66 bool separate_alpha = alpha_enable &&
67 !(rt0->rgb_src_factor == rt0->alpha_src_factor &&
68 rt0->rgb_dst_factor == rt0->alpha_dst_factor);
69
70 if (alpha_enable) {
71 co->PE_ALPHA_CONFIG =
72 VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR |
73 COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) |
74 VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(translate_blend_factor(rt0->rgb_src_factor)) |
75 VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(translate_blend_factor(rt0->alpha_src_factor)) |
76 VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(translate_blend_factor(rt0->rgb_dst_factor)) |
77 VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(translate_blend_factor(rt0->alpha_dst_factor)) |
78 VIVS_PE_ALPHA_CONFIG_EQ_COLOR(translate_blend(rt0->rgb_func)) |
79 VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(translate_blend(rt0->alpha_func));
80 } else {
81 co->PE_ALPHA_CONFIG = 0;
82 }
83
84 logicop_enable = so->logicop_enable &&
85 VIV_FEATURE(ctx->screen, chipMinorFeatures2, LOGIC_OP);
86
87 co->PE_LOGIC_OP =
88 VIVS_PE_LOGIC_OP_OP(logicop_enable ? so->logicop_func : LOGIC_OP_COPY) |
89 0x000E4000 /* ??? */;
90
91 co->fo_allowed = !alpha_enable && !logicop_enable;
92
93 /* independent_blend_enable not needed: only one rt supported */
94 /* XXX alpha_to_coverage / alpha_to_one? */
95 /* Set dither registers based on dither status. These registers set the
96 * dither pattern,
97 * for now, set the same values as the blob.
98 */
99 if (so->dither) {
100 co->PE_DITHER[0] = 0x6e4ca280;
101 co->PE_DITHER[1] = 0x5d7f91b3;
102 } else {
103 co->PE_DITHER[0] = 0xffffffff;
104 co->PE_DITHER[1] = 0xffffffff;
105 }
106
107 return co;
108 }
109
110 bool
111 etna_update_blend(struct etna_context *ctx)
112 {
113 struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s;
114 struct pipe_blend_state *pblend = ctx->blend;
115 struct etna_blend_state *blend = etna_blend_state(pblend);
116 const struct pipe_rt_blend_state *rt0 = &pblend->rt[0];
117 const struct util_format_description *desc;
118 uint32_t colormask;
119
120 if (pfb->cbufs[0] &&
121 translate_rs_format_rb_swap(pfb->cbufs[0]->format)) {
122 colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G);
123 if (rt0->colormask & PIPE_MASK_R)
124 colormask |= PIPE_MASK_B;
125 if (rt0->colormask & PIPE_MASK_B)
126 colormask |= PIPE_MASK_R;
127 } else {
128 colormask = rt0->colormask;
129 }
130
131 /* If the complete render target is written, set full_overwrite:
132 * - The color mask covers all channels of the render target
133 * - No blending or logicop is used
134 */
135 if (pfb->cbufs[0])
136 desc = util_format_description(pfb->cbufs[0]->format);
137 bool full_overwrite = !pfb->cbufs[0] || ((blend->fo_allowed &&
138 util_format_colormask_full(desc, colormask)));
139 blend->PE_COLOR_FORMAT =
140 VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) |
141 COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);
142
143 return true;
144 }
145
146 void
147 etna_set_blend_color(struct pipe_context *pctx, const struct pipe_blend_color *bc)
148 {
149 struct etna_context *ctx = etna_context(pctx);
150 struct compiled_blend_color *cs = &ctx->blend_color;
151
152 memcpy(cs->color, bc->color, sizeof(float) * 4);
153
154 ctx->dirty |= ETNA_DIRTY_BLEND_COLOR;
155 }
156
157 bool
158 etna_update_blend_color(struct etna_context *ctx)
159 {
160 struct pipe_framebuffer_state *pfb = &ctx->framebuffer_s;
161 struct compiled_blend_color *cs = &ctx->blend_color;
162
163 if (pfb->cbufs[0] &&
164 translate_rs_format_rb_swap(pfb->cbufs[0]->format)) {
165 cs->PE_ALPHA_BLEND_COLOR =
166 VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[2])) |
167 VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(cs->color[1])) |
168 VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(cs->color[0])) |
169 VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(cs->color[3]));
170 } else {
171 cs->PE_ALPHA_BLEND_COLOR =
172 VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[0])) |
173 VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(cs->color[1])) |
174 VIVS_PE_ALPHA_BLEND_COLOR_B(etna_cfloat_to_uint8(cs->color[2])) |
175 VIVS_PE_ALPHA_BLEND_COLOR_A(etna_cfloat_to_uint8(cs->color[3]));
176 }
177
178 return true;
179 }