2 * Copyright (c) 2017 Etnaviv Project
3 * Copyright (C) 2017 Zodiac Inflight Innovations
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_blt.h"
29 #include "etnaviv_emit.h"
30 #include "etnaviv_clear_blit.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_emit.h"
33 #include "etnaviv_format.h"
34 #include "etnaviv_resource.h"
35 #include "etnaviv_surface.h"
36 #include "etnaviv_translate.h"
38 #include "util/u_math.h"
39 #include "pipe/p_defines.h"
40 #include "pipe/p_state.h"
41 #include "util/u_blitter.h"
42 #include "util/u_inlines.h"
43 #include "util/u_memory.h"
44 #include "util/u_surface.h"
46 #include "hw/common_3d.xml.h"
47 #include "hw/state_blt.xml.h"
48 #include "hw/common.xml.h"
52 /* Currently, used BLT formats overlap 100% with RS formats */
53 #define translate_blt_format translate_rs_format
55 static inline uint32_t
56 blt_compute_stride_bits(const struct blt_imginfo
*img
)
58 return VIVS_BLT_DEST_STRIDE_TILING(img
->tiling
== ETNA_LAYOUT_LINEAR
? 0 : 3) | /* 1/3? */
59 VIVS_BLT_DEST_STRIDE_FORMAT(img
->format
) |
60 VIVS_BLT_DEST_STRIDE_STRIDE(img
->stride
);
63 static inline uint32_t
64 blt_compute_img_config_bits(const struct blt_imginfo
*img
, bool for_dest
)
66 uint32_t tiling_bits
= 0;
67 if (img
->tiling
== ETNA_LAYOUT_SUPER_TILED
) {
68 tiling_bits
|= for_dest
? BLT_IMAGE_CONFIG_TO_SUPER_TILED
: BLT_IMAGE_CONFIG_FROM_SUPER_TILED
;
71 return BLT_IMAGE_CONFIG_CACHE_MODE(img
->cache_mode
) |
72 COND(img
->use_ts
, BLT_IMAGE_CONFIG_TS
) |
73 COND(img
->compressed
, BLT_IMAGE_CONFIG_COMPRESSION
) |
74 BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(img
->compress_fmt
) |
75 COND(for_dest
, BLT_IMAGE_CONFIG_UNK22
) |
76 BLT_IMAGE_CONFIG_SWIZ_R(0) | /* not used? */
77 BLT_IMAGE_CONFIG_SWIZ_G(1) |
78 BLT_IMAGE_CONFIG_SWIZ_B(2) |
79 BLT_IMAGE_CONFIG_SWIZ_A(3) |
83 static inline uint32_t
84 blt_compute_swizzle_bits(const struct blt_imginfo
*img
, bool for_dest
)
86 uint32_t swiz
= VIVS_BLT_SWIZZLE_SRC_R(img
->swizzle
[0]) |
87 VIVS_BLT_SWIZZLE_SRC_G(img
->swizzle
[1]) |
88 VIVS_BLT_SWIZZLE_SRC_B(img
->swizzle
[2]) |
89 VIVS_BLT_SWIZZLE_SRC_A(img
->swizzle
[3]);
90 return for_dest
? (swiz
<< 12) : swiz
;
93 /* Clear (part of) an image */
95 emit_blt_clearimage(struct etna_cmd_stream
*stream
, const struct blt_clear_op
*op
)
97 etna_cmd_stream_reserve(stream
, 64*2); /* Make sure BLT op doesn't get broken up */
99 etna_set_state(stream
, VIVS_BLT_ENABLE
, 0x00000001);
100 assert(op
->dest
.bpp
);
101 etna_set_state(stream
, VIVS_BLT_CONFIG
, VIVS_BLT_CONFIG_CLEAR_BPP(op
->dest
.bpp
-1));
102 /* NB: blob sets format to 1 in dest/src config for clear, and the swizzle to RRRR.
103 * does this matter? It seems to just be ignored. But if we run into issues with BLT
104 * behaving stragely, it's something to look at.
106 etna_set_state(stream
, VIVS_BLT_DEST_STRIDE
, blt_compute_stride_bits(&op
->dest
));
107 etna_set_state(stream
, VIVS_BLT_DEST_CONFIG
, blt_compute_img_config_bits(&op
->dest
, true));
108 etna_set_state_reloc(stream
, VIVS_BLT_DEST_ADDR
, &op
->dest
.addr
);
109 etna_set_state(stream
, VIVS_BLT_SRC_STRIDE
, blt_compute_stride_bits(&op
->dest
));
110 etna_set_state(stream
, VIVS_BLT_SRC_CONFIG
, blt_compute_img_config_bits(&op
->dest
, false));
111 etna_set_state_reloc(stream
, VIVS_BLT_SRC_ADDR
, &op
->dest
.addr
);
112 etna_set_state(stream
, VIVS_BLT_DEST_POS
, VIVS_BLT_DEST_POS_X(op
->rect_x
) | VIVS_BLT_DEST_POS_Y(op
->rect_y
));
113 etna_set_state(stream
, VIVS_BLT_IMAGE_SIZE
, VIVS_BLT_IMAGE_SIZE_WIDTH(op
->rect_w
) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op
->rect_h
));
114 etna_set_state(stream
, VIVS_BLT_CLEAR_COLOR0
, op
->clear_value
[0]);
115 etna_set_state(stream
, VIVS_BLT_CLEAR_COLOR1
, op
->clear_value
[1]);
116 etna_set_state(stream
, VIVS_BLT_CLEAR_BITS0
, op
->clear_bits
[0]);
117 etna_set_state(stream
, VIVS_BLT_CLEAR_BITS1
, op
->clear_bits
[1]);
118 if (op
->dest
.use_ts
) {
119 etna_set_state_reloc(stream
, VIVS_BLT_DEST_TS
, &op
->dest
.ts_addr
);
120 etna_set_state_reloc(stream
, VIVS_BLT_SRC_TS
, &op
->dest
.ts_addr
);
121 etna_set_state(stream
, VIVS_BLT_DEST_TS_CLEAR_VALUE0
, op
->dest
.ts_clear_value
[0]);
122 etna_set_state(stream
, VIVS_BLT_DEST_TS_CLEAR_VALUE1
, op
->dest
.ts_clear_value
[1]);
123 etna_set_state(stream
, VIVS_BLT_SRC_TS_CLEAR_VALUE0
, op
->dest
.ts_clear_value
[0]);
124 etna_set_state(stream
, VIVS_BLT_SRC_TS_CLEAR_VALUE1
, op
->dest
.ts_clear_value
[1]);
126 etna_set_state(stream
, VIVS_BLT_SET_COMMAND
, 0x00000003);
127 etna_set_state(stream
, VIVS_BLT_COMMAND
, VIVS_BLT_COMMAND_COMMAND_CLEAR_IMAGE
);
128 etna_set_state(stream
, VIVS_BLT_SET_COMMAND
, 0x00000003);
129 etna_set_state(stream
, VIVS_BLT_ENABLE
, 0x00000000);
132 /* Copy (a subset of) an image to another image. */
134 emit_blt_copyimage(struct etna_cmd_stream
*stream
, const struct blt_imgcopy_op
*op
)
136 etna_cmd_stream_reserve(stream
, 64*2); /* Never allow BLT sequences to be broken up */
138 etna_set_state(stream
, VIVS_BLT_ENABLE
, 0x00000001);
139 etna_set_state(stream
, VIVS_BLT_CONFIG
,
140 VIVS_BLT_CONFIG_SRC_ENDIAN(op
->src
.endian_mode
) |
141 VIVS_BLT_CONFIG_DEST_ENDIAN(op
->dest
.endian_mode
));
142 etna_set_state(stream
, VIVS_BLT_SRC_STRIDE
, blt_compute_stride_bits(&op
->src
));
143 etna_set_state(stream
, VIVS_BLT_SRC_CONFIG
, blt_compute_img_config_bits(&op
->src
, false));
144 etna_set_state(stream
, VIVS_BLT_SWIZZLE
,
145 blt_compute_swizzle_bits(&op
->src
, false) |
146 blt_compute_swizzle_bits(&op
->dest
, true));
147 etna_set_state(stream
, VIVS_BLT_UNK140A0
, 0x00040004);
148 etna_set_state(stream
, VIVS_BLT_UNK1409C
, 0x00400040);
149 if (op
->src
.use_ts
) {
150 etna_set_state_reloc(stream
, VIVS_BLT_SRC_TS
, &op
->src
.ts_addr
);
151 etna_set_state(stream
, VIVS_BLT_SRC_TS_CLEAR_VALUE0
, op
->src
.ts_clear_value
[0]);
152 etna_set_state(stream
, VIVS_BLT_SRC_TS_CLEAR_VALUE1
, op
->src
.ts_clear_value
[1]);
154 etna_set_state_reloc(stream
, VIVS_BLT_SRC_ADDR
, &op
->src
.addr
);
155 etna_set_state(stream
, VIVS_BLT_DEST_STRIDE
, blt_compute_stride_bits(&op
->dest
));
156 etna_set_state(stream
, VIVS_BLT_DEST_CONFIG
,
157 blt_compute_img_config_bits(&op
->dest
, true) |
158 COND(op
->flip_y
, BLT_IMAGE_CONFIG_FLIP_Y
));
159 assert(!op
->dest
.use_ts
); /* Dest TS path doesn't work for copies? */
160 if (op
->dest
.use_ts
) {
161 etna_set_state_reloc(stream
, VIVS_BLT_DEST_TS
, &op
->dest
.ts_addr
);
162 etna_set_state(stream
, VIVS_BLT_DEST_TS_CLEAR_VALUE0
, op
->dest
.ts_clear_value
[0]);
163 etna_set_state(stream
, VIVS_BLT_DEST_TS_CLEAR_VALUE1
, op
->dest
.ts_clear_value
[1]);
165 etna_set_state_reloc(stream
, VIVS_BLT_DEST_ADDR
, &op
->dest
.addr
);
166 etna_set_state(stream
, VIVS_BLT_SRC_POS
, VIVS_BLT_DEST_POS_X(op
->src_x
) | VIVS_BLT_DEST_POS_Y(op
->src_y
));
167 etna_set_state(stream
, VIVS_BLT_DEST_POS
, VIVS_BLT_DEST_POS_X(op
->dest_x
) | VIVS_BLT_DEST_POS_Y(op
->dest_y
));
168 etna_set_state(stream
, VIVS_BLT_IMAGE_SIZE
, VIVS_BLT_IMAGE_SIZE_WIDTH(op
->rect_w
) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op
->rect_h
));
169 etna_set_state(stream
, VIVS_BLT_UNK14058
, 0xffffffff);
170 etna_set_state(stream
, VIVS_BLT_UNK1405C
, 0xffffffff);
171 etna_set_state(stream
, VIVS_BLT_SET_COMMAND
, 0x00000003);
172 etna_set_state(stream
, VIVS_BLT_COMMAND
, VIVS_BLT_COMMAND_COMMAND_COPY_IMAGE
);
173 etna_set_state(stream
, VIVS_BLT_SET_COMMAND
, 0x00000003);
174 etna_set_state(stream
, VIVS_BLT_ENABLE
, 0x00000000);
177 /* Emit in-place resolve using BLT. */
179 emit_blt_inplace(struct etna_cmd_stream
*stream
, const struct blt_inplace_op
*op
)
181 assert(op
->bpp
> 0 && util_is_power_of_two_nonzero(op
->bpp
));
182 etna_cmd_stream_reserve(stream
, 64*2); /* Never allow BLT sequences to be broken up */
183 etna_set_state(stream
, VIVS_BLT_ENABLE
, 0x00000001);
184 etna_set_state(stream
, VIVS_BLT_CONFIG
,
185 VIVS_BLT_CONFIG_INPLACE_CACHE_MODE(op
->cache_mode
) |
186 VIVS_BLT_CONFIG_INPLACE_BOTH
|
187 (util_logbase2(op
->bpp
) << VIVS_BLT_CONFIG_INPLACE_BPP__SHIFT
));
188 etna_set_state(stream
, VIVS_BLT_DEST_TS_CLEAR_VALUE0
, op
->ts_clear_value
[0]);
189 etna_set_state(stream
, VIVS_BLT_DEST_TS_CLEAR_VALUE1
, op
->ts_clear_value
[1]);
190 etna_set_state_reloc(stream
, VIVS_BLT_DEST_ADDR
, &op
->addr
);
191 etna_set_state_reloc(stream
, VIVS_BLT_DEST_TS
, &op
->ts_addr
);
192 etna_set_state(stream
, 0x14068, op
->num_tiles
);
193 etna_set_state(stream
, VIVS_BLT_SET_COMMAND
, 0x00000003);
194 etna_set_state(stream
, VIVS_BLT_COMMAND
, 0x00000004);
195 etna_set_state(stream
, VIVS_BLT_SET_COMMAND
, 0x00000003);
196 etna_set_state(stream
, VIVS_BLT_ENABLE
, 0x00000000);
200 etna_blit_clear_color_blt(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
201 const union pipe_color_union
*color
)
203 struct etna_context
*ctx
= etna_context(pctx
);
204 struct etna_surface
*surf
= etna_surface(dst
);
205 uint32_t new_clear_value
= etna_clear_blit_pack_rgba(surf
->base
.format
, color
->f
);
207 struct etna_resource
*res
= etna_resource(surf
->base
.texture
);
208 struct blt_clear_op clr
= {};
209 clr
.dest
.addr
.bo
= res
->bo
;
210 clr
.dest
.addr
.offset
= surf
->surf
.offset
;
211 clr
.dest
.addr
.flags
= ETNA_RELOC_WRITE
;
212 clr
.dest
.bpp
= util_format_get_blocksize(surf
->base
.format
);
213 clr
.dest
.stride
= surf
->surf
.stride
;
214 /* TODO: color compression
215 clr.dest.compressed = 1;
216 clr.dest.compress_fmt = 3;
218 clr
.dest
.tiling
= res
->layout
;
219 clr
.dest
.cache_mode
= TS_CACHE_MODE_128
; /* TODO: cache modes */
221 if (surf
->surf
.ts_size
) {
223 clr
.dest
.ts_addr
.bo
= res
->ts_bo
;
224 clr
.dest
.ts_addr
.offset
= 0;
225 clr
.dest
.ts_addr
.flags
= ETNA_RELOC_WRITE
;
226 clr
.dest
.ts_clear_value
[0] = new_clear_value
;
227 clr
.dest
.ts_clear_value
[1] = new_clear_value
;
230 clr
.clear_value
[0] = new_clear_value
;
231 clr
.clear_value
[1] = new_clear_value
;
232 clr
.clear_bits
[0] = 0xffffffff; /* TODO: Might want to clear only specific channels? */
233 clr
.clear_bits
[1] = 0xffffffff;
234 clr
.rect_x
= 0; /* What about scissors? */
236 clr
.rect_w
= surf
->surf
.width
;
237 clr
.rect_h
= surf
->surf
.height
;
239 emit_blt_clearimage(ctx
->stream
, &clr
);
241 /* This made the TS valid */
242 if (surf
->surf
.ts_size
) {
243 ctx
->framebuffer
.TS_COLOR_CLEAR_VALUE
= new_clear_value
;
244 surf
->level
->ts_valid
= true;
247 surf
->level
->clear_value
= new_clear_value
;
248 resource_written(ctx
, surf
->base
.texture
);
249 etna_resource(surf
->base
.texture
)->seqno
++;
253 etna_blit_clear_zs_blt(struct pipe_context
*pctx
, struct pipe_surface
*dst
,
254 unsigned buffers
, double depth
, unsigned stencil
)
256 struct etna_context
*ctx
= etna_context(pctx
);
257 struct etna_surface
*surf
= etna_surface(dst
);
258 uint32_t new_clear_value
= translate_clear_depth_stencil(surf
->base
.format
, depth
, stencil
);
259 uint32_t new_clear_bits
= 0, clear_bits_depth
, clear_bits_stencil
;
261 /* Get the channels to clear */
262 switch (surf
->base
.format
) {
263 case PIPE_FORMAT_Z16_UNORM
:
264 clear_bits_depth
= 0xffffffff;
265 clear_bits_stencil
= 0x00000000;
267 case PIPE_FORMAT_X8Z24_UNORM
:
268 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
269 clear_bits_depth
= 0xffffff00;
270 clear_bits_stencil
= 0x000000ff;
273 clear_bits_depth
= clear_bits_stencil
= 0xffffffff;
277 if (buffers
& PIPE_CLEAR_DEPTH
)
278 new_clear_bits
|= clear_bits_depth
;
279 if (buffers
& PIPE_CLEAR_STENCIL
)
280 new_clear_bits
|= clear_bits_stencil
;
282 /* TODO unduplicate this */
283 struct etna_resource
*res
= etna_resource(surf
->base
.texture
);
284 struct blt_clear_op clr
= {};
285 clr
.dest
.addr
.bo
= res
->bo
;
286 clr
.dest
.addr
.offset
= surf
->surf
.offset
;
287 clr
.dest
.addr
.flags
= ETNA_RELOC_WRITE
;
288 clr
.dest
.bpp
= util_format_get_blocksize(surf
->base
.format
);
289 clr
.dest
.stride
= surf
->surf
.stride
;
290 #if 0 /* TODO depth compression */
291 clr
.dest
.compressed
= 1;
292 clr
.dest
.compress_fmt
= COLOR_COMPRESSION_FORMAT_D24S8
;
294 clr
.dest
.tiling
= res
->layout
;
295 clr
.dest
.cache_mode
= TS_CACHE_MODE_128
; /* TODO: cache modes */
297 if (surf
->surf
.ts_size
) {
299 clr
.dest
.ts_addr
.bo
= res
->ts_bo
;
300 clr
.dest
.ts_addr
.offset
= 0;
301 clr
.dest
.ts_addr
.flags
= ETNA_RELOC_WRITE
;
302 clr
.dest
.ts_clear_value
[0] = new_clear_value
;
303 clr
.dest
.ts_clear_value
[1] = new_clear_value
;
306 clr
.clear_value
[0] = new_clear_value
;
307 clr
.clear_value
[1] = new_clear_value
;
308 clr
.clear_bits
[0] = new_clear_bits
;
309 clr
.clear_bits
[1] = new_clear_bits
;
310 clr
.rect_x
= 0; /* What about scissors? */
312 clr
.rect_w
= surf
->surf
.width
;
313 clr
.rect_h
= surf
->surf
.height
;
315 emit_blt_clearimage(ctx
->stream
, &clr
);
317 /* This made the TS valid */
318 if (surf
->surf
.ts_size
) {
319 ctx
->framebuffer
.TS_DEPTH_CLEAR_VALUE
= new_clear_value
;
320 surf
->level
->ts_valid
= true;
323 surf
->level
->clear_value
= new_clear_value
;
324 resource_written(ctx
, surf
->base
.texture
);
325 etna_resource(surf
->base
.texture
)->seqno
++;
329 etna_clear_blt(struct pipe_context
*pctx
, unsigned buffers
,
330 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
332 struct etna_context
*ctx
= etna_context(pctx
);
334 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, 0x00000c23);
335 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, VIVS_TS_FLUSH_CACHE_FLUSH
);
337 if (buffers
& PIPE_CLEAR_COLOR
) {
338 for (int idx
= 0; idx
< ctx
->framebuffer_s
.nr_cbufs
; ++idx
) {
339 etna_blit_clear_color_blt(pctx
, ctx
->framebuffer_s
.cbufs
[idx
],
344 if ((buffers
& PIPE_CLEAR_DEPTHSTENCIL
) && ctx
->framebuffer_s
.zsbuf
!= NULL
)
345 etna_blit_clear_zs_blt(pctx
, ctx
->framebuffer_s
.zsbuf
, buffers
, depth
, stencil
);
347 etna_stall(ctx
->stream
, SYNC_RECIPIENT_RA
, SYNC_RECIPIENT_BLT
);
349 if ((buffers
& PIPE_CLEAR_COLOR
) && (buffers
& PIPE_CLEAR_DEPTH
))
350 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, 0x00000c23);
352 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, 0x00000002);
357 etna_try_blt_blit(struct pipe_context
*pctx
,
358 const struct pipe_blit_info
*blit_info
)
360 struct etna_context
*ctx
= etna_context(pctx
);
361 struct etna_resource
*src
= etna_resource(blit_info
->src
.resource
);
362 struct etna_resource
*dst
= etna_resource(blit_info
->dst
.resource
);
363 int msaa_xscale
= 1, msaa_yscale
= 1;
365 /* Ensure that the level is valid */
366 assert(blit_info
->src
.level
<= src
->base
.last_level
);
367 assert(blit_info
->dst
.level
<= dst
->base
.last_level
);
369 if (!translate_samples_to_xyscale(src
->base
.nr_samples
, &msaa_xscale
, &msaa_yscale
, NULL
))
372 /* The width/height are in pixels; they do not change as a result of
373 * multi-sampling. So, when blitting from a 4x multisampled surface
374 * to a non-multisampled surface, the width and height will be
375 * identical. As we do not support scaling, reject different sizes.
376 * TODO: could handle 2x downsample here with emit_blt_genmipmaps */
377 if (blit_info
->dst
.box
.width
!= blit_info
->src
.box
.width
||
378 blit_info
->dst
.box
.height
!= abs(blit_info
->src
.box
.height
)) { /* allow y flip for glTexImage2D */
379 DBG("scaling requested: source %dx%d destination %dx%d",
380 blit_info
->src
.box
.width
, blit_info
->src
.box
.height
,
381 blit_info
->dst
.box
.width
, blit_info
->dst
.box
.height
);
385 /* No masks - not sure if BLT can copy individual channels */
386 unsigned mask
= util_format_get_mask(blit_info
->dst
.format
);
387 if ((blit_info
->mask
& mask
) != mask
) {
388 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info
->mask
, mask
);
392 /* TODO: 1 byte per pixel formats aren't handled by etna_compatible_rs_format nor
393 * translate_rs_format.
394 * Also this should be smarter about format conversions; etna_compatible_rs_format
395 * assumes all 2-byte pixel format are laid out as 4444, all 4-byte pixel formats
398 unsigned src_format
= etna_compatible_rs_format(blit_info
->src
.format
);
399 unsigned dst_format
= etna_compatible_rs_format(blit_info
->dst
.format
);
400 if (translate_blt_format(src_format
) == ETNA_NO_MATCH
||
401 translate_blt_format(dst_format
) == ETNA_NO_MATCH
||
402 blit_info
->scissor_enable
||
403 blit_info
->dst
.box
.depth
!= blit_info
->src
.box
.depth
||
404 blit_info
->dst
.box
.depth
!= 1) {
408 /* Ensure that the Z coordinate is sane */
409 assert(dst
->base
.target
== PIPE_TEXTURE_CUBE
|| blit_info
->dst
.box
.z
== 0);
410 assert(src
->base
.target
== PIPE_TEXTURE_CUBE
|| blit_info
->src
.box
.z
== 0);
411 assert(blit_info
->src
.box
.z
< src
->base
.array_size
);
412 assert(blit_info
->dst
.box
.z
< dst
->base
.array_size
);
414 struct etna_resource_level
*src_lev
= &src
->levels
[blit_info
->src
.level
];
415 struct etna_resource_level
*dst_lev
= &dst
->levels
[blit_info
->dst
.level
];
417 /* Kick off BLT here */
419 /* Resolve-in-place */
420 assert(!memcmp(&blit_info
->src
, &blit_info
->dst
, sizeof(blit_info
->src
)));
421 if (!src_lev
->ts_size
|| !src_lev
->ts_valid
) /* No TS, no worries */
423 struct blt_inplace_op op
= {};
425 op
.addr
.bo
= src
->bo
;
426 op
.addr
.offset
= src_lev
->offset
+ blit_info
->src
.box
.z
* src_lev
->layer_stride
;
427 op
.addr
.flags
= ETNA_RELOC_READ
| ETNA_RELOC_WRITE
;
428 op
.ts_addr
.bo
= src
->ts_bo
;
429 op
.ts_addr
.offset
= src_lev
->ts_offset
+ blit_info
->src
.box
.z
* src_lev
->ts_layer_stride
;
430 op
.ts_addr
.flags
= ETNA_RELOC_READ
;
431 op
.ts_clear_value
[0] = src_lev
->clear_value
;
432 op
.ts_clear_value
[1] = src_lev
->clear_value
;
433 op
.cache_mode
= TS_CACHE_MODE_128
; /* TODO: cache modes */
434 op
.num_tiles
= src_lev
->size
/ 128; /* TODO: cache modes */
435 op
.bpp
= util_format_get_blocksize(src
->base
.format
);
437 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, 0x00000c23);
438 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, 0x00000001);
439 emit_blt_inplace(ctx
->stream
, &op
);
442 struct blt_imgcopy_op op
= {};
444 op
.src
.addr
.bo
= src
->bo
;
445 op
.src
.addr
.offset
= src_lev
->offset
+ blit_info
->src
.box
.z
* src_lev
->layer_stride
;
446 op
.src
.addr
.flags
= ETNA_RELOC_READ
;
447 op
.src
.format
= translate_blt_format(src_format
);
448 op
.src
.stride
= src_lev
->stride
;
449 op
.src
.tiling
= src
->layout
;
450 op
.src
.cache_mode
= TS_CACHE_MODE_128
; /* TODO: cache modes */
451 const struct util_format_description
*src_format_desc
=
452 util_format_description(blit_info
->src
.format
);
453 for (unsigned x
=0; x
<4; ++x
)
454 op
.src
.swizzle
[x
] = src_format_desc
->swizzle
[x
];
456 if (src_lev
->ts_size
&& src_lev
->ts_valid
) {
458 op
.src
.ts_addr
.bo
= src
->ts_bo
;
459 op
.src
.ts_addr
.offset
= src_lev
->ts_offset
+ blit_info
->src
.box
.z
* src_lev
->ts_layer_stride
;
460 op
.src
.ts_addr
.flags
= ETNA_RELOC_READ
;
461 op
.src
.ts_clear_value
[0] = src_lev
->clear_value
;
462 op
.src
.ts_clear_value
[1] = src_lev
->clear_value
;
465 op
.dest
.addr
.bo
= dst
->bo
;
466 op
.dest
.addr
.offset
= dst_lev
->offset
+ blit_info
->dst
.box
.z
* dst_lev
->layer_stride
;
467 op
.dest
.addr
.flags
= ETNA_RELOC_WRITE
;
468 op
.dest
.format
= translate_blt_format(dst_format
);
469 op
.dest
.stride
= dst_lev
->stride
;
470 /* TODO color compression
471 op.dest.compressed = 1;
472 op.dest.compress_fmt = 3;
474 op
.dest
.tiling
= dst
->layout
;
475 op
.dest
.cache_mode
= TS_CACHE_MODE_128
; /* TODO cache modes */
476 const struct util_format_description
*dst_format_desc
=
477 util_format_description(blit_info
->dst
.format
);
478 for (unsigned x
=0; x
<4; ++x
)
479 op
.dest
.swizzle
[x
] = dst_format_desc
->swizzle
[x
];
481 op
.dest_x
= blit_info
->dst
.box
.x
;
482 op
.dest_y
= blit_info
->dst
.box
.y
;
483 op
.src_x
= blit_info
->src
.box
.x
;
484 op
.src_y
= blit_info
->src
.box
.y
;
485 op
.rect_w
= blit_info
->dst
.box
.width
;
486 op
.rect_h
= blit_info
->dst
.box
.height
;
488 if (blit_info
->src
.box
.height
< 0) { /* flipped? fix up base y */
490 op
.src_y
+= blit_info
->src
.box
.height
;
493 assert(op
.src_x
< src_lev
->padded_width
);
494 assert(op
.src_y
< src_lev
->padded_height
);
495 assert((op
.src_x
+ op
.rect_w
) <= src_lev
->padded_width
);
496 assert((op
.src_y
+ op
.rect_h
) <= src_lev
->padded_height
);
497 assert(op
.dest_x
< dst_lev
->padded_width
);
498 assert(op
.dest_y
< dst_lev
->padded_height
);
499 assert((op
.dest_x
+ op
.rect_w
) <= dst_lev
->padded_width
);
500 assert((op
.dest_y
+ op
.rect_h
) <= dst_lev
->padded_height
);
502 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, 0x00000c23);
503 etna_set_state(ctx
->stream
, VIVS_TS_FLUSH_CACHE
, 0x00000001);
504 emit_blt_copyimage(ctx
->stream
, &op
);
507 /* Make FE wait for BLT, in case we want to do something with the image next.
508 * This probably shouldn't be here, and depend on what is done with the resource.
510 etna_stall(ctx
->stream
, SYNC_RECIPIENT_FE
, SYNC_RECIPIENT_BLT
);
511 etna_set_state(ctx
->stream
, VIVS_GL_FLUSH_CACHE
, 0x00000c23);
513 resource_read(ctx
, &src
->base
);
514 resource_written(ctx
, &dst
->base
);
517 dst_lev
->ts_valid
= false;
523 etna_blit_blt(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
525 struct etna_context
*ctx
= etna_context(pctx
);
526 struct pipe_blit_info info
= *blit_info
;
528 if (info
.src
.resource
->nr_samples
> 1 &&
529 info
.dst
.resource
->nr_samples
<= 1 &&
530 !util_format_is_depth_or_stencil(info
.src
.resource
->format
) &&
531 !util_format_is_pure_integer(info
.src
.resource
->format
)) {
532 DBG("color resolve unimplemented");
536 if (etna_try_blt_blit(pctx
, blit_info
))
539 if (util_try_blit_via_copy_region(pctx
, blit_info
))
542 if (info
.mask
& PIPE_MASK_S
) {
543 DBG("cannot blit stencil, skipping");
544 info
.mask
&= ~PIPE_MASK_S
;
547 if (!util_blitter_is_blit_supported(ctx
->blitter
, &info
)) {
548 DBG("blit unsupported %s -> %s",
549 util_format_short_name(info
.src
.resource
->format
),
550 util_format_short_name(info
.dst
.resource
->format
));
554 etna_blit_save_state(ctx
);
555 util_blitter_blit(ctx
->blitter
, &info
);
559 etna_clear_blit_blt_init(struct pipe_context
*pctx
)
561 DBG("etnaviv: Using BLT blit engine");
562 pctx
->clear
= etna_clear_blt
;
563 pctx
->blit
= etna_blit_blt
;