66c644453309a090f33fed27c397112d7c7ecfdc
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_clear_blit.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_clear_blit.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_context.h"
32 #include "etnaviv_emit.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_resource.h"
36 #include "etnaviv_surface.h"
37 #include "etnaviv_translate.h"
38
39 #include "pipe/p_defines.h"
40 #include "pipe/p_state.h"
41 #include "util/u_blitter.h"
42 #include "util/u_inlines.h"
43 #include "util/u_memory.h"
44 #include "util/u_surface.h"
45
46 /* Save current state for blitter operation */
47 static void
48 etna_blit_save_state(struct etna_context *ctx)
49 {
50 util_blitter_save_vertex_buffer_slot(ctx->blitter, ctx->vertex_buffer.vb);
51 util_blitter_save_vertex_elements(ctx->blitter, ctx->vertex_elements);
52 util_blitter_save_vertex_shader(ctx->blitter, ctx->shader.bind_vs);
53 util_blitter_save_rasterizer(ctx->blitter, ctx->rasterizer);
54 util_blitter_save_viewport(ctx->blitter, &ctx->viewport_s);
55 util_blitter_save_scissor(ctx->blitter, &ctx->scissor_s);
56 util_blitter_save_fragment_shader(ctx->blitter, ctx->shader.bind_fs);
57 util_blitter_save_blend(ctx->blitter, ctx->blend);
58 util_blitter_save_depth_stencil_alpha(ctx->blitter, ctx->zsa);
59 util_blitter_save_stencil_ref(ctx->blitter, &ctx->stencil_ref_s);
60 util_blitter_save_sample_mask(ctx->blitter, ctx->sample_mask);
61 util_blitter_save_framebuffer(ctx->blitter, &ctx->framebuffer_s);
62 util_blitter_save_fragment_sampler_states(ctx->blitter,
63 ctx->num_fragment_samplers, (void **)ctx->sampler);
64 util_blitter_save_fragment_sampler_views(ctx->blitter,
65 ctx->num_fragment_sampler_views, ctx->sampler_view);
66 }
67
68 /* Generate clear command for a surface (non-fast clear case) */
69 void
70 etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf,
71 uint32_t clear_value)
72 {
73 struct etna_resource *dst = etna_resource(surf->base.texture);
74 uint32_t format = translate_rs_format(surf->base.format);
75
76 if (format == ETNA_NO_MATCH) {
77 BUG("etna_rs_gen_clear_surface: Unhandled clear fmt %s", util_format_name(surf->base.format));
78 format = RS_FORMAT_A8R8G8B8;
79 assert(0);
80 }
81
82 /* use tiled clear if width is multiple of 16 */
83 bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
84 (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
85
86 etna_compile_rs_state( ctx, &surf->clear_command, &(struct rs_state) {
87 .source_format = format,
88 .dest_format = format,
89 .dest = dst->bo,
90 .dest_offset = surf->surf.offset,
91 .dest_stride = surf->surf.stride,
92 .dest_padded_height = surf->surf.padded_height,
93 .dest_tiling = tiled_clear ? dst->layout : ETNA_LAYOUT_LINEAR,
94 .dither = {0xffffffff, 0xffffffff},
95 .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
96 .height = surf->surf.padded_height,
97 .clear_value = {clear_value},
98 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
99 .clear_bits = 0xffff
100 });
101 }
102
103 static inline uint32_t
104 pack_rgba(enum pipe_format format, const float *rgba)
105 {
106 union util_color uc;
107 util_pack_color(rgba, format, &uc);
108 if (util_format_get_blocksize(format) == 2)
109 return uc.ui[0] << 16 | uc.ui[0];
110 else
111 return uc.ui[0];
112 }
113
114 static void
115 etna_blit_clear_color(struct pipe_context *pctx, struct pipe_surface *dst,
116 const union pipe_color_union *color)
117 {
118 struct etna_context *ctx = etna_context(pctx);
119 struct etna_surface *surf = etna_surface(dst);
120 uint32_t new_clear_value = pack_rgba(surf->base.format, color->f);
121
122 if (surf->surf.ts_size) { /* TS: use precompiled clear command */
123 ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
124
125 if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
126 /* Set number of color tiles to be filled */
127 etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
128 surf->surf.padded_width * surf->surf.padded_height / 16);
129 ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE;
130 }
131
132 surf->level->ts_valid = true;
133 ctx->dirty |= ETNA_DIRTY_TS;
134 } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
135 /* If clear color changed, re-generate stored command */
136 etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
137 }
138
139 etna_submit_rs_state(ctx, &surf->clear_command);
140 surf->level->clear_value = new_clear_value;
141 resource_written(ctx, surf->base.texture);
142 etna_resource(surf->base.texture)->seqno++;
143 }
144
145 static void
146 etna_blit_clear_zs(struct pipe_context *pctx, struct pipe_surface *dst,
147 unsigned buffers, double depth, unsigned stencil)
148 {
149 struct etna_context *ctx = etna_context(pctx);
150 struct etna_surface *surf = etna_surface(dst);
151 uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
152 uint32_t new_clear_bits = 0, clear_bits_depth, clear_bits_stencil;
153
154 /* Get the channels to clear */
155 switch (surf->base.format) {
156 case PIPE_FORMAT_Z16_UNORM:
157 clear_bits_depth = 0xffff;
158 clear_bits_stencil = 0;
159 break;
160 case PIPE_FORMAT_X8Z24_UNORM:
161 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
162 clear_bits_depth = 0xeeee;
163 clear_bits_stencil = 0x1111;
164 break;
165 default:
166 clear_bits_depth = clear_bits_stencil = 0xffff;
167 break;
168 }
169
170 if (buffers & PIPE_CLEAR_DEPTH)
171 new_clear_bits |= clear_bits_depth;
172 if (buffers & PIPE_CLEAR_STENCIL)
173 new_clear_bits |= clear_bits_stencil;
174
175 /* FIXME: when tile status is enabled, this becomes more complex as
176 * we may separately clear the depth from the stencil. In this case,
177 * we want to resolve the surface, and avoid using the tile status.
178 * We may be better off recording the pending clear operation,
179 * delaying the actual clear to the first use. This way, we can merge
180 * consecutive clears together. */
181 if (surf->surf.ts_size) { /* TS: use precompiled clear command */
182 /* Set new clear depth value */
183 ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
184 if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
185 /* Set number of depth tiles to be filled */
186 etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT,
187 surf->surf.padded_width * surf->surf.padded_height / 16);
188 ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE;
189 }
190
191 surf->level->ts_valid = true;
192 ctx->dirty |= ETNA_DIRTY_TS;
193 } else {
194 if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
195 /* If clear depth value changed, re-generate stored command */
196 etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
197 }
198 /* Update the channels to be cleared */
199 etna_modify_rs_clearbits(&surf->clear_command, new_clear_bits);
200 }
201
202 etna_submit_rs_state(ctx, &surf->clear_command);
203 surf->level->clear_value = new_clear_value;
204 resource_written(ctx, surf->base.texture);
205 etna_resource(surf->base.texture)->seqno++;
206 }
207
208 static void
209 etna_clear(struct pipe_context *pctx, unsigned buffers,
210 const union pipe_color_union *color, double depth, unsigned stencil)
211 {
212 struct etna_context *ctx = etna_context(pctx);
213
214 /* Flush color and depth cache before clearing anything.
215 * This is especially important when coming from another surface, as
216 * otherwise it may clear part of the old surface instead. */
217 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
218 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
219
220 /* Preparation: Flush the TS if needed. This must be done after flushing
221 * color and depth, otherwise it can result in crashes */
222 bool need_ts_flush = false;
223 if ((buffers & PIPE_CLEAR_COLOR) && ctx->framebuffer_s.nr_cbufs) {
224 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
225 if (surf->surf.ts_size)
226 need_ts_flush = true;
227 }
228 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL) {
229 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.zsbuf);
230
231 if (surf->surf.ts_size)
232 need_ts_flush = true;
233 }
234
235 if (need_ts_flush)
236 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
237
238 /* No need to set up the TS here as RS clear operations (in contrast to
239 * resolve and copy) do not require the TS state.
240 */
241 if (buffers & PIPE_CLEAR_COLOR) {
242 for (int idx = 0; idx < ctx->framebuffer_s.nr_cbufs; ++idx) {
243 etna_blit_clear_color(pctx, ctx->framebuffer_s.cbufs[idx],
244 &color[idx]);
245 }
246 }
247
248 /* Flush the color and depth caches before each RS clear operation
249 * This fixes a hang on GC600. */
250 if (buffers & PIPE_CLEAR_DEPTHSTENCIL && buffers & PIPE_CLEAR_COLOR)
251 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
252 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
253
254 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL)
255 etna_blit_clear_zs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
256
257 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
258 }
259
260 static void
261 etna_clear_render_target(struct pipe_context *pctx, struct pipe_surface *dst,
262 const union pipe_color_union *color, unsigned dstx,
263 unsigned dsty, unsigned width, unsigned height,
264 bool render_condition_enabled)
265 {
266 struct etna_context *ctx = etna_context(pctx);
267
268 /* XXX could fall back to RS when target area is full screen / resolveable
269 * and no TS. */
270 etna_blit_save_state(ctx);
271 util_blitter_clear_render_target(ctx->blitter, dst, color, dstx, dsty, width, height);
272 }
273
274 static void
275 etna_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *dst,
276 unsigned clear_flags, double depth, unsigned stencil,
277 unsigned dstx, unsigned dsty, unsigned width,
278 unsigned height, bool render_condition_enabled)
279 {
280 struct etna_context *ctx = etna_context(pctx);
281
282 /* XXX could fall back to RS when target area is full screen / resolveable
283 * and no TS. */
284 etna_blit_save_state(ctx);
285 util_blitter_clear_depth_stencil(ctx->blitter, dst, clear_flags, depth,
286 stencil, dstx, dsty, width, height);
287 }
288
289 static void
290 etna_resource_copy_region(struct pipe_context *pctx, struct pipe_resource *dst,
291 unsigned dst_level, unsigned dstx, unsigned dsty,
292 unsigned dstz, struct pipe_resource *src,
293 unsigned src_level, const struct pipe_box *src_box)
294 {
295 struct etna_context *ctx = etna_context(pctx);
296
297 /* The resource must be of the same format. */
298 assert(src->format == dst->format);
299
300 /* XXX we can use the RS as a literal copy engine here
301 * the only complexity is tiling; the size of the boxes needs to be aligned
302 * to the tile size
303 * how to handle the case where a resource is copied from/to a non-aligned
304 * position?
305 * from non-aligned: can fall back to rendering-based copy?
306 * to non-aligned: can fall back to rendering-based copy?
307 * XXX this goes wrong when source surface is supertiled.
308 */
309 if (util_blitter_is_copy_supported(ctx->blitter, dst, src)) {
310 etna_blit_save_state(ctx);
311 util_blitter_copy_texture(ctx->blitter, dst, dst_level, dstx, dsty, dstz,
312 src, src_level, src_box);
313 } else {
314 util_resource_copy_region(pctx, dst, dst_level, dstx, dsty, dstz, src,
315 src_level, src_box);
316 }
317 }
318
319 static bool
320 etna_manual_blit(struct etna_resource *dst, struct etna_resource_level *dst_lev,
321 unsigned int dst_offset, struct etna_resource *src,
322 struct etna_resource_level *src_lev, unsigned int src_offset,
323 const struct pipe_blit_info *blit_info)
324 {
325 void *smap, *srow, *dmap, *drow;
326 size_t tile_size;
327
328 assert(src->layout == ETNA_LAYOUT_TILED);
329 assert(dst->layout == ETNA_LAYOUT_TILED);
330 assert(src->base.nr_samples == 0);
331 assert(dst->base.nr_samples == 0);
332
333 tile_size = util_format_get_blocksize(blit_info->src.format) * 4 * 4;
334
335 smap = etna_bo_map(src->bo);
336 if (!smap)
337 return false;
338
339 dmap = etna_bo_map(dst->bo);
340 if (!dmap)
341 return false;
342
343 srow = smap + src_offset;
344 drow = dmap + dst_offset;
345
346 etna_bo_cpu_prep(src->bo, DRM_ETNA_PREP_READ);
347 etna_bo_cpu_prep(dst->bo, DRM_ETNA_PREP_WRITE);
348
349 for (int y = 0; y < blit_info->src.box.height; y += 4) {
350 memcpy(drow, srow, tile_size * blit_info->src.box.width);
351 srow += src_lev->stride * 4;
352 drow += dst_lev->stride * 4;
353 }
354
355 etna_bo_cpu_fini(dst->bo);
356 etna_bo_cpu_fini(src->bo);
357
358 return true;
359 }
360
361 static bool
362 etna_try_rs_blit(struct pipe_context *pctx,
363 const struct pipe_blit_info *blit_info)
364 {
365 struct etna_context *ctx = etna_context(pctx);
366 struct etna_resource *src = etna_resource(blit_info->src.resource);
367 struct etna_resource *dst = etna_resource(blit_info->dst.resource);
368 struct compiled_rs_state copy_to_screen;
369 uint32_t ts_mem_config = 0;
370 int msaa_xscale = 1, msaa_yscale = 1;
371
372 /* Ensure that the level is valid */
373 assert(blit_info->src.level <= src->base.last_level);
374 assert(blit_info->dst.level <= dst->base.last_level);
375
376 if (!translate_samples_to_xyscale(src->base.nr_samples, &msaa_xscale, &msaa_yscale, NULL))
377 return FALSE;
378
379 /* The width/height are in pixels; they do not change as a result of
380 * multi-sampling. So, when blitting from a 4x multisampled surface
381 * to a non-multisampled surface, the width and height will be
382 * identical. As we do not support scaling, reject different sizes. */
383 if (blit_info->dst.box.width != blit_info->src.box.width ||
384 blit_info->dst.box.height != blit_info->src.box.height) {
385 DBG("scaling requested: source %dx%d destination %dx%d",
386 blit_info->src.box.width, blit_info->src.box.height,
387 blit_info->dst.box.width, blit_info->dst.box.height);
388 return FALSE;
389 }
390
391 /* No masks - RS can't copy specific channels */
392 unsigned mask = util_format_get_mask(blit_info->dst.format);
393 if ((blit_info->mask & mask) != mask) {
394 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info->mask, mask);
395 return FALSE;
396 }
397
398 unsigned src_format = etna_compatible_rs_format(blit_info->src.format);
399 unsigned dst_format = etna_compatible_rs_format(blit_info->src.format);
400 if (translate_rs_format(src_format) == ETNA_NO_MATCH ||
401 translate_rs_format(dst_format) == ETNA_NO_MATCH ||
402 blit_info->scissor_enable || blit_info->src.box.x != 0 ||
403 blit_info->src.box.y != 0 || blit_info->dst.box.x != 0 ||
404 blit_info->dst.box.y != 0 ||
405 blit_info->dst.box.depth != blit_info->src.box.depth ||
406 blit_info->dst.box.depth != 1) {
407 return FALSE;
408 }
409
410 /* Ensure that the Z coordinate is sane */
411 if (dst->base.target != PIPE_TEXTURE_CUBE)
412 assert(blit_info->dst.box.z == 0);
413 if (src->base.target != PIPE_TEXTURE_CUBE)
414 assert(blit_info->src.box.z == 0);
415
416 assert(blit_info->src.box.z < src->base.array_size);
417 assert(blit_info->dst.box.z < dst->base.array_size);
418
419 struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
420 struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
421
422 /* we may be given coordinates up to the padded width to avoid
423 * any alignment issues with different tiling formats */
424 assert((blit_info->src.box.x + blit_info->src.box.width) * msaa_xscale <= src_lev->padded_width);
425 assert((blit_info->src.box.y + blit_info->src.box.height) * msaa_yscale <= src_lev->padded_height);
426 assert(blit_info->dst.box.x + blit_info->dst.box.width <= dst_lev->padded_width);
427 assert(blit_info->dst.box.y + blit_info->dst.box.height <= dst_lev->padded_height);
428
429 unsigned src_offset =
430 src_lev->offset + blit_info->src.box.z * src_lev->layer_stride;
431 unsigned dst_offset =
432 dst_lev->offset + blit_info->dst.box.z * dst_lev->layer_stride;
433
434 if (src_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
435 dst_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
436 src_lev->padded_height <= ETNA_RS_HEIGHT_MASK ||
437 dst_lev->padded_height <= ETNA_RS_HEIGHT_MASK)
438 goto manual;
439
440 /* If the width is not aligned to the RS width, but is within our
441 * padding, adjust the width to suite the RS width restriction.
442 * Note: the RS width/height are converted to source samples here. */
443 unsigned int width = blit_info->src.box.width * msaa_xscale;
444 unsigned int height = blit_info->src.box.height * msaa_yscale;
445 unsigned int w_align = ETNA_RS_WIDTH_MASK + 1;
446 unsigned int h_align = (ETNA_RS_HEIGHT_MASK + 1) * ctx->specs.pixel_pipes;
447
448 if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
449 width = align(width, w_align);
450
451 if (height & (h_align - 1) && height >= src_lev->height * msaa_yscale && height >= dst_lev->height)
452 height = align(height, h_align);
453
454 /* The padded dimensions are in samples */
455 if (width > src_lev->padded_width ||
456 width > dst_lev->padded_width * msaa_xscale ||
457 height > src_lev->padded_height ||
458 height > dst_lev->padded_height * msaa_yscale ||
459 width & (w_align - 1) || height & (h_align - 1))
460 goto manual;
461
462 if (src->base.nr_samples > 1) {
463 uint32_t msaa_format = translate_msaa_format(src_format);
464 assert(msaa_format != ETNA_NO_MATCH);
465 ts_mem_config |= VIVS_TS_MEM_CONFIG_MSAA | msaa_format;
466 }
467
468 /* Always flush color and depth cache together before resolving. This works
469 * around artifacts that appear in some cases when scanning out a texture
470 * directly after it has been rendered to, such as rendering an animated web
471 * page in a QtWebEngine based WebView on GC2000. The artifacts look like
472 * the texture sampler samples zeroes instead of texture data in a small,
473 * irregular triangle in the lower right of each browser tile quad. Other
474 * attempts to avoid these artifacts, including a pipeline stall before the
475 * color flush or a TS cache flush afterwards, or flushing multiple times,
476 * with stalls before and after each flush, have shown no effect. */
477 if (src->base.bind & PIPE_BIND_RENDER_TARGET ||
478 src->base.bind & PIPE_BIND_DEPTH_STENCIL) {
479 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
480 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
481 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
482 }
483
484 /* Set up color TS to source surface before blit, if needed */
485 if (src->levels[blit_info->src.level].ts_size &&
486 src->levels[blit_info->src.level].ts_valid) {
487 struct etna_reloc reloc;
488 unsigned ts_offset =
489 src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
490
491 etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG,
492 VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config);
493
494 memset(&reloc, 0, sizeof(struct etna_reloc));
495 reloc.bo = src->ts_bo;
496 reloc.offset = ts_offset;
497 reloc.flags = ETNA_RELOC_READ;
498 etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_STATUS_BASE, &reloc);
499
500 memset(&reloc, 0, sizeof(struct etna_reloc));
501 reloc.bo = src->bo;
502 reloc.offset = src_offset;
503 reloc.flags = ETNA_RELOC_READ;
504 etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_SURFACE_BASE, &reloc);
505
506 etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE,
507 src->levels[blit_info->src.level].clear_value);
508 } else {
509 etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, ts_mem_config);
510 }
511 ctx->dirty |= ETNA_DIRTY_TS;
512
513 /* Kick off RS here */
514 etna_compile_rs_state(ctx, &copy_to_screen, &(struct rs_state) {
515 .source_format = translate_rs_format(src_format),
516 .source_tiling = src->layout,
517 .source = src->bo,
518 .source_offset = src_offset,
519 .source_stride = src_lev->stride,
520 .source_padded_height = src_lev->padded_height,
521 .dest_format = translate_rs_format(dst_format),
522 .dest_tiling = dst->layout,
523 .dest = dst->bo,
524 .dest_offset = dst_offset,
525 .dest_stride = dst_lev->stride,
526 .dest_padded_height = dst_lev->padded_height,
527 .downsample_x = msaa_xscale > 1,
528 .downsample_y = msaa_yscale > 1,
529 .swap_rb = translate_rb_src_dst_swap(src->base.format, dst->base.format),
530 .dither = {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
531 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
532 .width = width,
533 .height = height
534 });
535
536 etna_submit_rs_state(ctx, &copy_to_screen);
537 resource_written(ctx, &dst->base);
538 dst->seqno++;
539 dst->levels[blit_info->dst.level].ts_valid = false;
540
541 return TRUE;
542
543 manual:
544 if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) {
545 if ((src->status & ETNA_PENDING_WRITE) ||
546 (dst->status & ETNA_PENDING_WRITE))
547 pctx->flush(pctx, NULL, 0);
548 return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info);
549 }
550
551 return FALSE;
552 }
553
554 static void
555 etna_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
556 {
557 /* This is a more extended version of resource_copy_region */
558 /* TODO Some cases can be handled by RS; if not, fall back to rendering or
559 * even CPU copy block of pixels from info->src to info->dst
560 * (resource, level, box, format);
561 * function is used for scaling, flipping in x and y direction (negative
562 * width/height), format conversion, mask and filter and even a scissor rectangle
563 *
564 * What can the RS do for us:
565 * convert between tiling formats (layouts)
566 * downsample 2x in x and y
567 * convert between a limited number of pixel formats
568 *
569 * For the rest, fall back to util_blitter
570 * XXX this goes wrong when source surface is supertiled. */
571 struct etna_context *ctx = etna_context(pctx);
572 struct pipe_blit_info info = *blit_info;
573
574 if (info.src.resource->nr_samples > 1 &&
575 info.dst.resource->nr_samples <= 1 &&
576 !util_format_is_depth_or_stencil(info.src.resource->format) &&
577 !util_format_is_pure_integer(info.src.resource->format)) {
578 DBG("color resolve unimplemented");
579 return;
580 }
581
582 if (etna_try_rs_blit(pctx, blit_info))
583 return;
584
585 if (util_try_blit_via_copy_region(pctx, blit_info))
586 return;
587
588 if (info.mask & PIPE_MASK_S) {
589 DBG("cannot blit stencil, skipping");
590 info.mask &= ~PIPE_MASK_S;
591 }
592
593 if (!util_blitter_is_blit_supported(ctx->blitter, &info)) {
594 DBG("blit unsupported %s -> %s",
595 util_format_short_name(info.src.resource->format),
596 util_format_short_name(info.dst.resource->format));
597 return;
598 }
599
600 etna_blit_save_state(ctx);
601 util_blitter_blit(ctx->blitter, &info);
602 }
603
604 static void
605 etna_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
606 {
607 struct etna_resource *rsc = etna_resource(prsc);
608
609 if (rsc->scanout) {
610 if (etna_resource_older(etna_resource(rsc->scanout->prime), rsc)) {
611 etna_copy_resource(pctx, rsc->scanout->prime, prsc, 0, 0);
612 etna_resource(rsc->scanout->prime)->seqno = rsc->seqno;
613 }
614 } else if (etna_resource_needs_flush(rsc)) {
615 etna_copy_resource(pctx, prsc, prsc, 0, 0);
616 rsc->flush_seqno = rsc->seqno;
617 }
618 }
619
620 void
621 etna_copy_resource(struct pipe_context *pctx, struct pipe_resource *dst,
622 struct pipe_resource *src, int first_level, int last_level)
623 {
624 struct etna_resource *src_priv = etna_resource(src);
625 struct etna_resource *dst_priv = etna_resource(dst);
626
627 assert(src->format == dst->format);
628 assert(src->array_size == dst->array_size);
629 assert(last_level <= dst->last_level && last_level <= src->last_level);
630
631 struct pipe_blit_info blit = {};
632 blit.mask = util_format_get_mask(dst->format);
633 blit.filter = PIPE_TEX_FILTER_NEAREST;
634 blit.src.resource = src;
635 blit.src.format = src->format;
636 blit.dst.resource = dst;
637 blit.dst.format = dst->format;
638 blit.dst.box.depth = blit.src.box.depth = 1;
639
640 /* Copy each level and each layer */
641 for (int level = first_level; level <= last_level; level++) {
642 blit.src.level = blit.dst.level = level;
643 blit.src.box.width = blit.dst.box.width =
644 MIN2(src_priv->levels[level].padded_width, dst_priv->levels[level].padded_width);
645 blit.src.box.height = blit.dst.box.height =
646 MIN2(src_priv->levels[level].padded_height, dst_priv->levels[level].padded_height);
647
648 for (int layer = 0; layer < dst->array_size; layer++) {
649 blit.src.box.z = blit.dst.box.z = layer;
650 pctx->blit(pctx, &blit);
651 }
652 }
653 }
654
655 void
656 etna_clear_blit_init(struct pipe_context *pctx)
657 {
658 pctx->clear = etna_clear;
659 pctx->clear_render_target = etna_clear_render_target;
660 pctx->clear_depth_stencil = etna_clear_depth_stencil;
661 pctx->resource_copy_region = etna_resource_copy_region;
662 pctx->blit = etna_blit;
663 pctx->flush_resource = etna_flush_resource;
664 }