src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c

   1 /*
   2  * Copyright (c) 2012-2019 Etnaviv Project
   3  * Copyright (c) 2019 Zodiac Inflight Innovations
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jonathan Marek <jonathan@marek.ca>
  26  *    Wladimir J. van der Laan <laanwj@gmail.com>
  27  */
  28
  29 #include "etnaviv_compiler.h"
  30 #include "etnaviv_compiler_nir.h"
  31 #include "etnaviv_asm.h"
  32 #include "etnaviv_context.h"
  33 #include "etnaviv_debug.h"
  34 #include "etnaviv_disasm.h"
  35 #include "etnaviv_nir.h"
  36 #include "etnaviv_uniforms.h"
  37 #include "etnaviv_util.h"
  38
  39 #include <math.h>
  40 #include "util/u_memory.h"
  41 #include "util/register_allocate.h"
  42 #include "compiler/nir/nir_builder.h"
  43
  44 #include "tgsi/tgsi_strings.h"
  45 #include "util/u_half.h"
  46
  47 struct etna_compile {
  48    nir_shader *nir;
  49 #define is_fs(c) ((c)->nir->info.stage == MESA_SHADER_FRAGMENT)
  50    const struct etna_specs *specs;
  51    struct etna_shader_variant *variant;
  52
  53    /* block # to instr index */
  54    unsigned *block_ptr;
  55
  56    /* Code generation */
  57    int inst_ptr; /* current instruction pointer */
  58    struct etna_inst code[ETNA_MAX_INSTRUCTIONS * ETNA_INST_SIZE];
  59
  60    /* constants */
  61    uint64_t consts[ETNA_MAX_IMM];
  62
  63    /* There was an error during compilation */
  64    bool error;
  65 };
  66
  67
  68
  69 static bool
  70 etna_alu_to_scalar_filter_cb(const nir_instr *instr, const void *data)
  71 {
  72    const struct etna_specs *specs = data;
  73
  74    if (instr->type != nir_instr_type_alu)
  75       return false;
  76
  77    nir_alu_instr *alu = nir_instr_as_alu(instr);
  78    switch (alu->op) {
  79    case nir_op_frsq:
  80    case nir_op_frcp:
  81    case nir_op_flog2:
  82    case nir_op_fexp2:
  83    case nir_op_fsqrt:
  84    case nir_op_fcos:
  85    case nir_op_fsin:
  86    case nir_op_fdiv:
  87    case nir_op_imul:
  88       return true;
  89    /* TODO: can do better than alu_to_scalar for vector compares */
  90    case nir_op_b32all_fequal2:
  91    case nir_op_b32all_fequal3:
  92    case nir_op_b32all_fequal4:
  93    case nir_op_b32any_fnequal2:
  94    case nir_op_b32any_fnequal3:
  95    case nir_op_b32any_fnequal4:
  96    case nir_op_b32all_iequal2:
  97    case nir_op_b32all_iequal3:
  98    case nir_op_b32all_iequal4:
  99    case nir_op_b32any_inequal2:
 100    case nir_op_b32any_inequal3:
 101    case nir_op_b32any_inequal4:
 102       return true;
 103    case nir_op_fdot2:
 104       if (!specs->has_halti2_instructions)
 105          return true;
 106       break;
 107    default:
 108       break;
 109    }
 110
 111    return false;
 112 }
 113
 114 static void
 115 emit_inst(struct etna_compile *c, struct etna_inst *inst)
 116 {
 117    c->code[c->inst_ptr++] = *inst;
 118 }
 119
 120 /* to map nir srcs should to etna_inst srcs */
 121 enum {
 122    SRC_0_1_2 = (0 << 0) | (1 << 2) | (2 << 4),
 123    SRC_0_1_X = (0 << 0) | (1 << 2) | (3 << 4),
 124    SRC_0_X_X = (0 << 0) | (3 << 2) | (3 << 4),
 125    SRC_0_X_1 = (0 << 0) | (3 << 2) | (1 << 4),
 126    SRC_0_1_0 = (0 << 0) | (1 << 2) | (0 << 4),
 127    SRC_X_X_0 = (3 << 0) | (3 << 2) | (0 << 4),
 128    SRC_0_X_0 = (0 << 0) | (3 << 2) | (0 << 4),
 129 };
 130
 131 /* info to translate a nir op to etna_inst */
 132 struct etna_op_info {
 133    uint8_t opcode; /* INST_OPCODE_ */
 134    uint8_t src; /* SRC_ enum  */
 135    uint8_t cond; /* INST_CONDITION_ */
 136    uint8_t type; /* INST_TYPE_ */
 137 };
 138
 139 static const struct etna_op_info etna_ops[] = {
 140    [0 ... nir_num_opcodes - 1] = {0xff},
 141 #undef TRUE
 142 #undef FALSE
 143 #define OPCT(nir, op, src, cond, type) [nir_op_##nir] = { \
 144    INST_OPCODE_##op, \
 145    SRC_##src, \
 146    INST_CONDITION_##cond, \
 147    INST_TYPE_##type \
 148 }
 149 #define OPC(nir, op, src, cond) OPCT(nir, op, src, cond, F32)
 150 #define IOPC(nir, op, src, cond) OPCT(nir, op, src, cond, S32)
 151 #define UOPC(nir, op, src, cond) OPCT(nir, op, src, cond, U32)
 152 #define OP(nir, op, src) OPC(nir, op, src, TRUE)
 153 #define IOP(nir, op, src) IOPC(nir, op, src, TRUE)
 154 #define UOP(nir, op, src) UOPC(nir, op, src, TRUE)
 155    OP(mov, MOV, X_X_0), OP(fneg, MOV, X_X_0), OP(fabs, MOV, X_X_0), OP(fsat, MOV, X_X_0),
 156    OP(fmul, MUL, 0_1_X), OP(fadd, ADD, 0_X_1), OP(ffma, MAD, 0_1_2),
 157    OP(fdot2, DP2, 0_1_X), OP(fdot3, DP3, 0_1_X), OP(fdot4, DP4, 0_1_X),
 158    OPC(fmin, SELECT, 0_1_0, GT), OPC(fmax, SELECT, 0_1_0, LT),
 159    OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
 160    OP(fsqrt, SQRT, X_X_0), OP(fsin, SIN, X_X_0), OP(fcos, COS, X_X_0),
 161    OP(fsign, SIGN, X_X_0), OP(ffloor, FLOOR, X_X_0), OP(fceil, CEIL, X_X_0),
 162    OP(flog2, LOG, X_X_0), OP(fexp2, EXP, X_X_0),
 163    OPC(seq, SET, 0_1_X, EQ), OPC(sne, SET, 0_1_X, NE), OPC(sge, SET, 0_1_X, GE), OPC(slt, SET, 0_1_X, LT),
 164    OPC(fcsel, SELECT, 0_1_2, NZ),
 165    OP(fdiv, DIV, 0_1_X),
 166    OP(fddx, DSX, 0_X_0), OP(fddy, DSY, 0_X_0),
 167
 168    /* type convert */
 169    IOP(i2f32, I2F, 0_X_X),
 170    UOP(u2f32, I2F, 0_X_X),
 171    IOP(f2i32, F2I, 0_X_X),
 172    UOP(f2u32, F2I, 0_X_X),
 173    UOP(b2f32, AND, 0_X_X), /* AND with fui(1.0f) */
 174    UOP(b2i32, AND, 0_X_X), /* AND with 1 */
 175    OPC(f2b32, CMP, 0_X_X, NE), /* != 0.0 */
 176    UOPC(i2b32, CMP, 0_X_X, NE), /* != 0 */
 177
 178    /* arithmetic */
 179    IOP(iadd, ADD, 0_X_1),
 180    IOP(imul, IMULLO0, 0_1_X),
 181    /* IOP(imad, IMADLO0, 0_1_2), */
 182    IOP(ineg, ADD, X_X_0), /* ADD 0, -x */
 183    IOP(iabs, IABS, X_X_0),
 184    IOP(isign, SIGN, X_X_0),
 185    IOPC(imin, SELECT, 0_1_0, GT),
 186    IOPC(imax, SELECT, 0_1_0, LT),
 187    UOPC(umin, SELECT, 0_1_0, GT),
 188    UOPC(umax, SELECT, 0_1_0, LT),
 189
 190    /* select */
 191    UOPC(b32csel, SELECT, 0_1_2, NZ),
 192
 193    /* compare with int result */
 194     OPC(feq32, CMP, 0_1_X, EQ),
 195     OPC(fne32, CMP, 0_1_X, NE),
 196     OPC(fge32, CMP, 0_1_X, GE),
 197     OPC(flt32, CMP, 0_1_X, LT),
 198    IOPC(ieq32, CMP, 0_1_X, EQ),
 199    IOPC(ine32, CMP, 0_1_X, NE),
 200    IOPC(ige32, CMP, 0_1_X, GE),
 201    IOPC(ilt32, CMP, 0_1_X, LT),
 202    UOPC(uge32, CMP, 0_1_X, GE),
 203    UOPC(ult32, CMP, 0_1_X, LT),
 204
 205    /* bit ops */
 206    IOP(ior,  OR,  0_X_1),
 207    IOP(iand, AND, 0_X_1),
 208    IOP(ixor, XOR, 0_X_1),
 209    IOP(inot, NOT, X_X_0),
 210    IOP(ishl, LSHIFT, 0_X_1),
 211    IOP(ishr, RSHIFT, 0_X_1),
 212    UOP(ushr, RSHIFT, 0_X_1),
 213 };
 214
 215 static void
 216 etna_emit_block_start(struct etna_compile *c, unsigned block)
 217 {
 218    c->block_ptr[block] = c->inst_ptr;
 219 }
 220
 221 static void
 222 etna_emit_alu(struct etna_compile *c, nir_op op, struct etna_inst_dst dst,
 223               struct etna_inst_src src[3], bool saturate)
 224 {
 225    struct etna_op_info ei = etna_ops[op];
 226    unsigned swiz_scalar = INST_SWIZ_BROADCAST(ffs(dst.write_mask) - 1);
 227
 228    if (ei.opcode == 0xff)
 229       compile_error(c, "Unhandled ALU op: %s\n", nir_op_infos[op].name);
 230
 231    struct etna_inst inst = {
 232       .opcode = ei.opcode,
 233       .type = ei.type,
 234       .cond = ei.cond,
 235       .dst = dst,
 236       .sat = saturate,
 237    };
 238
 239    switch (op) {
 240    case nir_op_fdiv:
 241    case nir_op_flog2:
 242    case nir_op_fsin:
 243    case nir_op_fcos:
 244       if (c->specs->has_new_transcendentals)
 245          inst.tex.amode = 1;
 246       /* fall through */
 247    case nir_op_frsq:
 248    case nir_op_frcp:
 249    case nir_op_fexp2:
 250    case nir_op_fsqrt:
 251    case nir_op_imul:
 252       /* scalar instructions we want src to be in x component */
 253       src[0].swiz = inst_swiz_compose(src[0].swiz, swiz_scalar);
 254       src[1].swiz = inst_swiz_compose(src[1].swiz, swiz_scalar);
 255       break;
 256    /* deal with instructions which don't have 1:1 mapping */
 257    case nir_op_b2f32:
 258       inst.src[2] = etna_immediate_float(1.0f);
 259       break;
 260    case nir_op_b2i32:
 261       inst.src[2] = etna_immediate_int(1);
 262       break;
 263    case nir_op_f2b32:
 264       inst.src[1] = etna_immediate_float(0.0f);
 265       break;
 266    case nir_op_i2b32:
 267       inst.src[1] = etna_immediate_int(0);
 268       break;
 269    case nir_op_ineg:
 270       inst.src[0] = etna_immediate_int(0);
 271       src[0].neg = 1;
 272       break;
 273    default:
 274       break;
 275    }
 276
 277    /* set the "true" value for CMP instructions */
 278    if (inst.opcode == INST_OPCODE_CMP)
 279       inst.src[2] = etna_immediate_int(-1);
 280
 281    for (unsigned j = 0; j < 3; j++) {
 282       unsigned i = ((ei.src >> j*2) & 3);
 283       if (i < 3)
 284          inst.src[j] = src[i];
 285    }
 286
 287    emit_inst(c, &inst);
 288 }
 289
 290 static void
 291 etna_emit_tex(struct etna_compile *c, nir_texop op, unsigned texid, unsigned dst_swiz,
 292               struct etna_inst_dst dst, struct etna_inst_src coord,
 293               struct etna_inst_src lod_bias, struct etna_inst_src compare)
 294 {
 295    struct etna_inst inst = {
 296       .dst = dst,
 297       .tex.id = texid + (is_fs(c) ? 0 : c->specs->vertex_sampler_offset),
 298       .tex.swiz = dst_swiz,
 299       .src[0] = coord,
 300    };
 301
 302    if (lod_bias.use)
 303       inst.src[1] = lod_bias;
 304
 305    if (compare.use)
 306       inst.src[2] = compare;
 307
 308    switch (op) {
 309    case nir_texop_tex: inst.opcode = INST_OPCODE_TEXLD; break;
 310    case nir_texop_txb: inst.opcode = INST_OPCODE_TEXLDB; break;
 311    case nir_texop_txl: inst.opcode = INST_OPCODE_TEXLDL; break;
 312    default:
 313       compile_error(c, "Unhandled NIR tex type: %d\n", op);
 314    }
 315
 316    emit_inst(c, &inst);
 317 }
 318
 319 static void
 320 etna_emit_jump(struct etna_compile *c, unsigned block, struct etna_inst_src condition)
 321 {
 322    if (!condition.use) {
 323       emit_inst(c, &(struct etna_inst) {.opcode = INST_OPCODE_BRANCH, .imm = block });
 324       return;
 325    }
 326
 327    struct etna_inst inst = {
 328       .opcode = INST_OPCODE_BRANCH,
 329       .cond = INST_CONDITION_NOT,
 330       .type = INST_TYPE_U32,
 331       .src[0] = condition,
 332       .imm = block,
 333    };
 334    inst.src[0].swiz = INST_SWIZ_BROADCAST(inst.src[0].swiz & 3);
 335    emit_inst(c, &inst);
 336 }
 337
 338 static void
 339 etna_emit_discard(struct etna_compile *c, struct etna_inst_src condition)
 340 {
 341    if (!condition.use) {
 342       emit_inst(c, &(struct etna_inst) { .opcode = INST_OPCODE_TEXKILL });
 343       return;
 344    }
 345
 346    struct etna_inst inst = {
 347       .opcode = INST_OPCODE_TEXKILL,
 348       .cond = INST_CONDITION_NZ,
 349       .type = (c->specs->halti < 2) ? INST_TYPE_F32 : INST_TYPE_U32,
 350       .src[0] = condition,
 351    };
 352    inst.src[0].swiz = INST_SWIZ_BROADCAST(inst.src[0].swiz & 3);
 353    emit_inst(c, &inst);
 354 }
 355
 356 static void
 357 etna_emit_output(struct etna_compile *c, nir_variable *var, struct etna_inst_src src)
 358 {
 359    struct etna_shader_io_file *sf = &c->variant->outfile;
 360
 361    if (is_fs(c)) {
 362       switch (var->data.location) {
 363       case FRAG_RESULT_COLOR:
 364       case FRAG_RESULT_DATA0: /* DATA0 is used by gallium shaders for color */
 365          c->variant->ps_color_out_reg = src.reg;
 366          break;
 367       case FRAG_RESULT_DEPTH:
 368          c->variant->ps_depth_out_reg = src.reg;
 369          break;
 370       default:
 371          unreachable("Unsupported fs output");
 372       }
 373       return;
 374    }
 375
 376    switch (var->data.location) {
 377    case VARYING_SLOT_POS:
 378       c->variant->vs_pos_out_reg = src.reg;
 379       break;
 380    case VARYING_SLOT_PSIZ:
 381       c->variant->vs_pointsize_out_reg = src.reg;
 382       break;
 383    default:
 384       sf->reg[sf->num_reg].reg = src.reg;
 385       sf->reg[sf->num_reg].slot = var->data.location;
 386       sf->reg[sf->num_reg].num_components = glsl_get_components(var->type);
 387       sf->num_reg++;
 388       break;
 389    }
 390 }
 391
 392 #define OPT(nir, pass, ...) ({                             \
 393    bool this_progress = false;                             \
 394    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 395    this_progress;                                          \
 396 })
 397
 398 static void
 399 etna_optimize_loop(nir_shader *s)
 400 {
 401    bool progress;
 402    do {
 403       progress = false;
 404
 405       NIR_PASS_V(s, nir_lower_vars_to_ssa);
 406       progress |= OPT(s, nir_opt_copy_prop_vars);
 407       progress |= OPT(s, nir_copy_prop);
 408       progress |= OPT(s, nir_opt_dce);
 409       progress |= OPT(s, nir_opt_cse);
 410       progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 411       progress |= OPT(s, nir_opt_intrinsics);
 412       progress |= OPT(s, nir_opt_algebraic);
 413       progress |= OPT(s, nir_opt_constant_folding);
 414       progress |= OPT(s, nir_opt_dead_cf);
 415       if (OPT(s, nir_opt_trivial_continues)) {
 416          progress = true;
 417          /* If nir_opt_trivial_continues makes progress, then we need to clean
 418           * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 419           * to make progress.
 420           */
 421          OPT(s, nir_copy_prop);
 422          OPT(s, nir_opt_dce);
 423       }
 424       progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
 425       progress |= OPT(s, nir_opt_if, false);
 426       progress |= OPT(s, nir_opt_remove_phis);
 427       progress |= OPT(s, nir_opt_undef);
 428    }
 429    while (progress);
 430 }
 431
 432 static int
 433 etna_glsl_type_size(const struct glsl_type *type, bool bindless)
 434 {
 435    return glsl_count_attribute_slots(type, false);
 436 }
 437
 438 static void
 439 copy_uniform_state_to_shader(struct etna_shader_variant *sobj, uint64_t *consts, unsigned count)
 440 {
 441    struct etna_shader_uniform_info *uinfo = &sobj->uniforms;
 442
 443    uinfo->imm_count = count * 4;
 444    uinfo->imm_data = MALLOC(uinfo->imm_count * sizeof(*uinfo->imm_data));
 445    uinfo->imm_contents = MALLOC(uinfo->imm_count * sizeof(*uinfo->imm_contents));
 446
 447    for (unsigned i = 0; i < uinfo->imm_count; i++) {
 448       uinfo->imm_data[i] = consts[i];
 449       uinfo->imm_contents[i] = consts[i] >> 32;
 450    }
 451
 452    etna_set_shader_uniforms_dirty_flags(sobj);
 453 }
 454
 455 #include "etnaviv_compiler_nir_emit.h"
 456
 457 static bool
 458 etna_compile_check_limits(struct etna_shader_variant *v)
 459 {
 460    const struct etna_specs *specs = v->shader->specs;
 461    int max_uniforms = (v->stage == MESA_SHADER_VERTEX)
 462                          ? specs->max_vs_uniforms
 463                          : specs->max_ps_uniforms;
 464
 465    if (!specs->has_icache && v->needs_icache) {
 466       DBG("Number of instructions (%d) exceeds maximum %d", v->code_size / 4,
 467           specs->max_instructions);
 468       return false;
 469    }
 470
 471    if (v->num_temps > specs->max_registers) {
 472       DBG("Number of registers (%d) exceeds maximum %d", v->num_temps,
 473           specs->max_registers);
 474       return false;
 475    }
 476
 477    if (v->uniforms.imm_count / 4 > max_uniforms) {
 478       DBG("Number of uniforms (%d) exceeds maximum %d",
 479           v->uniforms.imm_count / 4, max_uniforms);
 480       return false;
 481    }
 482
 483    return true;
 484 }
 485
 486 static void
 487 fill_vs_mystery(struct etna_shader_variant *v)
 488 {
 489    const struct etna_specs *specs = v->shader->specs;
 490
 491    v->input_count_unk8 = DIV_ROUND_UP(v->infile.num_reg + 4, 16); /* XXX what is this */
 492
 493    /* fill in "mystery meat" load balancing value. This value determines how
 494     * work is scheduled between VS and PS
 495     * in the unified shader architecture. More precisely, it is determined from
 496     * the number of VS outputs, as well as chip-specific
 497     * vertex output buffer size, vertex cache size, and the number of shader
 498     * cores.
 499     *
 500     * XXX this is a conservative estimate, the "optimal" value is only known for
 501     * sure at link time because some
 502     * outputs may be unused and thus unmapped. Then again, in the general use
 503     * case with GLSL the vertex and fragment
 504     * shaders are linked already before submitting to Gallium, thus all outputs
 505     * are used.
 506     *
 507     * note: TGSI compiler counts all outputs (including position and pointsize), here
 508     * v->outfile.num_reg only counts varyings, +1 to compensate for the position output
 509     * TODO: might have a problem that we don't count pointsize when it is used
 510     */
 511
 512    int half_out = v->outfile.num_reg / 2 + 1;
 513    assert(half_out);
 514
 515    uint32_t b = ((20480 / (specs->vertex_output_buffer_size -
 516                            2 * half_out * specs->vertex_cache_size)) +
 517                  9) /
 518                 10;
 519    uint32_t a = (b + 256 / (specs->shader_core_count * half_out)) / 2;
 520    v->vs_load_balancing = VIVS_VS_LOAD_BALANCING_A(MIN2(a, 255)) |
 521                              VIVS_VS_LOAD_BALANCING_B(MIN2(b, 255)) |
 522                              VIVS_VS_LOAD_BALANCING_C(0x3f) |
 523                              VIVS_VS_LOAD_BALANCING_D(0x0f);
 524 }
 525
 526 bool
 527 etna_compile_shader_nir(struct etna_shader_variant *v)
 528 {
 529    if (unlikely(!v))
 530       return false;
 531
 532    struct etna_compile *c = CALLOC_STRUCT(etna_compile);
 533    if (!c)
 534       return false;
 535
 536    c->variant = v;
 537    c->specs = v->shader->specs;
 538    c->nir = nir_shader_clone(NULL, v->shader->nir);
 539
 540    nir_shader *s = c->nir;
 541    const struct etna_specs *specs = c->specs;
 542
 543    v->stage = s->info.stage;
 544    v->num_loops = 0; /* TODO */
 545    v->vs_id_in_reg = -1;
 546    v->vs_pos_out_reg = -1;
 547    v->vs_pointsize_out_reg = -1;
 548    v->ps_color_out_reg = 0; /* 0 for shader that doesn't write fragcolor.. */
 549    v->ps_depth_out_reg = -1;
 550
 551    /* setup input linking */
 552    struct etna_shader_io_file *sf = &v->infile;
 553    if (s->info.stage == MESA_SHADER_VERTEX) {
 554       nir_foreach_variable(var, &s->inputs) {
 555          unsigned idx = var->data.driver_location;
 556          sf->reg[idx].reg = idx;
 557          sf->reg[idx].slot = var->data.location;
 558          sf->reg[idx].num_components = glsl_get_components(var->type);
 559          sf->num_reg = MAX2(sf->num_reg, idx+1);
 560       }
 561    } else {
 562       unsigned count = 0;
 563       nir_foreach_variable(var, &s->inputs) {
 564          unsigned idx = var->data.driver_location;
 565          sf->reg[idx].reg = idx + 1;
 566          sf->reg[idx].slot = var->data.location;
 567          sf->reg[idx].num_components = glsl_get_components(var->type);
 568          sf->num_reg = MAX2(sf->num_reg, idx+1);
 569          count++;
 570       }
 571       assert(sf->num_reg == count);
 572    }
 573
 574    NIR_PASS_V(s, nir_lower_io, ~nir_var_shader_out, etna_glsl_type_size,
 575             (nir_lower_io_options)0);
 576
 577    NIR_PASS_V(s, nir_lower_regs_to_ssa);
 578    NIR_PASS_V(s, nir_lower_vars_to_ssa);
 579    NIR_PASS_V(s, nir_lower_indirect_derefs, nir_var_all);
 580    NIR_PASS_V(s, nir_lower_tex, &(struct nir_lower_tex_options) { .lower_txp = ~0u });
 581    NIR_PASS_V(s, nir_lower_alu_to_scalar, etna_alu_to_scalar_filter_cb, specs);
 582
 583    etna_optimize_loop(s);
 584
 585    NIR_PASS_V(s, etna_lower_io, v);
 586
 587    if (v->shader->specs->vs_need_z_div)
 588       NIR_PASS_V(s, nir_lower_clip_halfz);
 589
 590    /* lower pre-halti2 to float (halti0 has integers, but only scalar..) */
 591    if (c->specs->halti < 2) {
 592       /* use opt_algebraic between int_to_float and boot_to_float because
 593        * int_to_float emits ftrunc, and ftrunc lowering generates bool ops
 594        */
 595       NIR_PASS_V(s, nir_lower_int_to_float);
 596       NIR_PASS_V(s, nir_opt_algebraic);
 597       NIR_PASS_V(s, nir_lower_bool_to_float);
 598    } else {
 599       NIR_PASS_V(s, nir_lower_idiv, nir_lower_idiv_fast);
 600       NIR_PASS_V(s, nir_lower_bool_to_int32);
 601    }
 602
 603    etna_optimize_loop(s);
 604
 605    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
 606       nir_print_shader(s, stdout);
 607
 608    while( OPT(s, nir_opt_vectorize) );
 609    NIR_PASS_V(s, nir_lower_alu_to_scalar, etna_alu_to_scalar_filter_cb, specs);
 610
 611    NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
 612    NIR_PASS_V(s, nir_opt_algebraic_late);
 613
 614    NIR_PASS_V(s, nir_move_vec_src_uses_to_dest);
 615    NIR_PASS_V(s, nir_copy_prop);
 616    /* only HW supported integer source mod is ineg for iadd instruction (?) */
 617    NIR_PASS_V(s, nir_lower_to_source_mods, ~nir_lower_int_source_mods);
 618    /* need copy prop after uses_to_dest, and before src mods: see
 619     * dEQP-GLES2.functional.shaders.random.all_features.fragment.95
 620     */
 621
 622    NIR_PASS_V(s, nir_opt_dce);
 623
 624    NIR_PASS_V(s, etna_lower_alu, c->specs->has_new_transcendentals);
 625
 626    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
 627       nir_print_shader(s, stdout);
 628
 629    unsigned block_ptr[nir_shader_get_entrypoint(s)->num_blocks];
 630    c->block_ptr = block_ptr;
 631
 632    unsigned num_consts;
 633    ASSERTED bool ok = emit_shader(c, &v->num_temps, &num_consts);
 634    assert(ok);
 635
 636    /* empty shader, emit NOP */
 637    if (!c->inst_ptr)
 638       emit_inst(c, &(struct etna_inst) { .opcode = INST_OPCODE_NOP });
 639
 640    /* assemble instructions, fixing up labels */
 641    uint32_t *code = MALLOC(c->inst_ptr * 16);
 642    for (unsigned i = 0; i < c->inst_ptr; i++) {
 643       struct etna_inst *inst = &c->code[i];
 644       if (inst->opcode == INST_OPCODE_BRANCH)
 645          inst->imm = block_ptr[inst->imm];
 646
 647       inst->halti5 = specs->halti >= 5;
 648       etna_assemble(&code[i * 4], inst);
 649    }
 650
 651    v->code_size = c->inst_ptr * 4;
 652    v->code = code;
 653    v->needs_icache = c->inst_ptr > specs->max_instructions;
 654
 655    copy_uniform_state_to_shader(v, c->consts, num_consts);
 656
 657    if (s->info.stage == MESA_SHADER_FRAGMENT) {
 658       v->input_count_unk8 = 31; /* XXX what is this */
 659       assert(v->ps_depth_out_reg <= 0);
 660    } else {
 661       fill_vs_mystery(v);
 662    }
 663
 664    bool result = etna_compile_check_limits(v);
 665    ralloc_free(c->nir);
 666    FREE(c);
 667    return result;
 668 }
 669
 670 void
 671 etna_destroy_shader_nir(struct etna_shader_variant *shader)
 672 {
 673    assert(shader);
 674
 675    FREE(shader->code);
 676    FREE(shader->uniforms.imm_data);
 677    FREE(shader->uniforms.imm_contents);
 678    FREE(shader);
 679 }
 680
 681 extern const char *tgsi_swizzle_names[];
 682 void
 683 etna_dump_shader_nir(const struct etna_shader_variant *shader)
 684 {
 685    if (shader->stage == MESA_SHADER_VERTEX)
 686       printf("VERT\n");
 687    else
 688       printf("FRAG\n");
 689
 690    etna_disasm(shader->code, shader->code_size, PRINT_RAW);
 691
 692    printf("num loops: %i\n", shader->num_loops);
 693    printf("num temps: %i\n", shader->num_temps);
 694    printf("immediates:\n");
 695    for (int idx = 0; idx < shader->uniforms.imm_count; ++idx) {
 696       printf(" [%i].%s = %f (0x%08x) (%d)\n",
 697              idx / 4,
 698              tgsi_swizzle_names[idx % 4],
 699              *((float *)&shader->uniforms.imm_data[idx]),
 700              shader->uniforms.imm_data[idx],
 701              shader->uniforms.imm_contents[idx]);
 702    }
 703    printf("inputs:\n");
 704    for (int idx = 0; idx < shader->infile.num_reg; ++idx) {
 705       printf(" [%i] name=%s comps=%i\n", shader->infile.reg[idx].reg,
 706                (shader->stage == MESA_SHADER_VERTEX) ?
 707                gl_vert_attrib_name(shader->infile.reg[idx].slot) :
 708                gl_varying_slot_name(shader->infile.reg[idx].slot),
 709                shader->infile.reg[idx].num_components);
 710    }
 711    printf("outputs:\n");
 712    for (int idx = 0; idx < shader->outfile.num_reg; ++idx) {
 713       printf(" [%i] name=%s comps=%i\n", shader->outfile.reg[idx].reg,
 714                (shader->stage == MESA_SHADER_VERTEX) ?
 715                gl_varying_slot_name(shader->outfile.reg[idx].slot) :
 716                gl_frag_result_name(shader->outfile.reg[idx].slot),
 717                shader->outfile.reg[idx].num_components);
 718    }
 719    printf("special:\n");
 720    if (shader->stage == MESA_SHADER_VERTEX) {
 721       printf("  vs_pos_out_reg=%i\n", shader->vs_pos_out_reg);
 722       printf("  vs_pointsize_out_reg=%i\n", shader->vs_pointsize_out_reg);
 723       printf("  vs_load_balancing=0x%08x\n", shader->vs_load_balancing);
 724    } else {
 725       printf("  ps_color_out_reg=%i\n", shader->ps_color_out_reg);
 726       printf("  ps_depth_out_reg=%i\n", shader->ps_depth_out_reg);
 727    }
 728    printf("  input_count_unk8=0x%08x\n", shader->input_count_unk8);
 729 }
 730
 731 static const struct etna_shader_inout *
 732 etna_shader_vs_lookup(const struct etna_shader_variant *sobj,
 733                       const struct etna_shader_inout *in)
 734 {
 735    for (int i = 0; i < sobj->outfile.num_reg; i++)
 736       if (sobj->outfile.reg[i].slot == in->slot)
 737          return &sobj->outfile.reg[i];
 738
 739    return NULL;
 740 }
 741
 742 bool
 743 etna_link_shader_nir(struct etna_shader_link_info *info,
 744                      const struct etna_shader_variant *vs,
 745                      const struct etna_shader_variant *fs)
 746 {
 747    int comp_ofs = 0;
 748    /* For each fragment input we need to find the associated vertex shader
 749     * output, which can be found by matching on semantic name and index. A
 750     * binary search could be used because the vs outputs are sorted by their
 751     * semantic index and grouped by semantic type by fill_in_vs_outputs.
 752     */
 753    assert(fs->infile.num_reg < ETNA_NUM_INPUTS);
 754    info->pcoord_varying_comp_ofs = -1;
 755
 756    for (int idx = 0; idx < fs->infile.num_reg; ++idx) {
 757       const struct etna_shader_inout *fsio = &fs->infile.reg[idx];
 758       const struct etna_shader_inout *vsio = etna_shader_vs_lookup(vs, fsio);
 759       struct etna_varying *varying;
 760       bool interpolate_always = true;
 761
 762       assert(fsio->reg > 0 && fsio->reg <= ARRAY_SIZE(info->varyings));
 763
 764       if (fsio->reg > info->num_varyings)
 765          info->num_varyings = fsio->reg;
 766
 767       varying = &info->varyings[fsio->reg - 1];
 768       varying->num_components = fsio->num_components;
 769
 770       if (!interpolate_always) /* colors affected by flat shading */
 771          varying->pa_attributes = 0x200;
 772       else /* texture coord or other bypasses flat shading */
 773          varying->pa_attributes = 0x2f1;
 774
 775       varying->use[0] = VARYING_COMPONENT_USE_UNUSED;
 776       varying->use[1] = VARYING_COMPONENT_USE_UNUSED;
 777       varying->use[2] = VARYING_COMPONENT_USE_UNUSED;
 778       varying->use[3] = VARYING_COMPONENT_USE_UNUSED;
 779
 780       /* point coord is an input to the PS without matching VS output,
 781        * so it gets a varying slot without being assigned a VS register.
 782        */
 783       if (fsio->slot == VARYING_SLOT_PNTC) {
 784          varying->use[0] = VARYING_COMPONENT_USE_POINTCOORD_X;
 785          varying->use[1] = VARYING_COMPONENT_USE_POINTCOORD_Y;
 786
 787          info->pcoord_varying_comp_ofs = comp_ofs;
 788       } else {
 789          if (vsio == NULL) { /* not found -- link error */
 790             BUG("Semantic value not found in vertex shader outputs\n");
 791             return true;
 792          }
 793          varying->reg = vsio->reg;
 794       }
 795
 796       comp_ofs += varying->num_components;
 797    }
 798
 799    assert(info->num_varyings == fs->infile.num_reg);
 800
 801    return false;
 802 }