src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c

   1 /*
   2  * Copyright (c) 2012-2019 Etnaviv Project
   3  * Copyright (c) 2019 Zodiac Inflight Innovations
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jonathan Marek <jonathan@marek.ca>
  26  *    Wladimir J. van der Laan <laanwj@gmail.com>
  27  */
  28
  29 #include "etnaviv_compiler.h"
  30 #include "etnaviv_compiler_nir.h"
  31 #include "etnaviv_asm.h"
  32 #include "etnaviv_context.h"
  33 #include "etnaviv_debug.h"
  34 #include "etnaviv_disasm.h"
  35 #include "etnaviv_nir.h"
  36 #include "etnaviv_uniforms.h"
  37 #include "etnaviv_util.h"
  38
  39 #include <math.h>
  40 #include "util/u_memory.h"
  41 #include "util/register_allocate.h"
  42 #include "compiler/nir/nir_builder.h"
  43 #include "compiler/nir/nir_worklist.h"
  44
  45 #include "tgsi/tgsi_strings.h"
  46 #include "util/u_half.h"
  47
  48 struct etna_compile {
  49    nir_shader *nir;
  50 #define is_fs(c) ((c)->nir->info.stage == MESA_SHADER_FRAGMENT)
  51    const struct etna_specs *specs;
  52    struct etna_shader_variant *variant;
  53
  54    /* block # to instr index */
  55    unsigned *block_ptr;
  56
  57    /* Code generation */
  58    int inst_ptr; /* current instruction pointer */
  59    struct etna_inst code[ETNA_MAX_INSTRUCTIONS * ETNA_INST_SIZE];
  60
  61    /* constants */
  62    uint64_t consts[ETNA_MAX_IMM];
  63
  64    /* There was an error during compilation */
  65    bool error;
  66 };
  67
  68
  69
  70 static bool
  71 etna_alu_to_scalar_filter_cb(const nir_instr *instr, const void *data)
  72 {
  73    const struct etna_specs *specs = data;
  74
  75    if (instr->type != nir_instr_type_alu)
  76       return false;
  77
  78    nir_alu_instr *alu = nir_instr_as_alu(instr);
  79    switch (alu->op) {
  80    case nir_op_frsq:
  81    case nir_op_frcp:
  82    case nir_op_flog2:
  83    case nir_op_fexp2:
  84    case nir_op_fsqrt:
  85    case nir_op_fcos:
  86    case nir_op_fsin:
  87    case nir_op_fdiv:
  88    case nir_op_imul:
  89       return true;
  90    /* TODO: can do better than alu_to_scalar for vector compares */
  91    case nir_op_b32all_fequal2:
  92    case nir_op_b32all_fequal3:
  93    case nir_op_b32all_fequal4:
  94    case nir_op_b32any_fnequal2:
  95    case nir_op_b32any_fnequal3:
  96    case nir_op_b32any_fnequal4:
  97    case nir_op_b32all_iequal2:
  98    case nir_op_b32all_iequal3:
  99    case nir_op_b32all_iequal4:
 100    case nir_op_b32any_inequal2:
 101    case nir_op_b32any_inequal3:
 102    case nir_op_b32any_inequal4:
 103       return true;
 104    case nir_op_fdot2:
 105       if (!specs->has_halti2_instructions)
 106          return true;
 107       break;
 108    default:
 109       break;
 110    }
 111
 112    return false;
 113 }
 114
 115 static void
 116 emit_inst(struct etna_compile *c, struct etna_inst *inst)
 117 {
 118    c->code[c->inst_ptr++] = *inst;
 119 }
 120
 121 /* to map nir srcs should to etna_inst srcs */
 122 enum {
 123    SRC_0_1_2 = (0 << 0) | (1 << 2) | (2 << 4),
 124    SRC_0_1_X = (0 << 0) | (1 << 2) | (3 << 4),
 125    SRC_0_X_X = (0 << 0) | (3 << 2) | (3 << 4),
 126    SRC_0_X_1 = (0 << 0) | (3 << 2) | (1 << 4),
 127    SRC_0_1_0 = (0 << 0) | (1 << 2) | (0 << 4),
 128    SRC_X_X_0 = (3 << 0) | (3 << 2) | (0 << 4),
 129    SRC_0_X_0 = (0 << 0) | (3 << 2) | (0 << 4),
 130 };
 131
 132 /* info to translate a nir op to etna_inst */
 133 struct etna_op_info {
 134    uint8_t opcode; /* INST_OPCODE_ */
 135    uint8_t src; /* SRC_ enum  */
 136    uint8_t cond; /* INST_CONDITION_ */
 137    uint8_t type; /* INST_TYPE_ */
 138 };
 139
 140 static const struct etna_op_info etna_ops[] = {
 141    [0 ... nir_num_opcodes - 1] = {0xff},
 142 #undef TRUE
 143 #undef FALSE
 144 #define OPCT(nir, op, src, cond, type) [nir_op_##nir] = { \
 145    INST_OPCODE_##op, \
 146    SRC_##src, \
 147    INST_CONDITION_##cond, \
 148    INST_TYPE_##type \
 149 }
 150 #define OPC(nir, op, src, cond) OPCT(nir, op, src, cond, F32)
 151 #define IOPC(nir, op, src, cond) OPCT(nir, op, src, cond, S32)
 152 #define UOPC(nir, op, src, cond) OPCT(nir, op, src, cond, U32)
 153 #define OP(nir, op, src) OPC(nir, op, src, TRUE)
 154 #define IOP(nir, op, src) IOPC(nir, op, src, TRUE)
 155 #define UOP(nir, op, src) UOPC(nir, op, src, TRUE)
 156    OP(mov, MOV, X_X_0), OP(fneg, MOV, X_X_0), OP(fabs, MOV, X_X_0), OP(fsat, MOV, X_X_0),
 157    OP(fmul, MUL, 0_1_X), OP(fadd, ADD, 0_X_1), OP(ffma, MAD, 0_1_2),
 158    OP(fdot2, DP2, 0_1_X), OP(fdot3, DP3, 0_1_X), OP(fdot4, DP4, 0_1_X),
 159    OPC(fmin, SELECT, 0_1_0, GT), OPC(fmax, SELECT, 0_1_0, LT),
 160    OP(ffract, FRC, X_X_0), OP(frcp, RCP, X_X_0), OP(frsq, RSQ, X_X_0),
 161    OP(fsqrt, SQRT, X_X_0), OP(fsin, SIN, X_X_0), OP(fcos, COS, X_X_0),
 162    OP(fsign, SIGN, X_X_0), OP(ffloor, FLOOR, X_X_0), OP(fceil, CEIL, X_X_0),
 163    OP(flog2, LOG, X_X_0), OP(fexp2, EXP, X_X_0),
 164    OPC(seq, SET, 0_1_X, EQ), OPC(sne, SET, 0_1_X, NE), OPC(sge, SET, 0_1_X, GE), OPC(slt, SET, 0_1_X, LT),
 165    OPC(fcsel, SELECT, 0_1_2, NZ),
 166    OP(fdiv, DIV, 0_1_X),
 167    OP(fddx, DSX, 0_X_0), OP(fddy, DSY, 0_X_0),
 168
 169    /* type convert */
 170    IOP(i2f32, I2F, 0_X_X),
 171    UOP(u2f32, I2F, 0_X_X),
 172    IOP(f2i32, F2I, 0_X_X),
 173    UOP(f2u32, F2I, 0_X_X),
 174    UOP(b2f32, AND, 0_X_X), /* AND with fui(1.0f) */
 175    UOP(b2i32, AND, 0_X_X), /* AND with 1 */
 176    OPC(f2b32, CMP, 0_X_X, NE), /* != 0.0 */
 177    UOPC(i2b32, CMP, 0_X_X, NE), /* != 0 */
 178
 179    /* arithmetic */
 180    IOP(iadd, ADD, 0_X_1),
 181    IOP(imul, IMULLO0, 0_1_X),
 182    /* IOP(imad, IMADLO0, 0_1_2), */
 183    IOP(ineg, ADD, X_X_0), /* ADD 0, -x */
 184    IOP(iabs, IABS, X_X_0),
 185    IOP(isign, SIGN, X_X_0),
 186    IOPC(imin, SELECT, 0_1_0, GT),
 187    IOPC(imax, SELECT, 0_1_0, LT),
 188    UOPC(umin, SELECT, 0_1_0, GT),
 189    UOPC(umax, SELECT, 0_1_0, LT),
 190
 191    /* select */
 192    UOPC(b32csel, SELECT, 0_1_2, NZ),
 193
 194    /* compare with int result */
 195     OPC(feq32, CMP, 0_1_X, EQ),
 196     OPC(fne32, CMP, 0_1_X, NE),
 197     OPC(fge32, CMP, 0_1_X, GE),
 198     OPC(flt32, CMP, 0_1_X, LT),
 199    IOPC(ieq32, CMP, 0_1_X, EQ),
 200    IOPC(ine32, CMP, 0_1_X, NE),
 201    IOPC(ige32, CMP, 0_1_X, GE),
 202    IOPC(ilt32, CMP, 0_1_X, LT),
 203    UOPC(uge32, CMP, 0_1_X, GE),
 204    UOPC(ult32, CMP, 0_1_X, LT),
 205
 206    /* bit ops */
 207    IOP(ior,  OR,  0_X_1),
 208    IOP(iand, AND, 0_X_1),
 209    IOP(ixor, XOR, 0_X_1),
 210    IOP(inot, NOT, X_X_0),
 211    IOP(ishl, LSHIFT, 0_X_1),
 212    IOP(ishr, RSHIFT, 0_X_1),
 213    UOP(ushr, RSHIFT, 0_X_1),
 214 };
 215
 216 static void
 217 etna_emit_block_start(struct etna_compile *c, unsigned block)
 218 {
 219    c->block_ptr[block] = c->inst_ptr;
 220 }
 221
 222 static void
 223 etna_emit_alu(struct etna_compile *c, nir_op op, struct etna_inst_dst dst,
 224               struct etna_inst_src src[3], bool saturate)
 225 {
 226    struct etna_op_info ei = etna_ops[op];
 227    unsigned swiz_scalar = INST_SWIZ_BROADCAST(ffs(dst.write_mask) - 1);
 228
 229    if (ei.opcode == 0xff)
 230       compile_error(c, "Unhandled ALU op: %s\n", nir_op_infos[op].name);
 231
 232    struct etna_inst inst = {
 233       .opcode = ei.opcode,
 234       .type = ei.type,
 235       .cond = ei.cond,
 236       .dst = dst,
 237       .sat = saturate,
 238    };
 239
 240    switch (op) {
 241    case nir_op_fdiv:
 242    case nir_op_flog2:
 243    case nir_op_fsin:
 244    case nir_op_fcos:
 245       if (c->specs->has_new_transcendentals)
 246          inst.tex.amode = 1;
 247       /* fall through */
 248    case nir_op_frsq:
 249    case nir_op_frcp:
 250    case nir_op_fexp2:
 251    case nir_op_fsqrt:
 252    case nir_op_imul:
 253       /* scalar instructions we want src to be in x component */
 254       src[0].swiz = inst_swiz_compose(src[0].swiz, swiz_scalar);
 255       src[1].swiz = inst_swiz_compose(src[1].swiz, swiz_scalar);
 256       break;
 257    /* deal with instructions which don't have 1:1 mapping */
 258    case nir_op_b2f32:
 259       inst.src[2] = etna_immediate_float(1.0f);
 260       break;
 261    case nir_op_b2i32:
 262       inst.src[2] = etna_immediate_int(1);
 263       break;
 264    case nir_op_f2b32:
 265       inst.src[1] = etna_immediate_float(0.0f);
 266       break;
 267    case nir_op_i2b32:
 268       inst.src[1] = etna_immediate_int(0);
 269       break;
 270    case nir_op_ineg:
 271       inst.src[0] = etna_immediate_int(0);
 272       src[0].neg = 1;
 273       break;
 274    default:
 275       break;
 276    }
 277
 278    /* set the "true" value for CMP instructions */
 279    if (inst.opcode == INST_OPCODE_CMP)
 280       inst.src[2] = etna_immediate_int(-1);
 281
 282    for (unsigned j = 0; j < 3; j++) {
 283       unsigned i = ((ei.src >> j*2) & 3);
 284       if (i < 3)
 285          inst.src[j] = src[i];
 286    }
 287
 288    emit_inst(c, &inst);
 289 }
 290
 291 static void
 292 etna_emit_tex(struct etna_compile *c, nir_texop op, unsigned texid, unsigned dst_swiz,
 293               struct etna_inst_dst dst, struct etna_inst_src coord,
 294               struct etna_inst_src lod_bias, struct etna_inst_src compare)
 295 {
 296    struct etna_inst inst = {
 297       .dst = dst,
 298       .tex.id = texid + (is_fs(c) ? 0 : c->specs->vertex_sampler_offset),
 299       .tex.swiz = dst_swiz,
 300       .src[0] = coord,
 301    };
 302
 303    if (lod_bias.use)
 304       inst.src[1] = lod_bias;
 305
 306    if (compare.use)
 307       inst.src[2] = compare;
 308
 309    switch (op) {
 310    case nir_texop_tex: inst.opcode = INST_OPCODE_TEXLD; break;
 311    case nir_texop_txb: inst.opcode = INST_OPCODE_TEXLDB; break;
 312    case nir_texop_txl: inst.opcode = INST_OPCODE_TEXLDL; break;
 313    default:
 314       compile_error(c, "Unhandled NIR tex type: %d\n", op);
 315    }
 316
 317    emit_inst(c, &inst);
 318 }
 319
 320 static void
 321 etna_emit_jump(struct etna_compile *c, unsigned block, struct etna_inst_src condition)
 322 {
 323    if (!condition.use) {
 324       emit_inst(c, &(struct etna_inst) {.opcode = INST_OPCODE_BRANCH, .imm = block });
 325       return;
 326    }
 327
 328    struct etna_inst inst = {
 329       .opcode = INST_OPCODE_BRANCH,
 330       .cond = INST_CONDITION_NOT,
 331       .type = INST_TYPE_U32,
 332       .src[0] = condition,
 333       .imm = block,
 334    };
 335    inst.src[0].swiz = INST_SWIZ_BROADCAST(inst.src[0].swiz & 3);
 336    emit_inst(c, &inst);
 337 }
 338
 339 static void
 340 etna_emit_discard(struct etna_compile *c, struct etna_inst_src condition)
 341 {
 342    if (!condition.use) {
 343       emit_inst(c, &(struct etna_inst) { .opcode = INST_OPCODE_TEXKILL });
 344       return;
 345    }
 346
 347    struct etna_inst inst = {
 348       .opcode = INST_OPCODE_TEXKILL,
 349       .cond = INST_CONDITION_NZ,
 350       .type = (c->specs->halti < 2) ? INST_TYPE_F32 : INST_TYPE_U32,
 351       .src[0] = condition,
 352    };
 353    inst.src[0].swiz = INST_SWIZ_BROADCAST(inst.src[0].swiz & 3);
 354    emit_inst(c, &inst);
 355 }
 356
 357 static void
 358 etna_emit_output(struct etna_compile *c, nir_variable *var, struct etna_inst_src src)
 359 {
 360    struct etna_shader_io_file *sf = &c->variant->outfile;
 361
 362    if (is_fs(c)) {
 363       switch (var->data.location) {
 364       case FRAG_RESULT_COLOR:
 365       case FRAG_RESULT_DATA0: /* DATA0 is used by gallium shaders for color */
 366          c->variant->ps_color_out_reg = src.reg;
 367          break;
 368       case FRAG_RESULT_DEPTH:
 369          c->variant->ps_depth_out_reg = src.reg;
 370          break;
 371       default:
 372          unreachable("Unsupported fs output");
 373       }
 374       return;
 375    }
 376
 377    switch (var->data.location) {
 378    case VARYING_SLOT_POS:
 379       c->variant->vs_pos_out_reg = src.reg;
 380       break;
 381    case VARYING_SLOT_PSIZ:
 382       c->variant->vs_pointsize_out_reg = src.reg;
 383       break;
 384    default:
 385       sf->reg[sf->num_reg].reg = src.reg;
 386       sf->reg[sf->num_reg].slot = var->data.location;
 387       sf->reg[sf->num_reg].num_components = glsl_get_components(var->type);
 388       sf->num_reg++;
 389       break;
 390    }
 391 }
 392
 393 #define OPT(nir, pass, ...) ({                             \
 394    bool this_progress = false;                             \
 395    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 396    this_progress;                                          \
 397 })
 398
 399 static void
 400 etna_optimize_loop(nir_shader *s)
 401 {
 402    bool progress;
 403    do {
 404       progress = false;
 405
 406       NIR_PASS_V(s, nir_lower_vars_to_ssa);
 407       progress |= OPT(s, nir_opt_copy_prop_vars);
 408       progress |= OPT(s, nir_copy_prop);
 409       progress |= OPT(s, nir_opt_dce);
 410       progress |= OPT(s, nir_opt_cse);
 411       progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 412       progress |= OPT(s, nir_opt_intrinsics);
 413       progress |= OPT(s, nir_opt_algebraic);
 414       progress |= OPT(s, nir_opt_constant_folding);
 415       progress |= OPT(s, nir_opt_dead_cf);
 416       if (OPT(s, nir_opt_trivial_continues)) {
 417          progress = true;
 418          /* If nir_opt_trivial_continues makes progress, then we need to clean
 419           * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 420           * to make progress.
 421           */
 422          OPT(s, nir_copy_prop);
 423          OPT(s, nir_opt_dce);
 424       }
 425       progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
 426       progress |= OPT(s, nir_opt_if, false);
 427       progress |= OPT(s, nir_opt_remove_phis);
 428       progress |= OPT(s, nir_opt_undef);
 429    }
 430    while (progress);
 431 }
 432
 433 static int
 434 etna_glsl_type_size(const struct glsl_type *type, bool bindless)
 435 {
 436    return glsl_count_attribute_slots(type, false);
 437 }
 438
 439 static void
 440 copy_uniform_state_to_shader(struct etna_shader_variant *sobj, uint64_t *consts, unsigned count)
 441 {
 442    struct etna_shader_uniform_info *uinfo = &sobj->uniforms;
 443
 444    uinfo->imm_count = count * 4;
 445    uinfo->imm_data = MALLOC(uinfo->imm_count * sizeof(*uinfo->imm_data));
 446    uinfo->imm_contents = MALLOC(uinfo->imm_count * sizeof(*uinfo->imm_contents));
 447
 448    for (unsigned i = 0; i < uinfo->imm_count; i++) {
 449       uinfo->imm_data[i] = consts[i];
 450       uinfo->imm_contents[i] = consts[i] >> 32;
 451    }
 452
 453    etna_set_shader_uniforms_dirty_flags(sobj);
 454 }
 455
 456 #include "etnaviv_compiler_nir_emit.h"
 457
 458 static bool
 459 etna_compile_check_limits(struct etna_shader_variant *v)
 460 {
 461    const struct etna_specs *specs = v->shader->specs;
 462    int max_uniforms = (v->stage == MESA_SHADER_VERTEX)
 463                          ? specs->max_vs_uniforms
 464                          : specs->max_ps_uniforms;
 465
 466    if (!specs->has_icache && v->needs_icache) {
 467       DBG("Number of instructions (%d) exceeds maximum %d", v->code_size / 4,
 468           specs->max_instructions);
 469       return false;
 470    }
 471
 472    if (v->num_temps > specs->max_registers) {
 473       DBG("Number of registers (%d) exceeds maximum %d", v->num_temps,
 474           specs->max_registers);
 475       return false;
 476    }
 477
 478    if (v->uniforms.imm_count / 4 > max_uniforms) {
 479       DBG("Number of uniforms (%d) exceeds maximum %d",
 480           v->uniforms.imm_count / 4, max_uniforms);
 481       return false;
 482    }
 483
 484    return true;
 485 }
 486
 487 static void
 488 fill_vs_mystery(struct etna_shader_variant *v)
 489 {
 490    const struct etna_specs *specs = v->shader->specs;
 491
 492    v->input_count_unk8 = DIV_ROUND_UP(v->infile.num_reg + 4, 16); /* XXX what is this */
 493
 494    /* fill in "mystery meat" load balancing value. This value determines how
 495     * work is scheduled between VS and PS
 496     * in the unified shader architecture. More precisely, it is determined from
 497     * the number of VS outputs, as well as chip-specific
 498     * vertex output buffer size, vertex cache size, and the number of shader
 499     * cores.
 500     *
 501     * XXX this is a conservative estimate, the "optimal" value is only known for
 502     * sure at link time because some
 503     * outputs may be unused and thus unmapped. Then again, in the general use
 504     * case with GLSL the vertex and fragment
 505     * shaders are linked already before submitting to Gallium, thus all outputs
 506     * are used.
 507     *
 508     * note: TGSI compiler counts all outputs (including position and pointsize), here
 509     * v->outfile.num_reg only counts varyings, +1 to compensate for the position output
 510     * TODO: might have a problem that we don't count pointsize when it is used
 511     */
 512
 513    int half_out = v->outfile.num_reg / 2 + 1;
 514    assert(half_out);
 515
 516    uint32_t b = ((20480 / (specs->vertex_output_buffer_size -
 517                            2 * half_out * specs->vertex_cache_size)) +
 518                  9) /
 519                 10;
 520    uint32_t a = (b + 256 / (specs->shader_core_count * half_out)) / 2;
 521    v->vs_load_balancing = VIVS_VS_LOAD_BALANCING_A(MIN2(a, 255)) |
 522                              VIVS_VS_LOAD_BALANCING_B(MIN2(b, 255)) |
 523                              VIVS_VS_LOAD_BALANCING_C(0x3f) |
 524                              VIVS_VS_LOAD_BALANCING_D(0x0f);
 525 }
 526
 527 bool
 528 etna_compile_shader_nir(struct etna_shader_variant *v)
 529 {
 530    if (unlikely(!v))
 531       return false;
 532
 533    struct etna_compile *c = CALLOC_STRUCT(etna_compile);
 534    if (!c)
 535       return false;
 536
 537    c->variant = v;
 538    c->specs = v->shader->specs;
 539    c->nir = nir_shader_clone(NULL, v->shader->nir);
 540
 541    nir_shader *s = c->nir;
 542    const struct etna_specs *specs = c->specs;
 543
 544    v->stage = s->info.stage;
 545    v->num_loops = 0; /* TODO */
 546    v->vs_id_in_reg = -1;
 547    v->vs_pos_out_reg = -1;
 548    v->vs_pointsize_out_reg = -1;
 549    v->ps_color_out_reg = 0; /* 0 for shader that doesn't write fragcolor.. */
 550    v->ps_depth_out_reg = -1;
 551
 552    /* setup input linking */
 553    struct etna_shader_io_file *sf = &v->infile;
 554    if (s->info.stage == MESA_SHADER_VERTEX) {
 555       nir_foreach_variable(var, &s->inputs) {
 556          unsigned idx = var->data.driver_location;
 557          sf->reg[idx].reg = idx;
 558          sf->reg[idx].slot = var->data.location;
 559          sf->reg[idx].num_components = glsl_get_components(var->type);
 560          sf->num_reg = MAX2(sf->num_reg, idx+1);
 561       }
 562    } else {
 563       unsigned count = 0;
 564       nir_foreach_variable(var, &s->inputs) {
 565          unsigned idx = var->data.driver_location;
 566          sf->reg[idx].reg = idx + 1;
 567          sf->reg[idx].slot = var->data.location;
 568          sf->reg[idx].num_components = glsl_get_components(var->type);
 569          sf->num_reg = MAX2(sf->num_reg, idx+1);
 570          count++;
 571       }
 572       assert(sf->num_reg == count);
 573    }
 574
 575    NIR_PASS_V(s, nir_lower_io, ~nir_var_shader_out, etna_glsl_type_size,
 576             (nir_lower_io_options)0);
 577
 578    NIR_PASS_V(s, nir_lower_regs_to_ssa);
 579    NIR_PASS_V(s, nir_lower_vars_to_ssa);
 580    NIR_PASS_V(s, nir_lower_indirect_derefs, nir_var_all);
 581    NIR_PASS_V(s, nir_lower_tex, &(struct nir_lower_tex_options) { .lower_txp = ~0u });
 582    NIR_PASS_V(s, nir_lower_alu_to_scalar, etna_alu_to_scalar_filter_cb, specs);
 583
 584    etna_optimize_loop(s);
 585
 586    NIR_PASS_V(s, etna_lower_io, v);
 587
 588    if (v->shader->specs->vs_need_z_div)
 589       NIR_PASS_V(s, nir_lower_clip_halfz);
 590
 591    /* lower pre-halti2 to float (halti0 has integers, but only scalar..) */
 592    if (c->specs->halti < 2) {
 593       /* use opt_algebraic between int_to_float and boot_to_float because
 594        * int_to_float emits ftrunc, and ftrunc lowering generates bool ops
 595        */
 596       NIR_PASS_V(s, nir_lower_int_to_float);
 597       NIR_PASS_V(s, nir_opt_algebraic);
 598       NIR_PASS_V(s, nir_lower_bool_to_float);
 599    } else {
 600       NIR_PASS_V(s, nir_lower_idiv, nir_lower_idiv_fast);
 601       NIR_PASS_V(s, nir_lower_bool_to_int32);
 602    }
 603
 604    etna_optimize_loop(s);
 605
 606    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
 607       nir_print_shader(s, stdout);
 608
 609    while( OPT(s, nir_opt_vectorize) );
 610    NIR_PASS_V(s, nir_lower_alu_to_scalar, etna_alu_to_scalar_filter_cb, specs);
 611
 612    NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
 613    NIR_PASS_V(s, nir_opt_algebraic_late);
 614
 615    NIR_PASS_V(s, nir_move_vec_src_uses_to_dest);
 616    NIR_PASS_V(s, nir_copy_prop);
 617    /* only HW supported integer source mod is ineg for iadd instruction (?) */
 618    NIR_PASS_V(s, nir_lower_to_source_mods, ~nir_lower_int_source_mods);
 619    /* need copy prop after uses_to_dest, and before src mods: see
 620     * dEQP-GLES2.functional.shaders.random.all_features.fragment.95
 621     */
 622
 623    NIR_PASS_V(s, nir_opt_dce);
 624
 625    NIR_PASS_V(s, etna_lower_alu, c->specs->has_new_transcendentals);
 626
 627    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
 628       nir_print_shader(s, stdout);
 629
 630    unsigned block_ptr[nir_shader_get_entrypoint(s)->num_blocks];
 631    c->block_ptr = block_ptr;
 632
 633    unsigned num_consts;
 634    ASSERTED bool ok = emit_shader(c, &v->num_temps, &num_consts);
 635    assert(ok);
 636
 637    /* empty shader, emit NOP */
 638    if (!c->inst_ptr)
 639       emit_inst(c, &(struct etna_inst) { .opcode = INST_OPCODE_NOP });
 640
 641    /* assemble instructions, fixing up labels */
 642    uint32_t *code = MALLOC(c->inst_ptr * 16);
 643    for (unsigned i = 0; i < c->inst_ptr; i++) {
 644       struct etna_inst *inst = &c->code[i];
 645       if (inst->opcode == INST_OPCODE_BRANCH)
 646          inst->imm = block_ptr[inst->imm];
 647
 648       inst->halti5 = specs->halti >= 5;
 649       etna_assemble(&code[i * 4], inst);
 650    }
 651
 652    v->code_size = c->inst_ptr * 4;
 653    v->code = code;
 654    v->needs_icache = c->inst_ptr > specs->max_instructions;
 655
 656    copy_uniform_state_to_shader(v, c->consts, num_consts);
 657
 658    if (s->info.stage == MESA_SHADER_FRAGMENT) {
 659       v->input_count_unk8 = 31; /* XXX what is this */
 660       assert(v->ps_depth_out_reg <= 0);
 661    } else {
 662       fill_vs_mystery(v);
 663    }
 664
 665    bool result = etna_compile_check_limits(v);
 666    ralloc_free(c->nir);
 667    FREE(c);
 668    return result;
 669 }
 670
 671 void
 672 etna_destroy_shader_nir(struct etna_shader_variant *shader)
 673 {
 674    assert(shader);
 675
 676    FREE(shader->code);
 677    FREE(shader->uniforms.imm_data);
 678    FREE(shader->uniforms.imm_contents);
 679    FREE(shader);
 680 }
 681
 682 extern const char *tgsi_swizzle_names[];
 683 void
 684 etna_dump_shader_nir(const struct etna_shader_variant *shader)
 685 {
 686    if (shader->stage == MESA_SHADER_VERTEX)
 687       printf("VERT\n");
 688    else
 689       printf("FRAG\n");
 690
 691    etna_disasm(shader->code, shader->code_size, PRINT_RAW);
 692
 693    printf("num loops: %i\n", shader->num_loops);
 694    printf("num temps: %i\n", shader->num_temps);
 695    printf("immediates:\n");
 696    for (int idx = 0; idx < shader->uniforms.imm_count; ++idx) {
 697       printf(" [%i].%s = %f (0x%08x) (%d)\n",
 698              idx / 4,
 699              tgsi_swizzle_names[idx % 4],
 700              *((float *)&shader->uniforms.imm_data[idx]),
 701              shader->uniforms.imm_data[idx],
 702              shader->uniforms.imm_contents[idx]);
 703    }
 704    printf("inputs:\n");
 705    for (int idx = 0; idx < shader->infile.num_reg; ++idx) {
 706       printf(" [%i] name=%s comps=%i\n", shader->infile.reg[idx].reg,
 707                (shader->stage == MESA_SHADER_VERTEX) ?
 708                gl_vert_attrib_name(shader->infile.reg[idx].slot) :
 709                gl_varying_slot_name(shader->infile.reg[idx].slot),
 710                shader->infile.reg[idx].num_components);
 711    }
 712    printf("outputs:\n");
 713    for (int idx = 0; idx < shader->outfile.num_reg; ++idx) {
 714       printf(" [%i] name=%s comps=%i\n", shader->outfile.reg[idx].reg,
 715                (shader->stage == MESA_SHADER_VERTEX) ?
 716                gl_varying_slot_name(shader->outfile.reg[idx].slot) :
 717                gl_frag_result_name(shader->outfile.reg[idx].slot),
 718                shader->outfile.reg[idx].num_components);
 719    }
 720    printf("special:\n");
 721    if (shader->stage == MESA_SHADER_VERTEX) {
 722       printf("  vs_pos_out_reg=%i\n", shader->vs_pos_out_reg);
 723       printf("  vs_pointsize_out_reg=%i\n", shader->vs_pointsize_out_reg);
 724       printf("  vs_load_balancing=0x%08x\n", shader->vs_load_balancing);
 725    } else {
 726       printf("  ps_color_out_reg=%i\n", shader->ps_color_out_reg);
 727       printf("  ps_depth_out_reg=%i\n", shader->ps_depth_out_reg);
 728    }
 729    printf("  input_count_unk8=0x%08x\n", shader->input_count_unk8);
 730 }
 731
 732 static const struct etna_shader_inout *
 733 etna_shader_vs_lookup(const struct etna_shader_variant *sobj,
 734                       const struct etna_shader_inout *in)
 735 {
 736    for (int i = 0; i < sobj->outfile.num_reg; i++)
 737       if (sobj->outfile.reg[i].slot == in->slot)
 738          return &sobj->outfile.reg[i];
 739
 740    return NULL;
 741 }
 742
 743 bool
 744 etna_link_shader_nir(struct etna_shader_link_info *info,
 745                      const struct etna_shader_variant *vs,
 746                      const struct etna_shader_variant *fs)
 747 {
 748    int comp_ofs = 0;
 749    /* For each fragment input we need to find the associated vertex shader
 750     * output, which can be found by matching on semantic name and index. A
 751     * binary search could be used because the vs outputs are sorted by their
 752     * semantic index and grouped by semantic type by fill_in_vs_outputs.
 753     */
 754    assert(fs->infile.num_reg < ETNA_NUM_INPUTS);
 755    info->pcoord_varying_comp_ofs = -1;
 756
 757    for (int idx = 0; idx < fs->infile.num_reg; ++idx) {
 758       const struct etna_shader_inout *fsio = &fs->infile.reg[idx];
 759       const struct etna_shader_inout *vsio = etna_shader_vs_lookup(vs, fsio);
 760       struct etna_varying *varying;
 761       bool interpolate_always = true;
 762
 763       assert(fsio->reg > 0 && fsio->reg <= ARRAY_SIZE(info->varyings));
 764
 765       if (fsio->reg > info->num_varyings)
 766          info->num_varyings = fsio->reg;
 767
 768       varying = &info->varyings[fsio->reg - 1];
 769       varying->num_components = fsio->num_components;
 770
 771       if (!interpolate_always) /* colors affected by flat shading */
 772          varying->pa_attributes = 0x200;
 773       else /* texture coord or other bypasses flat shading */
 774          varying->pa_attributes = 0x2f1;
 775
 776       varying->use[0] = VARYING_COMPONENT_USE_UNUSED;
 777       varying->use[1] = VARYING_COMPONENT_USE_UNUSED;
 778       varying->use[2] = VARYING_COMPONENT_USE_UNUSED;
 779       varying->use[3] = VARYING_COMPONENT_USE_UNUSED;
 780
 781       /* point coord is an input to the PS without matching VS output,
 782        * so it gets a varying slot without being assigned a VS register.
 783        */
 784       if (fsio->slot == VARYING_SLOT_PNTC) {
 785          varying->use[0] = VARYING_COMPONENT_USE_POINTCOORD_X;
 786          varying->use[1] = VARYING_COMPONENT_USE_POINTCOORD_Y;
 787
 788          info->pcoord_varying_comp_ofs = comp_ofs;
 789       } else {
 790          if (vsio == NULL) { /* not found -- link error */
 791             BUG("Semantic value not found in vertex shader outputs\n");
 792             return true;
 793          }
 794          varying->reg = vsio->reg;
 795       }
 796
 797       comp_ofs += varying->num_components;
 798    }
 799
 800    assert(info->num_varyings == fs->infile.num_reg);
 801
 802    return false;
 803 }