2 * Copyright (c) 2019 Zodiac Inflight Innovations
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Jonathan Marek <jonathan@marek.ca>
27 #include "etnaviv_asm.h"
28 #include "etnaviv_context.h"
29 #include "etnaviv_compiler_nir.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir/nir_builder.h"
33 #include "compiler/nir/nir_worklist.h"
34 #include "util/register_allocate.h"
36 #define ALU_SWIZ(s) INST_SWIZ((s)->swizzle[0], (s)->swizzle[1], (s)->swizzle[2], (s)->swizzle[3])
37 #define SRC_DISABLE ((hw_src){})
38 #define SRC_CONST(idx, s) ((hw_src){.use=1, .rgroup = INST_RGROUP_UNIFORM_0, .reg=idx, .swiz=s})
39 #define SRC_REG(idx, s) ((hw_src){.use=1, .rgroup = INST_RGROUP_TEMP, .reg=idx, .swiz=s})
41 #define emit(type, args...) etna_emit_##type(state->c, args)
43 typedef struct etna_inst_dst hw_dst
;
44 typedef struct etna_inst_src hw_src
;
52 struct etna_compile
*c
;
57 nir_function_impl
*impl
;
67 src_swizzle(hw_src src
, unsigned swizzle
)
69 if (src
.rgroup
!= INST_RGROUP_IMMEDIATE
)
70 src
.swiz
= inst_swiz_compose(src
.swiz
, swizzle
);
75 static inline bool is_sysval(nir_instr
*instr
)
77 if (instr
->type
!= nir_instr_type_intrinsic
)
80 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
81 return intr
->intrinsic
== nir_intrinsic_load_front_face
||
82 intr
->intrinsic
== nir_intrinsic_load_frag_coord
;
85 /* constants are represented as 64-bit ints
86 * 32-bit for the value and 32-bit for the type (imm, uniform, etc)
89 #define CONST_VAL(a, b) (nir_const_value) {.u64 = (uint64_t)(a) << 32 | (uint64_t)(b)}
90 #define CONST(x) CONST_VAL(ETNA_IMMEDIATE_CONSTANT, x)
91 #define UNIFORM(x) CONST_VAL(ETNA_IMMEDIATE_UNIFORM, x)
92 #define TEXSCALE(x, i) CONST_VAL(ETNA_IMMEDIATE_TEXRECT_SCALE_X + (i), x)
95 const_add(uint64_t *c
, uint64_t value
)
97 for (unsigned i
= 0; i
< 4; i
++) {
98 if (c
[i
] == value
|| !c
[i
]) {
107 const_src(struct state
*state
, nir_const_value
*value
, unsigned num_components
)
109 /* use inline immediates if possible */
110 if (state
->c
->specs
->halti
>= 2 && num_components
== 1 &&
111 value
[0].u64
>> 32 == ETNA_IMMEDIATE_CONSTANT
) {
112 uint32_t bits
= value
[0].u32
;
114 /* "float" - shifted by 12 */
115 if ((bits
& 0xfff) == 0)
116 return etna_immediate_src(0, bits
>> 12);
118 /* "unsigned" - raw 20 bit value */
119 if (bits
< (1 << 20))
120 return etna_immediate_src(2, bits
);
122 /* "signed" - sign extended 20-bit (sign included) value */
123 if (bits
>= 0xfff80000)
124 return etna_immediate_src(1, bits
);
129 for (i
= 0; swiz
< 0; i
++) {
130 uint64_t *a
= &state
->c
->consts
[i
*4];
132 memcpy(save
, a
, sizeof(save
));
134 for (unsigned j
= 0; j
< num_components
; j
++) {
135 int c
= const_add(a
, value
[j
].u64
);
137 memcpy(a
, save
, sizeof(save
));
145 assert(i
<= ETNA_MAX_IMM
/ 4);
146 state
->const_count
= MAX2(state
->const_count
, i
);
148 return SRC_CONST(i
- 1, swiz
);
151 /* Swizzles and write masks can be used to layer virtual non-interfering
152 * registers on top of the real VEC4 registers. For example, the virtual
153 * VEC3_XYZ register and the virtual SCALAR_W register that use the same
154 * physical VEC4 base register do not interfere.
157 REG_CLASS_VIRT_SCALAR
,
161 /* special vec2 class for fast transcendentals, limited to XY or ZW */
162 REG_CLASS_VIRT_VEC2T
,
163 /* special classes for LOAD - contiguous components */
164 REG_CLASS_VIRT_VEC2C
,
165 REG_CLASS_VIRT_VEC3C
,
171 REG_TYPE_VIRT_VEC3_XYZ
,
172 REG_TYPE_VIRT_VEC3_XYW
,
173 REG_TYPE_VIRT_VEC3_XZW
,
174 REG_TYPE_VIRT_VEC3_YZW
,
175 REG_TYPE_VIRT_VEC2_XY
,
176 REG_TYPE_VIRT_VEC2_XZ
,
177 REG_TYPE_VIRT_VEC2_XW
,
178 REG_TYPE_VIRT_VEC2_YZ
,
179 REG_TYPE_VIRT_VEC2_YW
,
180 REG_TYPE_VIRT_VEC2_ZW
,
181 REG_TYPE_VIRT_SCALAR_X
,
182 REG_TYPE_VIRT_SCALAR_Y
,
183 REG_TYPE_VIRT_SCALAR_Z
,
184 REG_TYPE_VIRT_SCALAR_W
,
185 REG_TYPE_VIRT_VEC2T_XY
,
186 REG_TYPE_VIRT_VEC2T_ZW
,
187 REG_TYPE_VIRT_VEC2C_XY
,
188 REG_TYPE_VIRT_VEC2C_YZ
,
189 REG_TYPE_VIRT_VEC2C_ZW
,
190 REG_TYPE_VIRT_VEC3C_XYZ
,
191 REG_TYPE_VIRT_VEC3C_YZW
,
195 /* writemask when used as dest */
197 reg_writemask
[NUM_REG_TYPES
] = {
198 [REG_TYPE_VEC4
] = 0xf,
199 [REG_TYPE_VIRT_SCALAR_X
] = 0x1,
200 [REG_TYPE_VIRT_SCALAR_Y
] = 0x2,
201 [REG_TYPE_VIRT_VEC2_XY
] = 0x3,
202 [REG_TYPE_VIRT_VEC2T_XY
] = 0x3,
203 [REG_TYPE_VIRT_VEC2C_XY
] = 0x3,
204 [REG_TYPE_VIRT_SCALAR_Z
] = 0x4,
205 [REG_TYPE_VIRT_VEC2_XZ
] = 0x5,
206 [REG_TYPE_VIRT_VEC2_YZ
] = 0x6,
207 [REG_TYPE_VIRT_VEC2C_YZ
] = 0x6,
208 [REG_TYPE_VIRT_VEC3_XYZ
] = 0x7,
209 [REG_TYPE_VIRT_VEC3C_XYZ
] = 0x7,
210 [REG_TYPE_VIRT_SCALAR_W
] = 0x8,
211 [REG_TYPE_VIRT_VEC2_XW
] = 0x9,
212 [REG_TYPE_VIRT_VEC2_YW
] = 0xa,
213 [REG_TYPE_VIRT_VEC3_XYW
] = 0xb,
214 [REG_TYPE_VIRT_VEC2_ZW
] = 0xc,
215 [REG_TYPE_VIRT_VEC2T_ZW
] = 0xc,
216 [REG_TYPE_VIRT_VEC2C_ZW
] = 0xc,
217 [REG_TYPE_VIRT_VEC3_XZW
] = 0xd,
218 [REG_TYPE_VIRT_VEC3_YZW
] = 0xe,
219 [REG_TYPE_VIRT_VEC3C_YZW
] = 0xe,
222 /* how to swizzle when used as a src */
224 reg_swiz
[NUM_REG_TYPES
] = {
225 [REG_TYPE_VEC4
] = INST_SWIZ_IDENTITY
,
226 [REG_TYPE_VIRT_SCALAR_X
] = INST_SWIZ_IDENTITY
,
227 [REG_TYPE_VIRT_SCALAR_Y
] = SWIZZLE(Y
, Y
, Y
, Y
),
228 [REG_TYPE_VIRT_VEC2_XY
] = INST_SWIZ_IDENTITY
,
229 [REG_TYPE_VIRT_VEC2T_XY
] = INST_SWIZ_IDENTITY
,
230 [REG_TYPE_VIRT_VEC2C_XY
] = INST_SWIZ_IDENTITY
,
231 [REG_TYPE_VIRT_SCALAR_Z
] = SWIZZLE(Z
, Z
, Z
, Z
),
232 [REG_TYPE_VIRT_VEC2_XZ
] = SWIZZLE(X
, Z
, X
, Z
),
233 [REG_TYPE_VIRT_VEC2_YZ
] = SWIZZLE(Y
, Z
, Y
, Z
),
234 [REG_TYPE_VIRT_VEC2C_YZ
] = SWIZZLE(Y
, Z
, Y
, Z
),
235 [REG_TYPE_VIRT_VEC3_XYZ
] = INST_SWIZ_IDENTITY
,
236 [REG_TYPE_VIRT_VEC3C_XYZ
] = INST_SWIZ_IDENTITY
,
237 [REG_TYPE_VIRT_SCALAR_W
] = SWIZZLE(W
, W
, W
, W
),
238 [REG_TYPE_VIRT_VEC2_XW
] = SWIZZLE(X
, W
, X
, W
),
239 [REG_TYPE_VIRT_VEC2_YW
] = SWIZZLE(Y
, W
, Y
, W
),
240 [REG_TYPE_VIRT_VEC3_XYW
] = SWIZZLE(X
, Y
, W
, X
),
241 [REG_TYPE_VIRT_VEC2_ZW
] = SWIZZLE(Z
, W
, Z
, W
),
242 [REG_TYPE_VIRT_VEC2T_ZW
] = SWIZZLE(Z
, W
, Z
, W
),
243 [REG_TYPE_VIRT_VEC2C_ZW
] = SWIZZLE(Z
, W
, Z
, W
),
244 [REG_TYPE_VIRT_VEC3_XZW
] = SWIZZLE(X
, Z
, W
, X
),
245 [REG_TYPE_VIRT_VEC3_YZW
] = SWIZZLE(Y
, Z
, W
, X
),
246 [REG_TYPE_VIRT_VEC3C_YZW
] = SWIZZLE(Y
, Z
, W
, X
),
249 /* how to swizzle when used as a dest */
251 reg_dst_swiz
[NUM_REG_TYPES
] = {
252 [REG_TYPE_VEC4
] = INST_SWIZ_IDENTITY
,
253 [REG_TYPE_VIRT_SCALAR_X
] = INST_SWIZ_IDENTITY
,
254 [REG_TYPE_VIRT_SCALAR_Y
] = SWIZZLE(X
, X
, X
, X
),
255 [REG_TYPE_VIRT_VEC2_XY
] = INST_SWIZ_IDENTITY
,
256 [REG_TYPE_VIRT_VEC2T_XY
] = INST_SWIZ_IDENTITY
,
257 [REG_TYPE_VIRT_VEC2C_XY
] = INST_SWIZ_IDENTITY
,
258 [REG_TYPE_VIRT_SCALAR_Z
] = SWIZZLE(X
, X
, X
, X
),
259 [REG_TYPE_VIRT_VEC2_XZ
] = SWIZZLE(X
, X
, Y
, Y
),
260 [REG_TYPE_VIRT_VEC2_YZ
] = SWIZZLE(X
, X
, Y
, Y
),
261 [REG_TYPE_VIRT_VEC2C_YZ
] = SWIZZLE(X
, X
, Y
, Y
),
262 [REG_TYPE_VIRT_VEC3_XYZ
] = INST_SWIZ_IDENTITY
,
263 [REG_TYPE_VIRT_VEC3C_XYZ
] = INST_SWIZ_IDENTITY
,
264 [REG_TYPE_VIRT_SCALAR_W
] = SWIZZLE(X
, X
, X
, X
),
265 [REG_TYPE_VIRT_VEC2_XW
] = SWIZZLE(X
, X
, Y
, Y
),
266 [REG_TYPE_VIRT_VEC2_YW
] = SWIZZLE(X
, X
, Y
, Y
),
267 [REG_TYPE_VIRT_VEC3_XYW
] = SWIZZLE(X
, Y
, Z
, Z
),
268 [REG_TYPE_VIRT_VEC2_ZW
] = SWIZZLE(X
, X
, X
, Y
),
269 [REG_TYPE_VIRT_VEC2T_ZW
] = SWIZZLE(X
, X
, X
, Y
),
270 [REG_TYPE_VIRT_VEC2C_ZW
] = SWIZZLE(X
, X
, X
, Y
),
271 [REG_TYPE_VIRT_VEC3_XZW
] = SWIZZLE(X
, Y
, Y
, Z
),
272 [REG_TYPE_VIRT_VEC3_YZW
] = SWIZZLE(X
, X
, Y
, Z
),
273 [REG_TYPE_VIRT_VEC3C_YZW
] = SWIZZLE(X
, X
, Y
, Z
),
276 static inline int reg_get_type(int virt_reg
)
278 return virt_reg
% NUM_REG_TYPES
;
281 static inline int reg_get_base(struct state
*state
, int virt_reg
)
283 /* offset by 1 to avoid reserved position register */
284 if (state
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
)
285 return (virt_reg
/ NUM_REG_TYPES
+ 1) % ETNA_MAX_TEMPS
;
286 return virt_reg
/ NUM_REG_TYPES
;
289 /* use "r63.z" for depth reg, it will wrap around to r0.z by reg_get_base
290 * (fs registers are offset by 1 to avoid reserving r0)
292 #define REG_FRAG_DEPTH ((ETNA_MAX_TEMPS - 1) * NUM_REG_TYPES + REG_TYPE_VIRT_SCALAR_Z)
294 static inline int reg_get_class(int virt_reg
)
296 switch (reg_get_type(virt_reg
)) {
298 return REG_CLASS_VEC4
;
299 case REG_TYPE_VIRT_VEC3_XYZ
:
300 case REG_TYPE_VIRT_VEC3_XYW
:
301 case REG_TYPE_VIRT_VEC3_XZW
:
302 case REG_TYPE_VIRT_VEC3_YZW
:
303 return REG_CLASS_VIRT_VEC3
;
304 case REG_TYPE_VIRT_VEC2_XY
:
305 case REG_TYPE_VIRT_VEC2_XZ
:
306 case REG_TYPE_VIRT_VEC2_XW
:
307 case REG_TYPE_VIRT_VEC2_YZ
:
308 case REG_TYPE_VIRT_VEC2_YW
:
309 case REG_TYPE_VIRT_VEC2_ZW
:
310 return REG_CLASS_VIRT_VEC2
;
311 case REG_TYPE_VIRT_SCALAR_X
:
312 case REG_TYPE_VIRT_SCALAR_Y
:
313 case REG_TYPE_VIRT_SCALAR_Z
:
314 case REG_TYPE_VIRT_SCALAR_W
:
315 return REG_CLASS_VIRT_SCALAR
;
316 case REG_TYPE_VIRT_VEC2T_XY
:
317 case REG_TYPE_VIRT_VEC2T_ZW
:
318 return REG_CLASS_VIRT_VEC2T
;
319 case REG_TYPE_VIRT_VEC2C_XY
:
320 case REG_TYPE_VIRT_VEC2C_YZ
:
321 case REG_TYPE_VIRT_VEC2C_ZW
:
322 return REG_CLASS_VIRT_VEC2C
;
323 case REG_TYPE_VIRT_VEC3C_XYZ
:
324 case REG_TYPE_VIRT_VEC3C_YZW
:
325 return REG_CLASS_VIRT_VEC3C
;
332 /* get unique ssa/reg index for nir_src */
334 src_index(nir_function_impl
*impl
, nir_src
*src
)
336 return src
->is_ssa
? src
->ssa
->index
: (src
->reg
.reg
->index
+ impl
->ssa_alloc
);
339 /* get unique ssa/reg index for nir_dest */
341 dest_index(nir_function_impl
*impl
, nir_dest
*dest
)
343 return dest
->is_ssa
? dest
->ssa
.index
: (dest
->reg
.reg
->index
+ impl
->ssa_alloc
);
346 /* nir_src to allocated register */
348 ra_src(struct state
*state
, nir_src
*src
)
350 unsigned reg
= ra_get_node_reg(state
->g
, state
->live_map
[src_index(state
->impl
, src
)]);
351 return SRC_REG(reg_get_base(state
, reg
), reg_swiz
[reg_get_type(reg
)]);
355 get_src(struct state
*state
, nir_src
*src
)
358 return ra_src(state
, src
);
360 nir_instr
*instr
= src
->ssa
->parent_instr
;
362 if (instr
->pass_flags
& BYPASS_SRC
) {
363 assert(instr
->type
== nir_instr_type_alu
);
364 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
365 assert(alu
->op
== nir_op_mov
);
366 return src_swizzle(get_src(state
, &alu
->src
[0].src
), ALU_SWIZ(&alu
->src
[0]));
369 switch (instr
->type
) {
370 case nir_instr_type_load_const
:
371 return const_src(state
, nir_instr_as_load_const(instr
)->value
, src
->ssa
->num_components
);
372 case nir_instr_type_intrinsic
: {
373 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
374 switch (intr
->intrinsic
) {
375 case nir_intrinsic_load_input
:
376 case nir_intrinsic_load_instance_id
:
377 case nir_intrinsic_load_uniform
:
378 case nir_intrinsic_load_ubo
:
379 return ra_src(state
, src
);
380 case nir_intrinsic_load_front_face
:
381 return (hw_src
) { .use
= 1, .rgroup
= INST_RGROUP_INTERNAL
};
382 case nir_intrinsic_load_frag_coord
:
383 return SRC_REG(0, INST_SWIZ_IDENTITY
);
385 compile_error(state
->c
, "Unhandled NIR intrinsic type: %s\n",
386 nir_intrinsic_infos
[intr
->intrinsic
].name
);
390 case nir_instr_type_alu
:
391 case nir_instr_type_tex
:
392 return ra_src(state
, src
);
393 case nir_instr_type_ssa_undef
: {
394 /* return zero to deal with broken Blur demo */
395 nir_const_value value
= CONST(0);
396 return src_swizzle(const_src(state
, &value
, 1), SWIZZLE(X
,X
,X
,X
));
399 compile_error(state
->c
, "Unhandled NIR instruction type: %d\n", instr
->type
);
407 update_swiz_mask(nir_alu_instr
*alu
, nir_dest
*dest
, unsigned *swiz
, unsigned *mask
)
412 bool is_vec
= dest
!= NULL
;
413 unsigned swizzle
= 0, write_mask
= 0;
414 for (unsigned i
= 0; i
< 4; i
++) {
415 /* channel not written */
416 if (!(alu
->dest
.write_mask
& (1 << i
)))
418 /* src is different (only check for vecN) */
419 if (is_vec
&& alu
->src
[i
].src
.ssa
!= &dest
->ssa
)
422 unsigned src_swiz
= is_vec
? alu
->src
[i
].swizzle
[0] : alu
->src
[0].swizzle
[i
];
423 swizzle
|= (*swiz
>> src_swiz
* 2 & 3) << i
* 2;
424 /* this channel isn't written through this chain */
425 if (*mask
& (1 << src_swiz
))
426 write_mask
|= 1 << i
;
433 vec_dest_has_swizzle(nir_alu_instr
*vec
, nir_ssa_def
*ssa
)
435 for (unsigned i
= 0; i
< 4; i
++) {
436 if (!(vec
->dest
.write_mask
& (1 << i
)) || vec
->src
[i
].src
.ssa
!= ssa
)
439 if (vec
->src
[i
].swizzle
[0] != i
)
443 /* don't deal with possible bypassed vec/mov chain */
444 nir_foreach_use(use_src
, ssa
) {
445 nir_instr
*instr
= use_src
->parent_instr
;
446 if (instr
->type
!= nir_instr_type_alu
)
449 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
465 real_dest(nir_dest
*dest
, unsigned *swiz
, unsigned *mask
)
467 if (!dest
|| !dest
->is_ssa
)
470 bool can_bypass_src
= !list_length(&dest
->ssa
.if_uses
);
471 nir_instr
*p_instr
= dest
->ssa
.parent_instr
;
473 /* if used by a vecN, the "real" destination becomes the vecN destination
474 * lower_alu guarantees that values used by a vecN are only used by that vecN
475 * we can apply the same logic to movs in a some cases too
477 nir_foreach_use(use_src
, &dest
->ssa
) {
478 nir_instr
*instr
= use_src
->parent_instr
;
480 /* src bypass check: for now only deal with tex src mov case
481 * note: for alu don't bypass mov for multiple uniform sources
483 switch (instr
->type
) {
484 case nir_instr_type_tex
:
485 if (p_instr
->type
== nir_instr_type_alu
&&
486 nir_instr_as_alu(p_instr
)->op
== nir_op_mov
) {
490 can_bypass_src
= false;
494 if (instr
->type
!= nir_instr_type_alu
)
497 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
503 assert(list_length(&dest
->ssa
.if_uses
) == 0);
504 nir_foreach_use(use_src
, &dest
->ssa
)
505 assert(use_src
->parent_instr
== instr
);
507 update_swiz_mask(alu
, dest
, swiz
, mask
);
510 switch (dest
->ssa
.parent_instr
->type
) {
511 case nir_instr_type_alu
:
512 case nir_instr_type_tex
:
517 if (list_length(&dest
->ssa
.if_uses
) || list_length(&dest
->ssa
.uses
) > 1)
520 update_swiz_mask(alu
, NULL
, swiz
, mask
);
527 assert(!(instr
->pass_flags
& BYPASS_SRC
));
528 instr
->pass_flags
|= BYPASS_DST
;
529 return real_dest(&alu
->dest
.dest
, swiz
, mask
);
532 if (can_bypass_src
&& !(p_instr
->pass_flags
& BYPASS_DST
)) {
533 p_instr
->pass_flags
|= BYPASS_SRC
;
540 /* get allocated dest register for nir_dest
541 * *p_swiz tells how the components need to be placed into register
544 ra_dest(struct state
*state
, nir_dest
*dest
, unsigned *p_swiz
)
546 unsigned swiz
= INST_SWIZ_IDENTITY
, mask
= 0xf;
547 dest
= real_dest(dest
, &swiz
, &mask
);
549 unsigned r
= ra_get_node_reg(state
->g
, state
->live_map
[dest_index(state
->impl
, dest
)]);
550 unsigned t
= reg_get_type(r
);
552 *p_swiz
= inst_swiz_compose(swiz
, reg_dst_swiz
[t
]);
556 .reg
= reg_get_base(state
, r
),
557 .write_mask
= inst_write_mask_compose(mask
, reg_writemask
[t
]),
561 /* if instruction dest needs a register, return nir_dest for it */
563 dest_for_instr(nir_instr
*instr
)
565 nir_dest
*dest
= NULL
;
567 switch (instr
->type
) {
568 case nir_instr_type_alu
:
569 dest
= &nir_instr_as_alu(instr
)->dest
.dest
;
571 case nir_instr_type_tex
:
572 dest
= &nir_instr_as_tex(instr
)->dest
;
574 case nir_instr_type_intrinsic
: {
575 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
576 if (intr
->intrinsic
== nir_intrinsic_load_uniform
||
577 intr
->intrinsic
== nir_intrinsic_load_ubo
||
578 intr
->intrinsic
== nir_intrinsic_load_input
||
579 intr
->intrinsic
== nir_intrinsic_load_instance_id
)
582 case nir_instr_type_deref
:
587 return real_dest(dest
, NULL
, NULL
);
592 nir_dest
*dest
; /* cached dest_for_instr */
593 unsigned live_start
, live_end
; /* live range */
597 range_include(struct live_def
*def
, unsigned index
)
599 if (def
->live_start
> index
)
600 def
->live_start
= index
;
601 if (def
->live_end
< index
)
602 def
->live_end
= index
;
605 struct live_defs_state
{
607 unsigned bitset_words
;
609 nir_function_impl
*impl
;
610 nir_block
*block
; /* current block pointer */
611 unsigned index
; /* current live index */
613 struct live_def
*defs
;
614 unsigned *live_map
; /* to map ssa/reg index into defs array */
616 nir_block_worklist worklist
;
620 init_liveness_block(nir_block
*block
,
621 struct live_defs_state
*state
)
623 block
->live_in
= reralloc(block
, block
->live_in
, BITSET_WORD
,
624 state
->bitset_words
);
625 memset(block
->live_in
, 0, state
->bitset_words
* sizeof(BITSET_WORD
));
627 block
->live_out
= reralloc(block
, block
->live_out
, BITSET_WORD
,
628 state
->bitset_words
);
629 memset(block
->live_out
, 0, state
->bitset_words
* sizeof(BITSET_WORD
));
631 nir_block_worklist_push_head(&state
->worklist
, block
);
637 set_src_live(nir_src
*src
, void *void_state
)
639 struct live_defs_state
*state
= void_state
;
642 nir_instr
*instr
= src
->ssa
->parent_instr
;
644 if (is_sysval(instr
) || instr
->type
== nir_instr_type_deref
)
647 switch (instr
->type
) {
648 case nir_instr_type_load_const
:
649 case nir_instr_type_ssa_undef
:
651 case nir_instr_type_alu
: {
653 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
654 if (instr
->pass_flags
& BYPASS_SRC
) {
655 for (unsigned i
= 0; i
< nir_op_infos
[alu
->op
].num_inputs
; i
++)
656 set_src_live(&alu
->src
[i
].src
, state
);
665 unsigned i
= state
->live_map
[src_index(state
->impl
, src
)];
668 BITSET_SET(state
->block
->live_in
, i
);
669 range_include(&state
->defs
[i
], state
->index
);
675 propagate_across_edge(nir_block
*pred
, nir_block
*succ
,
676 struct live_defs_state
*state
)
678 BITSET_WORD progress
= 0;
679 for (unsigned i
= 0; i
< state
->bitset_words
; ++i
) {
680 progress
|= succ
->live_in
[i
] & ~pred
->live_out
[i
];
681 pred
->live_out
[i
] |= succ
->live_in
[i
];
683 return progress
!= 0;
687 live_defs(nir_function_impl
*impl
, struct live_def
*defs
, unsigned *live_map
)
689 struct live_defs_state state
;
690 unsigned block_live_index
[impl
->num_blocks
+ 1];
694 state
.live_map
= live_map
;
697 nir_foreach_block(block
, impl
) {
698 block_live_index
[block
->index
] = state
.num_defs
;
699 nir_foreach_instr(instr
, block
) {
700 nir_dest
*dest
= dest_for_instr(instr
);
704 unsigned idx
= dest_index(impl
, dest
);
705 /* register is already in defs */
706 if (live_map
[idx
] != ~0u)
709 defs
[state
.num_defs
] = (struct live_def
) {instr
, dest
, state
.num_defs
, 0};
711 /* input live from the start */
712 if (instr
->type
== nir_instr_type_intrinsic
) {
713 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
714 if (intr
->intrinsic
== nir_intrinsic_load_input
||
715 intr
->intrinsic
== nir_intrinsic_load_instance_id
)
716 defs
[state
.num_defs
].live_start
= 0;
719 live_map
[idx
] = state
.num_defs
;
723 block_live_index
[impl
->num_blocks
] = state
.num_defs
;
725 nir_block_worklist_init(&state
.worklist
, impl
->num_blocks
, NULL
);
727 /* We now know how many unique ssa definitions we have and we can go
728 * ahead and allocate live_in and live_out sets and add all of the
729 * blocks to the worklist.
731 state
.bitset_words
= BITSET_WORDS(state
.num_defs
);
732 nir_foreach_block(block
, impl
) {
733 init_liveness_block(block
, &state
);
736 /* We're now ready to work through the worklist and update the liveness
737 * sets of each of the blocks. By the time we get to this point, every
738 * block in the function implementation has been pushed onto the
739 * worklist in reverse order. As long as we keep the worklist
740 * up-to-date as we go, everything will get covered.
742 while (!nir_block_worklist_is_empty(&state
.worklist
)) {
743 /* We pop them off in the reverse order we pushed them on. This way
744 * the first walk of the instructions is backwards so we only walk
745 * once in the case of no control flow.
747 nir_block
*block
= nir_block_worklist_pop_head(&state
.worklist
);
750 memcpy(block
->live_in
, block
->live_out
,
751 state
.bitset_words
* sizeof(BITSET_WORD
));
753 state
.index
= block_live_index
[block
->index
+ 1];
755 nir_if
*following_if
= nir_block_get_following_if(block
);
757 set_src_live(&following_if
->condition
, &state
);
759 nir_foreach_instr_reverse(instr
, block
) {
760 /* when we come across the next "live" instruction, decrement index */
761 if (state
.index
&& instr
== defs
[state
.index
- 1].instr
) {
763 /* the only source of writes to registers is phis:
764 * we don't expect any partial write_mask alus
765 * so clearing live_in here is OK
767 BITSET_CLEAR(block
->live_in
, state
.index
);
770 /* don't set_src_live for not-emitted instructions */
771 if (instr
->pass_flags
)
774 unsigned index
= state
.index
;
776 /* output live till the end */
777 if (instr
->type
== nir_instr_type_intrinsic
) {
778 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
779 if (intr
->intrinsic
== nir_intrinsic_store_deref
)
783 nir_foreach_src(instr
, set_src_live
, &state
);
787 assert(state
.index
== block_live_index
[block
->index
]);
789 /* Walk over all of the predecessors of the current block updating
790 * their live in with the live out of this one. If anything has
791 * changed, add the predecessor to the work list so that we ensure
792 * that the new information is used.
794 set_foreach(block
->predecessors
, entry
) {
795 nir_block
*pred
= (nir_block
*)entry
->key
;
796 if (propagate_across_edge(pred
, block
, &state
))
797 nir_block_worklist_push_tail(&state
.worklist
, pred
);
801 nir_block_worklist_fini(&state
.worklist
);
803 /* apply live_in/live_out to ranges */
805 nir_foreach_block(block
, impl
) {
808 BITSET_FOREACH_SET(i
, block
->live_in
, state
.num_defs
)
809 range_include(&state
.defs
[i
], block_live_index
[block
->index
]);
811 BITSET_FOREACH_SET(i
, block
->live_out
, state
.num_defs
)
812 range_include(&state
.defs
[i
], block_live_index
[block
->index
+ 1]);
815 return state
.num_defs
;
818 /* precomputed by register_allocate */
819 static unsigned int *q_values
[] = {
820 (unsigned int[]) {1, 2, 3, 4, 2, 2, 3, },
821 (unsigned int[]) {3, 5, 6, 6, 5, 5, 6, },
822 (unsigned int[]) {3, 4, 4, 4, 4, 4, 4, },
823 (unsigned int[]) {1, 1, 1, 1, 1, 1, 1, },
824 (unsigned int[]) {1, 2, 2, 2, 1, 2, 2, },
825 (unsigned int[]) {2, 3, 3, 3, 2, 3, 3, },
826 (unsigned int[]) {2, 2, 2, 2, 2, 2, 2, },
830 ra_assign(struct state
*state
, nir_shader
*shader
)
832 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, ETNA_MAX_TEMPS
*
833 NUM_REG_TYPES
, false);
835 /* classes always be created from index 0, so equal to the class enum
836 * which represents a register with (c+1) components
838 for (int c
= 0; c
< NUM_REG_CLASSES
; c
++)
839 ra_alloc_reg_class(regs
);
840 /* add each register of each class */
841 for (int r
= 0; r
< NUM_REG_TYPES
* ETNA_MAX_TEMPS
; r
++)
842 ra_class_add_reg(regs
, reg_get_class(r
), r
);
844 for (int r
= 0; r
< ETNA_MAX_TEMPS
; r
++) {
845 for (int i
= 0; i
< NUM_REG_TYPES
; i
++) {
846 for (int j
= 0; j
< i
; j
++) {
847 if (reg_writemask
[i
] & reg_writemask
[j
]) {
848 ra_add_reg_conflict(regs
, NUM_REG_TYPES
* r
+ i
,
849 NUM_REG_TYPES
* r
+ j
);
854 ra_set_finalize(regs
, q_values
);
856 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
858 /* liveness and interference */
860 nir_index_blocks(impl
);
861 nir_index_ssa_defs(impl
);
862 nir_foreach_block(block
, impl
) {
863 nir_foreach_instr(instr
, block
)
864 instr
->pass_flags
= 0;
867 /* this gives an approximation/upper limit on how many nodes are needed
868 * (some ssa values do not represent an allocated register)
870 unsigned max_nodes
= impl
->ssa_alloc
+ impl
->reg_alloc
;
871 unsigned *live_map
= ralloc_array(NULL
, unsigned, max_nodes
);
872 memset(live_map
, 0xff, sizeof(unsigned) * max_nodes
);
873 struct live_def
*defs
= rzalloc_array(NULL
, struct live_def
, max_nodes
);
875 unsigned num_nodes
= live_defs(impl
, defs
, live_map
);
876 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, num_nodes
);
878 /* set classes from num_components */
879 for (unsigned i
= 0; i
< num_nodes
; i
++) {
880 nir_instr
*instr
= defs
[i
].instr
;
881 nir_dest
*dest
= defs
[i
].dest
;
882 unsigned c
= nir_dest_num_components(*dest
) - 1;
884 if (instr
->type
== nir_instr_type_alu
&&
885 state
->c
->specs
->has_new_transcendentals
) {
886 switch (nir_instr_as_alu(instr
)->op
) {
891 assert(dest
->is_ssa
);
892 c
= REG_CLASS_VIRT_VEC2T
;
898 if (instr
->type
== nir_instr_type_intrinsic
) {
899 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
900 /* can't have dst swizzle or sparse writemask on UBO loads */
901 if (intr
->intrinsic
== nir_intrinsic_load_ubo
) {
902 assert(dest
== &intr
->dest
);
903 if (dest
->ssa
.num_components
== 2)
904 c
= REG_CLASS_VIRT_VEC2C
;
905 if (dest
->ssa
.num_components
== 3)
906 c
= REG_CLASS_VIRT_VEC3C
;
910 ra_set_node_class(g
, i
, c
);
913 nir_foreach_block(block
, impl
) {
914 nir_foreach_instr(instr
, block
) {
915 if (instr
->type
!= nir_instr_type_intrinsic
)
918 nir_dest
*dest
= dest_for_instr(instr
);
919 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
922 switch (intr
->intrinsic
) {
923 case nir_intrinsic_store_deref
: {
924 /* don't want outputs to be swizzled
925 * TODO: better would be to set the type to X/XY/XYZ/XYZW
926 * TODO: what if fragcoord.z is read after writing fragdepth?
928 nir_deref_instr
*deref
= nir_src_as_deref(intr
->src
[0]);
929 unsigned index
= live_map
[src_index(impl
, &intr
->src
[1])];
931 if (shader
->info
.stage
== MESA_SHADER_FRAGMENT
&&
932 deref
->var
->data
.location
== FRAG_RESULT_DEPTH
) {
933 ra_set_node_reg(g
, index
, REG_FRAG_DEPTH
);
935 ra_set_node_class(g
, index
, REG_CLASS_VEC4
);
938 case nir_intrinsic_load_input
:
939 reg
= nir_intrinsic_base(intr
) * NUM_REG_TYPES
+ (unsigned[]) {
940 REG_TYPE_VIRT_SCALAR_X
,
941 REG_TYPE_VIRT_VEC2_XY
,
942 REG_TYPE_VIRT_VEC3_XYZ
,
944 }[nir_dest_num_components(*dest
) - 1];
946 case nir_intrinsic_load_instance_id
:
947 reg
= state
->c
->variant
->infile
.num_reg
* NUM_REG_TYPES
+ REG_TYPE_VIRT_SCALAR_Y
;
953 ra_set_node_reg(g
, live_map
[dest_index(impl
, dest
)], reg
);
957 /* add interference for intersecting live ranges */
958 for (unsigned i
= 0; i
< num_nodes
; i
++) {
959 assert(defs
[i
].live_start
< defs
[i
].live_end
);
960 for (unsigned j
= 0; j
< i
; j
++) {
961 if (defs
[i
].live_start
>= defs
[j
].live_end
|| defs
[j
].live_start
>= defs
[i
].live_end
)
963 ra_add_node_interference(g
, i
, j
);
969 /* Allocate registers */
970 ASSERTED
bool ok
= ra_allocate(g
);
975 state
->live_map
= live_map
;
976 state
->num_nodes
= num_nodes
;
980 ra_finish(struct state
*state
)
982 /* TODO: better way to get number of registers used? */
984 for (unsigned i
= 0; i
< state
->num_nodes
; i
++) {
985 j
= MAX2(j
, reg_get_base(state
, ra_get_node_reg(state
->g
, i
)) + 1);
988 ralloc_free(state
->g
);
989 ralloc_free(state
->regs
);
990 ralloc_free(state
->live_map
);
996 emit_alu(struct state
*state
, nir_alu_instr
* alu
)
998 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1000 /* marked as dead instruction (vecN and other bypassed instr) */
1001 if (alu
->instr
.pass_flags
)
1004 assert(!(alu
->op
>= nir_op_vec2
&& alu
->op
<= nir_op_vec4
));
1007 hw_dst dst
= ra_dest(state
, &alu
->dest
.dest
, &dst_swiz
);
1009 /* compose alu write_mask with RA write mask */
1010 if (!alu
->dest
.dest
.is_ssa
)
1011 dst
.write_mask
= inst_write_mask_compose(alu
->dest
.write_mask
, dst
.write_mask
);
1017 /* not per-component - don't compose dst_swiz */
1018 dst_swiz
= INST_SWIZ_IDENTITY
;
1026 for (int i
= 0; i
< info
->num_inputs
; i
++) {
1027 nir_alu_src
*asrc
= &alu
->src
[i
];
1030 src
= src_swizzle(get_src(state
, &asrc
->src
), ALU_SWIZ(asrc
));
1031 src
= src_swizzle(src
, dst_swiz
);
1033 if (src
.rgroup
!= INST_RGROUP_IMMEDIATE
) {
1034 src
.neg
= asrc
->negate
|| (alu
->op
== nir_op_fneg
);
1035 src
.abs
= asrc
->abs
|| (alu
->op
== nir_op_fabs
);
1037 assert(!asrc
->negate
&& alu
->op
!= nir_op_fneg
);
1038 assert(!asrc
->abs
&& alu
->op
!= nir_op_fabs
);
1044 emit(alu
, alu
->op
, dst
, srcs
, alu
->dest
.saturate
|| (alu
->op
== nir_op_fsat
));
1048 emit_tex(struct state
*state
, nir_tex_instr
* tex
)
1051 hw_dst dst
= ra_dest(state
, &tex
->dest
, &dst_swiz
);
1052 nir_src
*coord
= NULL
, *lod_bias
= NULL
, *compare
= NULL
;
1054 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
1055 switch (tex
->src
[i
].src_type
) {
1056 case nir_tex_src_coord
:
1057 coord
= &tex
->src
[i
].src
;
1059 case nir_tex_src_bias
:
1060 case nir_tex_src_lod
:
1062 lod_bias
= &tex
->src
[i
].src
;
1064 case nir_tex_src_comparator
:
1065 compare
= &tex
->src
[i
].src
;
1068 compile_error(state
->c
, "Unhandled NIR tex src type: %d\n",
1069 tex
->src
[i
].src_type
);
1074 emit(tex
, tex
->op
, tex
->sampler_index
, dst_swiz
, dst
, get_src(state
, coord
),
1075 lod_bias
? get_src(state
, lod_bias
) : SRC_DISABLE
,
1076 compare
? get_src(state
, compare
) : SRC_DISABLE
);
1080 emit_intrinsic(struct state
*state
, nir_intrinsic_instr
* intr
)
1082 switch (intr
->intrinsic
) {
1083 case nir_intrinsic_store_deref
:
1084 emit(output
, nir_src_as_deref(intr
->src
[0])->var
, get_src(state
, &intr
->src
[1]));
1086 case nir_intrinsic_discard_if
:
1087 emit(discard
, get_src(state
, &intr
->src
[0]));
1089 case nir_intrinsic_discard
:
1090 emit(discard
, SRC_DISABLE
);
1092 case nir_intrinsic_load_uniform
: {
1094 struct etna_inst_dst dst
= ra_dest(state
, &intr
->dest
, &dst_swiz
);
1096 /* TODO: rework so extra MOV isn't required, load up to 4 addresses at once */
1097 emit_inst(state
->c
, &(struct etna_inst
) {
1098 .opcode
= INST_OPCODE_MOVAR
,
1099 .dst
.write_mask
= 0x1,
1100 .src
[2] = get_src(state
, &intr
->src
[0]),
1102 emit_inst(state
->c
, &(struct etna_inst
) {
1103 .opcode
= INST_OPCODE_MOV
,
1107 .rgroup
= INST_RGROUP_UNIFORM_0
,
1108 .reg
= nir_intrinsic_base(intr
),
1110 .amode
= INST_AMODE_ADD_A_X
,
1114 case nir_intrinsic_load_ubo
: {
1115 /* TODO: if offset is of the form (x + C) then add C to the base instead */
1116 unsigned idx
= nir_src_as_const_value(intr
->src
[0])[0].u32
;
1118 emit_inst(state
->c
, &(struct etna_inst
) {
1119 .opcode
= INST_OPCODE_LOAD
,
1120 .type
= INST_TYPE_U32
,
1121 .dst
= ra_dest(state
, &intr
->dest
, &dst_swiz
),
1122 .src
[0] = get_src(state
, &intr
->src
[1]),
1123 .src
[1] = const_src(state
, &CONST_VAL(ETNA_IMMEDIATE_UBO0_ADDR
+ idx
, 0), 1),
1126 case nir_intrinsic_load_front_face
:
1127 case nir_intrinsic_load_frag_coord
:
1128 assert(intr
->dest
.is_ssa
); /* TODO - lower phis could cause this */
1130 case nir_intrinsic_load_input
:
1131 case nir_intrinsic_load_instance_id
:
1134 compile_error(state
->c
, "Unhandled NIR intrinsic type: %s\n",
1135 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1140 emit_instr(struct state
*state
, nir_instr
* instr
)
1142 switch (instr
->type
) {
1143 case nir_instr_type_alu
:
1144 emit_alu(state
, nir_instr_as_alu(instr
));
1146 case nir_instr_type_tex
:
1147 emit_tex(state
, nir_instr_as_tex(instr
));
1149 case nir_instr_type_intrinsic
:
1150 emit_intrinsic(state
, nir_instr_as_intrinsic(instr
));
1152 case nir_instr_type_jump
:
1153 assert(nir_instr_is_last(instr
));
1154 case nir_instr_type_load_const
:
1155 case nir_instr_type_ssa_undef
:
1156 case nir_instr_type_deref
:
1159 compile_error(state
->c
, "Unhandled NIR instruction type: %d\n", instr
->type
);
1165 emit_block(struct state
*state
, nir_block
* block
)
1167 emit(block_start
, block
->index
);
1169 nir_foreach_instr(instr
, block
)
1170 emit_instr(state
, instr
);
1172 /* succs->index < block->index is for the loop case */
1173 nir_block
*succs
= block
->successors
[0];
1174 if (nir_block_ends_in_jump(block
) || succs
->index
< block
->index
)
1175 emit(jump
, succs
->index
, SRC_DISABLE
);
1179 emit_cf_list(struct state
*state
, struct exec_list
*list
);
1182 emit_if(struct state
*state
, nir_if
* nif
)
1184 emit(jump
, nir_if_first_else_block(nif
)->index
, get_src(state
, &nif
->condition
));
1185 emit_cf_list(state
, &nif
->then_list
);
1187 /* jump at end of then_list to skip else_list
1188 * not needed if then_list already ends with a jump or else_list is empty
1190 if (!nir_block_ends_in_jump(nir_if_last_then_block(nif
)) &&
1191 !nir_cf_list_is_empty_block(&nif
->else_list
))
1192 emit(jump
, nir_if_last_else_block(nif
)->successors
[0]->index
, SRC_DISABLE
);
1194 emit_cf_list(state
, &nif
->else_list
);
1198 emit_cf_list(struct state
*state
, struct exec_list
*list
)
1200 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1201 switch (node
->type
) {
1202 case nir_cf_node_block
:
1203 emit_block(state
, nir_cf_node_as_block(node
));
1205 case nir_cf_node_if
:
1206 emit_if(state
, nir_cf_node_as_if(node
));
1208 case nir_cf_node_loop
:
1209 emit_cf_list(state
, &nir_cf_node_as_loop(node
)->body
);
1212 compile_error(state
->c
, "Unknown NIR node type\n");
1218 /* based on nir_lower_vec_to_movs */
1220 insert_vec_mov(nir_alu_instr
*vec
, unsigned start_idx
, nir_shader
*shader
)
1222 assert(start_idx
< nir_op_infos
[vec
->op
].num_inputs
);
1223 unsigned write_mask
= (1u << start_idx
);
1225 nir_alu_instr
*mov
= nir_alu_instr_create(shader
, nir_op_mov
);
1226 nir_alu_src_copy(&mov
->src
[0], &vec
->src
[start_idx
], mov
);
1228 mov
->src
[0].swizzle
[0] = vec
->src
[start_idx
].swizzle
[0];
1229 mov
->src
[0].negate
= vec
->src
[start_idx
].negate
;
1230 mov
->src
[0].abs
= vec
->src
[start_idx
].abs
;
1232 unsigned num_components
= 1;
1234 for (unsigned i
= start_idx
+ 1; i
< 4; i
++) {
1235 if (!(vec
->dest
.write_mask
& (1 << i
)))
1238 if (nir_srcs_equal(vec
->src
[i
].src
, vec
->src
[start_idx
].src
) &&
1239 vec
->src
[i
].negate
== vec
->src
[start_idx
].negate
&&
1240 vec
->src
[i
].abs
== vec
->src
[start_idx
].abs
) {
1241 write_mask
|= (1 << i
);
1242 mov
->src
[0].swizzle
[num_components
] = vec
->src
[i
].swizzle
[0];
1247 mov
->dest
.write_mask
= (1 << num_components
) - 1;
1248 nir_ssa_dest_init(&mov
->instr
, &mov
->dest
.dest
, num_components
, 32, NULL
);
1250 /* replace vec srcs with inserted mov */
1251 for (unsigned i
= 0, j
= 0; i
< 4; i
++) {
1252 if (!(write_mask
& (1 << i
)))
1255 nir_instr_rewrite_src(&vec
->instr
, &vec
->src
[i
].src
, nir_src_for_ssa(&mov
->dest
.dest
.ssa
));
1256 vec
->src
[i
].swizzle
[0] = j
++;
1259 nir_instr_insert_before(&vec
->instr
, &mov
->instr
);
1265 * for vecN instructions:
1266 * -merge constant sources into a single src
1267 * -insert movs (nir_lower_vec_to_movs equivalent)
1268 * for non-vecN instructions:
1269 * -try to merge constants as single constant
1270 * -insert movs for multiple constants (pre-HALTI5)
1273 lower_alu(struct state
*state
, nir_alu_instr
*alu
)
1275 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
1278 nir_builder_init(&b
, state
->impl
);
1279 b
.cursor
= nir_before_instr(&alu
->instr
);
1287 /* pre-GC7000L can only have 1 uniform src per instruction */
1288 if (state
->c
->specs
->halti
>= 5)
1291 nir_const_value value
[4] = {};
1292 uint8_t swizzle
[4][4] = {};
1293 unsigned swiz_max
= 0, num_const
= 0;
1295 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
1296 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
1300 unsigned num_components
= info
->input_sizes
[i
] ?: alu
->dest
.dest
.ssa
.num_components
;
1301 for (unsigned j
= 0; j
< num_components
; j
++) {
1302 int idx
= const_add(&value
[0].u64
, cv
[alu
->src
[i
].swizzle
[j
]].u64
);
1303 swizzle
[i
][j
] = idx
;
1304 swiz_max
= MAX2(swiz_max
, (unsigned) idx
);
1313 /* resolve with single combined const src */
1315 nir_ssa_def
*def
= nir_build_imm(&b
, swiz_max
+ 1, 32, value
);
1317 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
1318 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
1322 nir_instr_rewrite_src(&alu
->instr
, &alu
->src
[i
].src
, nir_src_for_ssa(def
));
1324 for (unsigned j
= 0; j
< 4; j
++)
1325 alu
->src
[i
].swizzle
[j
] = swizzle
[i
][j
];
1330 /* resolve with movs */
1332 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
1333 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
1341 nir_ssa_def
*mov
= nir_mov(&b
, alu
->src
[i
].src
.ssa
);
1342 nir_instr_rewrite_src(&alu
->instr
, &alu
->src
[i
].src
, nir_src_for_ssa(mov
));
1347 nir_const_value value
[4];
1348 unsigned num_components
= 0;
1350 for (unsigned i
= 0; i
< info
->num_inputs
; i
++) {
1351 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
1353 value
[num_components
++] = cv
[alu
->src
[i
].swizzle
[0]];
1356 /* if there is more than one constant source to the vecN, combine them
1357 * into a single load_const (removing the vecN completely if all components
1360 if (num_components
> 1) {
1361 nir_ssa_def
*def
= nir_build_imm(&b
, num_components
, 32, value
);
1363 if (num_components
== info
->num_inputs
) {
1364 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(def
));
1365 nir_instr_remove(&alu
->instr
);
1369 for (unsigned i
= 0, j
= 0; i
< info
->num_inputs
; i
++) {
1370 nir_const_value
*cv
= nir_src_as_const_value(alu
->src
[i
].src
);
1374 nir_instr_rewrite_src(&alu
->instr
, &alu
->src
[i
].src
, nir_src_for_ssa(def
));
1375 alu
->src
[i
].swizzle
[0] = j
++;
1379 unsigned finished_write_mask
= 0;
1380 for (unsigned i
= 0; i
< 4; i
++) {
1381 if (!(alu
->dest
.write_mask
& (1 << i
)))
1384 nir_ssa_def
*ssa
= alu
->src
[i
].src
.ssa
;
1386 /* check that vecN instruction is only user of this */
1387 bool need_mov
= list_length(&ssa
->if_uses
) != 0;
1388 nir_foreach_use(use_src
, ssa
) {
1389 if (use_src
->parent_instr
!= &alu
->instr
)
1393 nir_instr
*instr
= ssa
->parent_instr
;
1394 switch (instr
->type
) {
1395 case nir_instr_type_alu
:
1396 case nir_instr_type_tex
:
1398 case nir_instr_type_intrinsic
:
1399 if (nir_instr_as_intrinsic(instr
)->intrinsic
== nir_intrinsic_load_input
) {
1400 need_mov
= vec_dest_has_swizzle(alu
, &nir_instr_as_intrinsic(instr
)->dest
.ssa
);
1407 if (need_mov
&& !(finished_write_mask
& (1 << i
)))
1408 finished_write_mask
|= insert_vec_mov(alu
, i
, state
->shader
);
1413 emit_shader(struct etna_compile
*c
, unsigned *num_temps
, unsigned *num_consts
)
1415 nir_shader
*shader
= c
->nir
;
1417 struct state state
= {
1420 .impl
= nir_shader_get_entrypoint(shader
),
1422 bool have_indirect_uniform
= false;
1423 unsigned indirect_max
= 0;
1426 nir_builder_init(&b
, state
.impl
);
1428 /* convert non-dynamic uniform loads to constants, etc */
1429 nir_foreach_block(block
, state
.impl
) {
1430 nir_foreach_instr_safe(instr
, block
) {
1431 switch(instr
->type
) {
1432 case nir_instr_type_alu
:
1433 /* deals with vecN and const srcs */
1434 lower_alu(&state
, nir_instr_as_alu(instr
));
1436 case nir_instr_type_load_const
: {
1437 nir_load_const_instr
*load_const
= nir_instr_as_load_const(instr
);
1438 for (unsigned i
= 0; i
< load_const
->def
.num_components
; i
++)
1439 load_const
->value
[i
] = CONST(load_const
->value
[i
].u32
);
1441 case nir_instr_type_intrinsic
: {
1442 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1443 /* TODO: load_ubo can also become a constant in some cases
1444 * (at the moment it can end up emitting a LOAD with two
1445 * uniform sources, which could be a problem on HALTI2)
1447 if (intr
->intrinsic
!= nir_intrinsic_load_uniform
)
1449 nir_const_value
*off
= nir_src_as_const_value(intr
->src
[0]);
1450 if (!off
|| off
[0].u64
>> 32 != ETNA_IMMEDIATE_CONSTANT
) {
1451 have_indirect_uniform
= true;
1452 indirect_max
= nir_intrinsic_base(intr
) + nir_intrinsic_range(intr
);
1456 unsigned base
= nir_intrinsic_base(intr
);
1457 /* pre halti2 uniform offset will be float */
1458 if (c
->specs
->halti
< 2)
1459 base
+= (unsigned) off
[0].f32
;
1462 nir_const_value value
[4];
1464 for (unsigned i
= 0; i
< intr
->dest
.ssa
.num_components
; i
++) {
1465 if (nir_intrinsic_base(intr
) < 0)
1466 value
[i
] = TEXSCALE(~nir_intrinsic_base(intr
), i
);
1468 value
[i
] = UNIFORM(base
* 4 + i
);
1471 b
.cursor
= nir_after_instr(instr
);
1472 nir_ssa_def
*def
= nir_build_imm(&b
, intr
->dest
.ssa
.num_components
, 32, value
);
1474 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(def
));
1475 nir_instr_remove(instr
);
1483 /* TODO: only emit required indirect uniform ranges */
1484 if (have_indirect_uniform
) {
1485 for (unsigned i
= 0; i
< indirect_max
* 4; i
++)
1486 c
->consts
[i
] = UNIFORM(i
).u64
;
1487 state
.const_count
= indirect_max
;
1490 /* add mov for any store output using sysval/const */
1491 nir_foreach_block(block
, state
.impl
) {
1492 nir_foreach_instr_safe(instr
, block
) {
1493 if (instr
->type
!= nir_instr_type_intrinsic
)
1496 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
1498 switch (intr
->intrinsic
) {
1499 case nir_intrinsic_store_deref
: {
1500 nir_src
*src
= &intr
->src
[1];
1501 if (nir_src_is_const(*src
) || is_sysval(src
->ssa
->parent_instr
)) {
1502 b
.cursor
= nir_before_instr(instr
);
1503 nir_instr_rewrite_src(instr
, src
, nir_src_for_ssa(nir_mov(&b
, src
->ssa
)));
1512 /* call directly to avoid validation (load_const don't pass validation at this point) */
1513 nir_convert_from_ssa(shader
, true);
1514 nir_opt_dce(shader
);
1516 ra_assign(&state
, shader
);
1518 emit_cf_list(&state
, &nir_shader_get_entrypoint(shader
)->body
);
1520 *num_temps
= ra_finish(&state
);
1521 *num_consts
= state
.const_count
;