2 * Copyright (c) 2016 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Christian Gmeiner <christian.gmeiner@gmail.com>
27 #include "etnaviv_disasm.h"
28 #include "etnaviv_asm.h"
35 #include "hw/isa.xml.h"
36 #include "util/u_math.h"
37 #include "util/u_half.h"
45 uint32_t dst_amode
: 3;
47 uint32_t dst_comps
: 4;
51 uint32_t tex_amode
: 3;
52 uint32_t tex_swiz
: 8;
53 uint32_t src0_use
: 1;
54 uint32_t src0_reg
: 9;
55 uint32_t type_bit2
: 1;
56 uint32_t src0_swiz
: 8;
57 uint32_t src0_neg
: 1;
58 uint32_t src0_abs
: 1;
61 uint32_t src0_amode
: 3;
62 uint32_t src0_rgroup
: 3;
63 uint32_t src1_use
: 1;
64 uint32_t src1_reg
: 9;
65 uint32_t opcode_bit6
: 1;
66 uint32_t src1_swiz
: 8;
67 uint32_t src1_neg
: 1;
68 uint32_t src1_abs
: 1;
69 uint32_t src1_amode
: 3;
70 uint32_t type_bit01
: 2;
75 uint32_t src1_rgroup
: 3;
76 uint32_t src2_use
: 1;
77 uint32_t src2_reg
: 9;
79 uint32_t src2_swiz
: 8;
80 uint32_t src2_neg
: 1;
81 uint32_t src2_abs
: 1;
83 uint32_t src2_amode
: 3;
84 uint32_t src2_rgroup
: 3;
85 uint32_t dst_full
: 1;
91 struct etna_inst_dst
*dst
;
92 struct etna_inst_tex
*tex
;
93 struct etna_inst_src
*src0
;
94 struct etna_inst_src
*src1
;
95 struct etna_inst_src
*src2
;
101 printf_type(uint8_t type
)
105 /* as f32 is the default print nothing */
143 print_condition(uint8_t condition
)
146 case INST_CONDITION_TRUE
:
149 case INST_CONDITION_GT
:
153 case INST_CONDITION_LT
:
157 case INST_CONDITION_GE
:
161 case INST_CONDITION_LE
:
165 case INST_CONDITION_EQ
:
169 case INST_CONDITION_NE
:
173 case INST_CONDITION_AND
:
177 case INST_CONDITION_OR
:
181 case INST_CONDITION_XOR
:
185 case INST_CONDITION_NOT
:
189 case INST_CONDITION_NZ
:
193 case INST_CONDITION_GEZ
:
197 case INST_CONDITION_GZ
:
201 case INST_CONDITION_LEZ
:
205 case INST_CONDITION_LZ
:
216 print_rgroup(uint8_t rgoup
)
219 case INST_RGROUP_TEMP
:
223 case INST_RGROUP_INTERNAL
:
227 case INST_RGROUP_UNIFORM_0
:
228 case INST_RGROUP_UNIFORM_1
:
238 print_components(uint8_t components
)
240 if (components
== 15)
244 if (components
& INST_COMPS_X
)
249 if (components
& INST_COMPS_Y
)
254 if (components
& INST_COMPS_Z
)
259 if (components
& INST_COMPS_W
)
266 print_swiz_comp(uint8_t swiz_comp
)
269 case INST_SWIZ_COMP_X
:
273 case INST_SWIZ_COMP_Y
:
277 case INST_SWIZ_COMP_Z
:
281 case INST_SWIZ_COMP_W
:
292 print_swiz(uint8_t swiz
)
298 const unsigned x
= swiz
& 0x3;
299 const unsigned y
= (swiz
& 0x0C) >> 2;
300 const unsigned z
= (swiz
& 0x30) >> 4;
301 const unsigned w
= (swiz
& 0xc0) >> 6;
311 print_amode(uint8_t amode
)
314 case INST_AMODE_DIRECT
:
315 /* nothing to output */
318 case INST_AMODE_ADD_A_X
:
322 case INST_AMODE_ADD_A_Y
:
326 case INST_AMODE_ADD_A_Z
:
330 case INST_AMODE_ADD_A_W
:
341 print_dst(struct etna_inst_dst
*dst
, bool sep
)
344 printf("t%u", dst
->reg
);
345 print_amode(dst
->amode
);
346 print_components(dst
->write_mask
);
356 print_tex(struct etna_inst_tex
*tex
, bool sep
)
358 printf("tex%u", tex
->id
);
359 print_amode(tex
->amode
);
360 print_swiz(tex
->swiz
);
367 print_src(struct etna_inst_src
*src
, bool sep
)
370 if (src
->rgroup
== INST_RGROUP_IMMEDIATE
) {
371 switch (src
->imm_type
) {
373 printf("%f", uif(src
->imm_val
<< 12));
376 printf("%d", ((int) src
->imm_val
<< 12) >> 12);
378 case 2: /* unsigned */
379 printf("%d", src
->imm_val
);
382 printf("%f/%.5X", util_half_to_float(src
->imm_val
), src
->imm_val
);
392 if (src
->rgroup
== INST_RGROUP_UNIFORM_1
)
395 print_rgroup(src
->rgroup
);
396 printf("%u", src
->reg
);
397 print_amode(src
->amode
);
398 print_swiz(src
->swiz
);
412 print_opc_default(struct opc_operands
*operands
)
414 print_dst(operands
->dst
, true);
415 print_src(operands
->src0
, true);
416 print_src(operands
->src1
, true);
417 print_src(operands
->src2
, false);
421 print_opc_mov(struct opc_operands
*operands
)
424 printf("a%u", operands
->dst
->reg
);
425 print_components(operands
->dst
->write_mask
);
428 print_src(operands
->src0
, true);
429 print_src(operands
->src1
, true);
430 print_src(operands
->src2
, false);
434 print_opc_tex(struct opc_operands
*operands
)
436 print_dst(operands
->dst
, true);
437 print_tex(operands
->tex
, true);
438 print_src(operands
->src0
, true);
439 print_src(operands
->src1
, true);
440 print_src(operands
->src2
, false);
444 print_opc_imm(struct opc_operands
*operands
)
446 print_dst(operands
->dst
, true);
447 print_src(operands
->src0
, true);
448 print_src(operands
->src1
, true);
449 printf("label_%04d", operands
->imm
);
454 static const struct opc_info
{
456 void (*print
)(struct opc_operands
*operands
);
457 } opcs
[1 << OPC_BITS
] = {
458 #define OPC(opc) [INST_OPCODE_##opc] = {#opc, print_opc_default}
459 #define OPC_MOV(opc) [INST_OPCODE_##opc] = {#opc, print_opc_mov}
460 #define OPC_TEX(opc) [INST_OPCODE_##opc] = {#opc, print_opc_tex}
461 #define OPC_IMM(opc) [INST_OPCODE_##opc] = {#opc, print_opc_imm}
527 print_instr(uint32_t *dwords
, int n
, enum debug_t debug
)
529 struct instr
*instr
= (struct instr
*)dwords
;
530 const unsigned opc
= instr
->opc
| (instr
->opcode_bit6
<< 6);
531 const char *name
= opcs
[opc
].name
;
534 if (debug
& PRINT_RAW
)
535 printf("%08x %08x %08x %08x ", dwords
[0], dwords
[1], dwords
[2],
540 struct etna_inst_dst dst
= {
541 .use
= instr
->dst_use
,
542 .amode
= instr
->dst_amode
,
543 .reg
= instr
->dst_reg
,
544 .write_mask
= instr
->dst_comps
547 struct etna_inst_tex tex
= {
549 .amode
= instr
->tex_amode
,
550 .swiz
= instr
->tex_swiz
,
553 struct etna_inst_src src0
= {
554 .use
= instr
->src0_use
,
555 .neg
= instr
->src0_neg
,
556 .abs
= instr
->src0_abs
,
557 .rgroup
= instr
->src0_rgroup
,
558 .reg
= instr
->src0_reg
,
559 .swiz
= instr
->src0_swiz
,
560 .amode
= instr
->src0_amode
,
563 struct etna_inst_src src1
= {
564 .use
= instr
->src1_use
,
565 .neg
= instr
->src1_neg
,
566 .abs
= instr
->src1_abs
,
567 .rgroup
= instr
->src1_rgroup
,
568 .reg
= instr
->src1_reg
,
569 .swiz
= instr
->src1_swiz
,
570 .amode
= instr
->src1_amode
,
573 struct etna_inst_src src2
= {
574 .use
= instr
->src2_use
,
575 .neg
= instr
->src2_neg
,
576 .abs
= instr
->src2_abs
,
577 .rgroup
= instr
->src2_rgroup
,
578 .reg
= instr
->src2_reg
,
579 .swiz
= instr
->src2_swiz
,
580 .amode
= instr
->src2_amode
,
583 int imm
= (instr
->dword3
& VIV_ISA_WORD_3_SRC2_IMM__MASK
)
584 >> VIV_ISA_WORD_3_SRC2_IMM__SHIFT
;
586 struct opc_operands operands
= {
595 uint8_t type
= instr
->type_bit01
| (instr
->type_bit2
<< 2);
601 print_condition(instr
->cond
);
609 opcs
[opc
].print(&operands
);
611 printf("unknown (%d)", instr
->opc
);
618 etna_disasm(uint32_t *dwords
, int sizedwords
, enum debug_t debug
)
622 assert((sizedwords
% 2) == 0);
624 for (i
= 0; i
< sizedwords
; i
+= 4)
625 print_instr(&dwords
[i
], i
/ 4, debug
);