etnaviv: detect v4 compression
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_internal.h
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef H_ETNA_INTERNAL
25 #define H_ETNA_INTERNAL
26
27 #include <assert.h>
28 #include <stdbool.h>
29 #include <stdint.h>
30
31 #include "hw/state.xml.h"
32 #include "hw/state_3d.xml.h"
33
34 #include "drm/etnaviv_drmif.h"
35
36 #define ETNA_NUM_INPUTS (16)
37 #define ETNA_NUM_VARYINGS 8
38 #define ETNA_NUM_LOD (14)
39 #define ETNA_NUM_LAYERS (6)
40 #define ETNA_MAX_UNIFORMS (256)
41 #define ETNA_MAX_PIXELPIPES 2
42
43 /* All RS operations must have width%16 = 0 */
44 #define ETNA_RS_WIDTH_MASK (16 - 1)
45 /* RS tiled operations must have height%4 = 0 */
46 #define ETNA_RS_HEIGHT_MASK (3)
47 /* PE render targets must be aligned to 64 bytes */
48 #define ETNA_PE_ALIGNMENT (64)
49
50 /* These demarcate the margin (fixp16) between the computed sizes and the
51 value sent to the chip. These have been set to the numbers used by the
52 Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
53 am not sure whether older hardware was relying on these or they were just a
54 guess. But if so, these need to be moved to the _specs structure.
55 */
56 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
57 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
58 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
59 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
60
61 /* GPU chip 3D specs */
62 struct etna_specs {
63 /* HALTI (gross architecture) level. -1 for pre-HALTI. */
64 int halti : 8;
65 /* supports SUPERTILE (64x64) tiling? */
66 unsigned can_supertile : 1;
67 /* needs z=(z+w)/2, for older GCxxx */
68 unsigned vs_need_z_div : 1;
69 /* supports trigonometric instructions */
70 unsigned has_sin_cos_sqrt : 1;
71 /* has SIGN/FLOOR/CEIL instructions */
72 unsigned has_sign_floor_ceil : 1;
73 /* can use VS_RANGE, PS_RANGE registers*/
74 unsigned has_shader_range_registers : 1;
75 /* has the new sin/cos/log functions */
76 unsigned has_new_transcendentals : 1;
77 /* has the new dp2/dpX_norm instructions, among others */
78 unsigned has_halti2_instructions : 1;
79 /* has V4_COMPRESSION */
80 unsigned v4_compression : 1;
81 /* supports single-buffer rendering with multiple pixel pipes */
82 unsigned single_buffer : 1;
83 /* has unified uniforms memory */
84 unsigned has_unified_uniforms : 1;
85 /* can load shader instructions from memory */
86 unsigned has_icache : 1;
87 /* ASTC texture support (and has associated states) */
88 unsigned tex_astc : 1;
89 /* has BLT engine instead of RS */
90 unsigned use_blt : 1;
91 /* can use any kind of wrapping mode on npot textures */
92 unsigned npot_tex_any_wrap : 1;
93 /* number of bits per TS tile */
94 unsigned bits_per_tile;
95 /* clear value for TS (dependent on bits_per_tile) */
96 uint32_t ts_clear_value;
97 /* base of vertex texture units */
98 unsigned vertex_sampler_offset;
99 /* number of fragment sampler units */
100 unsigned fragment_sampler_count;
101 /* number of vertex sampler units */
102 unsigned vertex_sampler_count;
103 /* size of vertex shader output buffer */
104 unsigned vertex_output_buffer_size;
105 /* maximum number of vertex element configurations */
106 unsigned vertex_max_elements;
107 /* size of a cached vertex (?) */
108 unsigned vertex_cache_size;
109 /* number of shader cores */
110 unsigned shader_core_count;
111 /* number of vertex streams */
112 unsigned stream_count;
113 /* vertex shader memory address*/
114 uint32_t vs_offset;
115 /* pixel shader memory address*/
116 uint32_t ps_offset;
117 /* vertex shader uniforms address*/
118 uint32_t vs_uniforms_offset;
119 /* pixel shader uniforms address*/
120 uint32_t ps_uniforms_offset;
121 /* vertex/fragment shader max instructions */
122 uint32_t max_instructions;
123 /* maximum number of varyings */
124 unsigned max_varyings;
125 /* maximum number of registers */
126 unsigned max_registers;
127 /* maximum vertex uniforms */
128 unsigned max_vs_uniforms;
129 /* maximum pixel uniforms */
130 unsigned max_ps_uniforms;
131 /* maximum texture size */
132 unsigned max_texture_size;
133 /* maximum texture size */
134 unsigned max_rendertarget_size;
135 /* available pixel pipes */
136 unsigned pixel_pipes;
137 /* number of constants */
138 unsigned num_constants;
139 };
140
141 /* Compiled Gallium state. All the different compiled state atoms are woven
142 * together and uploaded only when it is necessary to synchronize the state,
143 * for example before rendering. */
144
145 /* Compiled pipe_blend_color */
146 struct compiled_blend_color {
147 float color[4];
148 uint32_t PE_ALPHA_BLEND_COLOR;
149 };
150
151 /* Compiled pipe_stencil_ref */
152 struct compiled_stencil_ref {
153 uint32_t PE_STENCIL_CONFIG;
154 uint32_t PE_STENCIL_CONFIG_EXT;
155 };
156
157 /* Compiled pipe_scissor_state */
158 struct compiled_scissor_state {
159 uint32_t SE_SCISSOR_LEFT;
160 uint32_t SE_SCISSOR_TOP;
161 uint32_t SE_SCISSOR_RIGHT;
162 uint32_t SE_SCISSOR_BOTTOM;
163 uint32_t SE_CLIP_RIGHT;
164 uint32_t SE_CLIP_BOTTOM;
165 };
166
167 /* Compiled pipe_viewport_state */
168 struct compiled_viewport_state {
169 uint32_t PA_VIEWPORT_SCALE_X;
170 uint32_t PA_VIEWPORT_SCALE_Y;
171 uint32_t PA_VIEWPORT_SCALE_Z;
172 uint32_t PA_VIEWPORT_OFFSET_X;
173 uint32_t PA_VIEWPORT_OFFSET_Y;
174 uint32_t PA_VIEWPORT_OFFSET_Z;
175 uint32_t SE_SCISSOR_LEFT;
176 uint32_t SE_SCISSOR_TOP;
177 uint32_t SE_SCISSOR_RIGHT;
178 uint32_t SE_SCISSOR_BOTTOM;
179 uint32_t SE_CLIP_RIGHT;
180 uint32_t SE_CLIP_BOTTOM;
181 uint32_t PE_DEPTH_NEAR;
182 uint32_t PE_DEPTH_FAR;
183 };
184
185 /* Compiled pipe_framebuffer_state */
186 struct compiled_framebuffer_state {
187 uint32_t GL_MULTI_SAMPLE_CONFIG;
188 uint32_t PE_COLOR_FORMAT;
189 uint32_t PE_DEPTH_CONFIG;
190 struct etna_reloc PE_DEPTH_ADDR;
191 struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
192 uint32_t PE_DEPTH_STRIDE;
193 uint32_t PE_HDEPTH_CONTROL;
194 uint32_t PE_DEPTH_NORMALIZE;
195 struct etna_reloc PE_COLOR_ADDR;
196 struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
197 uint32_t PE_COLOR_STRIDE;
198 uint32_t PE_MEM_CONFIG;
199 uint32_t SE_SCISSOR_LEFT;
200 uint32_t SE_SCISSOR_TOP;
201 uint32_t SE_SCISSOR_RIGHT;
202 uint32_t SE_SCISSOR_BOTTOM;
203 uint32_t SE_CLIP_RIGHT;
204 uint32_t SE_CLIP_BOTTOM;
205 uint32_t RA_MULTISAMPLE_UNK00E04;
206 uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
207 uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
208 uint32_t TS_MEM_CONFIG;
209 uint32_t TS_DEPTH_CLEAR_VALUE;
210 struct etna_reloc TS_DEPTH_STATUS_BASE;
211 struct etna_reloc TS_DEPTH_SURFACE_BASE;
212 uint32_t TS_COLOR_CLEAR_VALUE;
213 struct etna_reloc TS_COLOR_STATUS_BASE;
214 struct etna_reloc TS_COLOR_SURFACE_BASE;
215 uint32_t PE_LOGIC_OP;
216 bool msaa_mode; /* adds input (and possible temp) to PS */
217 };
218
219 /* Compiled context->create_vertex_elements_state */
220 struct compiled_vertex_elements_state {
221 unsigned num_elements;
222 uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
223 uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN];
224 uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN];
225 uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN];
226 };
227
228 /* Compiled context->set_vertex_buffer result */
229 struct compiled_set_vertex_buffer {
230 uint32_t FE_VERTEX_STREAM_CONTROL;
231 uint32_t FE_VERTEX_STREAM_UNK14680;
232 struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
233 };
234
235 /* Compiled linked VS+PS shader state */
236 struct compiled_shader_state {
237 uint32_t RA_CONTROL;
238 uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
239 uint32_t PA_CONFIG;
240 uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
241 uint32_t VS_END_PC;
242 uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
243 uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
244 uint32_t VS_INPUT_COUNT;
245 uint32_t VS_TEMP_REGISTER_CONTROL;
246 uint32_t VS_OUTPUT[4];
247 uint32_t VS_INPUT[4];
248 uint32_t VS_LOAD_BALANCING;
249 uint32_t VS_START_PC;
250 uint32_t PS_END_PC;
251 uint32_t PS_OUTPUT_REG;
252 uint32_t PS_INPUT_COUNT;
253 uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
254 uint32_t PS_TEMP_REGISTER_CONTROL;
255 uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
256 uint32_t PS_CONTROL;
257 uint32_t PS_START_PC;
258 uint32_t GL_VARYING_TOTAL_COMPONENTS;
259 uint32_t GL_VARYING_NUM_COMPONENTS;
260 uint32_t GL_VARYING_COMPONENT_USE[2];
261 uint32_t GL_HALTI5_SH_SPECIALS;
262 unsigned vs_inst_mem_size;
263 unsigned vs_uniforms_size;
264 unsigned ps_inst_mem_size;
265 unsigned ps_uniforms_size;
266 uint32_t *VS_INST_MEM;
267 uint32_t VS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
268 uint32_t *PS_INST_MEM;
269 uint32_t PS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
270 struct etna_reloc PS_INST_ADDR;
271 struct etna_reloc VS_INST_ADDR;
272 };
273
274 /* state of some 3d and common registers relevant to etna driver */
275 struct etna_3d_state {
276 uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN];
277 uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN];
278 };
279
280 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
281 * field_size must be a power of two, and <= 32. */
282 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
283 uint32_t name[(num) * (field_size) / 32]
284
285 static inline void
286 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
287 size_t index, uint32_t value)
288 {
289 size_t shift = (index * field_size) % 32;
290 size_t offset = (index * field_size) / 32;
291
292 assert(index < array_size * 32 / field_size);
293 assert(value < 1 << field_size);
294
295 array[offset] |= value << shift;
296 }
297
298 #define etna_bitarray_set(array, field_size, index, value) \
299 etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
300
301 #endif