2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
28 #include "etnaviv_screen.h"
30 #include "hw/common.xml.h"
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
48 #include "state_tracker/drm_driver.h"
50 #include "drm-uapi/drm_fourcc.h"
52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
53 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
54 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
56 static const struct debug_named_value debug_options
[] = {
57 {"dbg_msgs", ETNA_DBG_MSGS
, "Print debug messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS
, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS
, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS
, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS
, "Print linker messages"},
62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS
, "Dump shaders"},
63 {"no_ts", ETNA_DBG_NO_TS
, "Disable TS"},
64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE
, "Disable autodisable"},
65 {"no_supertile", ETNA_DBG_NO_SUPERTILE
, "Disable supertiles"},
66 {"no_early_z", ETNA_DBG_NO_EARLY_Z
, "Disable early z"},
67 {"cflush_all", ETNA_DBG_CFLUSH_ALL
, "Flush every cache before state update"},
68 {"msaa2x", ETNA_DBG_MSAA_2X
, "Force 2x msaa"},
69 {"msaa4x", ETNA_DBG_MSAA_4X
, "Force 4x msaa"},
70 {"flush_all", ETNA_DBG_FLUSH_ALL
, "Flush after every rendered primitive"},
71 {"zero", ETNA_DBG_ZERO
, "Zero all resources after allocation"},
72 {"draw_stall", ETNA_DBG_DRAW_STALL
, "Stall FE/PE after each rendered primitive"},
73 {"shaderdb", ETNA_DBG_SHADERDB
, "Enable shaderdb output"},
74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF
, "Disable single buffer feature"},
75 {"nir", ETNA_DBG_NIR
, "use new NIR compiler"},
79 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug
, "ETNA_MESA_DEBUG", debug_options
, 0)
80 int etna_mesa_debug
= 0;
83 etna_screen_destroy(struct pipe_screen
*pscreen
)
85 struct etna_screen
*screen
= etna_screen(pscreen
);
87 _mesa_set_destroy(screen
->used_resources
, NULL
);
88 mtx_destroy(&screen
->lock
);
91 etna_perfmon_del(screen
->perfmon
);
94 etna_pipe_del(screen
->pipe
);
97 etna_gpu_del(screen
->gpu
);
103 etna_device_del(screen
->dev
);
109 etna_screen_get_name(struct pipe_screen
*pscreen
)
111 struct etna_screen
*priv
= etna_screen(pscreen
);
112 static char buffer
[128];
114 snprintf(buffer
, sizeof(buffer
), "Vivante GC%x rev %04x", priv
->model
,
121 etna_screen_get_vendor(struct pipe_screen
*pscreen
)
127 etna_screen_get_device_vendor(struct pipe_screen
*pscreen
)
133 etna_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
135 struct etna_screen
*screen
= etna_screen(pscreen
);
138 /* Supported features (boolean caps). */
139 case PIPE_CAP_ANISOTROPIC_FILTER
:
140 case PIPE_CAP_POINT_SPRITE
:
141 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
142 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
143 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
144 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
145 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
146 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
147 case PIPE_CAP_TEXTURE_BARRIER
:
148 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
149 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
150 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
151 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
152 case PIPE_CAP_TGSI_TEXCOORD
:
153 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
154 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
155 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
157 case PIPE_CAP_NATIVE_FENCE_FD
:
158 return screen
->drm_version
>= ETNA_DRM_VERSION_FENCE_FD
;
159 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
160 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
: /* note: not integer */
161 return DBG_ENABLED(ETNA_DBG_NIR
);
162 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
166 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
168 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
169 return 4; /* XXX could easily be supported */
171 case PIPE_CAP_NPOT_TEXTURES
:
172 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
173 NON_POWER_OF_TWO); */
175 case PIPE_CAP_TEXTURE_SWIZZLE
:
176 case PIPE_CAP_PRIMITIVE_RESTART
:
177 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
179 /* Unsupported features. */
180 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
181 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
182 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
186 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
187 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
190 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
192 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
196 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
197 return DBG_ENABLED(ETNA_DBG_NIR
) && screen
->specs
.halti
>= 2;
198 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
199 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
: /* TODO: verify */
200 return screen
->specs
.max_texture_size
;
201 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
202 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
204 int log2_max_tex_size
= util_last_bit(screen
->specs
.max_texture_size
);
205 assert(log2_max_tex_size
> 0);
206 return log2_max_tex_size
;
209 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
210 case PIPE_CAP_MIN_TEXEL_OFFSET
:
212 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
213 case PIPE_CAP_MAX_TEXEL_OFFSET
:
215 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
216 return VIV_FEATURE(screen
, chipMinorFeatures2
, SEAMLESS_CUBE_MAP
);
219 case PIPE_CAP_OCCLUSION_QUERY
:
220 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
221 case PIPE_CAP_QUERY_TIMESTAMP
:
225 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
228 case PIPE_CAP_MAX_VARYINGS
:
229 return screen
->specs
.max_varyings
;
231 case PIPE_CAP_PCI_GROUP
:
232 case PIPE_CAP_PCI_BUS
:
233 case PIPE_CAP_PCI_DEVICE
:
234 case PIPE_CAP_PCI_FUNCTION
:
236 case PIPE_CAP_ACCELERATED
:
238 case PIPE_CAP_VIDEO_MEMORY
:
243 return u_pipe_screen_get_param_defaults(pscreen
, param
);
248 etna_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
250 struct etna_screen
*screen
= etna_screen(pscreen
);
253 case PIPE_CAPF_MAX_LINE_WIDTH
:
254 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
255 case PIPE_CAPF_MAX_POINT_WIDTH
:
256 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
258 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
260 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
261 return util_last_bit(screen
->specs
.max_texture_size
);
262 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
263 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
264 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
268 debug_printf("unknown paramf %d", param
);
273 etna_screen_get_shader_param(struct pipe_screen
*pscreen
,
274 enum pipe_shader_type shader
,
275 enum pipe_shader_cap param
)
277 struct etna_screen
*screen
= etna_screen(pscreen
);
280 case PIPE_SHADER_FRAGMENT
:
281 case PIPE_SHADER_VERTEX
:
283 case PIPE_SHADER_COMPUTE
:
284 case PIPE_SHADER_GEOMETRY
:
285 case PIPE_SHADER_TESS_CTRL
:
286 case PIPE_SHADER_TESS_EVAL
:
289 DBG("unknown shader type %d", shader
);
294 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
295 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
296 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
297 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
298 return ETNA_MAX_TOKENS
;
299 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
300 return ETNA_MAX_DEPTH
; /* XXX */
301 case PIPE_SHADER_CAP_MAX_INPUTS
:
302 /* Maximum number of inputs for the vertex shader is the number
303 * of vertex elements - each element defines one vertex shader
304 * input register. For the fragment shader, this is the number
306 return shader
== PIPE_SHADER_FRAGMENT
? screen
->specs
.max_varyings
307 : screen
->specs
.vertex_max_elements
;
308 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
309 return 16; /* see VIVS_VS_OUTPUT */
310 case PIPE_SHADER_CAP_MAX_TEMPS
:
311 return 64; /* Max native temporaries. */
312 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
314 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
316 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
317 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
318 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
319 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
321 case PIPE_SHADER_CAP_SUBROUTINES
:
323 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
324 return VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
325 case PIPE_SHADER_CAP_INT64_ATOMICS
:
326 case PIPE_SHADER_CAP_FP16
:
328 case PIPE_SHADER_CAP_INTEGERS
:
329 return DBG_ENABLED(ETNA_DBG_NIR
) && screen
->specs
.halti
>= 2;
330 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
331 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
332 return shader
== PIPE_SHADER_FRAGMENT
333 ? screen
->specs
.fragment_sampler_count
334 : screen
->specs
.vertex_sampler_count
;
335 case PIPE_SHADER_CAP_PREFERRED_IR
:
336 return DBG_ENABLED(ETNA_DBG_NIR
) ? PIPE_SHADER_IR_NIR
: PIPE_SHADER_IR_TGSI
;
337 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
338 return shader
== PIPE_SHADER_FRAGMENT
339 ? screen
->specs
.max_ps_uniforms
* sizeof(float[4])
340 : screen
->specs
.max_vs_uniforms
* sizeof(float[4]);
341 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
342 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
343 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
344 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
345 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
347 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
349 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
351 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
352 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
353 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
354 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
355 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
356 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
360 debug_printf("unknown shader param %d", param
);
365 etna_screen_get_timestamp(struct pipe_screen
*pscreen
)
367 return os_time_get_nano();
371 gpu_supports_texture_target(struct etna_screen
*screen
,
372 enum pipe_texture_target target
)
374 if (target
== PIPE_TEXTURE_CUBE_ARRAY
)
377 /* pre-halti has no array/3D */
378 if (screen
->specs
.halti
< 0 &&
379 (target
== PIPE_TEXTURE_1D_ARRAY
||
380 target
== PIPE_TEXTURE_2D_ARRAY
||
381 target
== PIPE_TEXTURE_3D
))
388 gpu_supports_texture_format(struct etna_screen
*screen
, uint32_t fmt
,
389 enum pipe_format format
)
391 bool supported
= true;
393 if (fmt
== TEXTURE_FORMAT_ETC1
)
394 supported
= VIV_FEATURE(screen
, chipFeatures
, ETC1_TEXTURE_COMPRESSION
);
396 if (fmt
>= TEXTURE_FORMAT_DXT1
&& fmt
<= TEXTURE_FORMAT_DXT4_DXT5
)
397 supported
= VIV_FEATURE(screen
, chipFeatures
, DXT_TEXTURE_COMPRESSION
);
399 if (util_format_is_srgb(format
))
400 supported
= VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
402 if (fmt
& EXT_FORMAT
)
403 supported
= VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
405 if (fmt
& ASTC_FORMAT
) {
406 supported
= screen
->specs
.tex_astc
;
412 if (texture_format_needs_swiz(format
))
413 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
419 etna_screen_is_format_supported(struct pipe_screen
*pscreen
,
420 enum pipe_format format
,
421 enum pipe_texture_target target
,
422 unsigned sample_count
,
423 unsigned storage_sample_count
,
426 struct etna_screen
*screen
= etna_screen(pscreen
);
427 unsigned allowed
= 0;
429 if (!gpu_supports_texture_target(screen
, target
))
432 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
435 if (usage
& PIPE_BIND_RENDER_TARGET
) {
436 /* if render target, must be RS-supported format */
437 if (translate_rs_format(format
) != ETNA_NO_MATCH
) {
438 /* Validate MSAA; number of samples must be allowed, and render target
439 * must have MSAA'able format. */
440 if (sample_count
> 1) {
441 if (translate_samples_to_xyscale(sample_count
, NULL
, NULL
, NULL
) &&
442 translate_ts_format(format
) != ETNA_NO_MATCH
) {
443 allowed
|= PIPE_BIND_RENDER_TARGET
;
446 allowed
|= PIPE_BIND_RENDER_TARGET
;
451 if (usage
& PIPE_BIND_DEPTH_STENCIL
) {
452 if (translate_depth_format(format
) != ETNA_NO_MATCH
)
453 allowed
|= PIPE_BIND_DEPTH_STENCIL
;
456 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
457 uint32_t fmt
= translate_texture_format(format
);
459 if (!gpu_supports_texture_format(screen
, fmt
, format
))
462 if (sample_count
< 2 && fmt
!= ETNA_NO_MATCH
)
463 allowed
|= PIPE_BIND_SAMPLER_VIEW
;
466 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
467 if (translate_vertex_format_type(format
) != ETNA_NO_MATCH
)
468 allowed
|= PIPE_BIND_VERTEX_BUFFER
;
471 if (usage
& PIPE_BIND_INDEX_BUFFER
) {
472 /* must be supported index format */
473 if (format
== PIPE_FORMAT_I8_UINT
|| format
== PIPE_FORMAT_I16_UINT
||
474 (format
== PIPE_FORMAT_I32_UINT
&&
475 VIV_FEATURE(screen
, chipFeatures
, 32_BIT_INDICES
))) {
476 allowed
|= PIPE_BIND_INDEX_BUFFER
;
482 usage
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
);
484 if (usage
!= allowed
) {
485 DBG("not supported: format=%s, target=%d, sample_count=%d, "
486 "usage=%x, allowed=%x",
487 util_format_name(format
), target
, sample_count
, usage
, allowed
);
490 return usage
== allowed
;
493 const uint64_t supported_modifiers
[] = {
494 DRM_FORMAT_MOD_LINEAR
,
495 DRM_FORMAT_MOD_VIVANTE_TILED
,
496 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED
,
497 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED
,
498 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED
,
502 etna_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
503 enum pipe_format format
, int max
,
505 unsigned int *external_only
, int *count
)
507 struct etna_screen
*screen
= etna_screen(pscreen
);
508 int i
, num_modifiers
= 0;
510 if (max
> ARRAY_SIZE(supported_modifiers
))
511 max
= ARRAY_SIZE(supported_modifiers
);
515 max
= ARRAY_SIZE(supported_modifiers
);
518 for (i
= 0; num_modifiers
< max
; i
++) {
519 /* don't advertise split tiled formats on single pipe/buffer GPUs */
520 if ((screen
->specs
.pixel_pipes
== 1 || screen
->specs
.single_buffer
) &&
525 modifiers
[num_modifiers
] = supported_modifiers
[i
];
527 external_only
[num_modifiers
] = util_format_is_yuv(format
) ? 1 : 0;
531 *count
= num_modifiers
;
535 etna_determine_uniform_limits(struct etna_screen
*screen
)
537 /* values for the non unified case are taken from
538 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
539 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
541 if (screen
->model
== chipModel_GC2000
&&
542 (screen
->revision
== 0x5118 || screen
->revision
== 0x5140)) {
543 screen
->specs
.max_vs_uniforms
= 256;
544 screen
->specs
.max_ps_uniforms
= 64;
545 } else if (screen
->specs
.num_constants
== 320) {
546 screen
->specs
.max_vs_uniforms
= 256;
547 screen
->specs
.max_ps_uniforms
= 64;
548 } else if (screen
->specs
.num_constants
> 256 &&
549 screen
->model
== chipModel_GC1000
) {
550 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
551 screen
->specs
.max_vs_uniforms
= 256;
552 screen
->specs
.max_ps_uniforms
= 64;
553 } else if (screen
->specs
.num_constants
> 256) {
554 screen
->specs
.max_vs_uniforms
= 256;
555 screen
->specs
.max_ps_uniforms
= 256;
556 } else if (screen
->specs
.num_constants
== 256) {
557 screen
->specs
.max_vs_uniforms
= 256;
558 screen
->specs
.max_ps_uniforms
= 256;
560 screen
->specs
.max_vs_uniforms
= 168;
561 screen
->specs
.max_ps_uniforms
= 64;
566 etna_get_specs(struct etna_screen
*screen
)
569 uint32_t instruction_count
;
571 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_INSTRUCTION_COUNT
, &val
)) {
572 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
575 instruction_count
= val
;
577 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE
,
579 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
582 screen
->specs
.vertex_output_buffer_size
= val
;
584 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_CACHE_SIZE
, &val
)) {
585 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
588 screen
->specs
.vertex_cache_size
= val
;
590 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_SHADER_CORE_COUNT
, &val
)) {
591 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
594 screen
->specs
.shader_core_count
= val
;
596 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_STREAM_COUNT
, &val
)) {
597 DBG("could not get ETNA_GPU_STREAM_COUNT");
600 screen
->specs
.stream_count
= val
;
602 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REGISTER_MAX
, &val
)) {
603 DBG("could not get ETNA_GPU_REGISTER_MAX");
606 screen
->specs
.max_registers
= val
;
608 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_PIXEL_PIPES
, &val
)) {
609 DBG("could not get ETNA_GPU_PIXEL_PIPES");
612 screen
->specs
.pixel_pipes
= val
;
614 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_NUM_CONSTANTS
, &val
)) {
615 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
619 fprintf(stderr
, "Warning: zero num constants (update kernel?)\n");
622 screen
->specs
.num_constants
= val
;
624 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
625 * description of the differences. */
626 if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
))
627 screen
->specs
.halti
= 5; /* New GC7000/GC8x00 */
628 else if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI4
))
629 screen
->specs
.halti
= 4; /* Old GC7000/GC7400 */
630 else if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI3
))
631 screen
->specs
.halti
= 3; /* None? */
632 else if (VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
))
633 screen
->specs
.halti
= 2; /* GC2500/GC3000/GC5000/GC6400 */
634 else if (VIV_FEATURE(screen
, chipMinorFeatures2
, HALTI1
))
635 screen
->specs
.halti
= 1; /* GC900/GC4000/GC7000UL */
636 else if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
))
637 screen
->specs
.halti
= 0; /* GC880/GC2000/GC7000TM */
639 screen
->specs
.halti
= -1; /* GC7000nanolite / pre-GC2000 except GC880 */
640 if (screen
->specs
.halti
>= 0)
641 DBG("etnaviv: GPU arch: HALTI%d", screen
->specs
.halti
);
643 DBG("etnaviv: GPU arch: pre-HALTI");
645 screen
->specs
.can_supertile
=
646 VIV_FEATURE(screen
, chipMinorFeatures0
, SUPER_TILED
);
647 screen
->specs
.bits_per_tile
=
648 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 2 : 4;
649 screen
->specs
.ts_clear_value
=
650 VIV_FEATURE(screen
, chipMinorFeatures5
, BLT_ENGINE
) ? 0xffffffff :
651 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 0x55555555 :
655 /* vertex and fragment samplers live in one address space */
656 screen
->specs
.vertex_sampler_offset
= 8;
657 screen
->specs
.fragment_sampler_count
= 8;
658 screen
->specs
.vertex_sampler_count
= 4;
659 screen
->specs
.vs_need_z_div
=
660 screen
->model
< 0x1000 && screen
->model
!= 0x880;
661 screen
->specs
.has_sin_cos_sqrt
=
662 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
663 screen
->specs
.has_sign_floor_ceil
=
664 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SIGN_FLOOR_CEIL
);
665 screen
->specs
.has_shader_range_registers
=
666 screen
->model
>= 0x1000 || screen
->model
== 0x880;
667 screen
->specs
.npot_tex_any_wrap
=
668 VIV_FEATURE(screen
, chipMinorFeatures1
, NON_POWER_OF_TWO
);
669 screen
->specs
.has_new_transcendentals
=
670 VIV_FEATURE(screen
, chipMinorFeatures3
, HAS_FAST_TRANSCENDENTALS
);
671 screen
->specs
.has_halti2_instructions
=
672 VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
673 screen
->specs
.v4_compression
=
674 VIV_FEATURE(screen
, chipMinorFeatures6
, V4_COMPRESSION
);
676 if (screen
->specs
.halti
>= 5) {
677 /* GC7000 - this core must load shaders from memory. */
678 screen
->specs
.vs_offset
= 0;
679 screen
->specs
.ps_offset
= 0;
680 screen
->specs
.max_instructions
= 0; /* Do not program shaders manually */
681 screen
->specs
.has_icache
= true;
682 } else if (VIV_FEATURE(screen
, chipMinorFeatures3
, INSTRUCTION_CACHE
)) {
683 /* GC3000 - this core is capable of loading shaders from
684 * memory. It can also run shaders from registers, as a fallback, but
685 * "max_instructions" does not have the correct value. It has place for
686 * 2*256 instructions just like GC2000, but the offsets are slightly
689 screen
->specs
.vs_offset
= 0xC000;
690 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
691 * this mirror for writing PS instructions, probably safest to do the
694 screen
->specs
.ps_offset
= 0x8000 + 0x1000;
695 screen
->specs
.max_instructions
= 256; /* maximum number instructions for non-icache use */
696 screen
->specs
.has_icache
= true;
698 if (instruction_count
> 256) { /* unified instruction memory? */
699 screen
->specs
.vs_offset
= 0xC000;
700 screen
->specs
.ps_offset
= 0xD000; /* like vivante driver */
701 screen
->specs
.max_instructions
= 256;
703 screen
->specs
.vs_offset
= 0x4000;
704 screen
->specs
.ps_offset
= 0x6000;
705 screen
->specs
.max_instructions
= instruction_count
/ 2;
707 screen
->specs
.has_icache
= false;
710 if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
)) {
711 screen
->specs
.max_varyings
= 12;
712 screen
->specs
.vertex_max_elements
= 16;
714 screen
->specs
.max_varyings
= 8;
715 /* Etna_viv documentation seems confused over the correct value
716 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
717 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
718 screen
->specs
.vertex_max_elements
= 10;
721 /* Etna_viv documentation does not indicate where varyings above 8 are
722 * stored. Moreover, if we are passed more than 8 varyings, we will
723 * walk off the end of some arrays. Limit the maximum number of varyings. */
724 if (screen
->specs
.max_varyings
> ETNA_NUM_VARYINGS
)
725 screen
->specs
.max_varyings
= ETNA_NUM_VARYINGS
;
727 etna_determine_uniform_limits(screen
);
729 if (screen
->specs
.halti
>= 5) {
730 screen
->specs
.has_unified_uniforms
= true;
731 screen
->specs
.vs_uniforms_offset
= VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
732 screen
->specs
.ps_uniforms_offset
= VIVS_SH_HALTI5_UNIFORMS(screen
->specs
.max_vs_uniforms
*4);
733 } else if (screen
->specs
.halti
>= 1) {
734 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
736 screen
->specs
.has_unified_uniforms
= true;
737 screen
->specs
.vs_uniforms_offset
= VIVS_SH_UNIFORMS(0);
738 /* hardcode PS uniforms to start after end of VS uniforms -
739 * for more flexibility this offset could be variable based on the
742 screen
->specs
.ps_uniforms_offset
= VIVS_SH_UNIFORMS(screen
->specs
.max_vs_uniforms
*4);
744 screen
->specs
.has_unified_uniforms
= false;
745 screen
->specs
.vs_uniforms_offset
= VIVS_VS_UNIFORMS(0);
746 screen
->specs
.ps_uniforms_offset
= VIVS_PS_UNIFORMS(0);
749 screen
->specs
.max_texture_size
=
750 VIV_FEATURE(screen
, chipMinorFeatures0
, TEXTURE_8K
) ? 8192 : 2048;
751 screen
->specs
.max_rendertarget_size
=
752 VIV_FEATURE(screen
, chipMinorFeatures0
, RENDERTARGET_8K
) ? 8192 : 2048;
754 screen
->specs
.single_buffer
= VIV_FEATURE(screen
, chipMinorFeatures4
, SINGLE_BUFFER
);
755 if (screen
->specs
.single_buffer
)
756 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen
->specs
.pixel_pipes
);
758 screen
->specs
.tex_astc
= VIV_FEATURE(screen
, chipMinorFeatures4
, TEXTURE_ASTC
);
760 screen
->specs
.use_blt
= VIV_FEATURE(screen
, chipMinorFeatures5
, BLT_ENGINE
);
769 etna_screen_bo_from_handle(struct pipe_screen
*pscreen
,
770 struct winsys_handle
*whandle
, unsigned *out_stride
)
772 struct etna_screen
*screen
= etna_screen(pscreen
);
775 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
776 bo
= etna_bo_from_name(screen
->dev
, whandle
->handle
);
777 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
778 bo
= etna_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
780 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
785 DBG("ref name 0x%08x failed", whandle
->handle
);
789 *out_stride
= whandle
->stride
;
795 etna_get_compiler_options(struct pipe_screen
*pscreen
,
796 enum pipe_shader_ir ir
, unsigned shader
)
798 return &etna_screen(pscreen
)->options
;
802 etna_screen_create(struct etna_device
*dev
, struct etna_gpu
*gpu
,
803 struct renderonly
*ro
)
805 struct etna_screen
*screen
= CALLOC_STRUCT(etna_screen
);
806 struct pipe_screen
*pscreen
;
807 drmVersionPtr version
;
813 pscreen
= &screen
->base
;
816 screen
->ro
= renderonly_dup(ro
);
820 DBG("could not create renderonly object");
824 version
= drmGetVersion(screen
->ro
->gpu_fd
);
825 screen
->drm_version
= ETNA_DRM_VERSION(version
->version_major
,
826 version
->version_minor
);
827 drmFreeVersion(version
);
829 etna_mesa_debug
= debug_get_option_etna_mesa_debug();
831 /* Disable autodisable for correct rendering with TS */
832 etna_mesa_debug
|= ETNA_DBG_NO_AUTODISABLE
;
834 screen
->pipe
= etna_pipe_new(gpu
, ETNA_PIPE_3D
);
836 DBG("could not create 3d pipe");
840 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_MODEL
, &val
)) {
841 DBG("could not get ETNA_GPU_MODEL");
846 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REVISION
, &val
)) {
847 DBG("could not get ETNA_GPU_REVISION");
850 screen
->revision
= val
;
852 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_0
, &val
)) {
853 DBG("could not get ETNA_GPU_FEATURES_0");
856 screen
->features
[0] = val
;
858 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_1
, &val
)) {
859 DBG("could not get ETNA_GPU_FEATURES_1");
862 screen
->features
[1] = val
;
864 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_2
, &val
)) {
865 DBG("could not get ETNA_GPU_FEATURES_2");
868 screen
->features
[2] = val
;
870 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_3
, &val
)) {
871 DBG("could not get ETNA_GPU_FEATURES_3");
874 screen
->features
[3] = val
;
876 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_4
, &val
)) {
877 DBG("could not get ETNA_GPU_FEATURES_4");
880 screen
->features
[4] = val
;
882 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_5
, &val
)) {
883 DBG("could not get ETNA_GPU_FEATURES_5");
886 screen
->features
[5] = val
;
888 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_6
, &val
)) {
889 DBG("could not get ETNA_GPU_FEATURES_6");
892 screen
->features
[6] = val
;
894 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_7
, &val
)) {
895 DBG("could not get ETNA_GPU_FEATURES_7");
898 screen
->features
[7] = val
;
900 if (!etna_get_specs(screen
))
903 screen
->options
= (nir_shader_compiler_options
) {
906 .lower_ftrunc
= true,
908 .lower_bitops
= true,
909 .lower_all_io_to_temps
= true,
910 .vertex_id_zero_based
= true,
911 .lower_flrp32
= true,
913 .lower_vector_cmp
= true,
915 .lower_fdiv
= true, /* !screen->specs.has_new_transcendentals */
916 .lower_fsign
= !screen
->specs
.has_sign_floor_ceil
,
917 .lower_ffloor
= !screen
->specs
.has_sign_floor_ceil
,
918 .lower_fceil
= !screen
->specs
.has_sign_floor_ceil
,
919 .lower_fsqrt
= !screen
->specs
.has_sin_cos_sqrt
,
920 .lower_sincos
= !screen
->specs
.has_sin_cos_sqrt
,
923 /* apply debug options that disable individual features */
924 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z
))
925 screen
->features
[viv_chipFeatures
] |= chipFeatures_NO_EARLY_Z
;
926 if (DBG_ENABLED(ETNA_DBG_NO_TS
))
927 screen
->features
[viv_chipFeatures
] &= ~chipFeatures_FAST_CLEAR
;
928 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE
))
929 screen
->features
[viv_chipMinorFeatures1
] &= ~chipMinorFeatures1_AUTO_DISABLE
;
930 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE
))
931 screen
->specs
.can_supertile
= 0;
932 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF
))
933 screen
->specs
.single_buffer
= 0;
935 pscreen
->destroy
= etna_screen_destroy
;
936 pscreen
->get_param
= etna_screen_get_param
;
937 pscreen
->get_paramf
= etna_screen_get_paramf
;
938 pscreen
->get_shader_param
= etna_screen_get_shader_param
;
939 pscreen
->get_compiler_options
= etna_get_compiler_options
;
941 pscreen
->get_name
= etna_screen_get_name
;
942 pscreen
->get_vendor
= etna_screen_get_vendor
;
943 pscreen
->get_device_vendor
= etna_screen_get_device_vendor
;
945 pscreen
->get_timestamp
= etna_screen_get_timestamp
;
946 pscreen
->context_create
= etna_context_create
;
947 pscreen
->is_format_supported
= etna_screen_is_format_supported
;
948 pscreen
->query_dmabuf_modifiers
= etna_screen_query_dmabuf_modifiers
;
950 etna_fence_screen_init(pscreen
);
951 etna_query_screen_init(pscreen
);
952 etna_resource_screen_init(pscreen
);
954 util_dynarray_init(&screen
->supported_pm_queries
, NULL
);
955 slab_create_parent(&screen
->transfer_pool
, sizeof(struct etna_transfer
), 16);
957 if (screen
->drm_version
>= ETNA_DRM_VERSION_PERFMON
)
958 etna_pm_query_setup(screen
);
960 mtx_init(&screen
->lock
, mtx_recursive
);
961 screen
->used_resources
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
962 _mesa_key_pointer_equal
);
963 if (!screen
->used_resources
)
969 mtx_destroy(&screen
->lock
);
971 etna_screen_destroy(pscreen
);