2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
28 #include "etnaviv_screen.h"
30 #include "hw/common.xml.h"
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
48 #include "frontend/drm_driver.h"
50 #include "drm-uapi/drm_fourcc.h"
52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
53 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
54 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
56 static const struct debug_named_value debug_options
[] = {
57 {"dbg_msgs", ETNA_DBG_MSGS
, "Print debug messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS
, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS
, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS
, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS
, "Print linker messages"},
62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS
, "Dump shaders"},
63 {"no_ts", ETNA_DBG_NO_TS
, "Disable TS"},
64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE
, "Disable autodisable"},
65 {"no_supertile", ETNA_DBG_NO_SUPERTILE
, "Disable supertiles"},
66 {"no_early_z", ETNA_DBG_NO_EARLY_Z
, "Disable early z"},
67 {"cflush_all", ETNA_DBG_CFLUSH_ALL
, "Flush every cache before state update"},
68 {"msaa2x", ETNA_DBG_MSAA_2X
, "Force 2x msaa"},
69 {"msaa4x", ETNA_DBG_MSAA_4X
, "Force 4x msaa"},
70 {"flush_all", ETNA_DBG_FLUSH_ALL
, "Flush after every rendered primitive"},
71 {"zero", ETNA_DBG_ZERO
, "Zero all resources after allocation"},
72 {"draw_stall", ETNA_DBG_DRAW_STALL
, "Stall FE/PE after each rendered primitive"},
73 {"shaderdb", ETNA_DBG_SHADERDB
, "Enable shaderdb output"},
74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF
, "Disable single buffer feature"},
75 {"nir", ETNA_DBG_NIR
, "use new NIR compiler"},
76 {"deqp", ETNA_DBG_DEQP
, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */
80 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug
, "ETNA_MESA_DEBUG", debug_options
, 0)
81 int etna_mesa_debug
= 0;
84 etna_screen_destroy(struct pipe_screen
*pscreen
)
86 struct etna_screen
*screen
= etna_screen(pscreen
);
89 etna_perfmon_del(screen
->perfmon
);
92 etna_compiler_destroy(screen
->compiler
);
95 etna_pipe_del(screen
->pipe
);
98 etna_gpu_del(screen
->gpu
);
104 etna_device_del(screen
->dev
);
110 etna_screen_get_name(struct pipe_screen
*pscreen
)
112 struct etna_screen
*priv
= etna_screen(pscreen
);
113 static char buffer
[128];
115 snprintf(buffer
, sizeof(buffer
), "Vivante GC%x rev %04x", priv
->model
,
122 etna_screen_get_vendor(struct pipe_screen
*pscreen
)
128 etna_screen_get_device_vendor(struct pipe_screen
*pscreen
)
134 etna_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
136 struct etna_screen
*screen
= etna_screen(pscreen
);
139 /* Supported features (boolean caps). */
140 case PIPE_CAP_POINT_SPRITE
:
141 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
142 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
143 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
144 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
145 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
146 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
147 case PIPE_CAP_TEXTURE_BARRIER
:
148 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
149 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
150 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
151 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
152 case PIPE_CAP_TGSI_TEXCOORD
:
153 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
154 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
155 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
156 case PIPE_CAP_STRING_MARKER
:
157 case PIPE_CAP_SHAREABLE_SHADERS
:
159 case PIPE_CAP_NATIVE_FENCE_FD
:
160 return screen
->drm_version
>= ETNA_DRM_VERSION_FENCE_FD
;
161 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
162 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
: /* note: not integer */
163 return DBG_ENABLED(ETNA_DBG_NIR
);
164 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL
:
168 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
170 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
171 return 4; /* XXX could easily be supported */
173 case PIPE_CAP_NPOT_TEXTURES
:
174 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
175 NON_POWER_OF_TWO); */
177 case PIPE_CAP_ANISOTROPIC_FILTER
:
178 case PIPE_CAP_TEXTURE_SWIZZLE
:
179 case PIPE_CAP_PRIMITIVE_RESTART
:
180 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
181 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
183 /* Unsupported features. */
184 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
185 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
186 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
190 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
191 return DBG_ENABLED(ETNA_DBG_DEQP
) ? 4 : 0;
192 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
193 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
196 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
198 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
200 case PIPE_CAP_MAX_VERTEX_BUFFERS
:
201 return screen
->specs
.stream_count
;
202 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
203 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
207 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
208 return DBG_ENABLED(ETNA_DBG_NIR
) && screen
->specs
.halti
>= 2;
209 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
210 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
: /* TODO: verify */
211 return screen
->specs
.max_texture_size
;
212 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
213 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
215 int log2_max_tex_size
= util_last_bit(screen
->specs
.max_texture_size
);
216 assert(log2_max_tex_size
> 0);
217 return log2_max_tex_size
;
220 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
221 case PIPE_CAP_MIN_TEXEL_OFFSET
:
223 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
224 case PIPE_CAP_MAX_TEXEL_OFFSET
:
226 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
227 return screen
->specs
.seamless_cube_map
;
230 case PIPE_CAP_OCCLUSION_QUERY
:
231 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
234 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
236 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
: {
237 /* etnaviv is being run on systems as small as 256MB total RAM so
238 * we need to provide a sane value for such a device. Limit the
239 * memory budget to min(~3% of pyhiscal memory, 64MB).
241 * a simple divison by 32 provides the numbers we want.
245 uint64_t system_memory
;
247 if (!os_get_total_physical_memory(&system_memory
))
248 system_memory
= (uint64_t)4096 << 20;
250 return MIN2(system_memory
/ 32, 64 * 1024 * 1024);
253 case PIPE_CAP_MAX_VARYINGS
:
254 return screen
->specs
.max_varyings
;
256 case PIPE_CAP_PCI_GROUP
:
257 case PIPE_CAP_PCI_BUS
:
258 case PIPE_CAP_PCI_DEVICE
:
259 case PIPE_CAP_PCI_FUNCTION
:
261 case PIPE_CAP_ACCELERATED
:
263 case PIPE_CAP_VIDEO_MEMORY
:
268 return u_pipe_screen_get_param_defaults(pscreen
, param
);
273 etna_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
275 struct etna_screen
*screen
= etna_screen(pscreen
);
278 case PIPE_CAPF_MAX_LINE_WIDTH
:
279 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
280 case PIPE_CAPF_MAX_POINT_WIDTH
:
281 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
283 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
285 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
286 return util_last_bit(screen
->specs
.max_texture_size
);
287 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
288 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
289 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
293 debug_printf("unknown paramf %d", param
);
298 etna_screen_get_shader_param(struct pipe_screen
*pscreen
,
299 enum pipe_shader_type shader
,
300 enum pipe_shader_cap param
)
302 struct etna_screen
*screen
= etna_screen(pscreen
);
303 bool ubo_enable
= screen
->specs
.halti
>= 2 && DBG_ENABLED(ETNA_DBG_NIR
);
305 if (DBG_ENABLED(ETNA_DBG_DEQP
))
309 case PIPE_SHADER_FRAGMENT
:
310 case PIPE_SHADER_VERTEX
:
312 case PIPE_SHADER_COMPUTE
:
313 case PIPE_SHADER_GEOMETRY
:
314 case PIPE_SHADER_TESS_CTRL
:
315 case PIPE_SHADER_TESS_EVAL
:
318 DBG("unknown shader type %d", shader
);
323 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
324 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
325 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
326 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
327 return ETNA_MAX_TOKENS
;
328 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
329 return ETNA_MAX_DEPTH
; /* XXX */
330 case PIPE_SHADER_CAP_MAX_INPUTS
:
331 /* Maximum number of inputs for the vertex shader is the number
332 * of vertex elements - each element defines one vertex shader
333 * input register. For the fragment shader, this is the number
335 return shader
== PIPE_SHADER_FRAGMENT
? screen
->specs
.max_varyings
336 : screen
->specs
.vertex_max_elements
;
337 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
338 return 16; /* see VIVS_VS_OUTPUT */
339 case PIPE_SHADER_CAP_MAX_TEMPS
:
340 return 64; /* Max native temporaries. */
341 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
342 return ubo_enable
? ETNA_MAX_CONST_BUF
: 1;
343 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
345 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
346 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
347 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
348 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
350 case PIPE_SHADER_CAP_SUBROUTINES
:
352 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
353 return VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
354 case PIPE_SHADER_CAP_INT64_ATOMICS
:
355 case PIPE_SHADER_CAP_FP16
:
356 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
357 case PIPE_SHADER_CAP_INT16
:
358 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
360 case PIPE_SHADER_CAP_INTEGERS
:
361 return DBG_ENABLED(ETNA_DBG_NIR
) && screen
->specs
.halti
>= 2;
362 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
363 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
364 return shader
== PIPE_SHADER_FRAGMENT
365 ? screen
->specs
.fragment_sampler_count
366 : screen
->specs
.vertex_sampler_count
;
367 case PIPE_SHADER_CAP_PREFERRED_IR
:
368 return DBG_ENABLED(ETNA_DBG_NIR
) ? PIPE_SHADER_IR_NIR
: PIPE_SHADER_IR_TGSI
;
369 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
371 return 16384; /* 16384 so state tracker enables UBOs */
372 return shader
== PIPE_SHADER_FRAGMENT
373 ? screen
->specs
.max_ps_uniforms
* sizeof(float[4])
374 : screen
->specs
.max_vs_uniforms
* sizeof(float[4]);
375 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
376 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
377 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
378 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
379 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
381 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
383 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
385 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
386 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
387 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
388 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
389 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
390 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
394 debug_printf("unknown shader param %d", param
);
399 etna_screen_get_timestamp(struct pipe_screen
*pscreen
)
401 return os_time_get_nano();
405 gpu_supports_texture_target(struct etna_screen
*screen
,
406 enum pipe_texture_target target
)
408 if (target
== PIPE_TEXTURE_CUBE_ARRAY
)
411 /* pre-halti has no array/3D */
412 if (screen
->specs
.halti
< 0 &&
413 (target
== PIPE_TEXTURE_1D_ARRAY
||
414 target
== PIPE_TEXTURE_2D_ARRAY
||
415 target
== PIPE_TEXTURE_3D
))
422 gpu_supports_texture_format(struct etna_screen
*screen
, uint32_t fmt
,
423 enum pipe_format format
)
425 bool supported
= true;
427 if (fmt
== TEXTURE_FORMAT_ETC1
)
428 supported
= VIV_FEATURE(screen
, chipFeatures
, ETC1_TEXTURE_COMPRESSION
);
430 if (fmt
>= TEXTURE_FORMAT_DXT1
&& fmt
<= TEXTURE_FORMAT_DXT4_DXT5
)
431 supported
= VIV_FEATURE(screen
, chipFeatures
, DXT_TEXTURE_COMPRESSION
);
433 if (util_format_is_srgb(format
))
434 supported
= VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
436 if (fmt
& EXT_FORMAT
)
437 supported
= VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
439 if (fmt
& ASTC_FORMAT
) {
440 supported
= screen
->specs
.tex_astc
;
443 if (util_format_is_snorm(format
))
444 supported
= VIV_FEATURE(screen
, chipMinorFeatures2
, HALTI1
);
446 if (format
!= PIPE_FORMAT_S8_UINT_Z24_UNORM
&&
447 (util_format_is_pure_integer(format
) || util_format_is_float(format
)))
448 supported
= VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
454 if (texture_format_needs_swiz(format
))
455 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
461 gpu_supports_render_format(struct etna_screen
*screen
, enum pipe_format format
,
462 unsigned sample_count
)
464 const uint32_t fmt
= translate_pe_format(format
);
466 if (fmt
== ETNA_NO_MATCH
)
469 /* Validate MSAA; number of samples must be allowed, and render target
470 * must have MSAA'able format. */
471 if (sample_count
> 1) {
472 if (!VIV_FEATURE(screen
, chipFeatures
, MSAA
))
474 if (!translate_samples_to_xyscale(sample_count
, NULL
, NULL
))
476 if (translate_ts_format(format
) == ETNA_NO_MATCH
)
480 if (format
== PIPE_FORMAT_R8_UNORM
)
481 return VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
);
483 /* figure out 8bpp RS clear to enable these formats */
484 if (format
== PIPE_FORMAT_R8_SINT
|| format
== PIPE_FORMAT_R8_UINT
)
485 return VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
);
487 if (util_format_is_srgb(format
))
488 return VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI3
);
490 if (util_format_is_pure_integer(format
) || util_format_is_float(format
))
491 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
493 if (format
== PIPE_FORMAT_R8G8_UNORM
)
494 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
496 /* any other extended format is HALTI0 (only R10G10B10A2?) */
497 if (fmt
>= PE_FORMAT_R16F
)
498 return VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
);
504 gpu_supports_vertex_format(struct etna_screen
*screen
, enum pipe_format format
)
506 if (translate_vertex_format_type(format
) == ETNA_NO_MATCH
)
509 if (util_format_is_pure_integer(format
))
510 return VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
516 etna_screen_is_format_supported(struct pipe_screen
*pscreen
,
517 enum pipe_format format
,
518 enum pipe_texture_target target
,
519 unsigned sample_count
,
520 unsigned storage_sample_count
,
523 struct etna_screen
*screen
= etna_screen(pscreen
);
524 unsigned allowed
= 0;
526 if (!gpu_supports_texture_target(screen
, target
))
529 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
532 if (usage
& PIPE_BIND_RENDER_TARGET
) {
533 if (gpu_supports_render_format(screen
, format
, sample_count
))
534 allowed
|= PIPE_BIND_RENDER_TARGET
;
537 if (usage
& PIPE_BIND_DEPTH_STENCIL
) {
538 if (translate_depth_format(format
) != ETNA_NO_MATCH
)
539 allowed
|= PIPE_BIND_DEPTH_STENCIL
;
542 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
543 uint32_t fmt
= translate_texture_format(format
);
545 if (!gpu_supports_texture_format(screen
, fmt
, format
))
548 if (sample_count
< 2 && fmt
!= ETNA_NO_MATCH
)
549 allowed
|= PIPE_BIND_SAMPLER_VIEW
;
552 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
553 if (gpu_supports_vertex_format(screen
, format
))
554 allowed
|= PIPE_BIND_VERTEX_BUFFER
;
557 if (usage
& PIPE_BIND_INDEX_BUFFER
) {
558 /* must be supported index format */
559 if (format
== PIPE_FORMAT_I8_UINT
|| format
== PIPE_FORMAT_I16_UINT
||
560 (format
== PIPE_FORMAT_I32_UINT
&&
561 VIV_FEATURE(screen
, chipFeatures
, 32_BIT_INDICES
))) {
562 allowed
|= PIPE_BIND_INDEX_BUFFER
;
568 usage
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
);
570 if (usage
!= allowed
) {
571 DBG("not supported: format=%s, target=%d, sample_count=%d, "
572 "usage=%x, allowed=%x",
573 util_format_name(format
), target
, sample_count
, usage
, allowed
);
576 return usage
== allowed
;
579 const uint64_t supported_modifiers
[] = {
580 DRM_FORMAT_MOD_LINEAR
,
581 DRM_FORMAT_MOD_VIVANTE_TILED
,
582 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED
,
583 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED
,
584 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED
,
588 etna_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
589 enum pipe_format format
, int max
,
591 unsigned int *external_only
, int *count
)
593 struct etna_screen
*screen
= etna_screen(pscreen
);
594 int i
, num_modifiers
= 0;
596 if (max
> ARRAY_SIZE(supported_modifiers
))
597 max
= ARRAY_SIZE(supported_modifiers
);
601 max
= ARRAY_SIZE(supported_modifiers
);
604 for (i
= 0; num_modifiers
< max
; i
++) {
605 /* don't advertise split tiled formats on single pipe/buffer GPUs */
606 if ((screen
->specs
.pixel_pipes
== 1 || screen
->specs
.single_buffer
) &&
611 modifiers
[num_modifiers
] = supported_modifiers
[i
];
613 external_only
[num_modifiers
] = util_format_is_yuv(format
) ? 1 : 0;
617 *count
= num_modifiers
;
621 etna_determine_uniform_limits(struct etna_screen
*screen
)
623 /* values for the non unified case are taken from
624 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
625 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
627 if (screen
->model
== chipModel_GC2000
&&
628 (screen
->revision
== 0x5118 || screen
->revision
== 0x5140)) {
629 screen
->specs
.max_vs_uniforms
= 256;
630 screen
->specs
.max_ps_uniforms
= 64;
631 } else if (screen
->specs
.num_constants
== 320) {
632 screen
->specs
.max_vs_uniforms
= 256;
633 screen
->specs
.max_ps_uniforms
= 64;
634 } else if (screen
->specs
.num_constants
> 256 &&
635 screen
->model
== chipModel_GC1000
) {
636 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
637 screen
->specs
.max_vs_uniforms
= 256;
638 screen
->specs
.max_ps_uniforms
= 64;
639 } else if (screen
->specs
.num_constants
> 256) {
640 screen
->specs
.max_vs_uniforms
= 256;
641 screen
->specs
.max_ps_uniforms
= 256;
642 } else if (screen
->specs
.num_constants
== 256) {
643 screen
->specs
.max_vs_uniforms
= 256;
644 screen
->specs
.max_ps_uniforms
= 256;
646 screen
->specs
.max_vs_uniforms
= 168;
647 screen
->specs
.max_ps_uniforms
= 64;
652 etna_get_specs(struct etna_screen
*screen
)
655 uint32_t instruction_count
;
657 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_INSTRUCTION_COUNT
, &val
)) {
658 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
661 instruction_count
= val
;
663 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE
,
665 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
668 screen
->specs
.vertex_output_buffer_size
= val
;
670 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_VERTEX_CACHE_SIZE
, &val
)) {
671 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
674 screen
->specs
.vertex_cache_size
= val
;
676 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_SHADER_CORE_COUNT
, &val
)) {
677 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
680 screen
->specs
.shader_core_count
= val
;
682 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_STREAM_COUNT
, &val
)) {
683 DBG("could not get ETNA_GPU_STREAM_COUNT");
686 screen
->specs
.stream_count
= val
;
688 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REGISTER_MAX
, &val
)) {
689 DBG("could not get ETNA_GPU_REGISTER_MAX");
692 screen
->specs
.max_registers
= val
;
694 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_PIXEL_PIPES
, &val
)) {
695 DBG("could not get ETNA_GPU_PIXEL_PIPES");
698 screen
->specs
.pixel_pipes
= val
;
700 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_NUM_CONSTANTS
, &val
)) {
701 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
705 fprintf(stderr
, "Warning: zero num constants (update kernel?)\n");
708 screen
->specs
.num_constants
= val
;
710 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_NUM_VARYINGS
, &val
)) {
711 DBG("could not get ETNA_GPU_NUM_VARYINGS");
714 screen
->specs
.max_varyings
= MAX2(val
, ETNA_NUM_VARYINGS
);
716 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
717 * description of the differences. */
718 if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI5
))
719 screen
->specs
.halti
= 5; /* New GC7000/GC8x00 */
720 else if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI4
))
721 screen
->specs
.halti
= 4; /* Old GC7000/GC7400 */
722 else if (VIV_FEATURE(screen
, chipMinorFeatures5
, HALTI3
))
723 screen
->specs
.halti
= 3; /* None? */
724 else if (VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
))
725 screen
->specs
.halti
= 2; /* GC2500/GC3000/GC5000/GC6400 */
726 else if (VIV_FEATURE(screen
, chipMinorFeatures2
, HALTI1
))
727 screen
->specs
.halti
= 1; /* GC900/GC4000/GC7000UL */
728 else if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
))
729 screen
->specs
.halti
= 0; /* GC880/GC2000/GC7000TM */
731 screen
->specs
.halti
= -1; /* GC7000nanolite / pre-GC2000 except GC880 */
732 if (screen
->specs
.halti
>= 0)
733 DBG("etnaviv: GPU arch: HALTI%d", screen
->specs
.halti
);
735 DBG("etnaviv: GPU arch: pre-HALTI");
737 screen
->specs
.can_supertile
=
738 VIV_FEATURE(screen
, chipMinorFeatures0
, SUPER_TILED
);
739 screen
->specs
.bits_per_tile
=
740 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 2 : 4;
741 screen
->specs
.ts_clear_value
=
742 VIV_FEATURE(screen
, chipMinorFeatures5
, BLT_ENGINE
) ? 0xffffffff :
743 VIV_FEATURE(screen
, chipMinorFeatures0
, 2BITPERTILE
) ? 0x55555555 :
747 /* vertex and fragment samplers live in one address space */
748 screen
->specs
.vertex_sampler_offset
= 8;
749 screen
->specs
.fragment_sampler_count
= 8;
750 screen
->specs
.vertex_sampler_count
= 4;
752 if (screen
->model
== 0x400)
753 screen
->specs
.vertex_sampler_count
= 0;
755 screen
->specs
.vs_need_z_div
=
756 screen
->model
< 0x1000 && screen
->model
!= 0x880;
757 screen
->specs
.has_sin_cos_sqrt
=
758 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SQRT_TRIG
);
759 screen
->specs
.has_sign_floor_ceil
=
760 VIV_FEATURE(screen
, chipMinorFeatures0
, HAS_SIGN_FLOOR_CEIL
);
761 screen
->specs
.has_shader_range_registers
=
762 screen
->model
>= 0x1000 || screen
->model
== 0x880;
763 screen
->specs
.npot_tex_any_wrap
=
764 VIV_FEATURE(screen
, chipMinorFeatures1
, NON_POWER_OF_TWO
);
765 screen
->specs
.has_new_transcendentals
=
766 VIV_FEATURE(screen
, chipMinorFeatures3
, HAS_FAST_TRANSCENDENTALS
);
767 screen
->specs
.has_halti2_instructions
=
768 VIV_FEATURE(screen
, chipMinorFeatures4
, HALTI2
);
769 screen
->specs
.v4_compression
=
770 VIV_FEATURE(screen
, chipMinorFeatures6
, V4_COMPRESSION
);
771 screen
->specs
.seamless_cube_map
=
772 (screen
->model
!= 0x880) && /* Seamless cubemap is broken on GC880? */
773 VIV_FEATURE(screen
, chipMinorFeatures2
, SEAMLESS_CUBE_MAP
);
775 if (screen
->specs
.halti
>= 5) {
776 /* GC7000 - this core must load shaders from memory. */
777 screen
->specs
.vs_offset
= 0;
778 screen
->specs
.ps_offset
= 0;
779 screen
->specs
.max_instructions
= 0; /* Do not program shaders manually */
780 screen
->specs
.has_icache
= true;
781 } else if (VIV_FEATURE(screen
, chipMinorFeatures3
, INSTRUCTION_CACHE
)) {
782 /* GC3000 - this core is capable of loading shaders from
783 * memory. It can also run shaders from registers, as a fallback, but
784 * "max_instructions" does not have the correct value. It has place for
785 * 2*256 instructions just like GC2000, but the offsets are slightly
788 screen
->specs
.vs_offset
= 0xC000;
789 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
790 * this mirror for writing PS instructions, probably safest to do the
793 screen
->specs
.ps_offset
= 0x8000 + 0x1000;
794 screen
->specs
.max_instructions
= 256; /* maximum number instructions for non-icache use */
795 screen
->specs
.has_icache
= true;
797 if (instruction_count
> 256) { /* unified instruction memory? */
798 screen
->specs
.vs_offset
= 0xC000;
799 screen
->specs
.ps_offset
= 0xD000; /* like vivante driver */
800 screen
->specs
.max_instructions
= 256;
802 screen
->specs
.vs_offset
= 0x4000;
803 screen
->specs
.ps_offset
= 0x6000;
804 screen
->specs
.max_instructions
= instruction_count
/ 2;
806 screen
->specs
.has_icache
= false;
809 if (VIV_FEATURE(screen
, chipMinorFeatures1
, HALTI0
)) {
810 screen
->specs
.vertex_max_elements
= 16;
812 /* Etna_viv documentation seems confused over the correct value
813 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
814 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
815 screen
->specs
.vertex_max_elements
= 10;
818 etna_determine_uniform_limits(screen
);
820 if (screen
->specs
.halti
>= 5) {
821 screen
->specs
.has_unified_uniforms
= true;
822 screen
->specs
.vs_uniforms_offset
= VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
823 screen
->specs
.ps_uniforms_offset
= VIVS_SH_HALTI5_UNIFORMS(screen
->specs
.max_vs_uniforms
*4);
824 } else if (screen
->specs
.halti
>= 1) {
825 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
827 screen
->specs
.has_unified_uniforms
= true;
828 screen
->specs
.vs_uniforms_offset
= VIVS_SH_UNIFORMS(0);
829 /* hardcode PS uniforms to start after end of VS uniforms -
830 * for more flexibility this offset could be variable based on the
833 screen
->specs
.ps_uniforms_offset
= VIVS_SH_UNIFORMS(screen
->specs
.max_vs_uniforms
*4);
835 screen
->specs
.has_unified_uniforms
= false;
836 screen
->specs
.vs_uniforms_offset
= VIVS_VS_UNIFORMS(0);
837 screen
->specs
.ps_uniforms_offset
= VIVS_PS_UNIFORMS(0);
840 screen
->specs
.max_texture_size
=
841 VIV_FEATURE(screen
, chipMinorFeatures0
, TEXTURE_8K
) ? 8192 : 2048;
842 screen
->specs
.max_rendertarget_size
=
843 VIV_FEATURE(screen
, chipMinorFeatures0
, RENDERTARGET_8K
) ? 8192 : 2048;
845 screen
->specs
.single_buffer
= VIV_FEATURE(screen
, chipMinorFeatures4
, SINGLE_BUFFER
);
846 if (screen
->specs
.single_buffer
)
847 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen
->specs
.pixel_pipes
);
849 screen
->specs
.tex_astc
= VIV_FEATURE(screen
, chipMinorFeatures4
, TEXTURE_ASTC
) &&
850 !VIV_FEATURE(screen
, chipMinorFeatures6
, NO_ASTC
);
852 screen
->specs
.use_blt
= VIV_FEATURE(screen
, chipMinorFeatures5
, BLT_ENGINE
);
861 etna_screen_bo_from_handle(struct pipe_screen
*pscreen
,
862 struct winsys_handle
*whandle
, unsigned *out_stride
)
864 struct etna_screen
*screen
= etna_screen(pscreen
);
867 if (whandle
->type
== WINSYS_HANDLE_TYPE_SHARED
) {
868 bo
= etna_bo_from_name(screen
->dev
, whandle
->handle
);
869 } else if (whandle
->type
== WINSYS_HANDLE_TYPE_FD
) {
870 bo
= etna_bo_from_dmabuf(screen
->dev
, whandle
->handle
);
872 DBG("Attempt to import unsupported handle type %d", whandle
->type
);
877 DBG("ref name 0x%08x failed", whandle
->handle
);
881 *out_stride
= whandle
->stride
;
887 etna_get_compiler_options(struct pipe_screen
*pscreen
,
888 enum pipe_shader_ir ir
, unsigned shader
)
890 return &etna_screen(pscreen
)->options
;
894 etna_screen_create(struct etna_device
*dev
, struct etna_gpu
*gpu
,
895 struct renderonly
*ro
)
897 struct etna_screen
*screen
= CALLOC_STRUCT(etna_screen
);
898 struct pipe_screen
*pscreen
;
899 drmVersionPtr version
;
905 pscreen
= &screen
->base
;
908 screen
->ro
= renderonly_dup(ro
);
912 DBG("could not create renderonly object");
916 version
= drmGetVersion(screen
->ro
->gpu_fd
);
917 screen
->drm_version
= ETNA_DRM_VERSION(version
->version_major
,
918 version
->version_minor
);
919 drmFreeVersion(version
);
921 etna_mesa_debug
= debug_get_option_etna_mesa_debug();
923 /* Disable autodisable for correct rendering with TS */
924 etna_mesa_debug
|= ETNA_DBG_NO_AUTODISABLE
;
926 screen
->pipe
= etna_pipe_new(gpu
, ETNA_PIPE_3D
);
928 DBG("could not create 3d pipe");
932 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_MODEL
, &val
)) {
933 DBG("could not get ETNA_GPU_MODEL");
938 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_REVISION
, &val
)) {
939 DBG("could not get ETNA_GPU_REVISION");
942 screen
->revision
= val
;
944 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_0
, &val
)) {
945 DBG("could not get ETNA_GPU_FEATURES_0");
948 screen
->features
[0] = val
;
950 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_1
, &val
)) {
951 DBG("could not get ETNA_GPU_FEATURES_1");
954 screen
->features
[1] = val
;
956 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_2
, &val
)) {
957 DBG("could not get ETNA_GPU_FEATURES_2");
960 screen
->features
[2] = val
;
962 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_3
, &val
)) {
963 DBG("could not get ETNA_GPU_FEATURES_3");
966 screen
->features
[3] = val
;
968 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_4
, &val
)) {
969 DBG("could not get ETNA_GPU_FEATURES_4");
972 screen
->features
[4] = val
;
974 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_5
, &val
)) {
975 DBG("could not get ETNA_GPU_FEATURES_5");
978 screen
->features
[5] = val
;
980 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_6
, &val
)) {
981 DBG("could not get ETNA_GPU_FEATURES_6");
984 screen
->features
[6] = val
;
986 if (etna_gpu_get_param(screen
->gpu
, ETNA_GPU_FEATURES_7
, &val
)) {
987 DBG("could not get ETNA_GPU_FEATURES_7");
990 screen
->features
[7] = val
;
992 if (!etna_get_specs(screen
))
995 if (screen
->specs
.halti
>= 5 && !etnaviv_device_softpin_capable(dev
)) {
996 DBG("halti5 requires softpin");
1000 screen
->options
= (nir_shader_compiler_options
) {
1003 .lower_ftrunc
= true,
1005 .lower_bitops
= true,
1006 .lower_all_io_to_temps
= true,
1007 .vertex_id_zero_based
= true,
1008 .lower_flrp32
= true,
1010 .lower_vector_cmp
= true,
1012 .lower_fdiv
= true, /* !screen->specs.has_new_transcendentals */
1013 .lower_fsign
= !screen
->specs
.has_sign_floor_ceil
,
1014 .lower_ffloor
= !screen
->specs
.has_sign_floor_ceil
,
1015 .lower_fceil
= !screen
->specs
.has_sign_floor_ceil
,
1016 .lower_fsqrt
= !screen
->specs
.has_sin_cos_sqrt
,
1017 .lower_sincos
= !screen
->specs
.has_sin_cos_sqrt
,
1020 /* apply debug options that disable individual features */
1021 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z
))
1022 screen
->features
[viv_chipFeatures
] |= chipFeatures_NO_EARLY_Z
;
1023 if (DBG_ENABLED(ETNA_DBG_NO_TS
))
1024 screen
->features
[viv_chipFeatures
] &= ~chipFeatures_FAST_CLEAR
;
1025 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE
))
1026 screen
->features
[viv_chipMinorFeatures1
] &= ~chipMinorFeatures1_AUTO_DISABLE
;
1027 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE
))
1028 screen
->specs
.can_supertile
= 0;
1029 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF
))
1030 screen
->specs
.single_buffer
= 0;
1032 pscreen
->destroy
= etna_screen_destroy
;
1033 pscreen
->get_param
= etna_screen_get_param
;
1034 pscreen
->get_paramf
= etna_screen_get_paramf
;
1035 pscreen
->get_shader_param
= etna_screen_get_shader_param
;
1036 pscreen
->get_compiler_options
= etna_get_compiler_options
;
1038 pscreen
->get_name
= etna_screen_get_name
;
1039 pscreen
->get_vendor
= etna_screen_get_vendor
;
1040 pscreen
->get_device_vendor
= etna_screen_get_device_vendor
;
1042 pscreen
->get_timestamp
= etna_screen_get_timestamp
;
1043 pscreen
->context_create
= etna_context_create
;
1044 pscreen
->is_format_supported
= etna_screen_is_format_supported
;
1045 pscreen
->query_dmabuf_modifiers
= etna_screen_query_dmabuf_modifiers
;
1047 screen
->compiler
= etna_compiler_create();
1048 if (!screen
->compiler
)
1051 etna_fence_screen_init(pscreen
);
1052 etna_query_screen_init(pscreen
);
1053 etna_resource_screen_init(pscreen
);
1055 util_dynarray_init(&screen
->supported_pm_queries
, NULL
);
1056 slab_create_parent(&screen
->transfer_pool
, sizeof(struct etna_transfer
), 16);
1058 if (screen
->drm_version
>= ETNA_DRM_VERSION_PERFMON
)
1059 etna_pm_query_setup(screen
);
1064 etna_screen_destroy(pscreen
);