src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #include <drm_fourcc.h>
  49
  50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  51 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  52
  53 static const struct debug_named_value debug_options[] = {
  54    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  55    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  56    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  57    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  58    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  59    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  60    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  61    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  62    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  63    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  64    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  65    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  66    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  67    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  68    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  69    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  70    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  71    DEBUG_NAMED_VALUE_END
  72 };
  73
  74 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  75 int etna_mesa_debug = 0;
  76
  77 static void
  78 etna_screen_destroy(struct pipe_screen *pscreen)
  79 {
  80    struct etna_screen *screen = etna_screen(pscreen);
  81
  82    if (screen->pipe)
  83       etna_pipe_del(screen->pipe);
  84
  85    if (screen->gpu)
  86       etna_gpu_del(screen->gpu);
  87
  88    if (screen->ro)
  89       FREE(screen->ro);
  90
  91    if (screen->dev)
  92       etna_device_del(screen->dev);
  93
  94    FREE(screen);
  95 }
  96
  97 static const char *
  98 etna_screen_get_name(struct pipe_screen *pscreen)
  99 {
 100    struct etna_screen *priv = etna_screen(pscreen);
 101    static char buffer[128];
 102
 103    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 104                  priv->revision);
 105
 106    return buffer;
 107 }
 108
 109 static const char *
 110 etna_screen_get_vendor(struct pipe_screen *pscreen)
 111 {
 112    return "etnaviv";
 113 }
 114
 115 static const char *
 116 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 117 {
 118    return "Vivante";
 119 }
 120
 121 static int
 122 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 123 {
 124    struct etna_screen *screen = etna_screen(pscreen);
 125
 126    switch (param) {
 127    /* Supported features (boolean caps). */
 128    case PIPE_CAP_TWO_SIDED_STENCIL:
 129    case PIPE_CAP_ANISOTROPIC_FILTER:
 130    case PIPE_CAP_POINT_SPRITE:
 131    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 132    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 133    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 134    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 135    case PIPE_CAP_SM3:
 136    case PIPE_CAP_TEXTURE_BARRIER:
 137    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 138    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 140    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 141    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 142    case PIPE_CAP_TGSI_TEXCOORD:
 143    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 144       return 1;
 145    case PIPE_CAP_NATIVE_FENCE_FD:
 146       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 147
 148    /* Memory */
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 152       return 4; /* XXX could easily be supported */
 153    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 154       return 120;
 155
 156    case PIPE_CAP_NPOT_TEXTURES:
 157       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 158                       NON_POWER_OF_TWO); */
 159
 160    case PIPE_CAP_TEXTURE_SWIZZLE:
 161    case PIPE_CAP_PRIMITIVE_RESTART:
 162       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 163
 164    case PIPE_CAP_ENDIANNESS:
 165       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 166                                     ENDIANNESS_CONFIG) */
 167
 168    /* Unsupported features. */
 169    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 170    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 172    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 173    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 174    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 175    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 176    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 177    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 178    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 179    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 180    case PIPE_CAP_INDEP_BLEND_ENABLE:
 181    case PIPE_CAP_INDEP_BLEND_FUNC:
 182    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 183    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 184    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 185    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 187    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 188    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 189    case PIPE_CAP_USER_VERTEX_BUFFERS:
 190    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 191    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 192    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 193    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 194    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 195    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 196    case PIPE_CAP_TEXTURE_GATHER_SM5:
 197    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 198    case PIPE_CAP_FAKE_SW_MSAA:
 199    case PIPE_CAP_TEXTURE_QUERY_LOD:
 200    case PIPE_CAP_SAMPLE_SHADING:
 201    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 202    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 203    case PIPE_CAP_DRAW_INDIRECT:
 204    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 205    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 206    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 207    case PIPE_CAP_CLIP_HALFZ:
 208    case PIPE_CAP_VERTEXID_NOBASE:
 209    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 211    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 212    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 213    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 214    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 215    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 217    case PIPE_CAP_TGSI_TXQS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 221    case PIPE_CAP_CLEAR_TEXTURE:
 222    case PIPE_CAP_DRAW_PARAMETERS:
 223    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 225    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 226    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 227    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 228    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 229    case PIPE_CAP_INVALIDATE_BUFFER:
 230    case PIPE_CAP_GENERATE_MIPMAP:
 231    case PIPE_CAP_STRING_MARKER:
 232    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 233    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 234    case PIPE_CAP_QUERY_MEMORY_INFO:
 235    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 236    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 237    case PIPE_CAP_CULL_DISTANCE:
 238    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 239    case PIPE_CAP_TGSI_VOTE:
 240    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 241    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 242    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 243    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 244    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 246    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 247    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 248    case PIPE_CAP_TGSI_FS_FBFETCH:
 249    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 250    case PIPE_CAP_DOUBLES:
 251    case PIPE_CAP_INT64:
 252    case PIPE_CAP_INT64_DIVMOD:
 253    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 254    case PIPE_CAP_TGSI_CLOCK:
 255    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 256    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 257    case PIPE_CAP_TGSI_BALLOT:
 258    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 259    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 260    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 261    case PIPE_CAP_POST_DEPTH_COVERAGE:
 262    case PIPE_CAP_BINDLESS_TEXTURE:
 263    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 264    case PIPE_CAP_QUERY_SO_OVERFLOW:
 265    case PIPE_CAP_MEMOBJ:
 266    case PIPE_CAP_LOAD_CONSTBUF:
 267    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 268    case PIPE_CAP_TILE_RASTER_ORDER:
 269    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 270    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 271       return 0;
 272
 273    /* Stream output. */
 274    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 275    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 276    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 277    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 278       return 0;
 279
 280    /* Geometry shader output, unsupported. */
 281    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 282    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 283    case PIPE_CAP_MAX_VERTEX_STREAMS:
 284       return 0;
 285
 286    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 287       return 128;
 288
 289    /* Texturing. */
 290    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 291    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 292    {
 293       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 294       assert(log2_max_tex_size > 0);
 295       return log2_max_tex_size;
 296    }
 297    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 298       return 5;
 299    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 300       return 0;
 301    case PIPE_CAP_CUBE_MAP_ARRAY:
 302       return 0;
 303    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 304    case PIPE_CAP_MIN_TEXEL_OFFSET:
 305       return -8;
 306    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 307    case PIPE_CAP_MAX_TEXEL_OFFSET:
 308       return 7;
 309    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 310       return 0;
 311    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 312       return 65536;
 313
 314    /* Render targets. */
 315    case PIPE_CAP_MAX_RENDER_TARGETS:
 316       return 1;
 317
 318    /* Viewports and scissors. */
 319    case PIPE_CAP_MAX_VIEWPORTS:
 320       return 1;
 321
 322    /* Timer queries. */
 323    case PIPE_CAP_QUERY_TIME_ELAPSED:
 324       return 0;
 325    case PIPE_CAP_OCCLUSION_QUERY:
 326       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 327    case PIPE_CAP_QUERY_TIMESTAMP:
 328       return 1;
 329    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 330       return 0;
 331
 332    /* Preferences */
 333    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 334       return 0;
 335
 336    case PIPE_CAP_PCI_GROUP:
 337    case PIPE_CAP_PCI_BUS:
 338    case PIPE_CAP_PCI_DEVICE:
 339    case PIPE_CAP_PCI_FUNCTION:
 340       return 0;
 341    case PIPE_CAP_VENDOR_ID:
 342    case PIPE_CAP_DEVICE_ID:
 343       return 0xFFFFFFFF;
 344    case PIPE_CAP_ACCELERATED:
 345       return 1;
 346    case PIPE_CAP_VIDEO_MEMORY:
 347       return 0;
 348    case PIPE_CAP_UMA:
 349       return 1;
 350    }
 351
 352    debug_printf("unknown param %d", param);
 353    return 0;
 354 }
 355
 356 static float
 357 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 358 {
 359    struct etna_screen *screen = etna_screen(pscreen);
 360
 361    switch (param) {
 362    case PIPE_CAPF_MAX_LINE_WIDTH:
 363    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 364    case PIPE_CAPF_MAX_POINT_WIDTH:
 365    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 366       return 8192.0f;
 367    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 368       return 16.0f;
 369    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 370       return util_last_bit(screen->specs.max_texture_size);
 371    case PIPE_CAPF_GUARD_BAND_LEFT:
 372    case PIPE_CAPF_GUARD_BAND_TOP:
 373    case PIPE_CAPF_GUARD_BAND_RIGHT:
 374    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 375       return 0.0f;
 376    }
 377
 378    debug_printf("unknown paramf %d", param);
 379    return 0;
 380 }
 381
 382 static int
 383 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 384                              enum pipe_shader_type shader,
 385                              enum pipe_shader_cap param)
 386 {
 387    struct etna_screen *screen = etna_screen(pscreen);
 388
 389    switch (shader) {
 390    case PIPE_SHADER_FRAGMENT:
 391    case PIPE_SHADER_VERTEX:
 392       break;
 393    case PIPE_SHADER_COMPUTE:
 394    case PIPE_SHADER_GEOMETRY:
 395    case PIPE_SHADER_TESS_CTRL:
 396    case PIPE_SHADER_TESS_EVAL:
 397       return 0;
 398    default:
 399       DBG("unknown shader type %d", shader);
 400       return 0;
 401    }
 402
 403    switch (param) {
 404    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 405    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 406    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 407    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 408       return ETNA_MAX_TOKENS;
 409    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 410       return ETNA_MAX_DEPTH; /* XXX */
 411    case PIPE_SHADER_CAP_MAX_INPUTS:
 412       /* Maximum number of inputs for the vertex shader is the number
 413        * of vertex elements - each element defines one vertex shader
 414        * input register.  For the fragment shader, this is the number
 415        * of varyings. */
 416       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 417                                             : screen->specs.vertex_max_elements;
 418    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 419       return 16; /* see VIVS_VS_OUTPUT */
 420    case PIPE_SHADER_CAP_MAX_TEMPS:
 421       return 64; /* Max native temporaries. */
 422    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 423       return 1;
 424    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 425       return 1;
 426    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 427    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 428    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 429    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 430       return 1;
 431    case PIPE_SHADER_CAP_SUBROUTINES:
 432       return 0;
 433    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 434       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 435    case PIPE_SHADER_CAP_INTEGERS:
 436    case PIPE_SHADER_CAP_INT64_ATOMICS:
 437    case PIPE_SHADER_CAP_FP16:
 438       return 0;
 439    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 440    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 441       return shader == PIPE_SHADER_FRAGMENT
 442                 ? screen->specs.fragment_sampler_count
 443                 : screen->specs.vertex_sampler_count;
 444    case PIPE_SHADER_CAP_PREFERRED_IR:
 445       return PIPE_SHADER_IR_TGSI;
 446    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 447       return 4096;
 448    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 449    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 450    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 451    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 452    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 453       return false;
 454    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 455       return 0;
 456    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 457       return 32;
 458    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 459    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 460    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 461    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 462       return 0;
 463    }
 464
 465    debug_printf("unknown shader param %d", param);
 466    return 0;
 467 }
 468
 469 static uint64_t
 470 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 471 {
 472    return os_time_get_nano();
 473 }
 474
 475 static bool
 476 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 477                            enum pipe_format format)
 478 {
 479    bool supported = true;
 480
 481    if (fmt == TEXTURE_FORMAT_ETC1)
 482       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 483
 484    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 485       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 486
 487    if (util_format_is_srgb(format))
 488       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 489
 490    if (fmt & EXT_FORMAT) {
 491       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 492
 493       /* ETC1 is checked above, as it has its own feature bit. ETC2 is
 494        * supported with HALTI0, however that implementation is buggy in hardware.
 495        * The blob driver does per-block patching to work around this. As this
 496        * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
 497        * only.
 498        */
 499       if (util_format_is_etc(format))
 500          supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
 501    }
 502
 503    if (fmt & ASTC_FORMAT) {
 504       supported = screen->specs.tex_astc;
 505    }
 506
 507    if (!supported)
 508       return false;
 509
 510    if (texture_format_needs_swiz(format))
 511       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 512
 513    return true;
 514 }
 515
 516 static boolean
 517 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 518                                 enum pipe_format format,
 519                                 enum pipe_texture_target target,
 520                                 unsigned sample_count, unsigned usage)
 521 {
 522    struct etna_screen *screen = etna_screen(pscreen);
 523    unsigned allowed = 0;
 524
 525    if (target != PIPE_BUFFER &&
 526        target != PIPE_TEXTURE_1D &&
 527        target != PIPE_TEXTURE_2D &&
 528        target != PIPE_TEXTURE_3D &&
 529        target != PIPE_TEXTURE_CUBE &&
 530        target != PIPE_TEXTURE_RECT)
 531       return FALSE;
 532
 533    if (usage & PIPE_BIND_RENDER_TARGET) {
 534       /* if render target, must be RS-supported format */
 535       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 536          /* Validate MSAA; number of samples must be allowed, and render target
 537           * must have MSAA'able format. */
 538          if (sample_count > 1) {
 539             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 540                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 541                allowed |= PIPE_BIND_RENDER_TARGET;
 542             }
 543          } else {
 544             allowed |= PIPE_BIND_RENDER_TARGET;
 545          }
 546       }
 547    }
 548
 549    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 550       if (translate_depth_format(format) != ETNA_NO_MATCH)
 551          allowed |= PIPE_BIND_DEPTH_STENCIL;
 552    }
 553
 554    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 555       uint32_t fmt = translate_texture_format(format);
 556
 557       if (!gpu_supports_texure_format(screen, fmt, format))
 558          fmt = ETNA_NO_MATCH;
 559
 560       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 561          allowed |= PIPE_BIND_SAMPLER_VIEW;
 562    }
 563
 564    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 565       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 566          allowed |= PIPE_BIND_VERTEX_BUFFER;
 567    }
 568
 569    if (usage & PIPE_BIND_INDEX_BUFFER) {
 570       /* must be supported index format */
 571       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 572           (format == PIPE_FORMAT_I32_UINT &&
 573            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 574          allowed |= PIPE_BIND_INDEX_BUFFER;
 575       }
 576    }
 577
 578    /* Always allowed */
 579    allowed |=
 580       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 581
 582    if (usage != allowed) {
 583       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 584           "usage=%x, allowed=%x",
 585           util_format_name(format), target, sample_count, usage, allowed);
 586    }
 587
 588    return usage == allowed;
 589 }
 590
 591 const uint64_t supported_modifiers[] = {
 592    DRM_FORMAT_MOD_LINEAR,
 593    DRM_FORMAT_MOD_VIVANTE_TILED,
 594    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 595    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 596    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 597 };
 598
 599 static void
 600 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 601                                    enum pipe_format format, int max,
 602                                    uint64_t *modifiers,
 603                                    unsigned int *external_only, int *count)
 604 {
 605    struct etna_screen *screen = etna_screen(pscreen);
 606    int i, num_modifiers = 0;
 607
 608    if (max > ARRAY_SIZE(supported_modifiers))
 609       max = ARRAY_SIZE(supported_modifiers);
 610
 611    if (!max) {
 612       modifiers = NULL;
 613       max = ARRAY_SIZE(supported_modifiers);
 614    }
 615
 616    for (i = 0; num_modifiers < max; i++) {
 617       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 618       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 619           i >= 3)
 620          break;
 621
 622       if (modifiers)
 623          modifiers[num_modifiers] = supported_modifiers[i];
 624       if (external_only)
 625          external_only[num_modifiers] = 0;
 626       num_modifiers++;
 627    }
 628
 629    *count = num_modifiers;
 630 }
 631
 632 static boolean
 633 etna_get_specs(struct etna_screen *screen)
 634 {
 635    uint64_t val;
 636    uint32_t instruction_count;
 637
 638    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 639       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 640       goto fail;
 641    }
 642    instruction_count = val;
 643
 644    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 645                           &val)) {
 646       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 647       goto fail;
 648    }
 649    screen->specs.vertex_output_buffer_size = val;
 650
 651    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 652       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 653       goto fail;
 654    }
 655    screen->specs.vertex_cache_size = val;
 656
 657    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 658       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 659       goto fail;
 660    }
 661    screen->specs.shader_core_count = val;
 662
 663    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 664       DBG("could not get ETNA_GPU_STREAM_COUNT");
 665       goto fail;
 666    }
 667    screen->specs.stream_count = val;
 668
 669    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 670       DBG("could not get ETNA_GPU_REGISTER_MAX");
 671       goto fail;
 672    }
 673    screen->specs.max_registers = val;
 674
 675    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 676       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 677       goto fail;
 678    }
 679    screen->specs.pixel_pipes = val;
 680
 681    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 682       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 683       goto fail;
 684    }
 685    if (val == 0) {
 686       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 687       val = 168;
 688    }
 689    screen->specs.num_constants = val;
 690
 691    screen->specs.can_supertile =
 692       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 693    screen->specs.bits_per_tile =
 694       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 695    screen->specs.ts_clear_value =
 696       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 697                                                            : 0x11111111;
 698
 699    /* vertex and fragment samplers live in one address space */
 700    screen->specs.vertex_sampler_offset = 8;
 701    screen->specs.fragment_sampler_count = 8;
 702    screen->specs.vertex_sampler_count = 4;
 703    screen->specs.vs_need_z_div =
 704       screen->model < 0x1000 && screen->model != 0x880;
 705    screen->specs.has_sin_cos_sqrt =
 706       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 707    screen->specs.has_sign_floor_ceil =
 708       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 709    screen->specs.has_shader_range_registers =
 710       screen->model >= 0x1000 || screen->model == 0x880;
 711    screen->specs.npot_tex_any_wrap =
 712       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 713    screen->specs.has_new_transcendentals =
 714       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 715    screen->specs.has_halti2_instructions =
 716       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 717
 718    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 719       /* GC3000 - this core is capable of loading shaders from
 720        * memory. It can also run shaders from registers, as a fallback, but
 721        * "max_instructions" does not have the correct value. It has place for
 722        * 2*256 instructions just like GC2000, but the offsets are slightly
 723        * different.
 724        */
 725       screen->specs.vs_offset = 0xC000;
 726       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 727        * this mirror for writing PS instructions, probably safest to do the
 728        * same.
 729        */
 730       screen->specs.ps_offset = 0x8000 + 0x1000;
 731       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 732       screen->specs.has_icache = true;
 733    } else {
 734       if (instruction_count > 256) { /* unified instruction memory? */
 735          screen->specs.vs_offset = 0xC000;
 736          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 737          screen->specs.max_instructions = 256;
 738       } else {
 739          screen->specs.vs_offset = 0x4000;
 740          screen->specs.ps_offset = 0x6000;
 741          screen->specs.max_instructions = instruction_count / 2;
 742       }
 743       screen->specs.has_icache = false;
 744    }
 745
 746    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 747       screen->specs.max_varyings = 12;
 748       screen->specs.vertex_max_elements = 16;
 749    } else {
 750       screen->specs.max_varyings = 8;
 751       /* Etna_viv documentation seems confused over the correct value
 752        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 753        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 754       screen->specs.vertex_max_elements = 10;
 755    }
 756
 757    /* Etna_viv documentation does not indicate where varyings above 8 are
 758     * stored. Moreover, if we are passed more than 8 varyings, we will
 759     * walk off the end of some arrays. Limit the maximum number of varyings. */
 760    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 761       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 762
 763    /* from QueryShaderCaps in kernel driver */
 764    if (screen->model < chipModel_GC4000) {
 765       screen->specs.max_vs_uniforms = 168;
 766       screen->specs.max_ps_uniforms = 64;
 767    } else {
 768       screen->specs.max_vs_uniforms = 256;
 769       screen->specs.max_ps_uniforms = 256;
 770    }
 771    /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 772    */
 773    if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) {
 774       screen->specs.has_unified_uniforms = true;
 775       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 776       /* hardcode PS uniforms to start after end of VS uniforms -
 777        * for more flexibility this offset could be variable based on the
 778        * shader.
 779        */
 780       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 781    } else {
 782       screen->specs.has_unified_uniforms = false;
 783       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 784       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 785    }
 786
 787    screen->specs.max_texture_size =
 788       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 789    screen->specs.max_rendertarget_size =
 790       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 791
 792    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 793    if (screen->specs.single_buffer)
 794       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 795
 796    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 797
 798    return true;
 799
 800 fail:
 801    return false;
 802 }
 803
 804 struct etna_bo *
 805 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 806                            struct winsys_handle *whandle, unsigned *out_stride)
 807 {
 808    struct etna_screen *screen = etna_screen(pscreen);
 809    struct etna_bo *bo;
 810
 811    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 812       bo = etna_bo_from_name(screen->dev, whandle->handle);
 813    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 814       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 815    } else {
 816       DBG("Attempt to import unsupported handle type %d", whandle->type);
 817       return NULL;
 818    }
 819
 820    if (!bo) {
 821       DBG("ref name 0x%08x failed", whandle->handle);
 822       return NULL;
 823    }
 824
 825    *out_stride = whandle->stride;
 826
 827    return bo;
 828 }
 829
 830 struct pipe_screen *
 831 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 832                    struct renderonly *ro)
 833 {
 834    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 835    struct pipe_screen *pscreen;
 836    drmVersionPtr version;
 837    uint64_t val;
 838
 839    if (!screen)
 840       return NULL;
 841
 842    pscreen = &screen->base;
 843    screen->dev = dev;
 844    screen->gpu = gpu;
 845    screen->ro = renderonly_dup(ro);
 846    screen->refcnt = 1;
 847
 848    if (!screen->ro) {
 849       DBG("could not create renderonly object");
 850       goto fail;
 851    }
 852
 853    version = drmGetVersion(screen->ro->gpu_fd);
 854    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 855                                           version->version_minor);
 856    drmFreeVersion(version);
 857
 858    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 859
 860    /* Disable autodisable for correct rendering with TS */
 861    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 862
 863    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 864    if (!screen->pipe) {
 865       DBG("could not create 3d pipe");
 866       goto fail;
 867    }
 868
 869    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 870       DBG("could not get ETNA_GPU_MODEL");
 871       goto fail;
 872    }
 873    screen->model = val;
 874
 875    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 876       DBG("could not get ETNA_GPU_REVISION");
 877       goto fail;
 878    }
 879    screen->revision = val;
 880
 881    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 882       DBG("could not get ETNA_GPU_FEATURES_0");
 883       goto fail;
 884    }
 885    screen->features[0] = val;
 886
 887    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 888       DBG("could not get ETNA_GPU_FEATURES_1");
 889       goto fail;
 890    }
 891    screen->features[1] = val;
 892
 893    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 894       DBG("could not get ETNA_GPU_FEATURES_2");
 895       goto fail;
 896    }
 897    screen->features[2] = val;
 898
 899    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 900       DBG("could not get ETNA_GPU_FEATURES_3");
 901       goto fail;
 902    }
 903    screen->features[3] = val;
 904
 905    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 906       DBG("could not get ETNA_GPU_FEATURES_4");
 907       goto fail;
 908    }
 909    screen->features[4] = val;
 910
 911    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 912       DBG("could not get ETNA_GPU_FEATURES_5");
 913       goto fail;
 914    }
 915    screen->features[5] = val;
 916
 917    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 918       DBG("could not get ETNA_GPU_FEATURES_6");
 919       goto fail;
 920    }
 921    screen->features[6] = val;
 922
 923    if (!etna_get_specs(screen))
 924       goto fail;
 925
 926    /* apply debug options that disable individual features */
 927    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 928       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 929    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 930          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 931    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 932       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 933    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 934       screen->specs.can_supertile = 0;
 935
 936    pscreen->destroy = etna_screen_destroy;
 937    pscreen->get_param = etna_screen_get_param;
 938    pscreen->get_paramf = etna_screen_get_paramf;
 939    pscreen->get_shader_param = etna_screen_get_shader_param;
 940
 941    pscreen->get_name = etna_screen_get_name;
 942    pscreen->get_vendor = etna_screen_get_vendor;
 943    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 944
 945    pscreen->get_timestamp = etna_screen_get_timestamp;
 946    pscreen->context_create = etna_context_create;
 947    pscreen->is_format_supported = etna_screen_is_format_supported;
 948    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 949
 950    etna_fence_screen_init(pscreen);
 951    etna_query_screen_init(pscreen);
 952    etna_resource_screen_init(pscreen);
 953
 954    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 955
 956    return pscreen;
 957
 958 fail:
 959    etna_screen_destroy(pscreen);
 960    return NULL;
 961 }