ec6f30210016b8cc870665d36bfcf3c251a599e8
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_screen.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
26 */
27
28 #include "etnaviv_screen.h"
29
30 #include "hw/common.xml.h"
31
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
40
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
47
48 #include "state_tracker/drm_driver.h"
49
50 #include "drm-uapi/drm_fourcc.h"
51
52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
53 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
54 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
55
56 static const struct debug_named_value debug_options[] = {
57 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"},
62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
63 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"},
64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
65 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
66 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"},
67 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
68 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"},
69 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"},
70 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
71 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
72 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
73 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
75 DEBUG_NAMED_VALUE_END
76 };
77
78 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
79 int etna_mesa_debug = 0;
80
81 static void
82 etna_screen_destroy(struct pipe_screen *pscreen)
83 {
84 struct etna_screen *screen = etna_screen(pscreen);
85
86 _mesa_set_destroy(screen->used_resources, NULL);
87 mtx_destroy(&screen->lock);
88
89 if (screen->perfmon)
90 etna_perfmon_del(screen->perfmon);
91
92 if (screen->pipe)
93 etna_pipe_del(screen->pipe);
94
95 if (screen->gpu)
96 etna_gpu_del(screen->gpu);
97
98 if (screen->ro)
99 FREE(screen->ro);
100
101 if (screen->dev)
102 etna_device_del(screen->dev);
103
104 FREE(screen);
105 }
106
107 static const char *
108 etna_screen_get_name(struct pipe_screen *pscreen)
109 {
110 struct etna_screen *priv = etna_screen(pscreen);
111 static char buffer[128];
112
113 util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
114 priv->revision);
115
116 return buffer;
117 }
118
119 static const char *
120 etna_screen_get_vendor(struct pipe_screen *pscreen)
121 {
122 return "etnaviv";
123 }
124
125 static const char *
126 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
127 {
128 return "Vivante";
129 }
130
131 static int
132 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
133 {
134 struct etna_screen *screen = etna_screen(pscreen);
135
136 switch (param) {
137 /* Supported features (boolean caps). */
138 case PIPE_CAP_ANISOTROPIC_FILTER:
139 case PIPE_CAP_POINT_SPRITE:
140 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
141 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
142 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
143 case PIPE_CAP_SM3:
144 case PIPE_CAP_TEXTURE_BARRIER:
145 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
146 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
147 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
148 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
149 case PIPE_CAP_TGSI_TEXCOORD:
150 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
151 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
152 return 1;
153 case PIPE_CAP_NATIVE_FENCE_FD:
154 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
155
156 /* Memory */
157 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
158 return 256;
159 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
160 return 4; /* XXX could easily be supported */
161
162 case PIPE_CAP_NPOT_TEXTURES:
163 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
164 NON_POWER_OF_TWO); */
165
166 case PIPE_CAP_TEXTURE_SWIZZLE:
167 case PIPE_CAP_PRIMITIVE_RESTART:
168 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
169
170 /* Unsupported features. */
171 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
172 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
173 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
174 return 0;
175
176 /* Stream output. */
177 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
178 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
179 return 0;
180
181 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
182 return 128;
183 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
184 return 255;
185
186 /* Texturing. */
187 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
188 return screen->specs.max_texture_size;
189 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
190 {
191 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
192 assert(log2_max_tex_size > 0);
193 return log2_max_tex_size;
194 }
195 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
196 return 5;
197 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
198 case PIPE_CAP_MIN_TEXEL_OFFSET:
199 return -8;
200 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
201 case PIPE_CAP_MAX_TEXEL_OFFSET:
202 return 7;
203 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
204 return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
205
206 /* Timer queries. */
207 case PIPE_CAP_OCCLUSION_QUERY:
208 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
209 case PIPE_CAP_QUERY_TIMESTAMP:
210 return 1;
211
212 /* Preferences */
213 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
214 return 0;
215
216 case PIPE_CAP_MAX_VARYINGS:
217 return screen->specs.max_varyings;
218
219 case PIPE_CAP_PCI_GROUP:
220 case PIPE_CAP_PCI_BUS:
221 case PIPE_CAP_PCI_DEVICE:
222 case PIPE_CAP_PCI_FUNCTION:
223 return 0;
224 case PIPE_CAP_ACCELERATED:
225 return 1;
226 case PIPE_CAP_VIDEO_MEMORY:
227 return 0;
228 case PIPE_CAP_UMA:
229 return 1;
230 default:
231 return u_pipe_screen_get_param_defaults(pscreen, param);
232 }
233 }
234
235 static float
236 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
237 {
238 struct etna_screen *screen = etna_screen(pscreen);
239
240 switch (param) {
241 case PIPE_CAPF_MAX_LINE_WIDTH:
242 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
243 case PIPE_CAPF_MAX_POINT_WIDTH:
244 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
245 return 8192.0f;
246 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
247 return 16.0f;
248 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
249 return util_last_bit(screen->specs.max_texture_size);
250 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
251 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
252 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
253 return 0.0f;
254 }
255
256 debug_printf("unknown paramf %d", param);
257 return 0;
258 }
259
260 static int
261 etna_screen_get_shader_param(struct pipe_screen *pscreen,
262 enum pipe_shader_type shader,
263 enum pipe_shader_cap param)
264 {
265 struct etna_screen *screen = etna_screen(pscreen);
266
267 switch (shader) {
268 case PIPE_SHADER_FRAGMENT:
269 case PIPE_SHADER_VERTEX:
270 break;
271 case PIPE_SHADER_COMPUTE:
272 case PIPE_SHADER_GEOMETRY:
273 case PIPE_SHADER_TESS_CTRL:
274 case PIPE_SHADER_TESS_EVAL:
275 return 0;
276 default:
277 DBG("unknown shader type %d", shader);
278 return 0;
279 }
280
281 switch (param) {
282 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
283 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
284 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
285 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
286 return ETNA_MAX_TOKENS;
287 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
288 return ETNA_MAX_DEPTH; /* XXX */
289 case PIPE_SHADER_CAP_MAX_INPUTS:
290 /* Maximum number of inputs for the vertex shader is the number
291 * of vertex elements - each element defines one vertex shader
292 * input register. For the fragment shader, this is the number
293 * of varyings. */
294 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
295 : screen->specs.vertex_max_elements;
296 case PIPE_SHADER_CAP_MAX_OUTPUTS:
297 return 16; /* see VIVS_VS_OUTPUT */
298 case PIPE_SHADER_CAP_MAX_TEMPS:
299 return 64; /* Max native temporaries. */
300 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
301 return 1;
302 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
303 return 1;
304 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
305 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
306 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
307 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
308 return 1;
309 case PIPE_SHADER_CAP_SUBROUTINES:
310 return 0;
311 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
312 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
313 case PIPE_SHADER_CAP_INTEGERS:
314 case PIPE_SHADER_CAP_INT64_ATOMICS:
315 case PIPE_SHADER_CAP_FP16:
316 return 0;
317 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
318 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
319 return shader == PIPE_SHADER_FRAGMENT
320 ? screen->specs.fragment_sampler_count
321 : screen->specs.vertex_sampler_count;
322 case PIPE_SHADER_CAP_PREFERRED_IR:
323 return PIPE_SHADER_IR_TGSI;
324 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
325 return 4096;
326 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
327 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
328 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
329 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
330 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
331 return false;
332 case PIPE_SHADER_CAP_SUPPORTED_IRS:
333 return 0;
334 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
335 return 32;
336 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
337 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
338 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
339 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
340 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
341 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
342 case PIPE_SHADER_CAP_SCALAR_ISA:
343 return 0;
344 }
345
346 debug_printf("unknown shader param %d", param);
347 return 0;
348 }
349
350 static uint64_t
351 etna_screen_get_timestamp(struct pipe_screen *pscreen)
352 {
353 return os_time_get_nano();
354 }
355
356 static bool
357 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
358 enum pipe_format format)
359 {
360 bool supported = true;
361
362 if (fmt == TEXTURE_FORMAT_ETC1)
363 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
364
365 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
366 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
367
368 if (util_format_is_srgb(format))
369 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
370
371 if (fmt & EXT_FORMAT)
372 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
373
374 if (fmt & ASTC_FORMAT) {
375 supported = screen->specs.tex_astc;
376 }
377
378 if (!supported)
379 return false;
380
381 if (texture_format_needs_swiz(format))
382 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
383
384 return true;
385 }
386
387 static boolean
388 etna_screen_is_format_supported(struct pipe_screen *pscreen,
389 enum pipe_format format,
390 enum pipe_texture_target target,
391 unsigned sample_count,
392 unsigned storage_sample_count,
393 unsigned usage)
394 {
395 struct etna_screen *screen = etna_screen(pscreen);
396 unsigned allowed = 0;
397
398 if (target != PIPE_BUFFER &&
399 target != PIPE_TEXTURE_1D &&
400 target != PIPE_TEXTURE_2D &&
401 target != PIPE_TEXTURE_3D &&
402 target != PIPE_TEXTURE_CUBE &&
403 target != PIPE_TEXTURE_RECT)
404 return FALSE;
405
406 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
407 return false;
408
409 if (usage & PIPE_BIND_RENDER_TARGET) {
410 /* if render target, must be RS-supported format */
411 if (translate_rs_format(format) != ETNA_NO_MATCH) {
412 /* Validate MSAA; number of samples must be allowed, and render target
413 * must have MSAA'able format. */
414 if (sample_count > 1) {
415 if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
416 translate_ts_format(format) != ETNA_NO_MATCH) {
417 allowed |= PIPE_BIND_RENDER_TARGET;
418 }
419 } else {
420 allowed |= PIPE_BIND_RENDER_TARGET;
421 }
422 }
423 }
424
425 if (usage & PIPE_BIND_DEPTH_STENCIL) {
426 if (translate_depth_format(format) != ETNA_NO_MATCH)
427 allowed |= PIPE_BIND_DEPTH_STENCIL;
428 }
429
430 if (usage & PIPE_BIND_SAMPLER_VIEW) {
431 uint32_t fmt = translate_texture_format(format);
432
433 if (!gpu_supports_texure_format(screen, fmt, format))
434 fmt = ETNA_NO_MATCH;
435
436 if (sample_count < 2 && fmt != ETNA_NO_MATCH)
437 allowed |= PIPE_BIND_SAMPLER_VIEW;
438 }
439
440 if (usage & PIPE_BIND_VERTEX_BUFFER) {
441 if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
442 allowed |= PIPE_BIND_VERTEX_BUFFER;
443 }
444
445 if (usage & PIPE_BIND_INDEX_BUFFER) {
446 /* must be supported index format */
447 if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
448 (format == PIPE_FORMAT_I32_UINT &&
449 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
450 allowed |= PIPE_BIND_INDEX_BUFFER;
451 }
452 }
453
454 /* Always allowed */
455 allowed |=
456 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
457
458 if (usage != allowed) {
459 DBG("not supported: format=%s, target=%d, sample_count=%d, "
460 "usage=%x, allowed=%x",
461 util_format_name(format), target, sample_count, usage, allowed);
462 }
463
464 return usage == allowed;
465 }
466
467 const uint64_t supported_modifiers[] = {
468 DRM_FORMAT_MOD_LINEAR,
469 DRM_FORMAT_MOD_VIVANTE_TILED,
470 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
471 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
472 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
473 };
474
475 static void
476 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
477 enum pipe_format format, int max,
478 uint64_t *modifiers,
479 unsigned int *external_only, int *count)
480 {
481 struct etna_screen *screen = etna_screen(pscreen);
482 int i, num_modifiers = 0;
483
484 if (max > ARRAY_SIZE(supported_modifiers))
485 max = ARRAY_SIZE(supported_modifiers);
486
487 if (!max) {
488 modifiers = NULL;
489 max = ARRAY_SIZE(supported_modifiers);
490 }
491
492 for (i = 0; num_modifiers < max; i++) {
493 /* don't advertise split tiled formats on single pipe/buffer GPUs */
494 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
495 i >= 3)
496 break;
497
498 if (modifiers)
499 modifiers[num_modifiers] = supported_modifiers[i];
500 if (external_only)
501 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
502 num_modifiers++;
503 }
504
505 *count = num_modifiers;
506 }
507
508 static boolean
509 etna_get_specs(struct etna_screen *screen)
510 {
511 uint64_t val;
512 uint32_t instruction_count;
513
514 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
515 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
516 goto fail;
517 }
518 instruction_count = val;
519
520 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
521 &val)) {
522 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
523 goto fail;
524 }
525 screen->specs.vertex_output_buffer_size = val;
526
527 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
528 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
529 goto fail;
530 }
531 screen->specs.vertex_cache_size = val;
532
533 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
534 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
535 goto fail;
536 }
537 screen->specs.shader_core_count = val;
538
539 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
540 DBG("could not get ETNA_GPU_STREAM_COUNT");
541 goto fail;
542 }
543 screen->specs.stream_count = val;
544
545 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
546 DBG("could not get ETNA_GPU_REGISTER_MAX");
547 goto fail;
548 }
549 screen->specs.max_registers = val;
550
551 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
552 DBG("could not get ETNA_GPU_PIXEL_PIPES");
553 goto fail;
554 }
555 screen->specs.pixel_pipes = val;
556
557 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
558 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
559 goto fail;
560 }
561 if (val == 0) {
562 fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
563 val = 168;
564 }
565 screen->specs.num_constants = val;
566
567 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
568 * description of the differences. */
569 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
570 screen->specs.halti = 5; /* New GC7000/GC8x00 */
571 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
572 screen->specs.halti = 4; /* Old GC7000/GC7400 */
573 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
574 screen->specs.halti = 3; /* None? */
575 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
576 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
577 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
578 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
579 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
580 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
581 else
582 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
583 if (screen->specs.halti >= 0)
584 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
585 else
586 DBG("etnaviv: GPU arch: pre-HALTI");
587
588 screen->specs.can_supertile =
589 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
590 screen->specs.bits_per_tile =
591 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
592 screen->specs.ts_clear_value =
593 VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE) ? 0xffffffff :
594 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 :
595 0x11111111;
596
597
598 /* vertex and fragment samplers live in one address space */
599 screen->specs.vertex_sampler_offset = 8;
600 screen->specs.fragment_sampler_count = 8;
601 screen->specs.vertex_sampler_count = 4;
602 screen->specs.vs_need_z_div =
603 screen->model < 0x1000 && screen->model != 0x880;
604 screen->specs.has_sin_cos_sqrt =
605 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
606 screen->specs.has_sign_floor_ceil =
607 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
608 screen->specs.has_shader_range_registers =
609 screen->model >= 0x1000 || screen->model == 0x880;
610 screen->specs.npot_tex_any_wrap =
611 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
612 screen->specs.has_new_transcendentals =
613 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
614 screen->specs.has_halti2_instructions =
615 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
616
617 if (screen->specs.halti >= 5) {
618 /* GC7000 - this core must load shaders from memory. */
619 screen->specs.vs_offset = 0;
620 screen->specs.ps_offset = 0;
621 screen->specs.max_instructions = 0; /* Do not program shaders manually */
622 screen->specs.has_icache = true;
623 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
624 /* GC3000 - this core is capable of loading shaders from
625 * memory. It can also run shaders from registers, as a fallback, but
626 * "max_instructions" does not have the correct value. It has place for
627 * 2*256 instructions just like GC2000, but the offsets are slightly
628 * different.
629 */
630 screen->specs.vs_offset = 0xC000;
631 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
632 * this mirror for writing PS instructions, probably safest to do the
633 * same.
634 */
635 screen->specs.ps_offset = 0x8000 + 0x1000;
636 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
637 screen->specs.has_icache = true;
638 } else {
639 if (instruction_count > 256) { /* unified instruction memory? */
640 screen->specs.vs_offset = 0xC000;
641 screen->specs.ps_offset = 0xD000; /* like vivante driver */
642 screen->specs.max_instructions = 256;
643 } else {
644 screen->specs.vs_offset = 0x4000;
645 screen->specs.ps_offset = 0x6000;
646 screen->specs.max_instructions = instruction_count / 2;
647 }
648 screen->specs.has_icache = false;
649 }
650
651 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
652 screen->specs.max_varyings = 12;
653 screen->specs.vertex_max_elements = 16;
654 } else {
655 screen->specs.max_varyings = 8;
656 /* Etna_viv documentation seems confused over the correct value
657 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
658 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
659 screen->specs.vertex_max_elements = 10;
660 }
661
662 /* Etna_viv documentation does not indicate where varyings above 8 are
663 * stored. Moreover, if we are passed more than 8 varyings, we will
664 * walk off the end of some arrays. Limit the maximum number of varyings. */
665 if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
666 screen->specs.max_varyings = ETNA_NUM_VARYINGS;
667
668 /* from QueryShaderCaps in kernel driver */
669 if (screen->model < chipModel_GC4000) {
670 screen->specs.max_vs_uniforms = 168;
671 screen->specs.max_ps_uniforms = 64;
672 } else {
673 screen->specs.max_vs_uniforms = 256;
674 screen->specs.max_ps_uniforms = 256;
675 }
676
677 if (screen->specs.halti >= 5) {
678 screen->specs.has_unified_uniforms = true;
679 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
680 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
681 } else if (screen->specs.halti >= 1) {
682 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
683 */
684 screen->specs.has_unified_uniforms = true;
685 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
686 /* hardcode PS uniforms to start after end of VS uniforms -
687 * for more flexibility this offset could be variable based on the
688 * shader.
689 */
690 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
691 } else {
692 screen->specs.has_unified_uniforms = false;
693 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
694 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
695 }
696
697 screen->specs.max_texture_size =
698 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
699 screen->specs.max_rendertarget_size =
700 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
701
702 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
703 if (screen->specs.single_buffer)
704 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
705
706 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
707
708 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
709
710 return true;
711
712 fail:
713 return false;
714 }
715
716 struct etna_bo *
717 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
718 struct winsys_handle *whandle, unsigned *out_stride)
719 {
720 struct etna_screen *screen = etna_screen(pscreen);
721 struct etna_bo *bo;
722
723 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
724 bo = etna_bo_from_name(screen->dev, whandle->handle);
725 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
726 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
727 } else {
728 DBG("Attempt to import unsupported handle type %d", whandle->type);
729 return NULL;
730 }
731
732 if (!bo) {
733 DBG("ref name 0x%08x failed", whandle->handle);
734 return NULL;
735 }
736
737 *out_stride = whandle->stride;
738
739 return bo;
740 }
741
742 struct pipe_screen *
743 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
744 struct renderonly *ro)
745 {
746 struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
747 struct pipe_screen *pscreen;
748 drmVersionPtr version;
749 uint64_t val;
750
751 if (!screen)
752 return NULL;
753
754 pscreen = &screen->base;
755 screen->dev = dev;
756 screen->gpu = gpu;
757 screen->ro = renderonly_dup(ro);
758 screen->refcnt = 1;
759
760 if (!screen->ro) {
761 DBG("could not create renderonly object");
762 goto fail;
763 }
764
765 version = drmGetVersion(screen->ro->gpu_fd);
766 screen->drm_version = ETNA_DRM_VERSION(version->version_major,
767 version->version_minor);
768 drmFreeVersion(version);
769
770 etna_mesa_debug = debug_get_option_etna_mesa_debug();
771
772 /* Disable autodisable for correct rendering with TS */
773 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
774
775 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
776 if (!screen->pipe) {
777 DBG("could not create 3d pipe");
778 goto fail;
779 }
780
781 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
782 DBG("could not get ETNA_GPU_MODEL");
783 goto fail;
784 }
785 screen->model = val;
786
787 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
788 DBG("could not get ETNA_GPU_REVISION");
789 goto fail;
790 }
791 screen->revision = val;
792
793 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
794 DBG("could not get ETNA_GPU_FEATURES_0");
795 goto fail;
796 }
797 screen->features[0] = val;
798
799 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
800 DBG("could not get ETNA_GPU_FEATURES_1");
801 goto fail;
802 }
803 screen->features[1] = val;
804
805 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
806 DBG("could not get ETNA_GPU_FEATURES_2");
807 goto fail;
808 }
809 screen->features[2] = val;
810
811 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
812 DBG("could not get ETNA_GPU_FEATURES_3");
813 goto fail;
814 }
815 screen->features[3] = val;
816
817 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
818 DBG("could not get ETNA_GPU_FEATURES_4");
819 goto fail;
820 }
821 screen->features[4] = val;
822
823 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
824 DBG("could not get ETNA_GPU_FEATURES_5");
825 goto fail;
826 }
827 screen->features[5] = val;
828
829 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
830 DBG("could not get ETNA_GPU_FEATURES_6");
831 goto fail;
832 }
833 screen->features[6] = val;
834
835 if (!etna_get_specs(screen))
836 goto fail;
837
838 /* apply debug options that disable individual features */
839 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
840 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
841 if (DBG_ENABLED(ETNA_DBG_NO_TS))
842 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
843 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
844 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
845 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
846 screen->specs.can_supertile = 0;
847 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
848 screen->specs.single_buffer = 0;
849
850 pscreen->destroy = etna_screen_destroy;
851 pscreen->get_param = etna_screen_get_param;
852 pscreen->get_paramf = etna_screen_get_paramf;
853 pscreen->get_shader_param = etna_screen_get_shader_param;
854
855 pscreen->get_name = etna_screen_get_name;
856 pscreen->get_vendor = etna_screen_get_vendor;
857 pscreen->get_device_vendor = etna_screen_get_device_vendor;
858
859 pscreen->get_timestamp = etna_screen_get_timestamp;
860 pscreen->context_create = etna_context_create;
861 pscreen->is_format_supported = etna_screen_is_format_supported;
862 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
863
864 etna_fence_screen_init(pscreen);
865 etna_query_screen_init(pscreen);
866 etna_resource_screen_init(pscreen);
867
868 util_dynarray_init(&screen->supported_pm_queries, NULL);
869 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
870
871 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
872 etna_pm_query_setup(screen);
873
874 mtx_init(&screen->lock, mtx_recursive);
875 screen->used_resources = _mesa_set_create(NULL, _mesa_hash_pointer,
876 _mesa_key_pointer_equal);
877 if (!screen->used_resources)
878 goto fail2;
879
880 return pscreen;
881
882 fail2:
883 mtx_destroy(&screen->lock);
884 fail:
885 etna_screen_destroy(pscreen);
886 return NULL;
887 }