etnaviv: Make contexts track resources
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_screen.c
1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
26 */
27
28 #include "etnaviv_screen.h"
29
30 #include "hw/common.xml.h"
31
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
40
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
47
48 #include "state_tracker/drm_driver.h"
49
50 #include "drm-uapi/drm_fourcc.h"
51
52 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
53 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
54 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
55
56 static const struct debug_named_value debug_options[] = {
57 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"},
62 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
63 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"},
64 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
65 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
66 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"},
67 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
68 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"},
69 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"},
70 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
71 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
72 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
73 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
74 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
75 {"nir", ETNA_DBG_NIR, "use new NIR compiler"},
76 DEBUG_NAMED_VALUE_END
77 };
78
79 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
80 int etna_mesa_debug = 0;
81
82 static void
83 etna_screen_destroy(struct pipe_screen *pscreen)
84 {
85 struct etna_screen *screen = etna_screen(pscreen);
86
87 mtx_destroy(&screen->lock);
88
89 if (screen->perfmon)
90 etna_perfmon_del(screen->perfmon);
91
92 if (screen->pipe)
93 etna_pipe_del(screen->pipe);
94
95 if (screen->gpu)
96 etna_gpu_del(screen->gpu);
97
98 if (screen->ro)
99 FREE(screen->ro);
100
101 if (screen->dev)
102 etna_device_del(screen->dev);
103
104 FREE(screen);
105 }
106
107 static const char *
108 etna_screen_get_name(struct pipe_screen *pscreen)
109 {
110 struct etna_screen *priv = etna_screen(pscreen);
111 static char buffer[128];
112
113 snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
114 priv->revision);
115
116 return buffer;
117 }
118
119 static const char *
120 etna_screen_get_vendor(struct pipe_screen *pscreen)
121 {
122 return "etnaviv";
123 }
124
125 static const char *
126 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
127 {
128 return "Vivante";
129 }
130
131 static int
132 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
133 {
134 struct etna_screen *screen = etna_screen(pscreen);
135
136 switch (param) {
137 /* Supported features (boolean caps). */
138 case PIPE_CAP_ANISOTROPIC_FILTER:
139 case PIPE_CAP_POINT_SPRITE:
140 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
141 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
142 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
143 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
144 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
145 case PIPE_CAP_VERTEX_SHADER_SATURATE:
146 case PIPE_CAP_TEXTURE_BARRIER:
147 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
148 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
149 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
150 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
151 case PIPE_CAP_TGSI_TEXCOORD:
152 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
153 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
154 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
155 return 1;
156 case PIPE_CAP_NATIVE_FENCE_FD:
157 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
158 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
159 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: /* note: not integer */
160 return DBG_ENABLED(ETNA_DBG_NIR);
161 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
162 return 0;
163
164 /* Memory */
165 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
166 return 256;
167 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
168 return 4; /* XXX could easily be supported */
169
170 case PIPE_CAP_NPOT_TEXTURES:
171 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
172 NON_POWER_OF_TWO); */
173
174 case PIPE_CAP_TEXTURE_SWIZZLE:
175 case PIPE_CAP_PRIMITIVE_RESTART:
176 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
177
178 /* Unsupported features. */
179 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
180 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
181 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
182 return 0;
183
184 /* Stream output. */
185 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
186 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
187 return 0;
188
189 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
190 return 128;
191 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
192 return 255;
193
194 /* Texturing. */
195 case PIPE_CAP_TEXTURE_SHADOW_MAP:
196 return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2;
197 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
198 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */
199 return screen->specs.max_texture_size;
200 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
201 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
202 {
203 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
204 assert(log2_max_tex_size > 0);
205 return log2_max_tex_size;
206 }
207
208 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
209 case PIPE_CAP_MIN_TEXEL_OFFSET:
210 return -8;
211 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
212 case PIPE_CAP_MAX_TEXEL_OFFSET:
213 return 7;
214 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
215 return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
216
217 /* Timer queries. */
218 case PIPE_CAP_OCCLUSION_QUERY:
219 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
220 case PIPE_CAP_QUERY_TIMESTAMP:
221 return 1;
222
223 /* Preferences */
224 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
225 return 0;
226
227 case PIPE_CAP_MAX_VARYINGS:
228 return screen->specs.max_varyings;
229
230 case PIPE_CAP_PCI_GROUP:
231 case PIPE_CAP_PCI_BUS:
232 case PIPE_CAP_PCI_DEVICE:
233 case PIPE_CAP_PCI_FUNCTION:
234 return 0;
235 case PIPE_CAP_ACCELERATED:
236 return 1;
237 case PIPE_CAP_VIDEO_MEMORY:
238 return 0;
239 case PIPE_CAP_UMA:
240 return 1;
241 default:
242 return u_pipe_screen_get_param_defaults(pscreen, param);
243 }
244 }
245
246 static float
247 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
248 {
249 struct etna_screen *screen = etna_screen(pscreen);
250
251 switch (param) {
252 case PIPE_CAPF_MAX_LINE_WIDTH:
253 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
254 case PIPE_CAPF_MAX_POINT_WIDTH:
255 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
256 return 8192.0f;
257 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
258 return 16.0f;
259 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
260 return util_last_bit(screen->specs.max_texture_size);
261 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
262 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
263 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
264 return 0.0f;
265 }
266
267 debug_printf("unknown paramf %d", param);
268 return 0;
269 }
270
271 static int
272 etna_screen_get_shader_param(struct pipe_screen *pscreen,
273 enum pipe_shader_type shader,
274 enum pipe_shader_cap param)
275 {
276 struct etna_screen *screen = etna_screen(pscreen);
277
278 switch (shader) {
279 case PIPE_SHADER_FRAGMENT:
280 case PIPE_SHADER_VERTEX:
281 break;
282 case PIPE_SHADER_COMPUTE:
283 case PIPE_SHADER_GEOMETRY:
284 case PIPE_SHADER_TESS_CTRL:
285 case PIPE_SHADER_TESS_EVAL:
286 return 0;
287 default:
288 DBG("unknown shader type %d", shader);
289 return 0;
290 }
291
292 switch (param) {
293 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
294 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
295 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
296 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
297 return ETNA_MAX_TOKENS;
298 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
299 return ETNA_MAX_DEPTH; /* XXX */
300 case PIPE_SHADER_CAP_MAX_INPUTS:
301 /* Maximum number of inputs for the vertex shader is the number
302 * of vertex elements - each element defines one vertex shader
303 * input register. For the fragment shader, this is the number
304 * of varyings. */
305 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
306 : screen->specs.vertex_max_elements;
307 case PIPE_SHADER_CAP_MAX_OUTPUTS:
308 return 16; /* see VIVS_VS_OUTPUT */
309 case PIPE_SHADER_CAP_MAX_TEMPS:
310 return 64; /* Max native temporaries. */
311 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
312 return 1;
313 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
314 return 1;
315 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
316 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
317 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
318 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
319 return 1;
320 case PIPE_SHADER_CAP_SUBROUTINES:
321 return 0;
322 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
323 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
324 case PIPE_SHADER_CAP_INT64_ATOMICS:
325 case PIPE_SHADER_CAP_FP16:
326 return 0;
327 case PIPE_SHADER_CAP_INTEGERS:
328 return DBG_ENABLED(ETNA_DBG_NIR) && screen->specs.halti >= 2;
329 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
330 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
331 return shader == PIPE_SHADER_FRAGMENT
332 ? screen->specs.fragment_sampler_count
333 : screen->specs.vertex_sampler_count;
334 case PIPE_SHADER_CAP_PREFERRED_IR:
335 return DBG_ENABLED(ETNA_DBG_NIR) ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
336 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
337 return shader == PIPE_SHADER_FRAGMENT
338 ? screen->specs.max_ps_uniforms * sizeof(float[4])
339 : screen->specs.max_vs_uniforms * sizeof(float[4]);
340 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
341 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
342 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
343 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
344 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
345 return false;
346 case PIPE_SHADER_CAP_SUPPORTED_IRS:
347 return 0;
348 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
349 return 32;
350 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
351 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
352 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
353 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
354 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
355 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
356 return 0;
357 }
358
359 debug_printf("unknown shader param %d", param);
360 return 0;
361 }
362
363 static uint64_t
364 etna_screen_get_timestamp(struct pipe_screen *pscreen)
365 {
366 return os_time_get_nano();
367 }
368
369 static bool
370 gpu_supports_texture_target(struct etna_screen *screen,
371 enum pipe_texture_target target)
372 {
373 if (target == PIPE_TEXTURE_CUBE_ARRAY)
374 return false;
375
376 /* pre-halti has no array/3D */
377 if (screen->specs.halti < 0 &&
378 (target == PIPE_TEXTURE_1D_ARRAY ||
379 target == PIPE_TEXTURE_2D_ARRAY ||
380 target == PIPE_TEXTURE_3D))
381 return false;
382
383 return true;
384 }
385
386 static bool
387 gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
388 enum pipe_format format)
389 {
390 bool supported = true;
391
392 if (fmt == TEXTURE_FORMAT_ETC1)
393 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
394
395 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
396 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
397
398 if (util_format_is_srgb(format))
399 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
400
401 if (fmt & EXT_FORMAT)
402 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
403
404 if (fmt & ASTC_FORMAT) {
405 supported = screen->specs.tex_astc;
406 }
407
408 if (!supported)
409 return false;
410
411 if (texture_format_needs_swiz(format))
412 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
413
414 return true;
415 }
416
417 static bool
418 etna_screen_is_format_supported(struct pipe_screen *pscreen,
419 enum pipe_format format,
420 enum pipe_texture_target target,
421 unsigned sample_count,
422 unsigned storage_sample_count,
423 unsigned usage)
424 {
425 struct etna_screen *screen = etna_screen(pscreen);
426 unsigned allowed = 0;
427
428 if (!gpu_supports_texture_target(screen, target))
429 return false;
430
431 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
432 return false;
433
434 if (usage & PIPE_BIND_RENDER_TARGET) {
435 /* if render target, must be RS-supported format */
436 if (translate_rs_format(format) != ETNA_NO_MATCH) {
437 /* Validate MSAA; number of samples must be allowed, and render target
438 * must have MSAA'able format. */
439 if (sample_count > 1) {
440 if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
441 translate_ts_format(format) != ETNA_NO_MATCH) {
442 allowed |= PIPE_BIND_RENDER_TARGET;
443 }
444 } else {
445 allowed |= PIPE_BIND_RENDER_TARGET;
446 }
447 }
448 }
449
450 if (usage & PIPE_BIND_DEPTH_STENCIL) {
451 if (translate_depth_format(format) != ETNA_NO_MATCH)
452 allowed |= PIPE_BIND_DEPTH_STENCIL;
453 }
454
455 if (usage & PIPE_BIND_SAMPLER_VIEW) {
456 uint32_t fmt = translate_texture_format(format);
457
458 if (!gpu_supports_texture_format(screen, fmt, format))
459 fmt = ETNA_NO_MATCH;
460
461 if (sample_count < 2 && fmt != ETNA_NO_MATCH)
462 allowed |= PIPE_BIND_SAMPLER_VIEW;
463 }
464
465 if (usage & PIPE_BIND_VERTEX_BUFFER) {
466 if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
467 allowed |= PIPE_BIND_VERTEX_BUFFER;
468 }
469
470 if (usage & PIPE_BIND_INDEX_BUFFER) {
471 /* must be supported index format */
472 if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
473 (format == PIPE_FORMAT_I32_UINT &&
474 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
475 allowed |= PIPE_BIND_INDEX_BUFFER;
476 }
477 }
478
479 /* Always allowed */
480 allowed |=
481 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
482
483 if (usage != allowed) {
484 DBG("not supported: format=%s, target=%d, sample_count=%d, "
485 "usage=%x, allowed=%x",
486 util_format_name(format), target, sample_count, usage, allowed);
487 }
488
489 return usage == allowed;
490 }
491
492 const uint64_t supported_modifiers[] = {
493 DRM_FORMAT_MOD_LINEAR,
494 DRM_FORMAT_MOD_VIVANTE_TILED,
495 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
496 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
497 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
498 };
499
500 static void
501 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
502 enum pipe_format format, int max,
503 uint64_t *modifiers,
504 unsigned int *external_only, int *count)
505 {
506 struct etna_screen *screen = etna_screen(pscreen);
507 int i, num_modifiers = 0;
508
509 if (max > ARRAY_SIZE(supported_modifiers))
510 max = ARRAY_SIZE(supported_modifiers);
511
512 if (!max) {
513 modifiers = NULL;
514 max = ARRAY_SIZE(supported_modifiers);
515 }
516
517 for (i = 0; num_modifiers < max; i++) {
518 /* don't advertise split tiled formats on single pipe/buffer GPUs */
519 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
520 i >= 3)
521 break;
522
523 if (modifiers)
524 modifiers[num_modifiers] = supported_modifiers[i];
525 if (external_only)
526 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
527 num_modifiers++;
528 }
529
530 *count = num_modifiers;
531 }
532
533 static void
534 etna_determine_uniform_limits(struct etna_screen *screen)
535 {
536 /* values for the non unified case are taken from
537 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
538 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
539 */
540 if (screen->model == chipModel_GC2000 &&
541 (screen->revision == 0x5118 || screen->revision == 0x5140)) {
542 screen->specs.max_vs_uniforms = 256;
543 screen->specs.max_ps_uniforms = 64;
544 } else if (screen->specs.num_constants == 320) {
545 screen->specs.max_vs_uniforms = 256;
546 screen->specs.max_ps_uniforms = 64;
547 } else if (screen->specs.num_constants > 256 &&
548 screen->model == chipModel_GC1000) {
549 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
550 screen->specs.max_vs_uniforms = 256;
551 screen->specs.max_ps_uniforms = 64;
552 } else if (screen->specs.num_constants > 256) {
553 screen->specs.max_vs_uniforms = 256;
554 screen->specs.max_ps_uniforms = 256;
555 } else if (screen->specs.num_constants == 256) {
556 screen->specs.max_vs_uniforms = 256;
557 screen->specs.max_ps_uniforms = 256;
558 } else {
559 screen->specs.max_vs_uniforms = 168;
560 screen->specs.max_ps_uniforms = 64;
561 }
562 }
563
564 static bool
565 etna_get_specs(struct etna_screen *screen)
566 {
567 uint64_t val;
568 uint32_t instruction_count;
569
570 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
571 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
572 goto fail;
573 }
574 instruction_count = val;
575
576 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
577 &val)) {
578 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
579 goto fail;
580 }
581 screen->specs.vertex_output_buffer_size = val;
582
583 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
584 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
585 goto fail;
586 }
587 screen->specs.vertex_cache_size = val;
588
589 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
590 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
591 goto fail;
592 }
593 screen->specs.shader_core_count = val;
594
595 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
596 DBG("could not get ETNA_GPU_STREAM_COUNT");
597 goto fail;
598 }
599 screen->specs.stream_count = val;
600
601 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
602 DBG("could not get ETNA_GPU_REGISTER_MAX");
603 goto fail;
604 }
605 screen->specs.max_registers = val;
606
607 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
608 DBG("could not get ETNA_GPU_PIXEL_PIPES");
609 goto fail;
610 }
611 screen->specs.pixel_pipes = val;
612
613 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
614 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
615 goto fail;
616 }
617 if (val == 0) {
618 fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
619 val = 168;
620 }
621 screen->specs.num_constants = val;
622
623 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
624 * description of the differences. */
625 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
626 screen->specs.halti = 5; /* New GC7000/GC8x00 */
627 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
628 screen->specs.halti = 4; /* Old GC7000/GC7400 */
629 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
630 screen->specs.halti = 3; /* None? */
631 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
632 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
633 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
634 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
635 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
636 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
637 else
638 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
639 if (screen->specs.halti >= 0)
640 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
641 else
642 DBG("etnaviv: GPU arch: pre-HALTI");
643
644 screen->specs.can_supertile =
645 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
646 screen->specs.bits_per_tile =
647 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
648 screen->specs.ts_clear_value =
649 VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE) ? 0xffffffff :
650 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 :
651 0x11111111;
652
653
654 /* vertex and fragment samplers live in one address space */
655 screen->specs.vertex_sampler_offset = 8;
656 screen->specs.fragment_sampler_count = 8;
657 screen->specs.vertex_sampler_count = 4;
658 screen->specs.vs_need_z_div =
659 screen->model < 0x1000 && screen->model != 0x880;
660 screen->specs.has_sin_cos_sqrt =
661 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
662 screen->specs.has_sign_floor_ceil =
663 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
664 screen->specs.has_shader_range_registers =
665 screen->model >= 0x1000 || screen->model == 0x880;
666 screen->specs.npot_tex_any_wrap =
667 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
668 screen->specs.has_new_transcendentals =
669 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
670 screen->specs.has_halti2_instructions =
671 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
672 screen->specs.v4_compression =
673 VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
674
675 if (screen->specs.halti >= 5) {
676 /* GC7000 - this core must load shaders from memory. */
677 screen->specs.vs_offset = 0;
678 screen->specs.ps_offset = 0;
679 screen->specs.max_instructions = 0; /* Do not program shaders manually */
680 screen->specs.has_icache = true;
681 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
682 /* GC3000 - this core is capable of loading shaders from
683 * memory. It can also run shaders from registers, as a fallback, but
684 * "max_instructions" does not have the correct value. It has place for
685 * 2*256 instructions just like GC2000, but the offsets are slightly
686 * different.
687 */
688 screen->specs.vs_offset = 0xC000;
689 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
690 * this mirror for writing PS instructions, probably safest to do the
691 * same.
692 */
693 screen->specs.ps_offset = 0x8000 + 0x1000;
694 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
695 screen->specs.has_icache = true;
696 } else {
697 if (instruction_count > 256) { /* unified instruction memory? */
698 screen->specs.vs_offset = 0xC000;
699 screen->specs.ps_offset = 0xD000; /* like vivante driver */
700 screen->specs.max_instructions = 256;
701 } else {
702 screen->specs.vs_offset = 0x4000;
703 screen->specs.ps_offset = 0x6000;
704 screen->specs.max_instructions = instruction_count / 2;
705 }
706 screen->specs.has_icache = false;
707 }
708
709 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
710 screen->specs.max_varyings = 12;
711 screen->specs.vertex_max_elements = 16;
712 } else {
713 screen->specs.max_varyings = 8;
714 /* Etna_viv documentation seems confused over the correct value
715 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
716 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
717 screen->specs.vertex_max_elements = 10;
718 }
719
720 /* Etna_viv documentation does not indicate where varyings above 8 are
721 * stored. Moreover, if we are passed more than 8 varyings, we will
722 * walk off the end of some arrays. Limit the maximum number of varyings. */
723 if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
724 screen->specs.max_varyings = ETNA_NUM_VARYINGS;
725
726 etna_determine_uniform_limits(screen);
727
728 if (screen->specs.halti >= 5) {
729 screen->specs.has_unified_uniforms = true;
730 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
731 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
732 } else if (screen->specs.halti >= 1) {
733 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
734 */
735 screen->specs.has_unified_uniforms = true;
736 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
737 /* hardcode PS uniforms to start after end of VS uniforms -
738 * for more flexibility this offset could be variable based on the
739 * shader.
740 */
741 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
742 } else {
743 screen->specs.has_unified_uniforms = false;
744 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
745 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
746 }
747
748 screen->specs.max_texture_size =
749 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
750 screen->specs.max_rendertarget_size =
751 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
752
753 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
754 if (screen->specs.single_buffer)
755 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
756
757 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
758
759 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
760
761 return true;
762
763 fail:
764 return false;
765 }
766
767 struct etna_bo *
768 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
769 struct winsys_handle *whandle, unsigned *out_stride)
770 {
771 struct etna_screen *screen = etna_screen(pscreen);
772 struct etna_bo *bo;
773
774 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
775 bo = etna_bo_from_name(screen->dev, whandle->handle);
776 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
777 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
778 } else {
779 DBG("Attempt to import unsupported handle type %d", whandle->type);
780 return NULL;
781 }
782
783 if (!bo) {
784 DBG("ref name 0x%08x failed", whandle->handle);
785 return NULL;
786 }
787
788 *out_stride = whandle->stride;
789
790 return bo;
791 }
792
793 static const void *
794 etna_get_compiler_options(struct pipe_screen *pscreen,
795 enum pipe_shader_ir ir, unsigned shader)
796 {
797 return &etna_screen(pscreen)->options;
798 }
799
800 struct pipe_screen *
801 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
802 struct renderonly *ro)
803 {
804 struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
805 struct pipe_screen *pscreen;
806 drmVersionPtr version;
807 uint64_t val;
808
809 if (!screen)
810 return NULL;
811
812 pscreen = &screen->base;
813 screen->dev = dev;
814 screen->gpu = gpu;
815 screen->ro = renderonly_dup(ro);
816 screen->refcnt = 1;
817
818 if (!screen->ro) {
819 DBG("could not create renderonly object");
820 goto fail;
821 }
822
823 version = drmGetVersion(screen->ro->gpu_fd);
824 screen->drm_version = ETNA_DRM_VERSION(version->version_major,
825 version->version_minor);
826 drmFreeVersion(version);
827
828 etna_mesa_debug = debug_get_option_etna_mesa_debug();
829
830 /* Disable autodisable for correct rendering with TS */
831 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
832
833 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
834 if (!screen->pipe) {
835 DBG("could not create 3d pipe");
836 goto fail;
837 }
838
839 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
840 DBG("could not get ETNA_GPU_MODEL");
841 goto fail;
842 }
843 screen->model = val;
844
845 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
846 DBG("could not get ETNA_GPU_REVISION");
847 goto fail;
848 }
849 screen->revision = val;
850
851 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
852 DBG("could not get ETNA_GPU_FEATURES_0");
853 goto fail;
854 }
855 screen->features[0] = val;
856
857 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
858 DBG("could not get ETNA_GPU_FEATURES_1");
859 goto fail;
860 }
861 screen->features[1] = val;
862
863 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
864 DBG("could not get ETNA_GPU_FEATURES_2");
865 goto fail;
866 }
867 screen->features[2] = val;
868
869 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
870 DBG("could not get ETNA_GPU_FEATURES_3");
871 goto fail;
872 }
873 screen->features[3] = val;
874
875 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
876 DBG("could not get ETNA_GPU_FEATURES_4");
877 goto fail;
878 }
879 screen->features[4] = val;
880
881 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
882 DBG("could not get ETNA_GPU_FEATURES_5");
883 goto fail;
884 }
885 screen->features[5] = val;
886
887 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
888 DBG("could not get ETNA_GPU_FEATURES_6");
889 goto fail;
890 }
891 screen->features[6] = val;
892
893 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) {
894 DBG("could not get ETNA_GPU_FEATURES_7");
895 goto fail;
896 }
897 screen->features[7] = val;
898
899 if (!etna_get_specs(screen))
900 goto fail;
901
902 screen->options = (nir_shader_compiler_options) {
903 .lower_fpow = true,
904 .lower_sub = true,
905 .lower_ftrunc = true,
906 .fuse_ffma = true,
907 .lower_bitops = true,
908 .lower_all_io_to_temps = true,
909 .vertex_id_zero_based = true,
910 .lower_flrp32 = true,
911 .lower_fmod = true,
912 .lower_vector_cmp = true,
913 .lower_fdph = true,
914 .lower_fdiv = true, /* !screen->specs.has_new_transcendentals */
915 .lower_fsign = !screen->specs.has_sign_floor_ceil,
916 .lower_ffloor = !screen->specs.has_sign_floor_ceil,
917 .lower_fceil = !screen->specs.has_sign_floor_ceil,
918 .lower_fsqrt = !screen->specs.has_sin_cos_sqrt,
919 .lower_sincos = !screen->specs.has_sin_cos_sqrt,
920 };
921
922 /* apply debug options that disable individual features */
923 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
924 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
925 if (DBG_ENABLED(ETNA_DBG_NO_TS))
926 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
927 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
928 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
929 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
930 screen->specs.can_supertile = 0;
931 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
932 screen->specs.single_buffer = 0;
933
934 pscreen->destroy = etna_screen_destroy;
935 pscreen->get_param = etna_screen_get_param;
936 pscreen->get_paramf = etna_screen_get_paramf;
937 pscreen->get_shader_param = etna_screen_get_shader_param;
938 pscreen->get_compiler_options = etna_get_compiler_options;
939
940 pscreen->get_name = etna_screen_get_name;
941 pscreen->get_vendor = etna_screen_get_vendor;
942 pscreen->get_device_vendor = etna_screen_get_device_vendor;
943
944 pscreen->get_timestamp = etna_screen_get_timestamp;
945 pscreen->context_create = etna_context_create;
946 pscreen->is_format_supported = etna_screen_is_format_supported;
947 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
948
949 etna_fence_screen_init(pscreen);
950 etna_query_screen_init(pscreen);
951 etna_resource_screen_init(pscreen);
952
953 util_dynarray_init(&screen->supported_pm_queries, NULL);
954 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
955
956 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
957 etna_pm_query_setup(screen);
958
959 mtx_init(&screen->lock, mtx_recursive);
960
961 return pscreen;
962
963 fail:
964 etna_screen_destroy(pscreen);
965 return NULL;
966 }