src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #include <drm_fourcc.h>
  49
  50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  51 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  52
  53 static const struct debug_named_value debug_options[] = {
  54    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  55    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  56    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  57    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  58    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  59    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  60    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  61    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  62    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  63    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  64    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  65    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  66    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  67    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  68    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  69    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  70    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  71    DEBUG_NAMED_VALUE_END
  72 };
  73
  74 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  75 int etna_mesa_debug = 0;
  76
  77 static void
  78 etna_screen_destroy(struct pipe_screen *pscreen)
  79 {
  80    struct etna_screen *screen = etna_screen(pscreen);
  81
  82    if (screen->pipe)
  83       etna_pipe_del(screen->pipe);
  84
  85    if (screen->gpu)
  86       etna_gpu_del(screen->gpu);
  87
  88    if (screen->ro)
  89       FREE(screen->ro);
  90
  91    if (screen->dev)
  92       etna_device_del(screen->dev);
  93
  94    FREE(screen);
  95 }
  96
  97 static const char *
  98 etna_screen_get_name(struct pipe_screen *pscreen)
  99 {
 100    struct etna_screen *priv = etna_screen(pscreen);
 101    static char buffer[128];
 102
 103    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 104                  priv->revision);
 105
 106    return buffer;
 107 }
 108
 109 static const char *
 110 etna_screen_get_vendor(struct pipe_screen *pscreen)
 111 {
 112    return "etnaviv";
 113 }
 114
 115 static const char *
 116 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 117 {
 118    return "Vivante";
 119 }
 120
 121 static int
 122 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 123 {
 124    struct etna_screen *screen = etna_screen(pscreen);
 125
 126    switch (param) {
 127    /* Supported features (boolean caps). */
 128    case PIPE_CAP_TWO_SIDED_STENCIL:
 129    case PIPE_CAP_ANISOTROPIC_FILTER:
 130    case PIPE_CAP_POINT_SPRITE:
 131    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 132    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 133    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 134    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 135    case PIPE_CAP_SM3:
 136    case PIPE_CAP_TEXTURE_BARRIER:
 137    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 138    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 140    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 141    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 142    case PIPE_CAP_TGSI_TEXCOORD:
 143    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 144       return 1;
 145    case PIPE_CAP_NATIVE_FENCE_FD:
 146       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 147
 148    /* Memory */
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 152       return 4; /* XXX could easily be supported */
 153    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 154       return 120;
 155
 156    case PIPE_CAP_NPOT_TEXTURES:
 157       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 158                       NON_POWER_OF_TWO); */
 159
 160    case PIPE_CAP_TEXTURE_SWIZZLE:
 161    case PIPE_CAP_PRIMITIVE_RESTART:
 162       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 163
 164    case PIPE_CAP_ENDIANNESS:
 165       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 166                                     ENDIANNESS_CONFIG) */
 167
 168    /* Unsupported features. */
 169    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 170    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 172    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 173    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 174    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 175    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 176    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 177    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 178    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 179    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 180    case PIPE_CAP_INDEP_BLEND_ENABLE:
 181    case PIPE_CAP_INDEP_BLEND_FUNC:
 182    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 183    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 184    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 185    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 187    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 188    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 189    case PIPE_CAP_USER_VERTEX_BUFFERS:
 190    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 191    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 192    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 193    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 194    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 195    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 196    case PIPE_CAP_TEXTURE_GATHER_SM5:
 197    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 198    case PIPE_CAP_FAKE_SW_MSAA:
 199    case PIPE_CAP_TEXTURE_QUERY_LOD:
 200    case PIPE_CAP_SAMPLE_SHADING:
 201    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 202    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 203    case PIPE_CAP_DRAW_INDIRECT:
 204    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 205    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 206    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 207    case PIPE_CAP_CLIP_HALFZ:
 208    case PIPE_CAP_VERTEXID_NOBASE:
 209    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 211    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 212    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 213    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 214    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 215    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 217    case PIPE_CAP_TGSI_TXQS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 221    case PIPE_CAP_CLEAR_TEXTURE:
 222    case PIPE_CAP_DRAW_PARAMETERS:
 223    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 225    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 226    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 227    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 228    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 229    case PIPE_CAP_INVALIDATE_BUFFER:
 230    case PIPE_CAP_GENERATE_MIPMAP:
 231    case PIPE_CAP_STRING_MARKER:
 232    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 233    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 234    case PIPE_CAP_QUERY_MEMORY_INFO:
 235    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 236    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 237    case PIPE_CAP_CULL_DISTANCE:
 238    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 239    case PIPE_CAP_TGSI_VOTE:
 240    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 241    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 242    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 243    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 244    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 246    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 247    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 248    case PIPE_CAP_TGSI_FS_FBFETCH:
 249    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 250    case PIPE_CAP_DOUBLES:
 251    case PIPE_CAP_INT64:
 252    case PIPE_CAP_INT64_DIVMOD:
 253    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 254    case PIPE_CAP_TGSI_CLOCK:
 255    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 256    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 257    case PIPE_CAP_TGSI_BALLOT:
 258    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 259    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 260    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 261    case PIPE_CAP_POST_DEPTH_COVERAGE:
 262    case PIPE_CAP_BINDLESS_TEXTURE:
 263    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 264    case PIPE_CAP_QUERY_SO_OVERFLOW:
 265    case PIPE_CAP_MEMOBJ:
 266    case PIPE_CAP_LOAD_CONSTBUF:
 267    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 268    case PIPE_CAP_TILE_RASTER_ORDER:
 269    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 270    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 271    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 272       return 0;
 273
 274    /* Stream output. */
 275    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 276    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 277    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 278    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 279       return 0;
 280
 281    /* Geometry shader output, unsupported. */
 282    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 283    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 284    case PIPE_CAP_MAX_VERTEX_STREAMS:
 285       return 0;
 286
 287    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 288       return 128;
 289
 290    /* Texturing. */
 291    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 292    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 293    {
 294       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 295       assert(log2_max_tex_size > 0);
 296       return log2_max_tex_size;
 297    }
 298    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 299       return 5;
 300    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 301       return 0;
 302    case PIPE_CAP_CUBE_MAP_ARRAY:
 303       return 0;
 304    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 305    case PIPE_CAP_MIN_TEXEL_OFFSET:
 306       return -8;
 307    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 308    case PIPE_CAP_MAX_TEXEL_OFFSET:
 309       return 7;
 310    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 311       return 0;
 312    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 313       return 65536;
 314
 315    /* Render targets. */
 316    case PIPE_CAP_MAX_RENDER_TARGETS:
 317       return 1;
 318
 319    /* Viewports and scissors. */
 320    case PIPE_CAP_MAX_VIEWPORTS:
 321       return 1;
 322
 323    /* Timer queries. */
 324    case PIPE_CAP_QUERY_TIME_ELAPSED:
 325       return 0;
 326    case PIPE_CAP_OCCLUSION_QUERY:
 327       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 328    case PIPE_CAP_QUERY_TIMESTAMP:
 329       return 1;
 330    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 331       return 0;
 332
 333    /* Preferences */
 334    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 335       return 0;
 336
 337    case PIPE_CAP_PCI_GROUP:
 338    case PIPE_CAP_PCI_BUS:
 339    case PIPE_CAP_PCI_DEVICE:
 340    case PIPE_CAP_PCI_FUNCTION:
 341       return 0;
 342    case PIPE_CAP_VENDOR_ID:
 343    case PIPE_CAP_DEVICE_ID:
 344       return 0xFFFFFFFF;
 345    case PIPE_CAP_ACCELERATED:
 346       return 1;
 347    case PIPE_CAP_VIDEO_MEMORY:
 348       return 0;
 349    case PIPE_CAP_UMA:
 350       return 1;
 351    }
 352
 353    debug_printf("unknown param %d", param);
 354    return 0;
 355 }
 356
 357 static float
 358 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 359 {
 360    struct etna_screen *screen = etna_screen(pscreen);
 361
 362    switch (param) {
 363    case PIPE_CAPF_MAX_LINE_WIDTH:
 364    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 365    case PIPE_CAPF_MAX_POINT_WIDTH:
 366    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 367       return 8192.0f;
 368    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 369       return 16.0f;
 370    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 371       return util_last_bit(screen->specs.max_texture_size);
 372    case PIPE_CAPF_GUARD_BAND_LEFT:
 373    case PIPE_CAPF_GUARD_BAND_TOP:
 374    case PIPE_CAPF_GUARD_BAND_RIGHT:
 375    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 376       return 0.0f;
 377    }
 378
 379    debug_printf("unknown paramf %d", param);
 380    return 0;
 381 }
 382
 383 static int
 384 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 385                              enum pipe_shader_type shader,
 386                              enum pipe_shader_cap param)
 387 {
 388    struct etna_screen *screen = etna_screen(pscreen);
 389
 390    switch (shader) {
 391    case PIPE_SHADER_FRAGMENT:
 392    case PIPE_SHADER_VERTEX:
 393       break;
 394    case PIPE_SHADER_COMPUTE:
 395    case PIPE_SHADER_GEOMETRY:
 396    case PIPE_SHADER_TESS_CTRL:
 397    case PIPE_SHADER_TESS_EVAL:
 398       return 0;
 399    default:
 400       DBG("unknown shader type %d", shader);
 401       return 0;
 402    }
 403
 404    switch (param) {
 405    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 406    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 407    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 408    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 409       return ETNA_MAX_TOKENS;
 410    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 411       return ETNA_MAX_DEPTH; /* XXX */
 412    case PIPE_SHADER_CAP_MAX_INPUTS:
 413       /* Maximum number of inputs for the vertex shader is the number
 414        * of vertex elements - each element defines one vertex shader
 415        * input register.  For the fragment shader, this is the number
 416        * of varyings. */
 417       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 418                                             : screen->specs.vertex_max_elements;
 419    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 420       return 16; /* see VIVS_VS_OUTPUT */
 421    case PIPE_SHADER_CAP_MAX_TEMPS:
 422       return 64; /* Max native temporaries. */
 423    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 424       return 1;
 425    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 426       return 1;
 427    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 428    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 429    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 430    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 431       return 1;
 432    case PIPE_SHADER_CAP_SUBROUTINES:
 433       return 0;
 434    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 435       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 436    case PIPE_SHADER_CAP_INTEGERS:
 437    case PIPE_SHADER_CAP_INT64_ATOMICS:
 438    case PIPE_SHADER_CAP_FP16:
 439       return 0;
 440    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 441    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 442       return shader == PIPE_SHADER_FRAGMENT
 443                 ? screen->specs.fragment_sampler_count
 444                 : screen->specs.vertex_sampler_count;
 445    case PIPE_SHADER_CAP_PREFERRED_IR:
 446       return PIPE_SHADER_IR_TGSI;
 447    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 448       return 4096;
 449    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 450    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 451    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 452    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 453    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 454       return false;
 455    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 456       return 0;
 457    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 458       return 32;
 459    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 460    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 461    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 462    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 463    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 464    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 465       return 0;
 466    }
 467
 468    debug_printf("unknown shader param %d", param);
 469    return 0;
 470 }
 471
 472 static uint64_t
 473 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 474 {
 475    return os_time_get_nano();
 476 }
 477
 478 static bool
 479 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 480                            enum pipe_format format)
 481 {
 482    bool supported = true;
 483
 484    if (fmt == TEXTURE_FORMAT_ETC1)
 485       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 486
 487    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 488       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 489
 490    if (util_format_is_srgb(format))
 491       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 492
 493    if (fmt & EXT_FORMAT) {
 494       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 495
 496       /* ETC1 is checked above, as it has its own feature bit. ETC2 is
 497        * supported with HALTI0, however that implementation is buggy in hardware.
 498        * The blob driver does per-block patching to work around this. As this
 499        * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
 500        * only.
 501        */
 502       if (util_format_is_etc(format))
 503          supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
 504    }
 505
 506    if (fmt & ASTC_FORMAT) {
 507       supported = screen->specs.tex_astc;
 508    }
 509
 510    if (!supported)
 511       return false;
 512
 513    if (texture_format_needs_swiz(format))
 514       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 515
 516    return true;
 517 }
 518
 519 static boolean
 520 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 521                                 enum pipe_format format,
 522                                 enum pipe_texture_target target,
 523                                 unsigned sample_count, unsigned usage)
 524 {
 525    struct etna_screen *screen = etna_screen(pscreen);
 526    unsigned allowed = 0;
 527
 528    if (target != PIPE_BUFFER &&
 529        target != PIPE_TEXTURE_1D &&
 530        target != PIPE_TEXTURE_2D &&
 531        target != PIPE_TEXTURE_3D &&
 532        target != PIPE_TEXTURE_CUBE &&
 533        target != PIPE_TEXTURE_RECT)
 534       return FALSE;
 535
 536    if (usage & PIPE_BIND_RENDER_TARGET) {
 537       /* if render target, must be RS-supported format */
 538       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 539          /* Validate MSAA; number of samples must be allowed, and render target
 540           * must have MSAA'able format. */
 541          if (sample_count > 1) {
 542             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 543                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 544                allowed |= PIPE_BIND_RENDER_TARGET;
 545             }
 546          } else {
 547             allowed |= PIPE_BIND_RENDER_TARGET;
 548          }
 549       }
 550    }
 551
 552    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 553       if (translate_depth_format(format) != ETNA_NO_MATCH)
 554          allowed |= PIPE_BIND_DEPTH_STENCIL;
 555    }
 556
 557    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 558       uint32_t fmt = translate_texture_format(format);
 559
 560       if (!gpu_supports_texure_format(screen, fmt, format))
 561          fmt = ETNA_NO_MATCH;
 562
 563       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 564          allowed |= PIPE_BIND_SAMPLER_VIEW;
 565    }
 566
 567    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 568       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 569          allowed |= PIPE_BIND_VERTEX_BUFFER;
 570    }
 571
 572    if (usage & PIPE_BIND_INDEX_BUFFER) {
 573       /* must be supported index format */
 574       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 575           (format == PIPE_FORMAT_I32_UINT &&
 576            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 577          allowed |= PIPE_BIND_INDEX_BUFFER;
 578       }
 579    }
 580
 581    /* Always allowed */
 582    allowed |=
 583       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 584
 585    if (usage != allowed) {
 586       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 587           "usage=%x, allowed=%x",
 588           util_format_name(format), target, sample_count, usage, allowed);
 589    }
 590
 591    return usage == allowed;
 592 }
 593
 594 const uint64_t supported_modifiers[] = {
 595    DRM_FORMAT_MOD_LINEAR,
 596    DRM_FORMAT_MOD_VIVANTE_TILED,
 597    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 598    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 599    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 600 };
 601
 602 static void
 603 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 604                                    enum pipe_format format, int max,
 605                                    uint64_t *modifiers,
 606                                    unsigned int *external_only, int *count)
 607 {
 608    struct etna_screen *screen = etna_screen(pscreen);
 609    int i, num_modifiers = 0;
 610
 611    if (max > ARRAY_SIZE(supported_modifiers))
 612       max = ARRAY_SIZE(supported_modifiers);
 613
 614    if (!max) {
 615       modifiers = NULL;
 616       max = ARRAY_SIZE(supported_modifiers);
 617    }
 618
 619    for (i = 0; num_modifiers < max; i++) {
 620       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 621       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 622           i >= 3)
 623          break;
 624
 625       if (modifiers)
 626          modifiers[num_modifiers] = supported_modifiers[i];
 627       if (external_only)
 628          external_only[num_modifiers] = 0;
 629       num_modifiers++;
 630    }
 631
 632    *count = num_modifiers;
 633 }
 634
 635 static boolean
 636 etna_get_specs(struct etna_screen *screen)
 637 {
 638    uint64_t val;
 639    uint32_t instruction_count;
 640
 641    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 642       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 643       goto fail;
 644    }
 645    instruction_count = val;
 646
 647    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 648                           &val)) {
 649       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 650       goto fail;
 651    }
 652    screen->specs.vertex_output_buffer_size = val;
 653
 654    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 655       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 656       goto fail;
 657    }
 658    screen->specs.vertex_cache_size = val;
 659
 660    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 661       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 662       goto fail;
 663    }
 664    screen->specs.shader_core_count = val;
 665
 666    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 667       DBG("could not get ETNA_GPU_STREAM_COUNT");
 668       goto fail;
 669    }
 670    screen->specs.stream_count = val;
 671
 672    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 673       DBG("could not get ETNA_GPU_REGISTER_MAX");
 674       goto fail;
 675    }
 676    screen->specs.max_registers = val;
 677
 678    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 679       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 680       goto fail;
 681    }
 682    screen->specs.pixel_pipes = val;
 683
 684    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 685       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 686       goto fail;
 687    }
 688    if (val == 0) {
 689       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 690       val = 168;
 691    }
 692    screen->specs.num_constants = val;
 693
 694    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 695     * description of the differences. */
 696    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 697       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 698    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 699       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 700    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 701       screen->specs.halti = 3; /* None? */
 702    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 703       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 704    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 705       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 706    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 707       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 708    else
 709       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 710    if (screen->specs.halti >= 0)
 711       DBG("etnaviv: GPU arch: HALTI%d\n", screen->specs.halti);
 712    else
 713       DBG("etnaviv: GPU arch: pre-HALTI\n");
 714
 715    screen->specs.can_supertile =
 716       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 717    screen->specs.bits_per_tile =
 718       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 719    screen->specs.ts_clear_value =
 720       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 721                                                            : 0x11111111;
 722
 723    /* vertex and fragment samplers live in one address space */
 724    screen->specs.vertex_sampler_offset = 8;
 725    screen->specs.fragment_sampler_count = 8;
 726    screen->specs.vertex_sampler_count = 4;
 727    screen->specs.vs_need_z_div =
 728       screen->model < 0x1000 && screen->model != 0x880;
 729    screen->specs.has_sin_cos_sqrt =
 730       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 731    screen->specs.has_sign_floor_ceil =
 732       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 733    screen->specs.has_shader_range_registers =
 734       screen->model >= 0x1000 || screen->model == 0x880;
 735    screen->specs.npot_tex_any_wrap =
 736       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 737    screen->specs.has_new_transcendentals =
 738       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 739    screen->specs.has_halti2_instructions =
 740       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 741
 742    if (screen->specs.halti >= 5) {
 743       /* GC7000 - this core must load shaders from memory. */
 744       screen->specs.vs_offset = 0;
 745       screen->specs.ps_offset = 0;
 746       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 747       screen->specs.has_icache = true;
 748    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 749       /* GC3000 - this core is capable of loading shaders from
 750        * memory. It can also run shaders from registers, as a fallback, but
 751        * "max_instructions" does not have the correct value. It has place for
 752        * 2*256 instructions just like GC2000, but the offsets are slightly
 753        * different.
 754        */
 755       screen->specs.vs_offset = 0xC000;
 756       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 757        * this mirror for writing PS instructions, probably safest to do the
 758        * same.
 759        */
 760       screen->specs.ps_offset = 0x8000 + 0x1000;
 761       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 762       screen->specs.has_icache = true;
 763    } else {
 764       if (instruction_count > 256) { /* unified instruction memory? */
 765          screen->specs.vs_offset = 0xC000;
 766          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 767          screen->specs.max_instructions = 256;
 768       } else {
 769          screen->specs.vs_offset = 0x4000;
 770          screen->specs.ps_offset = 0x6000;
 771          screen->specs.max_instructions = instruction_count / 2;
 772       }
 773       screen->specs.has_icache = false;
 774    }
 775
 776    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 777       screen->specs.max_varyings = 12;
 778       screen->specs.vertex_max_elements = 16;
 779    } else {
 780       screen->specs.max_varyings = 8;
 781       /* Etna_viv documentation seems confused over the correct value
 782        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 783        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 784       screen->specs.vertex_max_elements = 10;
 785    }
 786
 787    /* Etna_viv documentation does not indicate where varyings above 8 are
 788     * stored. Moreover, if we are passed more than 8 varyings, we will
 789     * walk off the end of some arrays. Limit the maximum number of varyings. */
 790    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 791       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 792
 793    /* from QueryShaderCaps in kernel driver */
 794    if (screen->model < chipModel_GC4000) {
 795       screen->specs.max_vs_uniforms = 168;
 796       screen->specs.max_ps_uniforms = 64;
 797    } else {
 798       screen->specs.max_vs_uniforms = 256;
 799       screen->specs.max_ps_uniforms = 256;
 800    }
 801
 802    if (screen->specs.halti >= 5) {
 803       screen->specs.has_unified_uniforms = true;
 804       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 805       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 806    } else if (screen->specs.halti >= 1) {
 807       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 808       */
 809       screen->specs.has_unified_uniforms = true;
 810       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 811       /* hardcode PS uniforms to start after end of VS uniforms -
 812        * for more flexibility this offset could be variable based on the
 813        * shader.
 814        */
 815       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 816    } else {
 817       screen->specs.has_unified_uniforms = false;
 818       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 819       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 820    }
 821
 822    screen->specs.max_texture_size =
 823       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 824    screen->specs.max_rendertarget_size =
 825       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 826
 827    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 828    if (screen->specs.single_buffer)
 829       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 830
 831    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 832
 833    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 834
 835    return true;
 836
 837 fail:
 838    return false;
 839 }
 840
 841 struct etna_bo *
 842 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 843                            struct winsys_handle *whandle, unsigned *out_stride)
 844 {
 845    struct etna_screen *screen = etna_screen(pscreen);
 846    struct etna_bo *bo;
 847
 848    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 849       bo = etna_bo_from_name(screen->dev, whandle->handle);
 850    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 851       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 852    } else {
 853       DBG("Attempt to import unsupported handle type %d", whandle->type);
 854       return NULL;
 855    }
 856
 857    if (!bo) {
 858       DBG("ref name 0x%08x failed", whandle->handle);
 859       return NULL;
 860    }
 861
 862    *out_stride = whandle->stride;
 863
 864    return bo;
 865 }
 866
 867 struct pipe_screen *
 868 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 869                    struct renderonly *ro)
 870 {
 871    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 872    struct pipe_screen *pscreen;
 873    drmVersionPtr version;
 874    uint64_t val;
 875
 876    if (!screen)
 877       return NULL;
 878
 879    pscreen = &screen->base;
 880    screen->dev = dev;
 881    screen->gpu = gpu;
 882    screen->ro = renderonly_dup(ro);
 883    screen->refcnt = 1;
 884
 885    if (!screen->ro) {
 886       DBG("could not create renderonly object");
 887       goto fail;
 888    }
 889
 890    version = drmGetVersion(screen->ro->gpu_fd);
 891    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 892                                           version->version_minor);
 893    drmFreeVersion(version);
 894
 895    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 896
 897    /* Disable autodisable for correct rendering with TS */
 898    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 899
 900    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 901    if (!screen->pipe) {
 902       DBG("could not create 3d pipe");
 903       goto fail;
 904    }
 905
 906    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 907       DBG("could not get ETNA_GPU_MODEL");
 908       goto fail;
 909    }
 910    screen->model = val;
 911
 912    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 913       DBG("could not get ETNA_GPU_REVISION");
 914       goto fail;
 915    }
 916    screen->revision = val;
 917
 918    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 919       DBG("could not get ETNA_GPU_FEATURES_0");
 920       goto fail;
 921    }
 922    screen->features[0] = val;
 923
 924    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 925       DBG("could not get ETNA_GPU_FEATURES_1");
 926       goto fail;
 927    }
 928    screen->features[1] = val;
 929
 930    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 931       DBG("could not get ETNA_GPU_FEATURES_2");
 932       goto fail;
 933    }
 934    screen->features[2] = val;
 935
 936    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 937       DBG("could not get ETNA_GPU_FEATURES_3");
 938       goto fail;
 939    }
 940    screen->features[3] = val;
 941
 942    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 943       DBG("could not get ETNA_GPU_FEATURES_4");
 944       goto fail;
 945    }
 946    screen->features[4] = val;
 947
 948    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 949       DBG("could not get ETNA_GPU_FEATURES_5");
 950       goto fail;
 951    }
 952    screen->features[5] = val;
 953
 954    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 955       DBG("could not get ETNA_GPU_FEATURES_6");
 956       goto fail;
 957    }
 958    screen->features[6] = val;
 959
 960    if (!etna_get_specs(screen))
 961       goto fail;
 962
 963    /* apply debug options that disable individual features */
 964    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 965       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 966    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 967          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 968    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 969       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 970    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 971       screen->specs.can_supertile = 0;
 972
 973    pscreen->destroy = etna_screen_destroy;
 974    pscreen->get_param = etna_screen_get_param;
 975    pscreen->get_paramf = etna_screen_get_paramf;
 976    pscreen->get_shader_param = etna_screen_get_shader_param;
 977
 978    pscreen->get_name = etna_screen_get_name;
 979    pscreen->get_vendor = etna_screen_get_vendor;
 980    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 981
 982    pscreen->get_timestamp = etna_screen_get_timestamp;
 983    pscreen->context_create = etna_context_create;
 984    pscreen->is_format_supported = etna_screen_is_format_supported;
 985    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 986
 987    etna_fence_screen_init(pscreen);
 988    etna_query_screen_init(pscreen);
 989    etna_resource_screen_init(pscreen);
 990
 991    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 992
 993    return pscreen;
 994
 995 fail:
 996    etna_screen_destroy(pscreen);
 997    return NULL;
 998 }