src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  49 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  50
  51 static const struct debug_named_value debug_options[] = {
  52    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  53    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  54    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  55    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  56    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  57    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  58    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  59    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  60    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  61    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  62    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  63    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  64    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  65    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  66    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  67    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  68    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  69    DEBUG_NAMED_VALUE_END
  70 };
  71
  72 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  73 int etna_mesa_debug = 0;
  74
  75 static void
  76 etna_screen_destroy(struct pipe_screen *pscreen)
  77 {
  78    struct etna_screen *screen = etna_screen(pscreen);
  79
  80    if (screen->pipe)
  81       etna_pipe_del(screen->pipe);
  82
  83    if (screen->gpu)
  84       etna_gpu_del(screen->gpu);
  85
  86    if (screen->ro)
  87       FREE(screen->ro);
  88
  89    if (screen->dev)
  90       etna_device_del(screen->dev);
  91
  92    FREE(screen);
  93 }
  94
  95 static const char *
  96 etna_screen_get_name(struct pipe_screen *pscreen)
  97 {
  98    struct etna_screen *priv = etna_screen(pscreen);
  99    static char buffer[128];
 100
 101    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 102                  priv->revision);
 103
 104    return buffer;
 105 }
 106
 107 static const char *
 108 etna_screen_get_vendor(struct pipe_screen *pscreen)
 109 {
 110    return "etnaviv";
 111 }
 112
 113 static const char *
 114 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 115 {
 116    return "Vivante";
 117 }
 118
 119 static int
 120 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 121 {
 122    struct etna_screen *screen = etna_screen(pscreen);
 123
 124    switch (param) {
 125    /* Supported features (boolean caps). */
 126    case PIPE_CAP_TWO_SIDED_STENCIL:
 127    case PIPE_CAP_ANISOTROPIC_FILTER:
 128    case PIPE_CAP_POINT_SPRITE:
 129    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 130    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 131    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 132    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 133    case PIPE_CAP_SM3:
 134    case PIPE_CAP_TEXTURE_BARRIER:
 135    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 136    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 137    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 142       return 1;
 143    case PIPE_CAP_NATIVE_FENCE_FD:
 144       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 145
 146    /* Memory */
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 150       return 4; /* XXX could easily be supported */
 151    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 152       return 120;
 153
 154    case PIPE_CAP_NPOT_TEXTURES:
 155       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 156                       NON_POWER_OF_TWO); */
 157
 158    case PIPE_CAP_PRIMITIVE_RESTART:
 159       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 160
 161    case PIPE_CAP_ENDIANNESS:
 162       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 163                                     ENDIANNESS_CONFIG) */
 164
 165    /* Unsupported features. */
 166    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 167    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
 168    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 169    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 170    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 171    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 172    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 173    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 174    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 175    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 176    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 177    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 178    case PIPE_CAP_INDEP_BLEND_ENABLE:
 179    case PIPE_CAP_INDEP_BLEND_FUNC:
 180    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 181    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 182    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 183    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 184    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 185    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 187    case PIPE_CAP_USER_VERTEX_BUFFERS:
 188    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 189    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 191    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 192    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 193    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 194    case PIPE_CAP_TEXTURE_GATHER_SM5:
 195    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 196    case PIPE_CAP_FAKE_SW_MSAA:
 197    case PIPE_CAP_TEXTURE_QUERY_LOD:
 198    case PIPE_CAP_SAMPLE_SHADING:
 199    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 200    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 201    case PIPE_CAP_DRAW_INDIRECT:
 202    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 203    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 204    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 205    case PIPE_CAP_CLIP_HALFZ:
 206    case PIPE_CAP_VERTEXID_NOBASE:
 207    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 208    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 209    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 210    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 211    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 212    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 213    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 214    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 215    case PIPE_CAP_TGSI_TXQS:
 216    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 217    case PIPE_CAP_SHAREABLE_SHADERS:
 218    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 219    case PIPE_CAP_CLEAR_TEXTURE:
 220    case PIPE_CAP_DRAW_PARAMETERS:
 221    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 222    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 223    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 224    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 225    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 226    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_GENERATE_MIPMAP:
 229    case PIPE_CAP_STRING_MARKER:
 230    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 231    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 232    case PIPE_CAP_QUERY_MEMORY_INFO:
 233    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 234    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 235    case PIPE_CAP_CULL_DISTANCE:
 236    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 237    case PIPE_CAP_TGSI_VOTE:
 238    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 239    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 240    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 241    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 242    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 243    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 244    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 245    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 246    case PIPE_CAP_TGSI_FS_FBFETCH:
 247    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 248    case PIPE_CAP_DOUBLES:
 249    case PIPE_CAP_INT64:
 250    case PIPE_CAP_INT64_DIVMOD:
 251    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 252    case PIPE_CAP_TGSI_CLOCK:
 253    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 254    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 255    case PIPE_CAP_TGSI_BALLOT:
 256    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 257    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 258    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 259    case PIPE_CAP_POST_DEPTH_COVERAGE:
 260       return 0;
 261
 262    /* Stream output. */
 263    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 264    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 265    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 266    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 267       return 0;
 268
 269    /* Geometry shader output, unsupported. */
 270    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 271    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 272    case PIPE_CAP_MAX_VERTEX_STREAMS:
 273       return 0;
 274
 275    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 276       return 128;
 277
 278    /* Texturing. */
 279    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 280    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 281    {
 282       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 283       assert(log2_max_tex_size > 0);
 284       return log2_max_tex_size;
 285    }
 286    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 287       return 5;
 288    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 289       return 0;
 290    case PIPE_CAP_CUBE_MAP_ARRAY:
 291       return 0;
 292    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 293    case PIPE_CAP_MIN_TEXEL_OFFSET:
 294       return -8;
 295    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 296    case PIPE_CAP_MAX_TEXEL_OFFSET:
 297       return 7;
 298    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 299       return 0;
 300    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 301       return 65536;
 302
 303    /* Render targets. */
 304    case PIPE_CAP_MAX_RENDER_TARGETS:
 305       return 1;
 306
 307    /* Viewports and scissors. */
 308    case PIPE_CAP_MAX_VIEWPORTS:
 309       return 1;
 310
 311    /* Timer queries. */
 312    case PIPE_CAP_QUERY_TIME_ELAPSED:
 313    case PIPE_CAP_OCCLUSION_QUERY:
 314       return 0;
 315    case PIPE_CAP_QUERY_TIMESTAMP:
 316       return 1;
 317    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 318       return 0;
 319
 320    /* Preferences */
 321    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 322       return 0;
 323
 324    case PIPE_CAP_PCI_GROUP:
 325    case PIPE_CAP_PCI_BUS:
 326    case PIPE_CAP_PCI_DEVICE:
 327    case PIPE_CAP_PCI_FUNCTION:
 328       return 0;
 329    case PIPE_CAP_VENDOR_ID:
 330    case PIPE_CAP_DEVICE_ID:
 331       return 0xFFFFFFFF;
 332    case PIPE_CAP_ACCELERATED:
 333       return 1;
 334    case PIPE_CAP_VIDEO_MEMORY:
 335       return 0;
 336    case PIPE_CAP_UMA:
 337       return 1;
 338    }
 339
 340    debug_printf("unknown param %d", param);
 341    return 0;
 342 }
 343
 344 static float
 345 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 346 {
 347    switch (param) {
 348    case PIPE_CAPF_MAX_LINE_WIDTH:
 349    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 350    case PIPE_CAPF_MAX_POINT_WIDTH:
 351    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 352       return 8192.0f;
 353    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 354       return 16.0f;
 355    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 356       return 16.0f;
 357    case PIPE_CAPF_GUARD_BAND_LEFT:
 358    case PIPE_CAPF_GUARD_BAND_TOP:
 359    case PIPE_CAPF_GUARD_BAND_RIGHT:
 360    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 361       return 0.0f;
 362    }
 363
 364    debug_printf("unknown paramf %d", param);
 365    return 0;
 366 }
 367
 368 static int
 369 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 370                              enum pipe_shader_type shader,
 371                              enum pipe_shader_cap param)
 372 {
 373    struct etna_screen *screen = etna_screen(pscreen);
 374
 375    switch (shader) {
 376    case PIPE_SHADER_FRAGMENT:
 377    case PIPE_SHADER_VERTEX:
 378       break;
 379    case PIPE_SHADER_COMPUTE:
 380    case PIPE_SHADER_GEOMETRY:
 381    case PIPE_SHADER_TESS_CTRL:
 382    case PIPE_SHADER_TESS_EVAL:
 383       return 0;
 384    default:
 385       DBG("unknown shader type %d", shader);
 386       return 0;
 387    }
 388
 389    switch (param) {
 390    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 391    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 392    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 393    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 394       return ETNA_MAX_TOKENS;
 395    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 396       return ETNA_MAX_DEPTH; /* XXX */
 397    case PIPE_SHADER_CAP_MAX_INPUTS:
 398       /* Maximum number of inputs for the vertex shader is the number
 399        * of vertex elements - each element defines one vertex shader
 400        * input register.  For the fragment shader, this is the number
 401        * of varyings. */
 402       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 403                                             : screen->specs.vertex_max_elements;
 404    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 405       return 16; /* see VIVS_VS_OUTPUT */
 406    case PIPE_SHADER_CAP_MAX_TEMPS:
 407       return 64; /* Max native temporaries. */
 408    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 409       return 1;
 410    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 411       return 1;
 412    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 413    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 414    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 415    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 416       return 1;
 417    case PIPE_SHADER_CAP_SUBROUTINES:
 418       return 0;
 419    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 420       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 421    case PIPE_SHADER_CAP_INTEGERS:
 422       return 0;
 423    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 424    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 425       return shader == PIPE_SHADER_FRAGMENT
 426                 ? screen->specs.fragment_sampler_count
 427                 : screen->specs.vertex_sampler_count;
 428    case PIPE_SHADER_CAP_PREFERRED_IR:
 429       return PIPE_SHADER_IR_TGSI;
 430    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 431       return 4096;
 432    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 433    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 434    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 435    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 436       return false;
 437    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 438       return 0;
 439    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 440       return 32;
 441    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 442    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 443    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 444    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 445       return 0;
 446    }
 447
 448    debug_printf("unknown shader param %d", param);
 449    return 0;
 450 }
 451
 452 static uint64_t
 453 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 454 {
 455    return os_time_get_nano();
 456 }
 457
 458 static bool
 459 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
 460 {
 461    if (fmt == TEXTURE_FORMAT_ETC1)
 462       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 463
 464    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 465       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 466
 467    return true;
 468 }
 469
 470 static boolean
 471 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 472                                 enum pipe_format format,
 473                                 enum pipe_texture_target target,
 474                                 unsigned sample_count, unsigned usage)
 475 {
 476    struct etna_screen *screen = etna_screen(pscreen);
 477    unsigned allowed = 0;
 478
 479    if (target != PIPE_BUFFER &&
 480        target != PIPE_TEXTURE_1D &&
 481        target != PIPE_TEXTURE_2D &&
 482        target != PIPE_TEXTURE_3D &&
 483        target != PIPE_TEXTURE_CUBE &&
 484        target != PIPE_TEXTURE_RECT)
 485       return FALSE;
 486
 487    if (usage & PIPE_BIND_RENDER_TARGET) {
 488       /* if render target, must be RS-supported format */
 489       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 490          /* Validate MSAA; number of samples must be allowed, and render target
 491           * must have MSAA'able format. */
 492          if (sample_count > 1) {
 493             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 494                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 495                allowed |= PIPE_BIND_RENDER_TARGET;
 496             }
 497          } else {
 498             allowed |= PIPE_BIND_RENDER_TARGET;
 499          }
 500       }
 501    }
 502
 503    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 504       if (translate_depth_format(format) != ETNA_NO_MATCH)
 505          allowed |= PIPE_BIND_DEPTH_STENCIL;
 506    }
 507
 508    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 509       uint32_t fmt = translate_texture_format(format);
 510
 511       if (!gpu_supports_texure_format(screen, fmt))
 512          fmt = ETNA_NO_MATCH;
 513
 514       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 515          allowed |= PIPE_BIND_SAMPLER_VIEW;
 516    }
 517
 518    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 519       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 520          allowed |= PIPE_BIND_VERTEX_BUFFER;
 521    }
 522
 523    if (usage & PIPE_BIND_INDEX_BUFFER) {
 524       /* must be supported index format */
 525       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 526           (format == PIPE_FORMAT_I32_UINT &&
 527            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 528          allowed |= PIPE_BIND_INDEX_BUFFER;
 529       }
 530    }
 531
 532    /* Always allowed */
 533    allowed |=
 534       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 535
 536    if (usage != allowed) {
 537       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 538           "usage=%x, allowed=%x",
 539           util_format_name(format), target, sample_count, usage, allowed);
 540    }
 541
 542    return usage == allowed;
 543 }
 544
 545 static boolean
 546 etna_get_specs(struct etna_screen *screen)
 547 {
 548    uint64_t val;
 549    uint32_t instruction_count;
 550
 551    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 552       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 553       goto fail;
 554    }
 555    instruction_count = val;
 556
 557    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 558                           &val)) {
 559       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 560       goto fail;
 561    }
 562    screen->specs.vertex_output_buffer_size = val;
 563
 564    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 565       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 566       goto fail;
 567    }
 568    screen->specs.vertex_cache_size = val;
 569
 570    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 571       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 572       goto fail;
 573    }
 574    screen->specs.shader_core_count = val;
 575
 576    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 577       DBG("could not get ETNA_GPU_STREAM_COUNT");
 578       goto fail;
 579    }
 580    screen->specs.stream_count = val;
 581
 582    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 583       DBG("could not get ETNA_GPU_REGISTER_MAX");
 584       goto fail;
 585    }
 586    screen->specs.max_registers = val;
 587
 588    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 589       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 590       goto fail;
 591    }
 592    screen->specs.pixel_pipes = val;
 593
 594    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 595       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 596       goto fail;
 597    }
 598    if (val == 0) {
 599       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 600       val = 168;
 601    }
 602    screen->specs.num_constants = val;
 603
 604    screen->specs.can_supertile =
 605       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 606    screen->specs.bits_per_tile =
 607       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 608    screen->specs.ts_clear_value =
 609       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 610                                                            : 0x11111111;
 611
 612    /* vertex and fragment samplers live in one address space */
 613    screen->specs.vertex_sampler_offset = 8;
 614    screen->specs.fragment_sampler_count = 8;
 615    screen->specs.vertex_sampler_count = 4;
 616    screen->specs.vs_need_z_div =
 617       screen->model < 0x1000 && screen->model != 0x880;
 618    screen->specs.has_sin_cos_sqrt =
 619       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 620    screen->specs.has_sign_floor_ceil =
 621       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 622    screen->specs.has_shader_range_registers =
 623       screen->model >= 0x1000 || screen->model == 0x880;
 624    screen->specs.npot_tex_any_wrap =
 625       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 626    screen->specs.has_new_sin_cos =
 627       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 628
 629    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 630       /* GC3000 - this core is capable of loading shaders from
 631        * memory. It can also run shaders from registers, as a fallback, but
 632        * "max_instructions" does not have the correct value. It has place for
 633        * 2*256 instructions just like GC2000, but the offsets are slightly
 634        * different.
 635        */
 636       screen->specs.vs_offset = 0xC000;
 637       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 638        * this mirror for writing PS instructions, probably safest to do the
 639        * same.
 640        */
 641       screen->specs.ps_offset = 0x8000 + 0x1000;
 642       screen->specs.max_instructions = 256;
 643    } else {
 644       if (instruction_count > 256) { /* unified instruction memory? */
 645          screen->specs.vs_offset = 0xC000;
 646          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 647          screen->specs.max_instructions = 256;
 648       } else {
 649          screen->specs.vs_offset = 0x4000;
 650          screen->specs.ps_offset = 0x6000;
 651          screen->specs.max_instructions = instruction_count / 2;
 652       }
 653    }
 654
 655    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 656       screen->specs.max_varyings = 12;
 657       screen->specs.vertex_max_elements = 16;
 658    } else {
 659       screen->specs.max_varyings = 8;
 660       /* Etna_viv documentation seems confused over the correct value
 661        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 662        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 663       screen->specs.vertex_max_elements = 10;
 664    }
 665
 666    /* Etna_viv documentation does not indicate where varyings above 8 are
 667     * stored. Moreover, if we are passed more than 8 varyings, we will
 668     * walk off the end of some arrays. Limit the maximum number of varyings. */
 669    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 670       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 671
 672    /* from QueryShaderCaps in kernel driver */
 673    if (screen->model < chipModel_GC4000) {
 674       screen->specs.max_vs_uniforms = 168;
 675       screen->specs.max_ps_uniforms = 64;
 676    } else {
 677       screen->specs.max_vs_uniforms = 256;
 678       screen->specs.max_ps_uniforms = 256;
 679    }
 680
 681    screen->specs.max_texture_size =
 682       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 683    screen->specs.max_rendertarget_size =
 684       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 685
 686    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 687    if (screen->specs.single_buffer)
 688       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 689
 690    return true;
 691
 692 fail:
 693    return false;
 694 }
 695
 696 boolean
 697 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
 698                           unsigned stride, struct winsys_handle *whandle)
 699 {
 700    whandle->stride = stride;
 701
 702    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 703       return etna_bo_get_name(bo, &whandle->handle) == 0;
 704    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 705       whandle->handle = etna_bo_handle(bo);
 706       return TRUE;
 707    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 708       whandle->handle = etna_bo_dmabuf(bo);
 709       return TRUE;
 710    } else {
 711       return FALSE;
 712    }
 713 }
 714
 715 struct etna_bo *
 716 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 717                            struct winsys_handle *whandle, unsigned *out_stride)
 718 {
 719    struct etna_screen *screen = etna_screen(pscreen);
 720    struct etna_bo *bo;
 721
 722    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 723       bo = etna_bo_from_name(screen->dev, whandle->handle);
 724    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 725       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 726    } else {
 727       DBG("Attempt to import unsupported handle type %d", whandle->type);
 728       return NULL;
 729    }
 730
 731    if (!bo) {
 732       DBG("ref name 0x%08x failed", whandle->handle);
 733       return NULL;
 734    }
 735
 736    *out_stride = whandle->stride;
 737
 738    return bo;
 739 }
 740
 741 struct pipe_screen *
 742 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 743                    struct renderonly *ro)
 744 {
 745    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 746    struct pipe_screen *pscreen;
 747    drmVersionPtr version;
 748    uint64_t val;
 749
 750    if (!screen)
 751       return NULL;
 752
 753    pscreen = &screen->base;
 754    screen->dev = dev;
 755    screen->gpu = gpu;
 756    screen->ro = renderonly_dup(ro);
 757
 758    if (!screen->ro) {
 759       DBG("could not create renderonly object");
 760       goto fail;
 761    }
 762
 763    version = drmGetVersion(screen->ro->gpu_fd);
 764    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 765                                           version->version_minor);
 766    drmFreeVersion(version);
 767
 768    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 769
 770    /* Disable autodisable for correct rendering with TS */
 771    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 772
 773    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 774    if (!screen->pipe) {
 775       DBG("could not create 3d pipe");
 776       goto fail;
 777    }
 778
 779    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 780       DBG("could not get ETNA_GPU_MODEL");
 781       goto fail;
 782    }
 783    screen->model = val;
 784
 785    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 786       DBG("could not get ETNA_GPU_REVISION");
 787       goto fail;
 788    }
 789    screen->revision = val;
 790
 791    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 792       DBG("could not get ETNA_GPU_FEATURES_0");
 793       goto fail;
 794    }
 795    screen->features[0] = val;
 796
 797    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 798       DBG("could not get ETNA_GPU_FEATURES_1");
 799       goto fail;
 800    }
 801    screen->features[1] = val;
 802
 803    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 804       DBG("could not get ETNA_GPU_FEATURES_2");
 805       goto fail;
 806    }
 807    screen->features[2] = val;
 808
 809    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 810       DBG("could not get ETNA_GPU_FEATURES_3");
 811       goto fail;
 812    }
 813    screen->features[3] = val;
 814
 815    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 816       DBG("could not get ETNA_GPU_FEATURES_4");
 817       goto fail;
 818    }
 819    screen->features[4] = val;
 820
 821    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 822       DBG("could not get ETNA_GPU_FEATURES_5");
 823       goto fail;
 824    }
 825    screen->features[5] = val;
 826
 827    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 828       DBG("could not get ETNA_GPU_FEATURES_6");
 829       goto fail;
 830    }
 831    screen->features[6] = val;
 832
 833    if (!etna_get_specs(screen))
 834       goto fail;
 835
 836    /* apply debug options that disable individual features */
 837    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 838       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 839    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 840          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 841    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 842       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 843    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 844       screen->specs.can_supertile = 0;
 845
 846    pscreen->destroy = etna_screen_destroy;
 847    pscreen->get_param = etna_screen_get_param;
 848    pscreen->get_paramf = etna_screen_get_paramf;
 849    pscreen->get_shader_param = etna_screen_get_shader_param;
 850
 851    pscreen->get_name = etna_screen_get_name;
 852    pscreen->get_vendor = etna_screen_get_vendor;
 853    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 854
 855    pscreen->get_timestamp = etna_screen_get_timestamp;
 856    pscreen->context_create = etna_context_create;
 857    pscreen->is_format_supported = etna_screen_is_format_supported;
 858
 859    etna_fence_screen_init(pscreen);
 860    etna_query_screen_init(pscreen);
 861    etna_resource_screen_init(pscreen);
 862
 863    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 864
 865    return pscreen;
 866
 867 fail:
 868    etna_screen_destroy(pscreen);
 869    return NULL;
 870 }