src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  49 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  50
  51 static const struct debug_named_value debug_options[] = {
  52    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  53    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  54    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  55    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  56    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  57    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  58    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  59    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  60    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  61    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  62    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  63    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  64    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  65    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  66    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  67    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  68    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  69    DEBUG_NAMED_VALUE_END
  70 };
  71
  72 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  73 int etna_mesa_debug = 0;
  74
  75 static void
  76 etna_screen_destroy(struct pipe_screen *pscreen)
  77 {
  78    struct etna_screen *screen = etna_screen(pscreen);
  79
  80    if (screen->pipe)
  81       etna_pipe_del(screen->pipe);
  82
  83    if (screen->gpu)
  84       etna_gpu_del(screen->gpu);
  85
  86    if (screen->ro)
  87       FREE(screen->ro);
  88
  89    if (screen->dev)
  90       etna_device_del(screen->dev);
  91
  92    FREE(screen);
  93 }
  94
  95 static const char *
  96 etna_screen_get_name(struct pipe_screen *pscreen)
  97 {
  98    struct etna_screen *priv = etna_screen(pscreen);
  99    static char buffer[128];
 100
 101    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 102                  priv->revision);
 103
 104    return buffer;
 105 }
 106
 107 static const char *
 108 etna_screen_get_vendor(struct pipe_screen *pscreen)
 109 {
 110    return "etnaviv";
 111 }
 112
 113 static const char *
 114 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 115 {
 116    return "Vivante";
 117 }
 118
 119 static int
 120 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 121 {
 122    struct etna_screen *screen = etna_screen(pscreen);
 123
 124    switch (param) {
 125    /* Supported features (boolean caps). */
 126    case PIPE_CAP_TWO_SIDED_STENCIL:
 127    case PIPE_CAP_ANISOTROPIC_FILTER:
 128    case PIPE_CAP_POINT_SPRITE:
 129    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 130    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 131    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 132    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 133    case PIPE_CAP_SM3:
 134    case PIPE_CAP_TEXTURE_BARRIER:
 135    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 136    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 137    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 142       return 1;
 143    case PIPE_CAP_NATIVE_FENCE_FD:
 144       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 145
 146    /* Memory */
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 150       return 4; /* XXX could easily be supported */
 151    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 152       return 120;
 153
 154    case PIPE_CAP_NPOT_TEXTURES:
 155       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 156                       NON_POWER_OF_TWO); */
 157
 158    case PIPE_CAP_PRIMITIVE_RESTART:
 159       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 160
 161    case PIPE_CAP_ENDIANNESS:
 162       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 163                                     ENDIANNESS_CONFIG) */
 164
 165    /* Unsupported features. */
 166    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 167    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
 168    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 169    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 170    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 171    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 172    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 173    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 174    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 175    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 176    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 177    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 178    case PIPE_CAP_INDEP_BLEND_ENABLE:
 179    case PIPE_CAP_INDEP_BLEND_FUNC:
 180    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 181    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 182    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 183    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 184    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 185    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 187    case PIPE_CAP_USER_VERTEX_BUFFERS:
 188    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 189    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 191    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 192    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 193    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 194    case PIPE_CAP_TEXTURE_GATHER_SM5:
 195    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 196    case PIPE_CAP_FAKE_SW_MSAA:
 197    case PIPE_CAP_TEXTURE_QUERY_LOD:
 198    case PIPE_CAP_SAMPLE_SHADING:
 199    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 200    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 201    case PIPE_CAP_DRAW_INDIRECT:
 202    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 203    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 204    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 205    case PIPE_CAP_CLIP_HALFZ:
 206    case PIPE_CAP_VERTEXID_NOBASE:
 207    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 208    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 209    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 210    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 211    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 212    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 213    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 214    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 215    case PIPE_CAP_TGSI_TXQS:
 216    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 217    case PIPE_CAP_SHAREABLE_SHADERS:
 218    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 219    case PIPE_CAP_CLEAR_TEXTURE:
 220    case PIPE_CAP_DRAW_PARAMETERS:
 221    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 222    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 223    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 224    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 225    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 226    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_GENERATE_MIPMAP:
 229    case PIPE_CAP_STRING_MARKER:
 230    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 231    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 232    case PIPE_CAP_QUERY_MEMORY_INFO:
 233    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 234    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 235    case PIPE_CAP_CULL_DISTANCE:
 236    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 237    case PIPE_CAP_TGSI_VOTE:
 238    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 239    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 240    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 241    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 242    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 243    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 244    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 245    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 246    case PIPE_CAP_TGSI_FS_FBFETCH:
 247    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 248    case PIPE_CAP_DOUBLES:
 249    case PIPE_CAP_INT64:
 250    case PIPE_CAP_INT64_DIVMOD:
 251    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 252    case PIPE_CAP_TGSI_CLOCK:
 253    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 254    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 255    case PIPE_CAP_TGSI_BALLOT:
 256    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 257    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 258    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 259    case PIPE_CAP_POST_DEPTH_COVERAGE:
 260    case PIPE_CAP_BINDLESS_TEXTURE:
 261       return 0;
 262
 263    /* Stream output. */
 264    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 265    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 266    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 267    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 268       return 0;
 269
 270    /* Geometry shader output, unsupported. */
 271    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 272    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 273    case PIPE_CAP_MAX_VERTEX_STREAMS:
 274       return 0;
 275
 276    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 277       return 128;
 278
 279    /* Texturing. */
 280    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 281    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 282    {
 283       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 284       assert(log2_max_tex_size > 0);
 285       return log2_max_tex_size;
 286    }
 287    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 288       return 5;
 289    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 290       return 0;
 291    case PIPE_CAP_CUBE_MAP_ARRAY:
 292       return 0;
 293    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 294    case PIPE_CAP_MIN_TEXEL_OFFSET:
 295       return -8;
 296    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 297    case PIPE_CAP_MAX_TEXEL_OFFSET:
 298       return 7;
 299    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 300       return 0;
 301    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 302       return 65536;
 303
 304    /* Render targets. */
 305    case PIPE_CAP_MAX_RENDER_TARGETS:
 306       return 1;
 307
 308    /* Viewports and scissors. */
 309    case PIPE_CAP_MAX_VIEWPORTS:
 310       return 1;
 311
 312    /* Timer queries. */
 313    case PIPE_CAP_QUERY_TIME_ELAPSED:
 314    case PIPE_CAP_OCCLUSION_QUERY:
 315       return 0;
 316    case PIPE_CAP_QUERY_TIMESTAMP:
 317       return 1;
 318    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 319       return 0;
 320
 321    /* Preferences */
 322    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 323       return 0;
 324
 325    case PIPE_CAP_PCI_GROUP:
 326    case PIPE_CAP_PCI_BUS:
 327    case PIPE_CAP_PCI_DEVICE:
 328    case PIPE_CAP_PCI_FUNCTION:
 329       return 0;
 330    case PIPE_CAP_VENDOR_ID:
 331    case PIPE_CAP_DEVICE_ID:
 332       return 0xFFFFFFFF;
 333    case PIPE_CAP_ACCELERATED:
 334       return 1;
 335    case PIPE_CAP_VIDEO_MEMORY:
 336       return 0;
 337    case PIPE_CAP_UMA:
 338       return 1;
 339    }
 340
 341    debug_printf("unknown param %d", param);
 342    return 0;
 343 }
 344
 345 static float
 346 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 347 {
 348    struct etna_screen *screen = etna_screen(pscreen);
 349
 350    switch (param) {
 351    case PIPE_CAPF_MAX_LINE_WIDTH:
 352    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 353    case PIPE_CAPF_MAX_POINT_WIDTH:
 354    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 355       return 8192.0f;
 356    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 357       return 16.0f;
 358    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 359       return util_last_bit(screen->specs.max_texture_size);
 360    case PIPE_CAPF_GUARD_BAND_LEFT:
 361    case PIPE_CAPF_GUARD_BAND_TOP:
 362    case PIPE_CAPF_GUARD_BAND_RIGHT:
 363    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 364       return 0.0f;
 365    }
 366
 367    debug_printf("unknown paramf %d", param);
 368    return 0;
 369 }
 370
 371 static int
 372 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 373                              enum pipe_shader_type shader,
 374                              enum pipe_shader_cap param)
 375 {
 376    struct etna_screen *screen = etna_screen(pscreen);
 377
 378    switch (shader) {
 379    case PIPE_SHADER_FRAGMENT:
 380    case PIPE_SHADER_VERTEX:
 381       break;
 382    case PIPE_SHADER_COMPUTE:
 383    case PIPE_SHADER_GEOMETRY:
 384    case PIPE_SHADER_TESS_CTRL:
 385    case PIPE_SHADER_TESS_EVAL:
 386       return 0;
 387    default:
 388       DBG("unknown shader type %d", shader);
 389       return 0;
 390    }
 391
 392    switch (param) {
 393    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 394    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 395    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 396    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 397       return ETNA_MAX_TOKENS;
 398    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 399       return ETNA_MAX_DEPTH; /* XXX */
 400    case PIPE_SHADER_CAP_MAX_INPUTS:
 401       /* Maximum number of inputs for the vertex shader is the number
 402        * of vertex elements - each element defines one vertex shader
 403        * input register.  For the fragment shader, this is the number
 404        * of varyings. */
 405       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 406                                             : screen->specs.vertex_max_elements;
 407    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 408       return 16; /* see VIVS_VS_OUTPUT */
 409    case PIPE_SHADER_CAP_MAX_TEMPS:
 410       return 64; /* Max native temporaries. */
 411    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 412       return 1;
 413    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 414       return 1;
 415    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 416    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 417    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 418    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 419       return 1;
 420    case PIPE_SHADER_CAP_SUBROUTINES:
 421       return 0;
 422    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 423       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 424    case PIPE_SHADER_CAP_INTEGERS:
 425       return 0;
 426    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 427    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 428       return shader == PIPE_SHADER_FRAGMENT
 429                 ? screen->specs.fragment_sampler_count
 430                 : screen->specs.vertex_sampler_count;
 431    case PIPE_SHADER_CAP_PREFERRED_IR:
 432       return PIPE_SHADER_IR_TGSI;
 433    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 434       return 4096;
 435    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 436    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 437    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 438    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 439       return false;
 440    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 441       return 0;
 442    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 443       return 32;
 444    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 445    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 446    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 447    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 448       return 0;
 449    }
 450
 451    debug_printf("unknown shader param %d", param);
 452    return 0;
 453 }
 454
 455 static uint64_t
 456 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 457 {
 458    return os_time_get_nano();
 459 }
 460
 461 static bool
 462 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
 463 {
 464    if (fmt == TEXTURE_FORMAT_ETC1)
 465       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 466
 467    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 468       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 469
 470    return true;
 471 }
 472
 473 static boolean
 474 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 475                                 enum pipe_format format,
 476                                 enum pipe_texture_target target,
 477                                 unsigned sample_count, unsigned usage)
 478 {
 479    struct etna_screen *screen = etna_screen(pscreen);
 480    unsigned allowed = 0;
 481
 482    if (target != PIPE_BUFFER &&
 483        target != PIPE_TEXTURE_1D &&
 484        target != PIPE_TEXTURE_2D &&
 485        target != PIPE_TEXTURE_3D &&
 486        target != PIPE_TEXTURE_CUBE &&
 487        target != PIPE_TEXTURE_RECT)
 488       return FALSE;
 489
 490    if (usage & PIPE_BIND_RENDER_TARGET) {
 491       /* if render target, must be RS-supported format */
 492       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 493          /* Validate MSAA; number of samples must be allowed, and render target
 494           * must have MSAA'able format. */
 495          if (sample_count > 1) {
 496             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 497                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 498                allowed |= PIPE_BIND_RENDER_TARGET;
 499             }
 500          } else {
 501             allowed |= PIPE_BIND_RENDER_TARGET;
 502          }
 503       }
 504    }
 505
 506    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 507       if (translate_depth_format(format) != ETNA_NO_MATCH)
 508          allowed |= PIPE_BIND_DEPTH_STENCIL;
 509    }
 510
 511    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 512       uint32_t fmt = translate_texture_format(format);
 513
 514       if (!gpu_supports_texure_format(screen, fmt))
 515          fmt = ETNA_NO_MATCH;
 516
 517       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 518          allowed |= PIPE_BIND_SAMPLER_VIEW;
 519    }
 520
 521    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 522       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 523          allowed |= PIPE_BIND_VERTEX_BUFFER;
 524    }
 525
 526    if (usage & PIPE_BIND_INDEX_BUFFER) {
 527       /* must be supported index format */
 528       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 529           (format == PIPE_FORMAT_I32_UINT &&
 530            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 531          allowed |= PIPE_BIND_INDEX_BUFFER;
 532       }
 533    }
 534
 535    /* Always allowed */
 536    allowed |=
 537       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 538
 539    if (usage != allowed) {
 540       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 541           "usage=%x, allowed=%x",
 542           util_format_name(format), target, sample_count, usage, allowed);
 543    }
 544
 545    return usage == allowed;
 546 }
 547
 548 static boolean
 549 etna_get_specs(struct etna_screen *screen)
 550 {
 551    uint64_t val;
 552    uint32_t instruction_count;
 553
 554    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 555       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 556       goto fail;
 557    }
 558    instruction_count = val;
 559
 560    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 561                           &val)) {
 562       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 563       goto fail;
 564    }
 565    screen->specs.vertex_output_buffer_size = val;
 566
 567    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 568       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 569       goto fail;
 570    }
 571    screen->specs.vertex_cache_size = val;
 572
 573    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 574       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 575       goto fail;
 576    }
 577    screen->specs.shader_core_count = val;
 578
 579    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 580       DBG("could not get ETNA_GPU_STREAM_COUNT");
 581       goto fail;
 582    }
 583    screen->specs.stream_count = val;
 584
 585    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 586       DBG("could not get ETNA_GPU_REGISTER_MAX");
 587       goto fail;
 588    }
 589    screen->specs.max_registers = val;
 590
 591    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 592       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 593       goto fail;
 594    }
 595    screen->specs.pixel_pipes = val;
 596
 597    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 598       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 599       goto fail;
 600    }
 601    if (val == 0) {
 602       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 603       val = 168;
 604    }
 605    screen->specs.num_constants = val;
 606
 607    screen->specs.can_supertile =
 608       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 609    screen->specs.bits_per_tile =
 610       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 611    screen->specs.ts_clear_value =
 612       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 613                                                            : 0x11111111;
 614
 615    /* vertex and fragment samplers live in one address space */
 616    screen->specs.vertex_sampler_offset = 8;
 617    screen->specs.fragment_sampler_count = 8;
 618    screen->specs.vertex_sampler_count = 4;
 619    screen->specs.vs_need_z_div =
 620       screen->model < 0x1000 && screen->model != 0x880;
 621    screen->specs.has_sin_cos_sqrt =
 622       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 623    screen->specs.has_sign_floor_ceil =
 624       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 625    screen->specs.has_shader_range_registers =
 626       screen->model >= 0x1000 || screen->model == 0x880;
 627    screen->specs.npot_tex_any_wrap =
 628       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 629    screen->specs.has_new_sin_cos =
 630       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 631
 632    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 633       /* GC3000 - this core is capable of loading shaders from
 634        * memory. It can also run shaders from registers, as a fallback, but
 635        * "max_instructions" does not have the correct value. It has place for
 636        * 2*256 instructions just like GC2000, but the offsets are slightly
 637        * different.
 638        */
 639       screen->specs.vs_offset = 0xC000;
 640       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 641        * this mirror for writing PS instructions, probably safest to do the
 642        * same.
 643        */
 644       screen->specs.ps_offset = 0x8000 + 0x1000;
 645       screen->specs.max_instructions = 256;
 646    } else {
 647       if (instruction_count > 256) { /* unified instruction memory? */
 648          screen->specs.vs_offset = 0xC000;
 649          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 650          screen->specs.max_instructions = 256;
 651       } else {
 652          screen->specs.vs_offset = 0x4000;
 653          screen->specs.ps_offset = 0x6000;
 654          screen->specs.max_instructions = instruction_count / 2;
 655       }
 656    }
 657
 658    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 659       screen->specs.max_varyings = 12;
 660       screen->specs.vertex_max_elements = 16;
 661    } else {
 662       screen->specs.max_varyings = 8;
 663       /* Etna_viv documentation seems confused over the correct value
 664        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 665        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 666       screen->specs.vertex_max_elements = 10;
 667    }
 668
 669    /* Etna_viv documentation does not indicate where varyings above 8 are
 670     * stored. Moreover, if we are passed more than 8 varyings, we will
 671     * walk off the end of some arrays. Limit the maximum number of varyings. */
 672    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 673       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 674
 675    /* from QueryShaderCaps in kernel driver */
 676    if (screen->model < chipModel_GC4000) {
 677       screen->specs.max_vs_uniforms = 168;
 678       screen->specs.max_ps_uniforms = 64;
 679    } else {
 680       screen->specs.max_vs_uniforms = 256;
 681       screen->specs.max_ps_uniforms = 256;
 682    }
 683
 684    screen->specs.max_texture_size =
 685       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 686    screen->specs.max_rendertarget_size =
 687       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 688
 689    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 690    if (screen->specs.single_buffer)
 691       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 692
 693    return true;
 694
 695 fail:
 696    return false;
 697 }
 698
 699 boolean
 700 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
 701                           unsigned stride, struct winsys_handle *whandle)
 702 {
 703    whandle->stride = stride;
 704
 705    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 706       return etna_bo_get_name(bo, &whandle->handle) == 0;
 707    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 708       whandle->handle = etna_bo_handle(bo);
 709       return TRUE;
 710    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 711       whandle->handle = etna_bo_dmabuf(bo);
 712       return TRUE;
 713    } else {
 714       return FALSE;
 715    }
 716 }
 717
 718 struct etna_bo *
 719 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 720                            struct winsys_handle *whandle, unsigned *out_stride)
 721 {
 722    struct etna_screen *screen = etna_screen(pscreen);
 723    struct etna_bo *bo;
 724
 725    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 726       bo = etna_bo_from_name(screen->dev, whandle->handle);
 727    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 728       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 729    } else {
 730       DBG("Attempt to import unsupported handle type %d", whandle->type);
 731       return NULL;
 732    }
 733
 734    if (!bo) {
 735       DBG("ref name 0x%08x failed", whandle->handle);
 736       return NULL;
 737    }
 738
 739    *out_stride = whandle->stride;
 740
 741    return bo;
 742 }
 743
 744 struct pipe_screen *
 745 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 746                    struct renderonly *ro)
 747 {
 748    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 749    struct pipe_screen *pscreen;
 750    drmVersionPtr version;
 751    uint64_t val;
 752
 753    if (!screen)
 754       return NULL;
 755
 756    pscreen = &screen->base;
 757    screen->dev = dev;
 758    screen->gpu = gpu;
 759    screen->ro = renderonly_dup(ro);
 760
 761    if (!screen->ro) {
 762       DBG("could not create renderonly object");
 763       goto fail;
 764    }
 765
 766    version = drmGetVersion(screen->ro->gpu_fd);
 767    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 768                                           version->version_minor);
 769    drmFreeVersion(version);
 770
 771    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 772
 773    /* Disable autodisable for correct rendering with TS */
 774    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 775
 776    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 777    if (!screen->pipe) {
 778       DBG("could not create 3d pipe");
 779       goto fail;
 780    }
 781
 782    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 783       DBG("could not get ETNA_GPU_MODEL");
 784       goto fail;
 785    }
 786    screen->model = val;
 787
 788    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 789       DBG("could not get ETNA_GPU_REVISION");
 790       goto fail;
 791    }
 792    screen->revision = val;
 793
 794    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 795       DBG("could not get ETNA_GPU_FEATURES_0");
 796       goto fail;
 797    }
 798    screen->features[0] = val;
 799
 800    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 801       DBG("could not get ETNA_GPU_FEATURES_1");
 802       goto fail;
 803    }
 804    screen->features[1] = val;
 805
 806    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 807       DBG("could not get ETNA_GPU_FEATURES_2");
 808       goto fail;
 809    }
 810    screen->features[2] = val;
 811
 812    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 813       DBG("could not get ETNA_GPU_FEATURES_3");
 814       goto fail;
 815    }
 816    screen->features[3] = val;
 817
 818    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 819       DBG("could not get ETNA_GPU_FEATURES_4");
 820       goto fail;
 821    }
 822    screen->features[4] = val;
 823
 824    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 825       DBG("could not get ETNA_GPU_FEATURES_5");
 826       goto fail;
 827    }
 828    screen->features[5] = val;
 829
 830    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 831       DBG("could not get ETNA_GPU_FEATURES_6");
 832       goto fail;
 833    }
 834    screen->features[6] = val;
 835
 836    if (!etna_get_specs(screen))
 837       goto fail;
 838
 839    /* apply debug options that disable individual features */
 840    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 841       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 842    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 843          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 844    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 845       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 846    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 847       screen->specs.can_supertile = 0;
 848
 849    pscreen->destroy = etna_screen_destroy;
 850    pscreen->get_param = etna_screen_get_param;
 851    pscreen->get_paramf = etna_screen_get_paramf;
 852    pscreen->get_shader_param = etna_screen_get_shader_param;
 853
 854    pscreen->get_name = etna_screen_get_name;
 855    pscreen->get_vendor = etna_screen_get_vendor;
 856    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 857
 858    pscreen->get_timestamp = etna_screen_get_timestamp;
 859    pscreen->context_create = etna_context_create;
 860    pscreen->is_format_supported = etna_screen_is_format_supported;
 861
 862    etna_fence_screen_init(pscreen);
 863    etna_query_screen_init(pscreen);
 864    etna_resource_screen_init(pscreen);
 865
 866    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 867
 868    return pscreen;
 869
 870 fail:
 871    etna_screen_destroy(pscreen);
 872    return NULL;
 873 }