src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 static const struct debug_named_value debug_options[] = {
  49    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  50    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  51    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  52    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  53    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  54    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  55    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  56    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  57    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  58    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  59    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  60    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  61    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  62    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  63    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  64    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  65    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  66    DEBUG_NAMED_VALUE_END
  67 };
  68
  69 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  70 int etna_mesa_debug = 0;
  71
  72 static void
  73 etna_screen_destroy(struct pipe_screen *pscreen)
  74 {
  75    struct etna_screen *screen = etna_screen(pscreen);
  76
  77    if (screen->pipe)
  78       etna_pipe_del(screen->pipe);
  79
  80    if (screen->gpu)
  81       etna_gpu_del(screen->gpu);
  82
  83    if (screen->ro)
  84       FREE(screen->ro);
  85
  86    if (screen->dev)
  87       etna_device_del(screen->dev);
  88
  89    FREE(screen);
  90 }
  91
  92 static const char *
  93 etna_screen_get_name(struct pipe_screen *pscreen)
  94 {
  95    struct etna_screen *priv = etna_screen(pscreen);
  96    static char buffer[128];
  97
  98    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
  99                  priv->revision);
 100
 101    return buffer;
 102 }
 103
 104 static const char *
 105 etna_screen_get_vendor(struct pipe_screen *pscreen)
 106 {
 107    return "etnaviv";
 108 }
 109
 110 static const char *
 111 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 112 {
 113    return "Vivante";
 114 }
 115
 116 static int
 117 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 118 {
 119    struct etna_screen *screen = etna_screen(pscreen);
 120
 121    switch (param) {
 122    /* Supported features (boolean caps). */
 123    case PIPE_CAP_TWO_SIDED_STENCIL:
 124    case PIPE_CAP_ANISOTROPIC_FILTER:
 125    case PIPE_CAP_POINT_SPRITE:
 126    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 127    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 128    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 129    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 130    case PIPE_CAP_SM3:
 131    case PIPE_CAP_TEXTURE_BARRIER:
 132    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 133    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 134    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 135    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 136    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 137    case PIPE_CAP_TGSI_TEXCOORD:
 138    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 139       return 1;
 140
 141    /* Memory */
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 145       return 4; /* XXX could easily be supported */
 146    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 147       return 120;
 148
 149    case PIPE_CAP_NPOT_TEXTURES:
 150       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 151                       NON_POWER_OF_TWO); */
 152
 153    case PIPE_CAP_PRIMITIVE_RESTART:
 154       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 155
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 158                                     ENDIANNESS_CONFIG) */
 159
 160    /* Unsupported features. */
 161    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 162    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
 163    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 164    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 165    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 166    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 167    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 168    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 169    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 170    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 172    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 173    case PIPE_CAP_INDEP_BLEND_ENABLE:
 174    case PIPE_CAP_INDEP_BLEND_FUNC:
 175    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 177    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 178    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 179    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 180    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 181    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 182    case PIPE_CAP_USER_VERTEX_BUFFERS:
 183    case PIPE_CAP_USER_INDEX_BUFFERS:
 184    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 185    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 186    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 187    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 188    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 189    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 190    case PIPE_CAP_TEXTURE_GATHER_SM5:
 191    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 192    case PIPE_CAP_FAKE_SW_MSAA:
 193    case PIPE_CAP_TEXTURE_QUERY_LOD:
 194    case PIPE_CAP_SAMPLE_SHADING:
 195    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 196    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 197    case PIPE_CAP_DRAW_INDIRECT:
 198    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 199    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 200    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 201    case PIPE_CAP_CLIP_HALFZ:
 202    case PIPE_CAP_VERTEXID_NOBASE:
 203    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 204    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 205    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 206    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 207    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 208    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 209    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 210    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 211    case PIPE_CAP_TGSI_TXQS:
 212    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 213    case PIPE_CAP_SHAREABLE_SHADERS:
 214    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 215    case PIPE_CAP_CLEAR_TEXTURE:
 216    case PIPE_CAP_DRAW_PARAMETERS:
 217    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 218    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 219    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 220    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 221    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 222    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 223    case PIPE_CAP_INVALIDATE_BUFFER:
 224    case PIPE_CAP_GENERATE_MIPMAP:
 225    case PIPE_CAP_STRING_MARKER:
 226    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 227    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 228    case PIPE_CAP_QUERY_MEMORY_INFO:
 229    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 230    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 231    case PIPE_CAP_CULL_DISTANCE:
 232    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 233    case PIPE_CAP_TGSI_VOTE:
 234    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 235    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 236    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 237    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 238    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 239    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 240    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 241    case PIPE_CAP_NATIVE_FENCE_FD:
 242    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 243    case PIPE_CAP_TGSI_FS_FBFETCH:
 244    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 245    case PIPE_CAP_DOUBLES:
 246    case PIPE_CAP_INT64:
 247    case PIPE_CAP_INT64_DIVMOD:
 248       return 0;
 249
 250    /* Stream output. */
 251    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 252    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 253    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 254    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 255       return 0;
 256
 257    /* Geometry shader output, unsupported. */
 258    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 259    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 260    case PIPE_CAP_MAX_VERTEX_STREAMS:
 261       return 0;
 262
 263    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 264       return 128;
 265
 266    /* Texturing. */
 267    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 268    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 269    {
 270       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 271       assert(log2_max_tex_size > 0);
 272       return log2_max_tex_size;
 273    }
 274    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 275       return 5;
 276    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 277       return 0;
 278    case PIPE_CAP_CUBE_MAP_ARRAY:
 279       return 0;
 280    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 281    case PIPE_CAP_MIN_TEXEL_OFFSET:
 282       return -8;
 283    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 284    case PIPE_CAP_MAX_TEXEL_OFFSET:
 285       return 7;
 286    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 287       return 0;
 288    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 289       return 65536;
 290
 291    /* Render targets. */
 292    case PIPE_CAP_MAX_RENDER_TARGETS:
 293       return 1;
 294
 295    /* Viewports and scissors. */
 296    case PIPE_CAP_MAX_VIEWPORTS:
 297       return 1;
 298
 299    /* Timer queries. */
 300    case PIPE_CAP_QUERY_TIME_ELAPSED:
 301    case PIPE_CAP_OCCLUSION_QUERY:
 302       return 0;
 303    case PIPE_CAP_QUERY_TIMESTAMP:
 304       return 1;
 305    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 306       return 0;
 307
 308    /* Preferences */
 309    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 310       return 0;
 311
 312    case PIPE_CAP_PCI_GROUP:
 313    case PIPE_CAP_PCI_BUS:
 314    case PIPE_CAP_PCI_DEVICE:
 315    case PIPE_CAP_PCI_FUNCTION:
 316       return 0;
 317    case PIPE_CAP_VENDOR_ID:
 318    case PIPE_CAP_DEVICE_ID:
 319       return 0xFFFFFFFF;
 320    case PIPE_CAP_ACCELERATED:
 321       return 1;
 322    case PIPE_CAP_VIDEO_MEMORY:
 323       return 0;
 324    case PIPE_CAP_UMA:
 325       return 1;
 326    }
 327
 328    debug_printf("unknown param %d", param);
 329    return 0;
 330 }
 331
 332 static float
 333 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 334 {
 335    switch (param) {
 336    case PIPE_CAPF_MAX_LINE_WIDTH:
 337    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 338    case PIPE_CAPF_MAX_POINT_WIDTH:
 339    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 340       return 8192.0f;
 341    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 342       return 16.0f;
 343    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 344       return 16.0f;
 345    case PIPE_CAPF_GUARD_BAND_LEFT:
 346    case PIPE_CAPF_GUARD_BAND_TOP:
 347    case PIPE_CAPF_GUARD_BAND_RIGHT:
 348    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 349       return 0.0f;
 350    }
 351
 352    debug_printf("unknown paramf %d", param);
 353    return 0;
 354 }
 355
 356 static int
 357 etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 358                              enum pipe_shader_cap param)
 359 {
 360    struct etna_screen *screen = etna_screen(pscreen);
 361
 362    switch (shader) {
 363    case PIPE_SHADER_FRAGMENT:
 364    case PIPE_SHADER_VERTEX:
 365       break;
 366    case PIPE_SHADER_COMPUTE:
 367    case PIPE_SHADER_GEOMETRY:
 368    case PIPE_SHADER_TESS_CTRL:
 369    case PIPE_SHADER_TESS_EVAL:
 370       return 0;
 371    default:
 372       DBG("unknown shader type %d", shader);
 373       return 0;
 374    }
 375
 376    switch (param) {
 377    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 378    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 379    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 380    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 381       return ETNA_MAX_TOKENS;
 382    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 383       return ETNA_MAX_DEPTH; /* XXX */
 384    case PIPE_SHADER_CAP_MAX_INPUTS:
 385       /* Maximum number of inputs for the vertex shader is the number
 386        * of vertex elements - each element defines one vertex shader
 387        * input register.  For the fragment shader, this is the number
 388        * of varyings. */
 389       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 390                                             : screen->specs.vertex_max_elements;
 391    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 392       return 16; /* see VIVS_VS_OUTPUT */
 393    case PIPE_SHADER_CAP_MAX_TEMPS:
 394       return 64; /* Max native temporaries. */
 395    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 396       return 1;
 397    case PIPE_SHADER_CAP_MAX_PREDS:
 398       return 0; /* nothing uses this */
 399    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 400       return 1;
 401    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 402    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 403    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 404    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 405       return 1;
 406    case PIPE_SHADER_CAP_SUBROUTINES:
 407       return 0;
 408    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 409       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 410    case PIPE_SHADER_CAP_INTEGERS:
 411       return 0;
 412    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 413    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 414       return shader == PIPE_SHADER_FRAGMENT
 415                 ? screen->specs.fragment_sampler_count
 416                 : screen->specs.vertex_sampler_count;
 417    case PIPE_SHADER_CAP_PREFERRED_IR:
 418       return PIPE_SHADER_IR_TGSI;
 419    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 420       return 4096;
 421    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 422    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 423    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 425       return false;
 426    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 427       return 0;
 428    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 429       return 32;
 430    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 431    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 432    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 433       return 0;
 434    }
 435
 436    debug_printf("unknown shader param %d", param);
 437    return 0;
 438 }
 439
 440 static uint64_t
 441 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 442 {
 443    return os_time_get_nano();
 444 }
 445
 446 static bool
 447 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
 448 {
 449    if (fmt == TEXTURE_FORMAT_ETC1)
 450       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 451
 452    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 453       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 454
 455    return true;
 456 }
 457
 458 static boolean
 459 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 460                                 enum pipe_format format,
 461                                 enum pipe_texture_target target,
 462                                 unsigned sample_count, unsigned usage)
 463 {
 464    struct etna_screen *screen = etna_screen(pscreen);
 465    unsigned allowed = 0;
 466
 467    if (target != PIPE_BUFFER &&
 468        target != PIPE_TEXTURE_1D &&
 469        target != PIPE_TEXTURE_2D &&
 470        target != PIPE_TEXTURE_3D &&
 471        target != PIPE_TEXTURE_CUBE &&
 472        target != PIPE_TEXTURE_RECT)
 473       return FALSE;
 474
 475    if (usage & PIPE_BIND_RENDER_TARGET) {
 476       /* If render target, must be RS-supported format that is not rb swapped.
 477        * Exposing rb swapped (or other swizzled) formats for rendering would
 478        * involve swizzing in the pixel shader.
 479        */
 480       if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) {
 481          /* Validate MSAA; number of samples must be allowed, and render target
 482           * must have MSAA'able format. */
 483          if (sample_count > 1) {
 484             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 485                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 486                allowed |= PIPE_BIND_RENDER_TARGET;
 487             }
 488          } else {
 489             allowed |= PIPE_BIND_RENDER_TARGET;
 490          }
 491       }
 492    }
 493
 494    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 495       if (translate_depth_format(format) != ETNA_NO_MATCH)
 496          allowed |= PIPE_BIND_DEPTH_STENCIL;
 497    }
 498
 499    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 500       uint32_t fmt = translate_texture_format(format);
 501
 502       if (!gpu_supports_texure_format(screen, fmt))
 503          fmt = ETNA_NO_MATCH;
 504
 505       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 506          allowed |= PIPE_BIND_SAMPLER_VIEW;
 507    }
 508
 509    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 510       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 511          allowed |= PIPE_BIND_VERTEX_BUFFER;
 512    }
 513
 514    if (usage & PIPE_BIND_INDEX_BUFFER) {
 515       /* must be supported index format */
 516       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 517           (format == PIPE_FORMAT_I32_UINT &&
 518            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 519          allowed |= PIPE_BIND_INDEX_BUFFER;
 520       }
 521    }
 522
 523    /* Always allowed */
 524    allowed |=
 525       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 526
 527    if (usage != allowed) {
 528       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 529           "usage=%x, allowed=%x",
 530           util_format_name(format), target, sample_count, usage, allowed);
 531    }
 532
 533    return usage == allowed;
 534 }
 535
 536 static boolean
 537 etna_get_specs(struct etna_screen *screen)
 538 {
 539    uint64_t val;
 540    uint32_t instruction_count;
 541
 542    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 543       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 544       goto fail;
 545    }
 546    instruction_count = val;
 547
 548    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 549                           &val)) {
 550       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 551       goto fail;
 552    }
 553    screen->specs.vertex_output_buffer_size = val;
 554
 555    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 556       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 557       goto fail;
 558    }
 559    screen->specs.vertex_cache_size = val;
 560
 561    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 562       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 563       goto fail;
 564    }
 565    screen->specs.shader_core_count = val;
 566
 567    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 568       DBG("could not get ETNA_GPU_STREAM_COUNT");
 569       goto fail;
 570    }
 571    screen->specs.stream_count = val;
 572
 573    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 574       DBG("could not get ETNA_GPU_REGISTER_MAX");
 575       goto fail;
 576    }
 577    screen->specs.max_registers = val;
 578
 579    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 580       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 581       goto fail;
 582    }
 583    if (val < 1 && val > ETNA_MAX_PIXELPIPES) {
 584       if (val == 0) {
 585          fprintf(stderr, "Warning: zero pixel pipes (update kernel?)\n");
 586          val = 1;
 587       } else {
 588          fprintf(stderr, "Error: bad pixel pipes value %u\n",
 589                  (unsigned int)val);
 590          goto fail;
 591       }
 592    }
 593    screen->specs.pixel_pipes = val;
 594
 595    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 596       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 597       goto fail;
 598    }
 599    if (val == 0) {
 600       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 601       val = 168;
 602    }
 603    screen->specs.num_constants = val;
 604
 605    screen->specs.can_supertile =
 606       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 607    screen->specs.bits_per_tile =
 608       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 609    screen->specs.ts_clear_value =
 610       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 611                                                            : 0x11111111;
 612
 613    /* vertex and fragment samplers live in one address space */
 614    screen->specs.vertex_sampler_offset = 8;
 615    screen->specs.fragment_sampler_count = 8;
 616    screen->specs.vertex_sampler_count = 4;
 617    screen->specs.vs_need_z_div =
 618       screen->model < 0x1000 && screen->model != 0x880;
 619    screen->specs.has_sin_cos_sqrt =
 620       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 621    screen->specs.has_sign_floor_ceil =
 622       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 623    screen->specs.has_shader_range_registers =
 624       screen->model >= 0x1000 || screen->model == 0x880;
 625    screen->specs.npot_tex_any_wrap =
 626       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 627    screen->specs.has_new_sin_cos =
 628       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 629
 630    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 631       /* GC3000 - this core is capable of loading shaders from
 632        * memory. It can also run shaders from registers, as a fallback, but
 633        * "max_instructions" does not have the correct value. It has place for
 634        * 2*256 instructions just like GC2000, but the offsets are slightly
 635        * different.
 636        */
 637       screen->specs.vs_offset = 0xC000;
 638       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 639        * this mirror for writing PS instructions, probably safest to do the
 640        * same.
 641        */
 642       screen->specs.ps_offset = 0x8000 + 0x1000;
 643       screen->specs.max_instructions = 256;
 644    } else {
 645       if (instruction_count > 256) { /* unified instruction memory? */
 646          screen->specs.vs_offset = 0xC000;
 647          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 648          screen->specs.max_instructions = 256;
 649       } else {
 650          screen->specs.vs_offset = 0x4000;
 651          screen->specs.ps_offset = 0x6000;
 652          screen->specs.max_instructions = instruction_count / 2;
 653       }
 654    }
 655
 656    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 657       screen->specs.max_varyings = 12;
 658       screen->specs.vertex_max_elements = 16;
 659    } else {
 660       screen->specs.max_varyings = 8;
 661       /* Etna_viv documentation seems confused over the correct value
 662        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 663        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 664       screen->specs.vertex_max_elements = 10;
 665    }
 666
 667    /* Etna_viv documentation does not indicate where varyings above 8 are
 668     * stored. Moreover, if we are passed more than 8 varyings, we will
 669     * walk off the end of some arrays. Limit the maximum number of varyings. */
 670    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 671       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 672
 673    /* from QueryShaderCaps in kernel driver */
 674    if (screen->model < chipModel_GC4000) {
 675       screen->specs.max_vs_uniforms = 168;
 676       screen->specs.max_ps_uniforms = 64;
 677    } else {
 678       screen->specs.max_vs_uniforms = 256;
 679       screen->specs.max_ps_uniforms = 256;
 680    }
 681
 682    screen->specs.max_texture_size =
 683       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 684    screen->specs.max_rendertarget_size =
 685       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 686
 687    return true;
 688
 689 fail:
 690    return false;
 691 }
 692
 693 boolean
 694 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
 695                           unsigned stride, struct winsys_handle *whandle)
 696 {
 697    whandle->stride = stride;
 698
 699    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 700       return etna_bo_get_name(bo, &whandle->handle) == 0;
 701    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 702       whandle->handle = etna_bo_handle(bo);
 703       return TRUE;
 704    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 705       whandle->handle = etna_bo_dmabuf(bo);
 706       return TRUE;
 707    } else {
 708       return FALSE;
 709    }
 710 }
 711
 712 struct etna_bo *
 713 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 714                            struct winsys_handle *whandle, unsigned *out_stride)
 715 {
 716    struct etna_screen *screen = etna_screen(pscreen);
 717    struct etna_bo *bo;
 718
 719    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 720       bo = etna_bo_from_name(screen->dev, whandle->handle);
 721    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 722       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 723    } else {
 724       DBG("Attempt to import unsupported handle type %d", whandle->type);
 725       return NULL;
 726    }
 727
 728    if (!bo) {
 729       DBG("ref name 0x%08x failed", whandle->handle);
 730       return NULL;
 731    }
 732
 733    *out_stride = whandle->stride;
 734
 735    return bo;
 736 }
 737
 738 struct pipe_screen *
 739 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 740                    struct renderonly *ro)
 741 {
 742    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 743    struct pipe_screen *pscreen;
 744    uint64_t val;
 745
 746    if (!screen)
 747       return NULL;
 748
 749    pscreen = &screen->base;
 750    screen->dev = dev;
 751    screen->gpu = gpu;
 752    screen->ro = renderonly_dup(ro);
 753
 754    if (!screen->ro) {
 755       DBG("could not create renderonly object");
 756       goto fail;
 757    }
 758
 759    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 760
 761    /* FIXME: Disable tile status for stability at the moment */
 762    etna_mesa_debug |= ETNA_DBG_NO_TS;
 763
 764    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 765    if (!screen->pipe) {
 766       DBG("could not create 3d pipe");
 767       goto fail;
 768    }
 769
 770    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 771       DBG("could not get ETNA_GPU_MODEL");
 772       goto fail;
 773    }
 774    screen->model = val;
 775
 776    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 777       DBG("could not get ETNA_GPU_REVISION");
 778       goto fail;
 779    }
 780    screen->revision = val;
 781
 782    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 783       DBG("could not get ETNA_GPU_FEATURES_0");
 784       goto fail;
 785    }
 786    screen->features[0] = val;
 787
 788    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 789       DBG("could not get ETNA_GPU_FEATURES_1");
 790       goto fail;
 791    }
 792    screen->features[1] = val;
 793
 794    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 795       DBG("could not get ETNA_GPU_FEATURES_2");
 796       goto fail;
 797    }
 798    screen->features[2] = val;
 799
 800    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 801       DBG("could not get ETNA_GPU_FEATURES_3");
 802       goto fail;
 803    }
 804    screen->features[3] = val;
 805
 806    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 807       DBG("could not get ETNA_GPU_FEATURES_4");
 808       goto fail;
 809    }
 810    screen->features[4] = val;
 811
 812    if (!etna_get_specs(screen))
 813       goto fail;
 814
 815    pscreen->destroy = etna_screen_destroy;
 816    pscreen->get_param = etna_screen_get_param;
 817    pscreen->get_paramf = etna_screen_get_paramf;
 818    pscreen->get_shader_param = etna_screen_get_shader_param;
 819
 820    pscreen->get_name = etna_screen_get_name;
 821    pscreen->get_vendor = etna_screen_get_vendor;
 822    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 823
 824    pscreen->get_timestamp = etna_screen_get_timestamp;
 825    pscreen->context_create = etna_context_create;
 826    pscreen->is_format_supported = etna_screen_is_format_supported;
 827
 828    etna_fence_screen_init(pscreen);
 829    etna_query_screen_init(pscreen);
 830    etna_resource_screen_init(pscreen);
 831
 832    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 833
 834    return pscreen;
 835
 836 fail:
 837    etna_screen_destroy(pscreen);
 838    return NULL;
 839 }