src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_screen.h"
  45 #include "util/u_string.h"
  46
  47 #include "state_tracker/drm_driver.h"
  48
  49 #include <drm_fourcc.h>
  50
  51 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  52 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  53 #define ETNA_DRM_VERSION_PERFMON       ETNA_DRM_VERSION(1, 2)
  54
  55 static const struct debug_named_value debug_options[] = {
  56    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  57    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  58    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  59    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  60    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  61    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  62    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  63    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  64    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  65    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  66    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
  67    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  68    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  69    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  70    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  71    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  72    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  73    {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
  74    DEBUG_NAMED_VALUE_END
  75 };
  76
  77 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  78 int etna_mesa_debug = 0;
  79
  80 static void
  81 etna_screen_destroy(struct pipe_screen *pscreen)
  82 {
  83    struct etna_screen *screen = etna_screen(pscreen);
  84
  85    if (screen->perfmon)
  86       etna_perfmon_del(screen->perfmon);
  87
  88    if (screen->pipe)
  89       etna_pipe_del(screen->pipe);
  90
  91    if (screen->gpu)
  92       etna_gpu_del(screen->gpu);
  93
  94    if (screen->ro)
  95       FREE(screen->ro);
  96
  97    if (screen->dev)
  98       etna_device_del(screen->dev);
  99
 100    FREE(screen);
 101 }
 102
 103 static const char *
 104 etna_screen_get_name(struct pipe_screen *pscreen)
 105 {
 106    struct etna_screen *priv = etna_screen(pscreen);
 107    static char buffer[128];
 108
 109    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 110                  priv->revision);
 111
 112    return buffer;
 113 }
 114
 115 static const char *
 116 etna_screen_get_vendor(struct pipe_screen *pscreen)
 117 {
 118    return "etnaviv";
 119 }
 120
 121 static const char *
 122 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 123 {
 124    return "Vivante";
 125 }
 126
 127 static int
 128 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 129 {
 130    struct etna_screen *screen = etna_screen(pscreen);
 131
 132    switch (param) {
 133    /* Supported features (boolean caps). */
 134    case PIPE_CAP_ANISOTROPIC_FILTER:
 135    case PIPE_CAP_POINT_SPRITE:
 136    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 137    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 138    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 139    case PIPE_CAP_SM3:
 140    case PIPE_CAP_TEXTURE_BARRIER:
 141    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 142    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 143    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 144    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 145    case PIPE_CAP_TGSI_TEXCOORD:
 146    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 147    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 148       return 1;
 149    case PIPE_CAP_NATIVE_FENCE_FD:
 150       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 151
 152    /* Memory */
 153    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 154       return 256;
 155    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 156       return 4; /* XXX could easily be supported */
 157    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 158    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 159       return 120;
 160
 161    case PIPE_CAP_NPOT_TEXTURES:
 162       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 163                       NON_POWER_OF_TWO); */
 164
 165    case PIPE_CAP_TEXTURE_SWIZZLE:
 166    case PIPE_CAP_PRIMITIVE_RESTART:
 167       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 168
 169    case PIPE_CAP_ENDIANNESS:
 170       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 171                                     ENDIANNESS_CONFIG) */
 172
 173    /* Unsupported features. */
 174    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 175    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 176    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 177    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 178    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 179    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 180    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 181    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 182    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 183    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 184    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 185    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: /* only mirrored repeat */
 186    case PIPE_CAP_INDEP_BLEND_ENABLE:
 187    case PIPE_CAP_INDEP_BLEND_FUNC:
 188    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 189    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 190    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 191    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 192    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 193    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 194    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 195    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 196    case PIPE_CAP_USER_VERTEX_BUFFERS:
 197    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 198    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 199    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 200    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 201    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 202    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 203    case PIPE_CAP_TEXTURE_GATHER_SM5:
 204    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 205    case PIPE_CAP_FAKE_SW_MSAA:
 206    case PIPE_CAP_TEXTURE_QUERY_LOD:
 207    case PIPE_CAP_SAMPLE_SHADING:
 208    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 209    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 210    case PIPE_CAP_DRAW_INDIRECT:
 211    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 212    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 213    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 214    case PIPE_CAP_CLIP_HALFZ:
 215    case PIPE_CAP_VERTEXID_NOBASE:
 216    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 217    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 218    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 219    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 220    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 221    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 222    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 223    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 224    case PIPE_CAP_TGSI_TXQS:
 225    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 226    case PIPE_CAP_SHAREABLE_SHADERS:
 227    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 228    case PIPE_CAP_CLEAR_TEXTURE:
 229    case PIPE_CAP_DRAW_PARAMETERS:
 230    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 231    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 232    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 233    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 234    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 235    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 236    case PIPE_CAP_INVALIDATE_BUFFER:
 237    case PIPE_CAP_GENERATE_MIPMAP:
 238    case PIPE_CAP_STRING_MARKER:
 239    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 240    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 241    case PIPE_CAP_QUERY_MEMORY_INFO:
 242    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 243    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 244    case PIPE_CAP_CULL_DISTANCE:
 245    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 246    case PIPE_CAP_TGSI_VOTE:
 247    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 248    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 249    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 250    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 251    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 252    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 253    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 254    case PIPE_CAP_TGSI_FS_FBFETCH:
 255    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 256    case PIPE_CAP_DOUBLES:
 257    case PIPE_CAP_INT64:
 258    case PIPE_CAP_INT64_DIVMOD:
 259    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 260    case PIPE_CAP_TGSI_CLOCK:
 261    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 262    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 263    case PIPE_CAP_TGSI_BALLOT:
 264    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 265    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 266    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 267    case PIPE_CAP_POST_DEPTH_COVERAGE:
 268    case PIPE_CAP_BINDLESS_TEXTURE:
 269    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 270    case PIPE_CAP_QUERY_SO_OVERFLOW:
 271    case PIPE_CAP_MEMOBJ:
 272    case PIPE_CAP_LOAD_CONSTBUF:
 273    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 274    case PIPE_CAP_TILE_RASTER_ORDER:
 275    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 276    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 277    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 278    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 279    case PIPE_CAP_FENCE_SIGNAL:
 280    case PIPE_CAP_CONSTBUF0_FLAGS:
 281    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 282    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 283    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 284    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 285    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 286    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 287    case PIPE_CAP_PACKED_UNIFORMS:
 288    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 289    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
 290       return 0;
 291
 292    case PIPE_CAP_MAX_GS_INVOCATIONS:
 293       return 32;
 294
 295    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 296       return 1 << 27;
 297
 298    /* Stream output. */
 299    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 300    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 301    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 303       return 0;
 304
 305    /* Geometry shader output, unsupported. */
 306    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 307    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 308    case PIPE_CAP_MAX_VERTEX_STREAMS:
 309       return 0;
 310
 311    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 312       return 128;
 313    case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 314       return 255;
 315
 316    /* Texturing. */
 317    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 318    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 319    {
 320       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 321       assert(log2_max_tex_size > 0);
 322       return log2_max_tex_size;
 323    }
 324    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 325       return 5;
 326    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 327       return 0;
 328    case PIPE_CAP_CUBE_MAP_ARRAY:
 329       return 0;
 330    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 331    case PIPE_CAP_MIN_TEXEL_OFFSET:
 332       return -8;
 333    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 334    case PIPE_CAP_MAX_TEXEL_OFFSET:
 335       return 7;
 336    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 337       return 0;
 338    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 339       return 65536;
 340
 341    /* Render targets. */
 342    case PIPE_CAP_MAX_RENDER_TARGETS:
 343       return 1;
 344
 345    /* Viewports and scissors. */
 346    case PIPE_CAP_MAX_VIEWPORTS:
 347       return 1;
 348
 349    /* Timer queries. */
 350    case PIPE_CAP_QUERY_TIME_ELAPSED:
 351       return 0;
 352    case PIPE_CAP_OCCLUSION_QUERY:
 353       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 354    case PIPE_CAP_QUERY_TIMESTAMP:
 355       return 1;
 356    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357       return 0;
 358
 359    /* Preferences */
 360    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 361       return 0;
 362
 363    case PIPE_CAP_MAX_VARYINGS:
 364       return screen->specs.max_varyings;
 365
 366    case PIPE_CAP_PCI_GROUP:
 367    case PIPE_CAP_PCI_BUS:
 368    case PIPE_CAP_PCI_DEVICE:
 369    case PIPE_CAP_PCI_FUNCTION:
 370       return 0;
 371    case PIPE_CAP_VENDOR_ID:
 372    case PIPE_CAP_DEVICE_ID:
 373       return 0xFFFFFFFF;
 374    case PIPE_CAP_ACCELERATED:
 375       return 1;
 376    case PIPE_CAP_VIDEO_MEMORY:
 377       return 0;
 378    case PIPE_CAP_UMA:
 379       return 1;
 380    default:
 381       return u_pipe_screen_get_param_defaults(pscreen, param);
 382    }
 383 }
 384
 385 static float
 386 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 387 {
 388    struct etna_screen *screen = etna_screen(pscreen);
 389
 390    switch (param) {
 391    case PIPE_CAPF_MAX_LINE_WIDTH:
 392    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 393    case PIPE_CAPF_MAX_POINT_WIDTH:
 394    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 395       return 8192.0f;
 396    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 397       return 16.0f;
 398    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 399       return util_last_bit(screen->specs.max_texture_size);
 400    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 401    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 402    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 403       return 0.0f;
 404    }
 405
 406    debug_printf("unknown paramf %d", param);
 407    return 0;
 408 }
 409
 410 static int
 411 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 412                              enum pipe_shader_type shader,
 413                              enum pipe_shader_cap param)
 414 {
 415    struct etna_screen *screen = etna_screen(pscreen);
 416
 417    switch (shader) {
 418    case PIPE_SHADER_FRAGMENT:
 419    case PIPE_SHADER_VERTEX:
 420       break;
 421    case PIPE_SHADER_COMPUTE:
 422    case PIPE_SHADER_GEOMETRY:
 423    case PIPE_SHADER_TESS_CTRL:
 424    case PIPE_SHADER_TESS_EVAL:
 425       return 0;
 426    default:
 427       DBG("unknown shader type %d", shader);
 428       return 0;
 429    }
 430
 431    switch (param) {
 432    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 433    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 434    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 435    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 436       return ETNA_MAX_TOKENS;
 437    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 438       return ETNA_MAX_DEPTH; /* XXX */
 439    case PIPE_SHADER_CAP_MAX_INPUTS:
 440       /* Maximum number of inputs for the vertex shader is the number
 441        * of vertex elements - each element defines one vertex shader
 442        * input register.  For the fragment shader, this is the number
 443        * of varyings. */
 444       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 445                                             : screen->specs.vertex_max_elements;
 446    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 447       return 16; /* see VIVS_VS_OUTPUT */
 448    case PIPE_SHADER_CAP_MAX_TEMPS:
 449       return 64; /* Max native temporaries. */
 450    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 451       return 1;
 452    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 453       return 1;
 454    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 455    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 456    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 457    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 458       return 1;
 459    case PIPE_SHADER_CAP_SUBROUTINES:
 460       return 0;
 461    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 462       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 463    case PIPE_SHADER_CAP_INTEGERS:
 464    case PIPE_SHADER_CAP_INT64_ATOMICS:
 465    case PIPE_SHADER_CAP_FP16:
 466       return 0;
 467    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 468    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 469       return shader == PIPE_SHADER_FRAGMENT
 470                 ? screen->specs.fragment_sampler_count
 471                 : screen->specs.vertex_sampler_count;
 472    case PIPE_SHADER_CAP_PREFERRED_IR:
 473       return PIPE_SHADER_IR_TGSI;
 474    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 475       return 4096;
 476    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 477    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 478    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 479    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 480    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 481       return false;
 482    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 483       return 0;
 484    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 485       return 32;
 486    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 487    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 488    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 489    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 490    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 491    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 492    case PIPE_SHADER_CAP_SCALAR_ISA:
 493       return 0;
 494    }
 495
 496    debug_printf("unknown shader param %d", param);
 497    return 0;
 498 }
 499
 500 static uint64_t
 501 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 502 {
 503    return os_time_get_nano();
 504 }
 505
 506 static bool
 507 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 508                            enum pipe_format format)
 509 {
 510    bool supported = true;
 511
 512    if (fmt == TEXTURE_FORMAT_ETC1)
 513       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 514
 515    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 516       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 517
 518    if (util_format_is_srgb(format))
 519       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 520
 521    if (fmt & EXT_FORMAT) {
 522       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 523
 524       /* ETC1 is checked above, as it has its own feature bit. ETC2 is
 525        * supported with HALTI0, however that implementation is buggy in hardware.
 526        * The blob driver does per-block patching to work around this. As this
 527        * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
 528        * only.
 529        */
 530       if (util_format_is_etc(format))
 531          supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
 532    }
 533
 534    if (fmt & ASTC_FORMAT) {
 535       supported = screen->specs.tex_astc;
 536    }
 537
 538    if (!supported)
 539       return false;
 540
 541    if (texture_format_needs_swiz(format))
 542       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 543
 544    return true;
 545 }
 546
 547 static boolean
 548 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 549                                 enum pipe_format format,
 550                                 enum pipe_texture_target target,
 551                                 unsigned sample_count,
 552                                 unsigned storage_sample_count,
 553                                 unsigned usage)
 554 {
 555    struct etna_screen *screen = etna_screen(pscreen);
 556    unsigned allowed = 0;
 557
 558    if (target != PIPE_BUFFER &&
 559        target != PIPE_TEXTURE_1D &&
 560        target != PIPE_TEXTURE_2D &&
 561        target != PIPE_TEXTURE_3D &&
 562        target != PIPE_TEXTURE_CUBE &&
 563        target != PIPE_TEXTURE_RECT)
 564       return FALSE;
 565
 566    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
 567       return false;
 568
 569    if (usage & PIPE_BIND_RENDER_TARGET) {
 570       /* if render target, must be RS-supported format */
 571       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 572          /* Validate MSAA; number of samples must be allowed, and render target
 573           * must have MSAA'able format. */
 574          if (sample_count > 1) {
 575             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 576                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 577                allowed |= PIPE_BIND_RENDER_TARGET;
 578             }
 579          } else {
 580             allowed |= PIPE_BIND_RENDER_TARGET;
 581          }
 582       }
 583    }
 584
 585    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 586       if (translate_depth_format(format) != ETNA_NO_MATCH)
 587          allowed |= PIPE_BIND_DEPTH_STENCIL;
 588    }
 589
 590    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 591       uint32_t fmt = translate_texture_format(format);
 592
 593       if (!gpu_supports_texure_format(screen, fmt, format))
 594          fmt = ETNA_NO_MATCH;
 595
 596       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 597          allowed |= PIPE_BIND_SAMPLER_VIEW;
 598    }
 599
 600    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 601       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 602          allowed |= PIPE_BIND_VERTEX_BUFFER;
 603    }
 604
 605    if (usage & PIPE_BIND_INDEX_BUFFER) {
 606       /* must be supported index format */
 607       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 608           (format == PIPE_FORMAT_I32_UINT &&
 609            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 610          allowed |= PIPE_BIND_INDEX_BUFFER;
 611       }
 612    }
 613
 614    /* Always allowed */
 615    allowed |=
 616       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 617
 618    if (usage != allowed) {
 619       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 620           "usage=%x, allowed=%x",
 621           util_format_name(format), target, sample_count, usage, allowed);
 622    }
 623
 624    return usage == allowed;
 625 }
 626
 627 const uint64_t supported_modifiers[] = {
 628    DRM_FORMAT_MOD_LINEAR,
 629    DRM_FORMAT_MOD_VIVANTE_TILED,
 630    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 631    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 632    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 633 };
 634
 635 static void
 636 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 637                                    enum pipe_format format, int max,
 638                                    uint64_t *modifiers,
 639                                    unsigned int *external_only, int *count)
 640 {
 641    struct etna_screen *screen = etna_screen(pscreen);
 642    int i, num_modifiers = 0;
 643
 644    if (max > ARRAY_SIZE(supported_modifiers))
 645       max = ARRAY_SIZE(supported_modifiers);
 646
 647    if (!max) {
 648       modifiers = NULL;
 649       max = ARRAY_SIZE(supported_modifiers);
 650    }
 651
 652    for (i = 0; num_modifiers < max; i++) {
 653       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 654       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 655           i >= 3)
 656          break;
 657
 658       if (modifiers)
 659          modifiers[num_modifiers] = supported_modifiers[i];
 660       if (external_only)
 661          external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
 662       num_modifiers++;
 663    }
 664
 665    *count = num_modifiers;
 666 }
 667
 668 static boolean
 669 etna_get_specs(struct etna_screen *screen)
 670 {
 671    uint64_t val;
 672    uint32_t instruction_count;
 673
 674    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 675       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 676       goto fail;
 677    }
 678    instruction_count = val;
 679
 680    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 681                           &val)) {
 682       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 683       goto fail;
 684    }
 685    screen->specs.vertex_output_buffer_size = val;
 686
 687    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 688       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 689       goto fail;
 690    }
 691    screen->specs.vertex_cache_size = val;
 692
 693    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 694       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 695       goto fail;
 696    }
 697    screen->specs.shader_core_count = val;
 698
 699    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 700       DBG("could not get ETNA_GPU_STREAM_COUNT");
 701       goto fail;
 702    }
 703    screen->specs.stream_count = val;
 704
 705    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 706       DBG("could not get ETNA_GPU_REGISTER_MAX");
 707       goto fail;
 708    }
 709    screen->specs.max_registers = val;
 710
 711    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 712       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 713       goto fail;
 714    }
 715    screen->specs.pixel_pipes = val;
 716
 717    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 718       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 719       goto fail;
 720    }
 721    if (val == 0) {
 722       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 723       val = 168;
 724    }
 725    screen->specs.num_constants = val;
 726
 727    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 728     * description of the differences. */
 729    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 730       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 731    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 732       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 733    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 734       screen->specs.halti = 3; /* None? */
 735    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 736       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 737    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 738       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 739    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 740       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 741    else
 742       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 743    if (screen->specs.halti >= 0)
 744       DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
 745    else
 746       DBG("etnaviv: GPU arch: pre-HALTI");
 747
 748    screen->specs.can_supertile =
 749       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 750    screen->specs.bits_per_tile =
 751       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 752    screen->specs.ts_clear_value =
 753       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 754                                                            : 0x11111111;
 755
 756    /* vertex and fragment samplers live in one address space */
 757    screen->specs.vertex_sampler_offset = 8;
 758    screen->specs.fragment_sampler_count = 8;
 759    screen->specs.vertex_sampler_count = 4;
 760    screen->specs.vs_need_z_div =
 761       screen->model < 0x1000 && screen->model != 0x880;
 762    screen->specs.has_sin_cos_sqrt =
 763       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 764    screen->specs.has_sign_floor_ceil =
 765       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 766    screen->specs.has_shader_range_registers =
 767       screen->model >= 0x1000 || screen->model == 0x880;
 768    screen->specs.npot_tex_any_wrap =
 769       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 770    screen->specs.has_new_transcendentals =
 771       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 772    screen->specs.has_halti2_instructions =
 773       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 774
 775    if (screen->specs.halti >= 5) {
 776       /* GC7000 - this core must load shaders from memory. */
 777       screen->specs.vs_offset = 0;
 778       screen->specs.ps_offset = 0;
 779       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 780       screen->specs.has_icache = true;
 781    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 782       /* GC3000 - this core is capable of loading shaders from
 783        * memory. It can also run shaders from registers, as a fallback, but
 784        * "max_instructions" does not have the correct value. It has place for
 785        * 2*256 instructions just like GC2000, but the offsets are slightly
 786        * different.
 787        */
 788       screen->specs.vs_offset = 0xC000;
 789       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 790        * this mirror for writing PS instructions, probably safest to do the
 791        * same.
 792        */
 793       screen->specs.ps_offset = 0x8000 + 0x1000;
 794       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 795       screen->specs.has_icache = true;
 796    } else {
 797       if (instruction_count > 256) { /* unified instruction memory? */
 798          screen->specs.vs_offset = 0xC000;
 799          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 800          screen->specs.max_instructions = 256;
 801       } else {
 802          screen->specs.vs_offset = 0x4000;
 803          screen->specs.ps_offset = 0x6000;
 804          screen->specs.max_instructions = instruction_count / 2;
 805       }
 806       screen->specs.has_icache = false;
 807    }
 808
 809    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 810       screen->specs.max_varyings = 12;
 811       screen->specs.vertex_max_elements = 16;
 812    } else {
 813       screen->specs.max_varyings = 8;
 814       /* Etna_viv documentation seems confused over the correct value
 815        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 816        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 817       screen->specs.vertex_max_elements = 10;
 818    }
 819
 820    /* Etna_viv documentation does not indicate where varyings above 8 are
 821     * stored. Moreover, if we are passed more than 8 varyings, we will
 822     * walk off the end of some arrays. Limit the maximum number of varyings. */
 823    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 824       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 825
 826    /* from QueryShaderCaps in kernel driver */
 827    if (screen->model < chipModel_GC4000) {
 828       screen->specs.max_vs_uniforms = 168;
 829       screen->specs.max_ps_uniforms = 64;
 830    } else {
 831       screen->specs.max_vs_uniforms = 256;
 832       screen->specs.max_ps_uniforms = 256;
 833    }
 834
 835    if (screen->specs.halti >= 5) {
 836       screen->specs.has_unified_uniforms = true;
 837       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 838       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 839    } else if (screen->specs.halti >= 1) {
 840       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 841       */
 842       screen->specs.has_unified_uniforms = true;
 843       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 844       /* hardcode PS uniforms to start after end of VS uniforms -
 845        * for more flexibility this offset could be variable based on the
 846        * shader.
 847        */
 848       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 849    } else {
 850       screen->specs.has_unified_uniforms = false;
 851       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 852       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 853    }
 854
 855    screen->specs.max_texture_size =
 856       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 857    screen->specs.max_rendertarget_size =
 858       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 859
 860    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 861    if (screen->specs.single_buffer)
 862       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
 863
 864    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 865
 866    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 867
 868    return true;
 869
 870 fail:
 871    return false;
 872 }
 873
 874 struct etna_bo *
 875 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 876                            struct winsys_handle *whandle, unsigned *out_stride)
 877 {
 878    struct etna_screen *screen = etna_screen(pscreen);
 879    struct etna_bo *bo;
 880
 881    if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 882       bo = etna_bo_from_name(screen->dev, whandle->handle);
 883    } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 884       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 885    } else {
 886       DBG("Attempt to import unsupported handle type %d", whandle->type);
 887       return NULL;
 888    }
 889
 890    if (!bo) {
 891       DBG("ref name 0x%08x failed", whandle->handle);
 892       return NULL;
 893    }
 894
 895    *out_stride = whandle->stride;
 896
 897    return bo;
 898 }
 899
 900 struct pipe_screen *
 901 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 902                    struct renderonly *ro)
 903 {
 904    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 905    struct pipe_screen *pscreen;
 906    drmVersionPtr version;
 907    uint64_t val;
 908
 909    if (!screen)
 910       return NULL;
 911
 912    pscreen = &screen->base;
 913    screen->dev = dev;
 914    screen->gpu = gpu;
 915    screen->ro = renderonly_dup(ro);
 916    screen->refcnt = 1;
 917
 918    if (!screen->ro) {
 919       DBG("could not create renderonly object");
 920       goto fail;
 921    }
 922
 923    version = drmGetVersion(screen->ro->gpu_fd);
 924    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 925                                           version->version_minor);
 926    drmFreeVersion(version);
 927
 928    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 929
 930    /* Disable autodisable for correct rendering with TS */
 931    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 932
 933    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 934    if (!screen->pipe) {
 935       DBG("could not create 3d pipe");
 936       goto fail;
 937    }
 938
 939    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 940       DBG("could not get ETNA_GPU_MODEL");
 941       goto fail;
 942    }
 943    screen->model = val;
 944
 945    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 946       DBG("could not get ETNA_GPU_REVISION");
 947       goto fail;
 948    }
 949    screen->revision = val;
 950
 951    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 952       DBG("could not get ETNA_GPU_FEATURES_0");
 953       goto fail;
 954    }
 955    screen->features[0] = val;
 956
 957    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 958       DBG("could not get ETNA_GPU_FEATURES_1");
 959       goto fail;
 960    }
 961    screen->features[1] = val;
 962
 963    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 964       DBG("could not get ETNA_GPU_FEATURES_2");
 965       goto fail;
 966    }
 967    screen->features[2] = val;
 968
 969    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 970       DBG("could not get ETNA_GPU_FEATURES_3");
 971       goto fail;
 972    }
 973    screen->features[3] = val;
 974
 975    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 976       DBG("could not get ETNA_GPU_FEATURES_4");
 977       goto fail;
 978    }
 979    screen->features[4] = val;
 980
 981    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 982       DBG("could not get ETNA_GPU_FEATURES_5");
 983       goto fail;
 984    }
 985    screen->features[5] = val;
 986
 987    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 988       DBG("could not get ETNA_GPU_FEATURES_6");
 989       goto fail;
 990    }
 991    screen->features[6] = val;
 992
 993    if (!etna_get_specs(screen))
 994       goto fail;
 995
 996    /* apply debug options that disable individual features */
 997    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 998       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 999    if (DBG_ENABLED(ETNA_DBG_NO_TS))
1000          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
1001    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
1002       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
1003    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
1004       screen->specs.can_supertile = 0;
1005    if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
1006       screen->specs.single_buffer = 0;
1007
1008    pscreen->destroy = etna_screen_destroy;
1009    pscreen->get_param = etna_screen_get_param;
1010    pscreen->get_paramf = etna_screen_get_paramf;
1011    pscreen->get_shader_param = etna_screen_get_shader_param;
1012
1013    pscreen->get_name = etna_screen_get_name;
1014    pscreen->get_vendor = etna_screen_get_vendor;
1015    pscreen->get_device_vendor = etna_screen_get_device_vendor;
1016
1017    pscreen->get_timestamp = etna_screen_get_timestamp;
1018    pscreen->context_create = etna_context_create;
1019    pscreen->is_format_supported = etna_screen_is_format_supported;
1020    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
1021
1022    etna_fence_screen_init(pscreen);
1023    etna_query_screen_init(pscreen);
1024    etna_resource_screen_init(pscreen);
1025
1026    util_dynarray_init(&screen->supported_pm_queries, NULL);
1027    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
1028
1029    if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
1030       etna_pm_query_setup(screen);
1031
1032    return pscreen;
1033
1034 fail:
1035    etna_screen_destroy(pscreen);
1036    return NULL;
1037 }