src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #include <drm_fourcc.h>
  49
  50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  51 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  52
  53 static const struct debug_named_value debug_options[] = {
  54    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  55    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  56    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  57    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  58    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  59    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  60    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  61    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  62    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  63    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  64    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  65    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  66    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  67    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  68    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  69    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  70    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  71    {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
  72    DEBUG_NAMED_VALUE_END
  73 };
  74
  75 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  76 int etna_mesa_debug = 0;
  77
  78 static void
  79 etna_screen_destroy(struct pipe_screen *pscreen)
  80 {
  81    struct etna_screen *screen = etna_screen(pscreen);
  82
  83    if (screen->pipe)
  84       etna_pipe_del(screen->pipe);
  85
  86    if (screen->gpu)
  87       etna_gpu_del(screen->gpu);
  88
  89    if (screen->ro)
  90       FREE(screen->ro);
  91
  92    if (screen->dev)
  93       etna_device_del(screen->dev);
  94
  95    FREE(screen);
  96 }
  97
  98 static const char *
  99 etna_screen_get_name(struct pipe_screen *pscreen)
 100 {
 101    struct etna_screen *priv = etna_screen(pscreen);
 102    static char buffer[128];
 103
 104    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 105                  priv->revision);
 106
 107    return buffer;
 108 }
 109
 110 static const char *
 111 etna_screen_get_vendor(struct pipe_screen *pscreen)
 112 {
 113    return "etnaviv";
 114 }
 115
 116 static const char *
 117 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 118 {
 119    return "Vivante";
 120 }
 121
 122 static int
 123 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 124 {
 125    struct etna_screen *screen = etna_screen(pscreen);
 126
 127    switch (param) {
 128    /* Supported features (boolean caps). */
 129    case PIPE_CAP_ANISOTROPIC_FILTER:
 130    case PIPE_CAP_POINT_SPRITE:
 131    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 132    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 133    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 134    case PIPE_CAP_SM3:
 135    case PIPE_CAP_TEXTURE_BARRIER:
 136    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 137    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 140    case PIPE_CAP_TGSI_TEXCOORD:
 141    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 142       return 1;
 143    case PIPE_CAP_NATIVE_FENCE_FD:
 144       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 145
 146    /* Memory */
 147    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148       return 256;
 149    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 150       return 4; /* XXX could easily be supported */
 151    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 152       return 120;
 153
 154    case PIPE_CAP_NPOT_TEXTURES:
 155       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 156                       NON_POWER_OF_TWO); */
 157
 158    case PIPE_CAP_TEXTURE_SWIZZLE:
 159    case PIPE_CAP_PRIMITIVE_RESTART:
 160       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 161
 162    case PIPE_CAP_ENDIANNESS:
 163       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 164                                     ENDIANNESS_CONFIG) */
 165
 166    /* Unsupported features. */
 167    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 168    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 169    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 170    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 171    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 172    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 173    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 174    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 175    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 176    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 177    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 178    case PIPE_CAP_INDEP_BLEND_ENABLE:
 179    case PIPE_CAP_INDEP_BLEND_FUNC:
 180    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 181    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 182    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 183    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 184    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 185    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 186    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 187    case PIPE_CAP_USER_VERTEX_BUFFERS:
 188    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 189    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 190    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 191    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 192    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 193    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 194    case PIPE_CAP_TEXTURE_GATHER_SM5:
 195    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 196    case PIPE_CAP_FAKE_SW_MSAA:
 197    case PIPE_CAP_TEXTURE_QUERY_LOD:
 198    case PIPE_CAP_SAMPLE_SHADING:
 199    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 200    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 201    case PIPE_CAP_DRAW_INDIRECT:
 202    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 203    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 204    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 205    case PIPE_CAP_CLIP_HALFZ:
 206    case PIPE_CAP_VERTEXID_NOBASE:
 207    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 208    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 209    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 210    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 211    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 212    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 213    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 214    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 215    case PIPE_CAP_TGSI_TXQS:
 216    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 217    case PIPE_CAP_SHAREABLE_SHADERS:
 218    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 219    case PIPE_CAP_CLEAR_TEXTURE:
 220    case PIPE_CAP_DRAW_PARAMETERS:
 221    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 222    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 223    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 224    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 225    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 226    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 227    case PIPE_CAP_INVALIDATE_BUFFER:
 228    case PIPE_CAP_GENERATE_MIPMAP:
 229    case PIPE_CAP_STRING_MARKER:
 230    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 231    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 232    case PIPE_CAP_QUERY_MEMORY_INFO:
 233    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 234    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 235    case PIPE_CAP_CULL_DISTANCE:
 236    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 237    case PIPE_CAP_TGSI_VOTE:
 238    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 239    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 240    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 241    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 242    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 243    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 244    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 245    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 246    case PIPE_CAP_TGSI_FS_FBFETCH:
 247    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 248    case PIPE_CAP_DOUBLES:
 249    case PIPE_CAP_INT64:
 250    case PIPE_CAP_INT64_DIVMOD:
 251    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 252    case PIPE_CAP_TGSI_CLOCK:
 253    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 254    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 255    case PIPE_CAP_TGSI_BALLOT:
 256    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 257    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 258    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 259    case PIPE_CAP_POST_DEPTH_COVERAGE:
 260    case PIPE_CAP_BINDLESS_TEXTURE:
 261    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 262    case PIPE_CAP_QUERY_SO_OVERFLOW:
 263    case PIPE_CAP_MEMOBJ:
 264    case PIPE_CAP_LOAD_CONSTBUF:
 265    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 266    case PIPE_CAP_TILE_RASTER_ORDER:
 267    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 268    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 269    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 270    case PIPE_CAP_FENCE_SIGNAL:
 271    case PIPE_CAP_CONSTBUF0_FLAGS:
 272       return 0;
 273
 274    /* Stream output. */
 275    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 276    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 277    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 278    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 279       return 0;
 280
 281    /* Geometry shader output, unsupported. */
 282    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 283    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 284    case PIPE_CAP_MAX_VERTEX_STREAMS:
 285       return 0;
 286
 287    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 288       return 128;
 289
 290    /* Texturing. */
 291    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 292    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 293    {
 294       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 295       assert(log2_max_tex_size > 0);
 296       return log2_max_tex_size;
 297    }
 298    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 299       return 5;
 300    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 301       return 0;
 302    case PIPE_CAP_CUBE_MAP_ARRAY:
 303       return 0;
 304    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 305    case PIPE_CAP_MIN_TEXEL_OFFSET:
 306       return -8;
 307    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 308    case PIPE_CAP_MAX_TEXEL_OFFSET:
 309       return 7;
 310    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 311       return 0;
 312    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 313       return 65536;
 314
 315    /* Render targets. */
 316    case PIPE_CAP_MAX_RENDER_TARGETS:
 317       return 1;
 318
 319    /* Viewports and scissors. */
 320    case PIPE_CAP_MAX_VIEWPORTS:
 321       return 1;
 322
 323    /* Timer queries. */
 324    case PIPE_CAP_QUERY_TIME_ELAPSED:
 325       return 0;
 326    case PIPE_CAP_OCCLUSION_QUERY:
 327       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 328    case PIPE_CAP_QUERY_TIMESTAMP:
 329       return 1;
 330    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 331       return 0;
 332
 333    /* Preferences */
 334    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 335       return 0;
 336
 337    case PIPE_CAP_PCI_GROUP:
 338    case PIPE_CAP_PCI_BUS:
 339    case PIPE_CAP_PCI_DEVICE:
 340    case PIPE_CAP_PCI_FUNCTION:
 341       return 0;
 342    case PIPE_CAP_VENDOR_ID:
 343    case PIPE_CAP_DEVICE_ID:
 344       return 0xFFFFFFFF;
 345    case PIPE_CAP_ACCELERATED:
 346       return 1;
 347    case PIPE_CAP_VIDEO_MEMORY:
 348       return 0;
 349    case PIPE_CAP_UMA:
 350       return 1;
 351    }
 352
 353    debug_printf("unknown param %d", param);
 354    return 0;
 355 }
 356
 357 static float
 358 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 359 {
 360    struct etna_screen *screen = etna_screen(pscreen);
 361
 362    switch (param) {
 363    case PIPE_CAPF_MAX_LINE_WIDTH:
 364    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 365    case PIPE_CAPF_MAX_POINT_WIDTH:
 366    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 367       return 8192.0f;
 368    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 369       return 16.0f;
 370    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 371       return util_last_bit(screen->specs.max_texture_size);
 372    }
 373
 374    debug_printf("unknown paramf %d", param);
 375    return 0;
 376 }
 377
 378 static int
 379 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 380                              enum pipe_shader_type shader,
 381                              enum pipe_shader_cap param)
 382 {
 383    struct etna_screen *screen = etna_screen(pscreen);
 384
 385    switch (shader) {
 386    case PIPE_SHADER_FRAGMENT:
 387    case PIPE_SHADER_VERTEX:
 388       break;
 389    case PIPE_SHADER_COMPUTE:
 390    case PIPE_SHADER_GEOMETRY:
 391    case PIPE_SHADER_TESS_CTRL:
 392    case PIPE_SHADER_TESS_EVAL:
 393       return 0;
 394    default:
 395       DBG("unknown shader type %d", shader);
 396       return 0;
 397    }
 398
 399    switch (param) {
 400    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 401    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 402    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 403    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 404       return ETNA_MAX_TOKENS;
 405    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 406       return ETNA_MAX_DEPTH; /* XXX */
 407    case PIPE_SHADER_CAP_MAX_INPUTS:
 408       /* Maximum number of inputs for the vertex shader is the number
 409        * of vertex elements - each element defines one vertex shader
 410        * input register.  For the fragment shader, this is the number
 411        * of varyings. */
 412       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 413                                             : screen->specs.vertex_max_elements;
 414    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 415       return 16; /* see VIVS_VS_OUTPUT */
 416    case PIPE_SHADER_CAP_MAX_TEMPS:
 417       return 64; /* Max native temporaries. */
 418    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 419       return 1;
 420    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 421       return 1;
 422    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 423    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 424    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 425    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 426       return 1;
 427    case PIPE_SHADER_CAP_SUBROUTINES:
 428       return 0;
 429    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 430       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 431    case PIPE_SHADER_CAP_INTEGERS:
 432    case PIPE_SHADER_CAP_INT64_ATOMICS:
 433    case PIPE_SHADER_CAP_FP16:
 434       return 0;
 435    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 436    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 437       return shader == PIPE_SHADER_FRAGMENT
 438                 ? screen->specs.fragment_sampler_count
 439                 : screen->specs.vertex_sampler_count;
 440    case PIPE_SHADER_CAP_PREFERRED_IR:
 441       return PIPE_SHADER_IR_TGSI;
 442    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 443       return 4096;
 444    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 445    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 446    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 447    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 448    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 449       return false;
 450    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 451       return 0;
 452    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 453       return 32;
 454    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 455    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 456    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 457    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 458    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 459    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 460       return 0;
 461    }
 462
 463    debug_printf("unknown shader param %d", param);
 464    return 0;
 465 }
 466
 467 static uint64_t
 468 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 469 {
 470    return os_time_get_nano();
 471 }
 472
 473 static bool
 474 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 475                            enum pipe_format format)
 476 {
 477    bool supported = true;
 478
 479    if (fmt == TEXTURE_FORMAT_ETC1)
 480       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 481
 482    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 483       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 484
 485    if (util_format_is_srgb(format))
 486       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 487
 488    if (fmt & EXT_FORMAT) {
 489       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 490
 491       /* ETC1 is checked above, as it has its own feature bit. ETC2 is
 492        * supported with HALTI0, however that implementation is buggy in hardware.
 493        * The blob driver does per-block patching to work around this. As this
 494        * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
 495        * only.
 496        */
 497       if (util_format_is_etc(format))
 498          supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
 499    }
 500
 501    if (fmt & ASTC_FORMAT) {
 502       supported = screen->specs.tex_astc;
 503    }
 504
 505    if (!supported)
 506       return false;
 507
 508    if (texture_format_needs_swiz(format))
 509       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 510
 511    return true;
 512 }
 513
 514 static boolean
 515 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 516                                 enum pipe_format format,
 517                                 enum pipe_texture_target target,
 518                                 unsigned sample_count, unsigned usage)
 519 {
 520    struct etna_screen *screen = etna_screen(pscreen);
 521    unsigned allowed = 0;
 522
 523    if (target != PIPE_BUFFER &&
 524        target != PIPE_TEXTURE_1D &&
 525        target != PIPE_TEXTURE_2D &&
 526        target != PIPE_TEXTURE_3D &&
 527        target != PIPE_TEXTURE_CUBE &&
 528        target != PIPE_TEXTURE_RECT)
 529       return FALSE;
 530
 531    if (usage & PIPE_BIND_RENDER_TARGET) {
 532       /* if render target, must be RS-supported format */
 533       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 534          /* Validate MSAA; number of samples must be allowed, and render target
 535           * must have MSAA'able format. */
 536          if (sample_count > 1) {
 537             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 538                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 539                allowed |= PIPE_BIND_RENDER_TARGET;
 540             }
 541          } else {
 542             allowed |= PIPE_BIND_RENDER_TARGET;
 543          }
 544       }
 545    }
 546
 547    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 548       if (translate_depth_format(format) != ETNA_NO_MATCH)
 549          allowed |= PIPE_BIND_DEPTH_STENCIL;
 550    }
 551
 552    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 553       uint32_t fmt = translate_texture_format(format);
 554
 555       if (!gpu_supports_texure_format(screen, fmt, format))
 556          fmt = ETNA_NO_MATCH;
 557
 558       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 559          allowed |= PIPE_BIND_SAMPLER_VIEW;
 560    }
 561
 562    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 563       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 564          allowed |= PIPE_BIND_VERTEX_BUFFER;
 565    }
 566
 567    if (usage & PIPE_BIND_INDEX_BUFFER) {
 568       /* must be supported index format */
 569       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 570           (format == PIPE_FORMAT_I32_UINT &&
 571            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 572          allowed |= PIPE_BIND_INDEX_BUFFER;
 573       }
 574    }
 575
 576    /* Always allowed */
 577    allowed |=
 578       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 579
 580    if (usage != allowed) {
 581       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 582           "usage=%x, allowed=%x",
 583           util_format_name(format), target, sample_count, usage, allowed);
 584    }
 585
 586    return usage == allowed;
 587 }
 588
 589 const uint64_t supported_modifiers[] = {
 590    DRM_FORMAT_MOD_LINEAR,
 591    DRM_FORMAT_MOD_VIVANTE_TILED,
 592    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 593    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 594    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 595 };
 596
 597 static void
 598 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 599                                    enum pipe_format format, int max,
 600                                    uint64_t *modifiers,
 601                                    unsigned int *external_only, int *count)
 602 {
 603    struct etna_screen *screen = etna_screen(pscreen);
 604    int i, num_modifiers = 0;
 605
 606    if (max > ARRAY_SIZE(supported_modifiers))
 607       max = ARRAY_SIZE(supported_modifiers);
 608
 609    if (!max) {
 610       modifiers = NULL;
 611       max = ARRAY_SIZE(supported_modifiers);
 612    }
 613
 614    for (i = 0; num_modifiers < max; i++) {
 615       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 616       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 617           i >= 3)
 618          break;
 619
 620       if (modifiers)
 621          modifiers[num_modifiers] = supported_modifiers[i];
 622       if (external_only)
 623          external_only[num_modifiers] = 0;
 624       num_modifiers++;
 625    }
 626
 627    *count = num_modifiers;
 628 }
 629
 630 static boolean
 631 etna_get_specs(struct etna_screen *screen)
 632 {
 633    uint64_t val;
 634    uint32_t instruction_count;
 635
 636    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 637       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 638       goto fail;
 639    }
 640    instruction_count = val;
 641
 642    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 643                           &val)) {
 644       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 645       goto fail;
 646    }
 647    screen->specs.vertex_output_buffer_size = val;
 648
 649    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 650       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 651       goto fail;
 652    }
 653    screen->specs.vertex_cache_size = val;
 654
 655    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 656       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 657       goto fail;
 658    }
 659    screen->specs.shader_core_count = val;
 660
 661    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 662       DBG("could not get ETNA_GPU_STREAM_COUNT");
 663       goto fail;
 664    }
 665    screen->specs.stream_count = val;
 666
 667    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 668       DBG("could not get ETNA_GPU_REGISTER_MAX");
 669       goto fail;
 670    }
 671    screen->specs.max_registers = val;
 672
 673    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 674       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 675       goto fail;
 676    }
 677    screen->specs.pixel_pipes = val;
 678
 679    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 680       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 681       goto fail;
 682    }
 683    if (val == 0) {
 684       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 685       val = 168;
 686    }
 687    screen->specs.num_constants = val;
 688
 689    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 690     * description of the differences. */
 691    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 692       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 693    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 694       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 695    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 696       screen->specs.halti = 3; /* None? */
 697    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 698       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 699    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 700       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 701    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 702       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 703    else
 704       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 705    if (screen->specs.halti >= 0)
 706       DBG("etnaviv: GPU arch: HALTI%d\n", screen->specs.halti);
 707    else
 708       DBG("etnaviv: GPU arch: pre-HALTI\n");
 709
 710    screen->specs.can_supertile =
 711       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 712    screen->specs.bits_per_tile =
 713       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 714    screen->specs.ts_clear_value =
 715       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 716                                                            : 0x11111111;
 717
 718    /* vertex and fragment samplers live in one address space */
 719    screen->specs.vertex_sampler_offset = 8;
 720    screen->specs.fragment_sampler_count = 8;
 721    screen->specs.vertex_sampler_count = 4;
 722    screen->specs.vs_need_z_div =
 723       screen->model < 0x1000 && screen->model != 0x880;
 724    screen->specs.has_sin_cos_sqrt =
 725       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 726    screen->specs.has_sign_floor_ceil =
 727       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 728    screen->specs.has_shader_range_registers =
 729       screen->model >= 0x1000 || screen->model == 0x880;
 730    screen->specs.npot_tex_any_wrap =
 731       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 732    screen->specs.has_new_transcendentals =
 733       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 734    screen->specs.has_halti2_instructions =
 735       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 736
 737    if (screen->specs.halti >= 5) {
 738       /* GC7000 - this core must load shaders from memory. */
 739       screen->specs.vs_offset = 0;
 740       screen->specs.ps_offset = 0;
 741       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 742       screen->specs.has_icache = true;
 743    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 744       /* GC3000 - this core is capable of loading shaders from
 745        * memory. It can also run shaders from registers, as a fallback, but
 746        * "max_instructions" does not have the correct value. It has place for
 747        * 2*256 instructions just like GC2000, but the offsets are slightly
 748        * different.
 749        */
 750       screen->specs.vs_offset = 0xC000;
 751       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 752        * this mirror for writing PS instructions, probably safest to do the
 753        * same.
 754        */
 755       screen->specs.ps_offset = 0x8000 + 0x1000;
 756       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 757       screen->specs.has_icache = true;
 758    } else {
 759       if (instruction_count > 256) { /* unified instruction memory? */
 760          screen->specs.vs_offset = 0xC000;
 761          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 762          screen->specs.max_instructions = 256;
 763       } else {
 764          screen->specs.vs_offset = 0x4000;
 765          screen->specs.ps_offset = 0x6000;
 766          screen->specs.max_instructions = instruction_count / 2;
 767       }
 768       screen->specs.has_icache = false;
 769    }
 770
 771    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 772       screen->specs.max_varyings = 12;
 773       screen->specs.vertex_max_elements = 16;
 774    } else {
 775       screen->specs.max_varyings = 8;
 776       /* Etna_viv documentation seems confused over the correct value
 777        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 778        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 779       screen->specs.vertex_max_elements = 10;
 780    }
 781
 782    /* Etna_viv documentation does not indicate where varyings above 8 are
 783     * stored. Moreover, if we are passed more than 8 varyings, we will
 784     * walk off the end of some arrays. Limit the maximum number of varyings. */
 785    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 786       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 787
 788    /* from QueryShaderCaps in kernel driver */
 789    if (screen->model < chipModel_GC4000) {
 790       screen->specs.max_vs_uniforms = 168;
 791       screen->specs.max_ps_uniforms = 64;
 792    } else {
 793       screen->specs.max_vs_uniforms = 256;
 794       screen->specs.max_ps_uniforms = 256;
 795    }
 796
 797    if (screen->specs.halti >= 5) {
 798       screen->specs.has_unified_uniforms = true;
 799       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 800       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 801    } else if (screen->specs.halti >= 1) {
 802       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 803       */
 804       screen->specs.has_unified_uniforms = true;
 805       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 806       /* hardcode PS uniforms to start after end of VS uniforms -
 807        * for more flexibility this offset could be variable based on the
 808        * shader.
 809        */
 810       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 811    } else {
 812       screen->specs.has_unified_uniforms = false;
 813       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 814       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 815    }
 816
 817    screen->specs.max_texture_size =
 818       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 819    screen->specs.max_rendertarget_size =
 820       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 821
 822    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 823    if (screen->specs.single_buffer)
 824       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 825
 826    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 827
 828    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 829
 830    return true;
 831
 832 fail:
 833    return false;
 834 }
 835
 836 struct etna_bo *
 837 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 838                            struct winsys_handle *whandle, unsigned *out_stride)
 839 {
 840    struct etna_screen *screen = etna_screen(pscreen);
 841    struct etna_bo *bo;
 842
 843    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 844       bo = etna_bo_from_name(screen->dev, whandle->handle);
 845    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 846       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 847    } else {
 848       DBG("Attempt to import unsupported handle type %d", whandle->type);
 849       return NULL;
 850    }
 851
 852    if (!bo) {
 853       DBG("ref name 0x%08x failed", whandle->handle);
 854       return NULL;
 855    }
 856
 857    *out_stride = whandle->stride;
 858
 859    return bo;
 860 }
 861
 862 struct pipe_screen *
 863 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 864                    struct renderonly *ro)
 865 {
 866    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 867    struct pipe_screen *pscreen;
 868    drmVersionPtr version;
 869    uint64_t val;
 870
 871    if (!screen)
 872       return NULL;
 873
 874    pscreen = &screen->base;
 875    screen->dev = dev;
 876    screen->gpu = gpu;
 877    screen->ro = renderonly_dup(ro);
 878    screen->refcnt = 1;
 879
 880    if (!screen->ro) {
 881       DBG("could not create renderonly object");
 882       goto fail;
 883    }
 884
 885    version = drmGetVersion(screen->ro->gpu_fd);
 886    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 887                                           version->version_minor);
 888    drmFreeVersion(version);
 889
 890    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 891
 892    /* Disable autodisable for correct rendering with TS */
 893    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 894
 895    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 896    if (!screen->pipe) {
 897       DBG("could not create 3d pipe");
 898       goto fail;
 899    }
 900
 901    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 902       DBG("could not get ETNA_GPU_MODEL");
 903       goto fail;
 904    }
 905    screen->model = val;
 906
 907    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 908       DBG("could not get ETNA_GPU_REVISION");
 909       goto fail;
 910    }
 911    screen->revision = val;
 912
 913    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 914       DBG("could not get ETNA_GPU_FEATURES_0");
 915       goto fail;
 916    }
 917    screen->features[0] = val;
 918
 919    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 920       DBG("could not get ETNA_GPU_FEATURES_1");
 921       goto fail;
 922    }
 923    screen->features[1] = val;
 924
 925    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 926       DBG("could not get ETNA_GPU_FEATURES_2");
 927       goto fail;
 928    }
 929    screen->features[2] = val;
 930
 931    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 932       DBG("could not get ETNA_GPU_FEATURES_3");
 933       goto fail;
 934    }
 935    screen->features[3] = val;
 936
 937    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 938       DBG("could not get ETNA_GPU_FEATURES_4");
 939       goto fail;
 940    }
 941    screen->features[4] = val;
 942
 943    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 944       DBG("could not get ETNA_GPU_FEATURES_5");
 945       goto fail;
 946    }
 947    screen->features[5] = val;
 948
 949    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 950       DBG("could not get ETNA_GPU_FEATURES_6");
 951       goto fail;
 952    }
 953    screen->features[6] = val;
 954
 955    if (!etna_get_specs(screen))
 956       goto fail;
 957
 958    /* apply debug options that disable individual features */
 959    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 960       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 961    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 962          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 963    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 964       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 965    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 966       screen->specs.can_supertile = 0;
 967    if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
 968       screen->specs.single_buffer = 0;
 969
 970    pscreen->destroy = etna_screen_destroy;
 971    pscreen->get_param = etna_screen_get_param;
 972    pscreen->get_paramf = etna_screen_get_paramf;
 973    pscreen->get_shader_param = etna_screen_get_shader_param;
 974
 975    pscreen->get_name = etna_screen_get_name;
 976    pscreen->get_vendor = etna_screen_get_vendor;
 977    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 978
 979    pscreen->get_timestamp = etna_screen_get_timestamp;
 980    pscreen->context_create = etna_context_create;
 981    pscreen->is_format_supported = etna_screen_is_format_supported;
 982    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 983
 984    etna_fence_screen_init(pscreen);
 985    etna_query_screen_init(pscreen);
 986    etna_resource_screen_init(pscreen);
 987
 988    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 989
 990    return pscreen;
 991
 992 fail:
 993    etna_screen_destroy(pscreen);
 994    return NULL;
 995 }