src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "util/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #include <drm_fourcc.h>
  49
  50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  51 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  52
  53 static const struct debug_named_value debug_options[] = {
  54    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  55    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  56    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  57    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  58    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  59    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  60    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  61    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  62    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  63    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  64    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  65    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  66    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  67    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  68    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  69    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  70    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  71    DEBUG_NAMED_VALUE_END
  72 };
  73
  74 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  75 int etna_mesa_debug = 0;
  76
  77 static void
  78 etna_screen_destroy(struct pipe_screen *pscreen)
  79 {
  80    struct etna_screen *screen = etna_screen(pscreen);
  81
  82    if (screen->pipe)
  83       etna_pipe_del(screen->pipe);
  84
  85    if (screen->gpu)
  86       etna_gpu_del(screen->gpu);
  87
  88    if (screen->ro)
  89       FREE(screen->ro);
  90
  91    if (screen->dev)
  92       etna_device_del(screen->dev);
  93
  94    FREE(screen);
  95 }
  96
  97 static const char *
  98 etna_screen_get_name(struct pipe_screen *pscreen)
  99 {
 100    struct etna_screen *priv = etna_screen(pscreen);
 101    static char buffer[128];
 102
 103    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 104                  priv->revision);
 105
 106    return buffer;
 107 }
 108
 109 static const char *
 110 etna_screen_get_vendor(struct pipe_screen *pscreen)
 111 {
 112    return "etnaviv";
 113 }
 114
 115 static const char *
 116 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 117 {
 118    return "Vivante";
 119 }
 120
 121 static int
 122 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 123 {
 124    struct etna_screen *screen = etna_screen(pscreen);
 125
 126    switch (param) {
 127    /* Supported features (boolean caps). */
 128    case PIPE_CAP_ANISOTROPIC_FILTER:
 129    case PIPE_CAP_POINT_SPRITE:
 130    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 131    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 132    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 133    case PIPE_CAP_SM3:
 134    case PIPE_CAP_TEXTURE_BARRIER:
 135    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 136    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 137    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 138    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_TGSI_TEXCOORD:
 140    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 141       return 1;
 142    case PIPE_CAP_NATIVE_FENCE_FD:
 143       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 144
 145    /* Memory */
 146    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 147       return 256;
 148    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 149       return 4; /* XXX could easily be supported */
 150    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 151       return 120;
 152
 153    case PIPE_CAP_NPOT_TEXTURES:
 154       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 155                       NON_POWER_OF_TWO); */
 156
 157    case PIPE_CAP_TEXTURE_SWIZZLE:
 158    case PIPE_CAP_PRIMITIVE_RESTART:
 159       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 160
 161    case PIPE_CAP_ENDIANNESS:
 162       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 163                                     ENDIANNESS_CONFIG) */
 164
 165    /* Unsupported features. */
 166    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 167    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 168    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 169    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 170    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 171    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 172    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 173    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 174    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 175    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 176    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 177    case PIPE_CAP_INDEP_BLEND_ENABLE:
 178    case PIPE_CAP_INDEP_BLEND_FUNC:
 179    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 180    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 181    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 182    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 183    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 184    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 185    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 186    case PIPE_CAP_USER_VERTEX_BUFFERS:
 187    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 188    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 189    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 190    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 191    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 192    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 193    case PIPE_CAP_TEXTURE_GATHER_SM5:
 194    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 195    case PIPE_CAP_FAKE_SW_MSAA:
 196    case PIPE_CAP_TEXTURE_QUERY_LOD:
 197    case PIPE_CAP_SAMPLE_SHADING:
 198    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 199    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 200    case PIPE_CAP_DRAW_INDIRECT:
 201    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 202    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 203    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 204    case PIPE_CAP_CLIP_HALFZ:
 205    case PIPE_CAP_VERTEXID_NOBASE:
 206    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 207    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 208    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 209    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 210    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 211    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 212    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 213    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 214    case PIPE_CAP_TGSI_TXQS:
 215    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 216    case PIPE_CAP_SHAREABLE_SHADERS:
 217    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 218    case PIPE_CAP_CLEAR_TEXTURE:
 219    case PIPE_CAP_DRAW_PARAMETERS:
 220    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 221    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 222    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 223    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 224    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 225    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 226    case PIPE_CAP_INVALIDATE_BUFFER:
 227    case PIPE_CAP_GENERATE_MIPMAP:
 228    case PIPE_CAP_STRING_MARKER:
 229    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 230    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 231    case PIPE_CAP_QUERY_MEMORY_INFO:
 232    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 233    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 234    case PIPE_CAP_CULL_DISTANCE:
 235    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 236    case PIPE_CAP_TGSI_VOTE:
 237    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 238    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 239    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 240    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 241    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 242    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 243    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 244    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 245    case PIPE_CAP_TGSI_FS_FBFETCH:
 246    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 247    case PIPE_CAP_DOUBLES:
 248    case PIPE_CAP_INT64:
 249    case PIPE_CAP_INT64_DIVMOD:
 250    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 251    case PIPE_CAP_TGSI_CLOCK:
 252    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 253    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 254    case PIPE_CAP_TGSI_BALLOT:
 255    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 256    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 257    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 258    case PIPE_CAP_POST_DEPTH_COVERAGE:
 259    case PIPE_CAP_BINDLESS_TEXTURE:
 260    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 261    case PIPE_CAP_QUERY_SO_OVERFLOW:
 262    case PIPE_CAP_MEMOBJ:
 263    case PIPE_CAP_LOAD_CONSTBUF:
 264    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 265    case PIPE_CAP_TILE_RASTER_ORDER:
 266    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 267    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 268    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 269    case PIPE_CAP_FENCE_SIGNAL:
 270    case PIPE_CAP_CONSTBUF0_FLAGS:
 271       return 0;
 272
 273    /* Stream output. */
 274    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 275    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 276    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 277    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 278       return 0;
 279
 280    /* Geometry shader output, unsupported. */
 281    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 282    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 283    case PIPE_CAP_MAX_VERTEX_STREAMS:
 284       return 0;
 285
 286    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 287       return 128;
 288
 289    /* Texturing. */
 290    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 291    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 292    {
 293       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 294       assert(log2_max_tex_size > 0);
 295       return log2_max_tex_size;
 296    }
 297    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 298       return 5;
 299    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 300       return 0;
 301    case PIPE_CAP_CUBE_MAP_ARRAY:
 302       return 0;
 303    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 304    case PIPE_CAP_MIN_TEXEL_OFFSET:
 305       return -8;
 306    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 307    case PIPE_CAP_MAX_TEXEL_OFFSET:
 308       return 7;
 309    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 310       return 0;
 311    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 312       return 65536;
 313
 314    /* Render targets. */
 315    case PIPE_CAP_MAX_RENDER_TARGETS:
 316       return 1;
 317
 318    /* Viewports and scissors. */
 319    case PIPE_CAP_MAX_VIEWPORTS:
 320       return 1;
 321
 322    /* Timer queries. */
 323    case PIPE_CAP_QUERY_TIME_ELAPSED:
 324       return 0;
 325    case PIPE_CAP_OCCLUSION_QUERY:
 326       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 327    case PIPE_CAP_QUERY_TIMESTAMP:
 328       return 1;
 329    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 330       return 0;
 331
 332    /* Preferences */
 333    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 334       return 0;
 335
 336    case PIPE_CAP_PCI_GROUP:
 337    case PIPE_CAP_PCI_BUS:
 338    case PIPE_CAP_PCI_DEVICE:
 339    case PIPE_CAP_PCI_FUNCTION:
 340       return 0;
 341    case PIPE_CAP_VENDOR_ID:
 342    case PIPE_CAP_DEVICE_ID:
 343       return 0xFFFFFFFF;
 344    case PIPE_CAP_ACCELERATED:
 345       return 1;
 346    case PIPE_CAP_VIDEO_MEMORY:
 347       return 0;
 348    case PIPE_CAP_UMA:
 349       return 1;
 350    }
 351
 352    debug_printf("unknown param %d", param);
 353    return 0;
 354 }
 355
 356 static float
 357 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 358 {
 359    struct etna_screen *screen = etna_screen(pscreen);
 360
 361    switch (param) {
 362    case PIPE_CAPF_MAX_LINE_WIDTH:
 363    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 364    case PIPE_CAPF_MAX_POINT_WIDTH:
 365    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 366       return 8192.0f;
 367    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 368       return 16.0f;
 369    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 370       return util_last_bit(screen->specs.max_texture_size);
 371    }
 372
 373    debug_printf("unknown paramf %d", param);
 374    return 0;
 375 }
 376
 377 static int
 378 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 379                              enum pipe_shader_type shader,
 380                              enum pipe_shader_cap param)
 381 {
 382    struct etna_screen *screen = etna_screen(pscreen);
 383
 384    switch (shader) {
 385    case PIPE_SHADER_FRAGMENT:
 386    case PIPE_SHADER_VERTEX:
 387       break;
 388    case PIPE_SHADER_COMPUTE:
 389    case PIPE_SHADER_GEOMETRY:
 390    case PIPE_SHADER_TESS_CTRL:
 391    case PIPE_SHADER_TESS_EVAL:
 392       return 0;
 393    default:
 394       DBG("unknown shader type %d", shader);
 395       return 0;
 396    }
 397
 398    switch (param) {
 399    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 400    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 401    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 402    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 403       return ETNA_MAX_TOKENS;
 404    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 405       return ETNA_MAX_DEPTH; /* XXX */
 406    case PIPE_SHADER_CAP_MAX_INPUTS:
 407       /* Maximum number of inputs for the vertex shader is the number
 408        * of vertex elements - each element defines one vertex shader
 409        * input register.  For the fragment shader, this is the number
 410        * of varyings. */
 411       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 412                                             : screen->specs.vertex_max_elements;
 413    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 414       return 16; /* see VIVS_VS_OUTPUT */
 415    case PIPE_SHADER_CAP_MAX_TEMPS:
 416       return 64; /* Max native temporaries. */
 417    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 418       return 1;
 419    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 420       return 1;
 421    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 422    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 423    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 424    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 425       return 1;
 426    case PIPE_SHADER_CAP_SUBROUTINES:
 427       return 0;
 428    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 429       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 430    case PIPE_SHADER_CAP_INTEGERS:
 431    case PIPE_SHADER_CAP_INT64_ATOMICS:
 432    case PIPE_SHADER_CAP_FP16:
 433       return 0;
 434    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 435    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 436       return shader == PIPE_SHADER_FRAGMENT
 437                 ? screen->specs.fragment_sampler_count
 438                 : screen->specs.vertex_sampler_count;
 439    case PIPE_SHADER_CAP_PREFERRED_IR:
 440       return PIPE_SHADER_IR_TGSI;
 441    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 442       return 4096;
 443    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 444    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 445    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 446    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 447    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 448       return false;
 449    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 450       return 0;
 451    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 452       return 32;
 453    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 454    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 455    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 456    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 457    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 458    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 459       return 0;
 460    }
 461
 462    debug_printf("unknown shader param %d", param);
 463    return 0;
 464 }
 465
 466 static uint64_t
 467 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 468 {
 469    return os_time_get_nano();
 470 }
 471
 472 static bool
 473 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 474                            enum pipe_format format)
 475 {
 476    bool supported = true;
 477
 478    if (fmt == TEXTURE_FORMAT_ETC1)
 479       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 480
 481    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 482       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 483
 484    if (util_format_is_srgb(format))
 485       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 486
 487    if (fmt & EXT_FORMAT) {
 488       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 489
 490       /* ETC1 is checked above, as it has its own feature bit. ETC2 is
 491        * supported with HALTI0, however that implementation is buggy in hardware.
 492        * The blob driver does per-block patching to work around this. As this
 493        * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
 494        * only.
 495        */
 496       if (util_format_is_etc(format))
 497          supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
 498    }
 499
 500    if (fmt & ASTC_FORMAT) {
 501       supported = screen->specs.tex_astc;
 502    }
 503
 504    if (!supported)
 505       return false;
 506
 507    if (texture_format_needs_swiz(format))
 508       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 509
 510    return true;
 511 }
 512
 513 static boolean
 514 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 515                                 enum pipe_format format,
 516                                 enum pipe_texture_target target,
 517                                 unsigned sample_count, unsigned usage)
 518 {
 519    struct etna_screen *screen = etna_screen(pscreen);
 520    unsigned allowed = 0;
 521
 522    if (target != PIPE_BUFFER &&
 523        target != PIPE_TEXTURE_1D &&
 524        target != PIPE_TEXTURE_2D &&
 525        target != PIPE_TEXTURE_3D &&
 526        target != PIPE_TEXTURE_CUBE &&
 527        target != PIPE_TEXTURE_RECT)
 528       return FALSE;
 529
 530    if (usage & PIPE_BIND_RENDER_TARGET) {
 531       /* if render target, must be RS-supported format */
 532       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 533          /* Validate MSAA; number of samples must be allowed, and render target
 534           * must have MSAA'able format. */
 535          if (sample_count > 1) {
 536             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 537                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 538                allowed |= PIPE_BIND_RENDER_TARGET;
 539             }
 540          } else {
 541             allowed |= PIPE_BIND_RENDER_TARGET;
 542          }
 543       }
 544    }
 545
 546    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 547       if (translate_depth_format(format) != ETNA_NO_MATCH)
 548          allowed |= PIPE_BIND_DEPTH_STENCIL;
 549    }
 550
 551    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 552       uint32_t fmt = translate_texture_format(format);
 553
 554       if (!gpu_supports_texure_format(screen, fmt, format))
 555          fmt = ETNA_NO_MATCH;
 556
 557       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 558          allowed |= PIPE_BIND_SAMPLER_VIEW;
 559    }
 560
 561    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 562       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 563          allowed |= PIPE_BIND_VERTEX_BUFFER;
 564    }
 565
 566    if (usage & PIPE_BIND_INDEX_BUFFER) {
 567       /* must be supported index format */
 568       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 569           (format == PIPE_FORMAT_I32_UINT &&
 570            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 571          allowed |= PIPE_BIND_INDEX_BUFFER;
 572       }
 573    }
 574
 575    /* Always allowed */
 576    allowed |=
 577       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 578
 579    if (usage != allowed) {
 580       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 581           "usage=%x, allowed=%x",
 582           util_format_name(format), target, sample_count, usage, allowed);
 583    }
 584
 585    return usage == allowed;
 586 }
 587
 588 const uint64_t supported_modifiers[] = {
 589    DRM_FORMAT_MOD_LINEAR,
 590    DRM_FORMAT_MOD_VIVANTE_TILED,
 591    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 592    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 593    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 594 };
 595
 596 static void
 597 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 598                                    enum pipe_format format, int max,
 599                                    uint64_t *modifiers,
 600                                    unsigned int *external_only, int *count)
 601 {
 602    struct etna_screen *screen = etna_screen(pscreen);
 603    int i, num_modifiers = 0;
 604
 605    if (max > ARRAY_SIZE(supported_modifiers))
 606       max = ARRAY_SIZE(supported_modifiers);
 607
 608    if (!max) {
 609       modifiers = NULL;
 610       max = ARRAY_SIZE(supported_modifiers);
 611    }
 612
 613    for (i = 0; num_modifiers < max; i++) {
 614       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 615       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 616           i >= 3)
 617          break;
 618
 619       if (modifiers)
 620          modifiers[num_modifiers] = supported_modifiers[i];
 621       if (external_only)
 622          external_only[num_modifiers] = 0;
 623       num_modifiers++;
 624    }
 625
 626    *count = num_modifiers;
 627 }
 628
 629 static boolean
 630 etna_get_specs(struct etna_screen *screen)
 631 {
 632    uint64_t val;
 633    uint32_t instruction_count;
 634
 635    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 636       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 637       goto fail;
 638    }
 639    instruction_count = val;
 640
 641    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 642                           &val)) {
 643       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 644       goto fail;
 645    }
 646    screen->specs.vertex_output_buffer_size = val;
 647
 648    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 649       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 650       goto fail;
 651    }
 652    screen->specs.vertex_cache_size = val;
 653
 654    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 655       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 656       goto fail;
 657    }
 658    screen->specs.shader_core_count = val;
 659
 660    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 661       DBG("could not get ETNA_GPU_STREAM_COUNT");
 662       goto fail;
 663    }
 664    screen->specs.stream_count = val;
 665
 666    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 667       DBG("could not get ETNA_GPU_REGISTER_MAX");
 668       goto fail;
 669    }
 670    screen->specs.max_registers = val;
 671
 672    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 673       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 674       goto fail;
 675    }
 676    screen->specs.pixel_pipes = val;
 677
 678    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 679       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 680       goto fail;
 681    }
 682    if (val == 0) {
 683       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 684       val = 168;
 685    }
 686    screen->specs.num_constants = val;
 687
 688    /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
 689     * description of the differences. */
 690    if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
 691       screen->specs.halti = 5; /* New GC7000/GC8x00  */
 692    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
 693       screen->specs.halti = 4; /* Old GC7000/GC7400 */
 694    else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
 695       screen->specs.halti = 3; /* None? */
 696    else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
 697       screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
 698    else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
 699       screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
 700    else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
 701       screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
 702    else
 703       screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
 704    if (screen->specs.halti >= 0)
 705       DBG("etnaviv: GPU arch: HALTI%d\n", screen->specs.halti);
 706    else
 707       DBG("etnaviv: GPU arch: pre-HALTI\n");
 708
 709    screen->specs.can_supertile =
 710       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 711    screen->specs.bits_per_tile =
 712       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 713    screen->specs.ts_clear_value =
 714       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 715                                                            : 0x11111111;
 716
 717    /* vertex and fragment samplers live in one address space */
 718    screen->specs.vertex_sampler_offset = 8;
 719    screen->specs.fragment_sampler_count = 8;
 720    screen->specs.vertex_sampler_count = 4;
 721    screen->specs.vs_need_z_div =
 722       screen->model < 0x1000 && screen->model != 0x880;
 723    screen->specs.has_sin_cos_sqrt =
 724       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 725    screen->specs.has_sign_floor_ceil =
 726       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 727    screen->specs.has_shader_range_registers =
 728       screen->model >= 0x1000 || screen->model == 0x880;
 729    screen->specs.npot_tex_any_wrap =
 730       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 731    screen->specs.has_new_transcendentals =
 732       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 733    screen->specs.has_halti2_instructions =
 734       VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
 735
 736    if (screen->specs.halti >= 5) {
 737       /* GC7000 - this core must load shaders from memory. */
 738       screen->specs.vs_offset = 0;
 739       screen->specs.ps_offset = 0;
 740       screen->specs.max_instructions = 0; /* Do not program shaders manually */
 741       screen->specs.has_icache = true;
 742    } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 743       /* GC3000 - this core is capable of loading shaders from
 744        * memory. It can also run shaders from registers, as a fallback, but
 745        * "max_instructions" does not have the correct value. It has place for
 746        * 2*256 instructions just like GC2000, but the offsets are slightly
 747        * different.
 748        */
 749       screen->specs.vs_offset = 0xC000;
 750       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 751        * this mirror for writing PS instructions, probably safest to do the
 752        * same.
 753        */
 754       screen->specs.ps_offset = 0x8000 + 0x1000;
 755       screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
 756       screen->specs.has_icache = true;
 757    } else {
 758       if (instruction_count > 256) { /* unified instruction memory? */
 759          screen->specs.vs_offset = 0xC000;
 760          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 761          screen->specs.max_instructions = 256;
 762       } else {
 763          screen->specs.vs_offset = 0x4000;
 764          screen->specs.ps_offset = 0x6000;
 765          screen->specs.max_instructions = instruction_count / 2;
 766       }
 767       screen->specs.has_icache = false;
 768    }
 769
 770    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 771       screen->specs.max_varyings = 12;
 772       screen->specs.vertex_max_elements = 16;
 773    } else {
 774       screen->specs.max_varyings = 8;
 775       /* Etna_viv documentation seems confused over the correct value
 776        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 777        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 778       screen->specs.vertex_max_elements = 10;
 779    }
 780
 781    /* Etna_viv documentation does not indicate where varyings above 8 are
 782     * stored. Moreover, if we are passed more than 8 varyings, we will
 783     * walk off the end of some arrays. Limit the maximum number of varyings. */
 784    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 785       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 786
 787    /* from QueryShaderCaps in kernel driver */
 788    if (screen->model < chipModel_GC4000) {
 789       screen->specs.max_vs_uniforms = 168;
 790       screen->specs.max_ps_uniforms = 64;
 791    } else {
 792       screen->specs.max_vs_uniforms = 256;
 793       screen->specs.max_ps_uniforms = 256;
 794    }
 795
 796    if (screen->specs.halti >= 5) {
 797       screen->specs.has_unified_uniforms = true;
 798       screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
 799       screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
 800    } else if (screen->specs.halti >= 1) {
 801       /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
 802       */
 803       screen->specs.has_unified_uniforms = true;
 804       screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
 805       /* hardcode PS uniforms to start after end of VS uniforms -
 806        * for more flexibility this offset could be variable based on the
 807        * shader.
 808        */
 809       screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
 810    } else {
 811       screen->specs.has_unified_uniforms = false;
 812       screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
 813       screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
 814    }
 815
 816    screen->specs.max_texture_size =
 817       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 818    screen->specs.max_rendertarget_size =
 819       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 820
 821    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 822    if (screen->specs.single_buffer)
 823       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 824
 825    screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
 826
 827    screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
 828
 829    return true;
 830
 831 fail:
 832    return false;
 833 }
 834
 835 struct etna_bo *
 836 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 837                            struct winsys_handle *whandle, unsigned *out_stride)
 838 {
 839    struct etna_screen *screen = etna_screen(pscreen);
 840    struct etna_bo *bo;
 841
 842    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 843       bo = etna_bo_from_name(screen->dev, whandle->handle);
 844    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 845       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 846    } else {
 847       DBG("Attempt to import unsupported handle type %d", whandle->type);
 848       return NULL;
 849    }
 850
 851    if (!bo) {
 852       DBG("ref name 0x%08x failed", whandle->handle);
 853       return NULL;
 854    }
 855
 856    *out_stride = whandle->stride;
 857
 858    return bo;
 859 }
 860
 861 struct pipe_screen *
 862 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 863                    struct renderonly *ro)
 864 {
 865    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 866    struct pipe_screen *pscreen;
 867    drmVersionPtr version;
 868    uint64_t val;
 869
 870    if (!screen)
 871       return NULL;
 872
 873    pscreen = &screen->base;
 874    screen->dev = dev;
 875    screen->gpu = gpu;
 876    screen->ro = renderonly_dup(ro);
 877    screen->refcnt = 1;
 878
 879    if (!screen->ro) {
 880       DBG("could not create renderonly object");
 881       goto fail;
 882    }
 883
 884    version = drmGetVersion(screen->ro->gpu_fd);
 885    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 886                                           version->version_minor);
 887    drmFreeVersion(version);
 888
 889    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 890
 891    /* Disable autodisable for correct rendering with TS */
 892    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 893
 894    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 895    if (!screen->pipe) {
 896       DBG("could not create 3d pipe");
 897       goto fail;
 898    }
 899
 900    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 901       DBG("could not get ETNA_GPU_MODEL");
 902       goto fail;
 903    }
 904    screen->model = val;
 905
 906    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 907       DBG("could not get ETNA_GPU_REVISION");
 908       goto fail;
 909    }
 910    screen->revision = val;
 911
 912    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 913       DBG("could not get ETNA_GPU_FEATURES_0");
 914       goto fail;
 915    }
 916    screen->features[0] = val;
 917
 918    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 919       DBG("could not get ETNA_GPU_FEATURES_1");
 920       goto fail;
 921    }
 922    screen->features[1] = val;
 923
 924    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 925       DBG("could not get ETNA_GPU_FEATURES_2");
 926       goto fail;
 927    }
 928    screen->features[2] = val;
 929
 930    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 931       DBG("could not get ETNA_GPU_FEATURES_3");
 932       goto fail;
 933    }
 934    screen->features[3] = val;
 935
 936    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 937       DBG("could not get ETNA_GPU_FEATURES_4");
 938       goto fail;
 939    }
 940    screen->features[4] = val;
 941
 942    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 943       DBG("could not get ETNA_GPU_FEATURES_5");
 944       goto fail;
 945    }
 946    screen->features[5] = val;
 947
 948    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 949       DBG("could not get ETNA_GPU_FEATURES_6");
 950       goto fail;
 951    }
 952    screen->features[6] = val;
 953
 954    if (!etna_get_specs(screen))
 955       goto fail;
 956
 957    /* apply debug options that disable individual features */
 958    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 959       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 960    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 961          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 962    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 963       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 964    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 965       screen->specs.can_supertile = 0;
 966
 967    pscreen->destroy = etna_screen_destroy;
 968    pscreen->get_param = etna_screen_get_param;
 969    pscreen->get_paramf = etna_screen_get_paramf;
 970    pscreen->get_shader_param = etna_screen_get_shader_param;
 971
 972    pscreen->get_name = etna_screen_get_name;
 973    pscreen->get_vendor = etna_screen_get_vendor;
 974    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 975
 976    pscreen->get_timestamp = etna_screen_get_timestamp;
 977    pscreen->context_create = etna_context_create;
 978    pscreen->is_format_supported = etna_screen_is_format_supported;
 979    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 980
 981    etna_fence_screen_init(pscreen);
 982    etna_query_screen_init(pscreen);
 983    etna_resource_screen_init(pscreen);
 984
 985    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 986
 987    return pscreen;
 988
 989 fail:
 990    etna_screen_destroy(pscreen);
 991    return NULL;
 992 }