src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 #include <drm_fourcc.h>
  49
  50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
  51 #define ETNA_DRM_VERSION_FENCE_FD      ETNA_DRM_VERSION(1, 1)
  52
  53 static const struct debug_named_value debug_options[] = {
  54    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  55    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  56    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  57    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  58    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  59    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  60    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  61    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  62    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  63    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  64    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  65    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  66    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  67    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  68    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  69    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  70    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  71    DEBUG_NAMED_VALUE_END
  72 };
  73
  74 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  75 int etna_mesa_debug = 0;
  76
  77 static void
  78 etna_screen_destroy(struct pipe_screen *pscreen)
  79 {
  80    struct etna_screen *screen = etna_screen(pscreen);
  81
  82    if (screen->pipe)
  83       etna_pipe_del(screen->pipe);
  84
  85    if (screen->gpu)
  86       etna_gpu_del(screen->gpu);
  87
  88    if (screen->ro)
  89       FREE(screen->ro);
  90
  91    if (screen->dev)
  92       etna_device_del(screen->dev);
  93
  94    FREE(screen);
  95 }
  96
  97 static const char *
  98 etna_screen_get_name(struct pipe_screen *pscreen)
  99 {
 100    struct etna_screen *priv = etna_screen(pscreen);
 101    static char buffer[128];
 102
 103    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
 104                  priv->revision);
 105
 106    return buffer;
 107 }
 108
 109 static const char *
 110 etna_screen_get_vendor(struct pipe_screen *pscreen)
 111 {
 112    return "etnaviv";
 113 }
 114
 115 static const char *
 116 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 117 {
 118    return "Vivante";
 119 }
 120
 121 static int
 122 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 123 {
 124    struct etna_screen *screen = etna_screen(pscreen);
 125
 126    switch (param) {
 127    /* Supported features (boolean caps). */
 128    case PIPE_CAP_TWO_SIDED_STENCIL:
 129    case PIPE_CAP_ANISOTROPIC_FILTER:
 130    case PIPE_CAP_POINT_SPRITE:
 131    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 132    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 133    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 134    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 135    case PIPE_CAP_SM3:
 136    case PIPE_CAP_TEXTURE_BARRIER:
 137    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 138    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 139    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 140    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 141    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 142    case PIPE_CAP_TGSI_TEXCOORD:
 143    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 144       return 1;
 145    case PIPE_CAP_NATIVE_FENCE_FD:
 146       return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
 147
 148    /* Memory */
 149    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 150       return 256;
 151    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 152       return 4; /* XXX could easily be supported */
 153    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 154       return 120;
 155
 156    case PIPE_CAP_NPOT_TEXTURES:
 157       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 158                       NON_POWER_OF_TWO); */
 159
 160    case PIPE_CAP_TEXTURE_SWIZZLE:
 161    case PIPE_CAP_PRIMITIVE_RESTART:
 162       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 163
 164    case PIPE_CAP_ENDIANNESS:
 165       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 166                                     ENDIANNESS_CONFIG) */
 167
 168    /* Unsupported features. */
 169    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 170    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 171    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 172    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 173    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 174    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 175    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 176    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 177    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 178    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 179    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 180    case PIPE_CAP_INDEP_BLEND_ENABLE:
 181    case PIPE_CAP_INDEP_BLEND_FUNC:
 182    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 183    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 184    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 185    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 187    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 188    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 189    case PIPE_CAP_USER_VERTEX_BUFFERS:
 190    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 191    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 192    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 193    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 194    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 195    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 196    case PIPE_CAP_TEXTURE_GATHER_SM5:
 197    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 198    case PIPE_CAP_FAKE_SW_MSAA:
 199    case PIPE_CAP_TEXTURE_QUERY_LOD:
 200    case PIPE_CAP_SAMPLE_SHADING:
 201    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 202    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 203    case PIPE_CAP_DRAW_INDIRECT:
 204    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 205    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 206    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 207    case PIPE_CAP_CLIP_HALFZ:
 208    case PIPE_CAP_VERTEXID_NOBASE:
 209    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 211    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 212    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 213    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 214    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 215    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 217    case PIPE_CAP_TGSI_TXQS:
 218    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219    case PIPE_CAP_SHAREABLE_SHADERS:
 220    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 221    case PIPE_CAP_CLEAR_TEXTURE:
 222    case PIPE_CAP_DRAW_PARAMETERS:
 223    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 224    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 225    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 226    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 227    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 228    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 229    case PIPE_CAP_INVALIDATE_BUFFER:
 230    case PIPE_CAP_GENERATE_MIPMAP:
 231    case PIPE_CAP_STRING_MARKER:
 232    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 233    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 234    case PIPE_CAP_QUERY_MEMORY_INFO:
 235    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 236    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 237    case PIPE_CAP_CULL_DISTANCE:
 238    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 239    case PIPE_CAP_TGSI_VOTE:
 240    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 241    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 242    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 243    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 244    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 246    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 247    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 248    case PIPE_CAP_TGSI_FS_FBFETCH:
 249    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 250    case PIPE_CAP_DOUBLES:
 251    case PIPE_CAP_INT64:
 252    case PIPE_CAP_INT64_DIVMOD:
 253    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 254    case PIPE_CAP_TGSI_CLOCK:
 255    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 256    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 257    case PIPE_CAP_TGSI_BALLOT:
 258    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 259    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 260    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 261    case PIPE_CAP_POST_DEPTH_COVERAGE:
 262    case PIPE_CAP_BINDLESS_TEXTURE:
 263       return 0;
 264
 265    /* Stream output. */
 266    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 267    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 268    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 269    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 270       return 0;
 271
 272    /* Geometry shader output, unsupported. */
 273    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 274    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 275    case PIPE_CAP_MAX_VERTEX_STREAMS:
 276       return 0;
 277
 278    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 279       return 128;
 280
 281    /* Texturing. */
 282    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 283    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 284    {
 285       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 286       assert(log2_max_tex_size > 0);
 287       return log2_max_tex_size;
 288    }
 289    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 290       return 5;
 291    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 292       return 0;
 293    case PIPE_CAP_CUBE_MAP_ARRAY:
 294       return 0;
 295    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 296    case PIPE_CAP_MIN_TEXEL_OFFSET:
 297       return -8;
 298    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 299    case PIPE_CAP_MAX_TEXEL_OFFSET:
 300       return 7;
 301    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 302       return 0;
 303    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 304       return 65536;
 305
 306    /* Render targets. */
 307    case PIPE_CAP_MAX_RENDER_TARGETS:
 308       return 1;
 309
 310    /* Viewports and scissors. */
 311    case PIPE_CAP_MAX_VIEWPORTS:
 312       return 1;
 313
 314    /* Timer queries. */
 315    case PIPE_CAP_QUERY_TIME_ELAPSED:
 316    case PIPE_CAP_OCCLUSION_QUERY:
 317       return 0;
 318    case PIPE_CAP_QUERY_TIMESTAMP:
 319       return 1;
 320    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 321       return 0;
 322
 323    /* Preferences */
 324    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 325       return 0;
 326
 327    case PIPE_CAP_PCI_GROUP:
 328    case PIPE_CAP_PCI_BUS:
 329    case PIPE_CAP_PCI_DEVICE:
 330    case PIPE_CAP_PCI_FUNCTION:
 331       return 0;
 332    case PIPE_CAP_VENDOR_ID:
 333    case PIPE_CAP_DEVICE_ID:
 334       return 0xFFFFFFFF;
 335    case PIPE_CAP_ACCELERATED:
 336       return 1;
 337    case PIPE_CAP_VIDEO_MEMORY:
 338       return 0;
 339    case PIPE_CAP_UMA:
 340       return 1;
 341    }
 342
 343    debug_printf("unknown param %d", param);
 344    return 0;
 345 }
 346
 347 static float
 348 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 349 {
 350    struct etna_screen *screen = etna_screen(pscreen);
 351
 352    switch (param) {
 353    case PIPE_CAPF_MAX_LINE_WIDTH:
 354    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 355    case PIPE_CAPF_MAX_POINT_WIDTH:
 356    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 357       return 8192.0f;
 358    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 359       return 16.0f;
 360    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 361       return util_last_bit(screen->specs.max_texture_size);
 362    case PIPE_CAPF_GUARD_BAND_LEFT:
 363    case PIPE_CAPF_GUARD_BAND_TOP:
 364    case PIPE_CAPF_GUARD_BAND_RIGHT:
 365    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 366       return 0.0f;
 367    }
 368
 369    debug_printf("unknown paramf %d", param);
 370    return 0;
 371 }
 372
 373 static int
 374 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 375                              enum pipe_shader_type shader,
 376                              enum pipe_shader_cap param)
 377 {
 378    struct etna_screen *screen = etna_screen(pscreen);
 379
 380    switch (shader) {
 381    case PIPE_SHADER_FRAGMENT:
 382    case PIPE_SHADER_VERTEX:
 383       break;
 384    case PIPE_SHADER_COMPUTE:
 385    case PIPE_SHADER_GEOMETRY:
 386    case PIPE_SHADER_TESS_CTRL:
 387    case PIPE_SHADER_TESS_EVAL:
 388       return 0;
 389    default:
 390       DBG("unknown shader type %d", shader);
 391       return 0;
 392    }
 393
 394    switch (param) {
 395    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 396    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 397    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 398    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 399       return ETNA_MAX_TOKENS;
 400    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 401       return ETNA_MAX_DEPTH; /* XXX */
 402    case PIPE_SHADER_CAP_MAX_INPUTS:
 403       /* Maximum number of inputs for the vertex shader is the number
 404        * of vertex elements - each element defines one vertex shader
 405        * input register.  For the fragment shader, this is the number
 406        * of varyings. */
 407       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 408                                             : screen->specs.vertex_max_elements;
 409    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 410       return 16; /* see VIVS_VS_OUTPUT */
 411    case PIPE_SHADER_CAP_MAX_TEMPS:
 412       return 64; /* Max native temporaries. */
 413    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 414       return 1;
 415    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 416       return 1;
 417    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 418    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 419    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 420    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 421       return 1;
 422    case PIPE_SHADER_CAP_SUBROUTINES:
 423       return 0;
 424    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 425       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 426    case PIPE_SHADER_CAP_INTEGERS:
 427       return 0;
 428    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 429    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 430       return shader == PIPE_SHADER_FRAGMENT
 431                 ? screen->specs.fragment_sampler_count
 432                 : screen->specs.vertex_sampler_count;
 433    case PIPE_SHADER_CAP_PREFERRED_IR:
 434       return PIPE_SHADER_IR_TGSI;
 435    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 436       return 4096;
 437    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 438    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 439    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 440    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 441       return false;
 442    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 443       return 0;
 444    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 445       return 32;
 446    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 447    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 448    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 449    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 450       return 0;
 451    }
 452
 453    debug_printf("unknown shader param %d", param);
 454    return 0;
 455 }
 456
 457 static uint64_t
 458 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 459 {
 460    return os_time_get_nano();
 461 }
 462
 463 static bool
 464 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
 465                            enum pipe_format format)
 466 {
 467    bool supported = true;
 468
 469    if (fmt == TEXTURE_FORMAT_ETC1)
 470       supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 471
 472    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 473       supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 474
 475    if (fmt & EXT_FORMAT)
 476       supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 477
 478    if (!supported)
 479       return false;
 480
 481    if (texture_format_needs_swiz(format))
 482       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 483
 484    return true;
 485 }
 486
 487 static boolean
 488 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 489                                 enum pipe_format format,
 490                                 enum pipe_texture_target target,
 491                                 unsigned sample_count, unsigned usage)
 492 {
 493    struct etna_screen *screen = etna_screen(pscreen);
 494    unsigned allowed = 0;
 495
 496    if (target != PIPE_BUFFER &&
 497        target != PIPE_TEXTURE_1D &&
 498        target != PIPE_TEXTURE_2D &&
 499        target != PIPE_TEXTURE_3D &&
 500        target != PIPE_TEXTURE_CUBE &&
 501        target != PIPE_TEXTURE_RECT)
 502       return FALSE;
 503
 504    if (usage & PIPE_BIND_RENDER_TARGET) {
 505       /* if render target, must be RS-supported format */
 506       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 507          /* Validate MSAA; number of samples must be allowed, and render target
 508           * must have MSAA'able format. */
 509          if (sample_count > 1) {
 510             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 511                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 512                allowed |= PIPE_BIND_RENDER_TARGET;
 513             }
 514          } else {
 515             allowed |= PIPE_BIND_RENDER_TARGET;
 516          }
 517       }
 518    }
 519
 520    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 521       if (translate_depth_format(format) != ETNA_NO_MATCH)
 522          allowed |= PIPE_BIND_DEPTH_STENCIL;
 523    }
 524
 525    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 526       uint32_t fmt = translate_texture_format(format);
 527
 528       if (!gpu_supports_texure_format(screen, fmt, format))
 529          fmt = ETNA_NO_MATCH;
 530
 531       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 532          allowed |= PIPE_BIND_SAMPLER_VIEW;
 533    }
 534
 535    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 536       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 537          allowed |= PIPE_BIND_VERTEX_BUFFER;
 538    }
 539
 540    if (usage & PIPE_BIND_INDEX_BUFFER) {
 541       /* must be supported index format */
 542       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 543           (format == PIPE_FORMAT_I32_UINT &&
 544            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 545          allowed |= PIPE_BIND_INDEX_BUFFER;
 546       }
 547    }
 548
 549    /* Always allowed */
 550    allowed |=
 551       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 552
 553    if (usage != allowed) {
 554       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 555           "usage=%x, allowed=%x",
 556           util_format_name(format), target, sample_count, usage, allowed);
 557    }
 558
 559    return usage == allowed;
 560 }
 561
 562 const uint64_t supported_modifiers[] = {
 563    DRM_FORMAT_MOD_LINEAR,
 564    DRM_FORMAT_MOD_VIVANTE_TILED,
 565    DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
 566    DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
 567    DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
 568 };
 569
 570 static void
 571 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
 572                                    enum pipe_format format, int max,
 573                                    uint64_t *modifiers,
 574                                    unsigned int *external_only, int *count)
 575 {
 576    struct etna_screen *screen = etna_screen(pscreen);
 577    int i, num_modifiers = 0;
 578
 579    if (max > ARRAY_SIZE(supported_modifiers))
 580       max = ARRAY_SIZE(supported_modifiers);
 581
 582    if (!max) {
 583       modifiers = NULL;
 584       max = ARRAY_SIZE(supported_modifiers);
 585    }
 586
 587    for (i = 0; num_modifiers < max; i++) {
 588       /* don't advertise split tiled formats on single pipe/buffer GPUs */
 589       if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
 590           i >= 3)
 591          break;
 592
 593       if (modifiers)
 594          modifiers[num_modifiers] = supported_modifiers[i];
 595       if (external_only)
 596          external_only[num_modifiers] = 0;
 597       num_modifiers++;
 598    }
 599
 600    *count = num_modifiers;
 601 }
 602
 603 static boolean
 604 etna_get_specs(struct etna_screen *screen)
 605 {
 606    uint64_t val;
 607    uint32_t instruction_count;
 608
 609    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 610       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 611       goto fail;
 612    }
 613    instruction_count = val;
 614
 615    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 616                           &val)) {
 617       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 618       goto fail;
 619    }
 620    screen->specs.vertex_output_buffer_size = val;
 621
 622    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 623       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 624       goto fail;
 625    }
 626    screen->specs.vertex_cache_size = val;
 627
 628    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 629       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 630       goto fail;
 631    }
 632    screen->specs.shader_core_count = val;
 633
 634    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 635       DBG("could not get ETNA_GPU_STREAM_COUNT");
 636       goto fail;
 637    }
 638    screen->specs.stream_count = val;
 639
 640    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 641       DBG("could not get ETNA_GPU_REGISTER_MAX");
 642       goto fail;
 643    }
 644    screen->specs.max_registers = val;
 645
 646    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 647       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 648       goto fail;
 649    }
 650    screen->specs.pixel_pipes = val;
 651
 652    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 653       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 654       goto fail;
 655    }
 656    if (val == 0) {
 657       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 658       val = 168;
 659    }
 660    screen->specs.num_constants = val;
 661
 662    screen->specs.can_supertile =
 663       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 664    screen->specs.bits_per_tile =
 665       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 666    screen->specs.ts_clear_value =
 667       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 668                                                            : 0x11111111;
 669
 670    /* vertex and fragment samplers live in one address space */
 671    screen->specs.vertex_sampler_offset = 8;
 672    screen->specs.fragment_sampler_count = 8;
 673    screen->specs.vertex_sampler_count = 4;
 674    screen->specs.vs_need_z_div =
 675       screen->model < 0x1000 && screen->model != 0x880;
 676    screen->specs.has_sin_cos_sqrt =
 677       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 678    screen->specs.has_sign_floor_ceil =
 679       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 680    screen->specs.has_shader_range_registers =
 681       screen->model >= 0x1000 || screen->model == 0x880;
 682    screen->specs.npot_tex_any_wrap =
 683       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 684    screen->specs.has_new_transcendentals =
 685       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 686
 687    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 688       /* GC3000 - this core is capable of loading shaders from
 689        * memory. It can also run shaders from registers, as a fallback, but
 690        * "max_instructions" does not have the correct value. It has place for
 691        * 2*256 instructions just like GC2000, but the offsets are slightly
 692        * different.
 693        */
 694       screen->specs.vs_offset = 0xC000;
 695       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 696        * this mirror for writing PS instructions, probably safest to do the
 697        * same.
 698        */
 699       screen->specs.ps_offset = 0x8000 + 0x1000;
 700       screen->specs.max_instructions = 256;
 701    } else {
 702       if (instruction_count > 256) { /* unified instruction memory? */
 703          screen->specs.vs_offset = 0xC000;
 704          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 705          screen->specs.max_instructions = 256;
 706       } else {
 707          screen->specs.vs_offset = 0x4000;
 708          screen->specs.ps_offset = 0x6000;
 709          screen->specs.max_instructions = instruction_count / 2;
 710       }
 711    }
 712
 713    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 714       screen->specs.max_varyings = 12;
 715       screen->specs.vertex_max_elements = 16;
 716    } else {
 717       screen->specs.max_varyings = 8;
 718       /* Etna_viv documentation seems confused over the correct value
 719        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 720        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 721       screen->specs.vertex_max_elements = 10;
 722    }
 723
 724    /* Etna_viv documentation does not indicate where varyings above 8 are
 725     * stored. Moreover, if we are passed more than 8 varyings, we will
 726     * walk off the end of some arrays. Limit the maximum number of varyings. */
 727    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 728       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 729
 730    /* from QueryShaderCaps in kernel driver */
 731    if (screen->model < chipModel_GC4000) {
 732       screen->specs.max_vs_uniforms = 168;
 733       screen->specs.max_ps_uniforms = 64;
 734    } else {
 735       screen->specs.max_vs_uniforms = 256;
 736       screen->specs.max_ps_uniforms = 256;
 737    }
 738
 739    screen->specs.max_texture_size =
 740       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 741    screen->specs.max_rendertarget_size =
 742       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 743
 744    screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
 745    if (screen->specs.single_buffer)
 746       DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
 747
 748    return true;
 749
 750 fail:
 751    return false;
 752 }
 753
 754 struct etna_bo *
 755 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 756                            struct winsys_handle *whandle, unsigned *out_stride)
 757 {
 758    struct etna_screen *screen = etna_screen(pscreen);
 759    struct etna_bo *bo;
 760
 761    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 762       bo = etna_bo_from_name(screen->dev, whandle->handle);
 763    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 764       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 765    } else {
 766       DBG("Attempt to import unsupported handle type %d", whandle->type);
 767       return NULL;
 768    }
 769
 770    if (!bo) {
 771       DBG("ref name 0x%08x failed", whandle->handle);
 772       return NULL;
 773    }
 774
 775    *out_stride = whandle->stride;
 776
 777    return bo;
 778 }
 779
 780 struct pipe_screen *
 781 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 782                    struct renderonly *ro)
 783 {
 784    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 785    struct pipe_screen *pscreen;
 786    drmVersionPtr version;
 787    uint64_t val;
 788
 789    if (!screen)
 790       return NULL;
 791
 792    pscreen = &screen->base;
 793    screen->dev = dev;
 794    screen->gpu = gpu;
 795    screen->ro = renderonly_dup(ro);
 796    screen->refcnt = 1;
 797
 798    if (!screen->ro) {
 799       DBG("could not create renderonly object");
 800       goto fail;
 801    }
 802
 803    version = drmGetVersion(screen->ro->gpu_fd);
 804    screen->drm_version = ETNA_DRM_VERSION(version->version_major,
 805                                           version->version_minor);
 806    drmFreeVersion(version);
 807
 808    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 809
 810    /* Disable autodisable for correct rendering with TS */
 811    etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
 812
 813    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 814    if (!screen->pipe) {
 815       DBG("could not create 3d pipe");
 816       goto fail;
 817    }
 818
 819    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 820       DBG("could not get ETNA_GPU_MODEL");
 821       goto fail;
 822    }
 823    screen->model = val;
 824
 825    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 826       DBG("could not get ETNA_GPU_REVISION");
 827       goto fail;
 828    }
 829    screen->revision = val;
 830
 831    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 832       DBG("could not get ETNA_GPU_FEATURES_0");
 833       goto fail;
 834    }
 835    screen->features[0] = val;
 836
 837    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 838       DBG("could not get ETNA_GPU_FEATURES_1");
 839       goto fail;
 840    }
 841    screen->features[1] = val;
 842
 843    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 844       DBG("could not get ETNA_GPU_FEATURES_2");
 845       goto fail;
 846    }
 847    screen->features[2] = val;
 848
 849    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 850       DBG("could not get ETNA_GPU_FEATURES_3");
 851       goto fail;
 852    }
 853    screen->features[3] = val;
 854
 855    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 856       DBG("could not get ETNA_GPU_FEATURES_4");
 857       goto fail;
 858    }
 859    screen->features[4] = val;
 860
 861    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
 862       DBG("could not get ETNA_GPU_FEATURES_5");
 863       goto fail;
 864    }
 865    screen->features[5] = val;
 866
 867    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
 868       DBG("could not get ETNA_GPU_FEATURES_6");
 869       goto fail;
 870    }
 871    screen->features[6] = val;
 872
 873    if (!etna_get_specs(screen))
 874       goto fail;
 875
 876    /* apply debug options that disable individual features */
 877    if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
 878       screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
 879    if (DBG_ENABLED(ETNA_DBG_NO_TS))
 880          screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
 881    if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
 882       screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
 883    if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
 884       screen->specs.can_supertile = 0;
 885
 886    pscreen->destroy = etna_screen_destroy;
 887    pscreen->get_param = etna_screen_get_param;
 888    pscreen->get_paramf = etna_screen_get_paramf;
 889    pscreen->get_shader_param = etna_screen_get_shader_param;
 890
 891    pscreen->get_name = etna_screen_get_name;
 892    pscreen->get_vendor = etna_screen_get_vendor;
 893    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 894
 895    pscreen->get_timestamp = etna_screen_get_timestamp;
 896    pscreen->context_create = etna_context_create;
 897    pscreen->is_format_supported = etna_screen_is_format_supported;
 898    pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
 899
 900    etna_fence_screen_init(pscreen);
 901    etna_query_screen_init(pscreen);
 902    etna_resource_screen_init(pscreen);
 903
 904    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 905
 906    return pscreen;
 907
 908 fail:
 909    etna_screen_destroy(pscreen);
 910    return NULL;
 911 }