src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 static const struct debug_named_value debug_options[] = {
  49    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  50    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  51    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  52    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  53    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  54    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  55    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  56    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  57    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  58    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  59    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  60    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  61    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  62    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  63    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  64    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  65    DEBUG_NAMED_VALUE_END
  66 };
  67
  68 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  69 int etna_mesa_debug = 0;
  70
  71 static void
  72 etna_screen_destroy(struct pipe_screen *pscreen)
  73 {
  74    struct etna_screen *screen = etna_screen(pscreen);
  75
  76    if (screen->pipe)
  77       etna_pipe_del(screen->pipe);
  78
  79    if (screen->gpu)
  80       etna_gpu_del(screen->gpu);
  81
  82    if (screen->ro)
  83       FREE(screen->ro);
  84
  85    if (screen->dev)
  86       etna_device_del(screen->dev);
  87
  88    FREE(screen);
  89 }
  90
  91 static const char *
  92 etna_screen_get_name(struct pipe_screen *pscreen)
  93 {
  94    struct etna_screen *priv = etna_screen(pscreen);
  95    static char buffer[128];
  96
  97    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
  98                  priv->revision);
  99
 100    return buffer;
 101 }
 102
 103 static const char *
 104 etna_screen_get_vendor(struct pipe_screen *pscreen)
 105 {
 106    return "etnaviv";
 107 }
 108
 109 static const char *
 110 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 111 {
 112    return "Vivante";
 113 }
 114
 115 static int
 116 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 117 {
 118    struct etna_screen *screen = etna_screen(pscreen);
 119
 120    switch (param) {
 121    /* Supported features (boolean caps). */
 122    case PIPE_CAP_TWO_SIDED_STENCIL:
 123    case PIPE_CAP_ANISOTROPIC_FILTER:
 124    case PIPE_CAP_POINT_SPRITE:
 125    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 126    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 127    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 128    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 129    case PIPE_CAP_SM3:
 130    case PIPE_CAP_TEXTURE_BARRIER:
 131    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 132    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 133    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 134    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 135    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 136    case PIPE_CAP_TGSI_TEXCOORD:
 137    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 138       return 1;
 139
 140    /* Memory */
 141    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 142       return 256;
 143    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 144       return 4; /* XXX could easily be supported */
 145    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 146       return 120;
 147
 148    case PIPE_CAP_NPOT_TEXTURES:
 149       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 150                       NON_POWER_OF_TWO); */
 151
 152    case PIPE_CAP_PRIMITIVE_RESTART:
 153       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 154
 155    case PIPE_CAP_ENDIANNESS:
 156       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 157                                     ENDIANNESS_CONFIG) */
 158
 159    /* Unsupported features. */
 160    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 161    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
 162    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 163    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 164    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 165    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 166    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 167    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 168    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 169    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 170    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 171    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 172    case PIPE_CAP_INDEP_BLEND_ENABLE:
 173    case PIPE_CAP_INDEP_BLEND_FUNC:
 174    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 175    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 176    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 177    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 178    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 179    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 180    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 181    case PIPE_CAP_USER_VERTEX_BUFFERS:
 182    case PIPE_CAP_USER_INDEX_BUFFERS:
 183    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 184    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 185    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 186    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 187    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 188    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189    case PIPE_CAP_TEXTURE_GATHER_SM5:
 190    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 191    case PIPE_CAP_FAKE_SW_MSAA:
 192    case PIPE_CAP_TEXTURE_QUERY_LOD:
 193    case PIPE_CAP_SAMPLE_SHADING:
 194    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 195    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 196    case PIPE_CAP_DRAW_INDIRECT:
 197    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 198    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 199    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 200    case PIPE_CAP_CLIP_HALFZ:
 201    case PIPE_CAP_VERTEXID_NOBASE:
 202    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 203    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 204    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 205    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 206    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 207    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 208    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 209    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 210    case PIPE_CAP_TGSI_TXQS:
 211    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 212    case PIPE_CAP_SHAREABLE_SHADERS:
 213    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 214    case PIPE_CAP_CLEAR_TEXTURE:
 215    case PIPE_CAP_DRAW_PARAMETERS:
 216    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 217    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 218    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 219    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 220    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 221    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 222    case PIPE_CAP_INVALIDATE_BUFFER:
 223    case PIPE_CAP_GENERATE_MIPMAP:
 224    case PIPE_CAP_STRING_MARKER:
 225    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 227    case PIPE_CAP_QUERY_MEMORY_INFO:
 228    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 229    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 230    case PIPE_CAP_CULL_DISTANCE:
 231    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 232    case PIPE_CAP_TGSI_VOTE:
 233    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 234    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 235    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 236    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 237    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 238    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 239    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 240    case PIPE_CAP_NATIVE_FENCE_FD:
 241    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 242       return 0;
 243
 244    /* Stream output. */
 245    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 246    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 247    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 248    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 249       return 0;
 250
 251    /* Geometry shader output, unsupported. */
 252    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 253    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 254    case PIPE_CAP_MAX_VERTEX_STREAMS:
 255       return 0;
 256
 257    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 258       return 128;
 259
 260    /* Texturing. */
 261    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 262    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 263    {
 264       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 265       assert(log2_max_tex_size > 0);
 266       return log2_max_tex_size;
 267    }
 268    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 269       return 5;
 270    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 271       return 0;
 272    case PIPE_CAP_CUBE_MAP_ARRAY:
 273       return 0;
 274    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 275    case PIPE_CAP_MIN_TEXEL_OFFSET:
 276       return -8;
 277    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 278    case PIPE_CAP_MAX_TEXEL_OFFSET:
 279       return 7;
 280    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 281       return 0;
 282    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 283       return 65536;
 284
 285    /* Render targets. */
 286    case PIPE_CAP_MAX_RENDER_TARGETS:
 287       return 1;
 288
 289    /* Viewports and scissors. */
 290    case PIPE_CAP_MAX_VIEWPORTS:
 291       return 1;
 292
 293    /* Timer queries. */
 294    case PIPE_CAP_QUERY_TIME_ELAPSED:
 295    case PIPE_CAP_OCCLUSION_QUERY:
 296       return 0;
 297    case PIPE_CAP_QUERY_TIMESTAMP:
 298       return 1;
 299    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 300       return 0;
 301
 302    /* Preferences */
 303    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 304       return 0;
 305
 306    case PIPE_CAP_PCI_GROUP:
 307    case PIPE_CAP_PCI_BUS:
 308    case PIPE_CAP_PCI_DEVICE:
 309    case PIPE_CAP_PCI_FUNCTION:
 310       return 0;
 311    case PIPE_CAP_VENDOR_ID:
 312    case PIPE_CAP_DEVICE_ID:
 313       return 0xFFFFFFFF;
 314    case PIPE_CAP_ACCELERATED:
 315       return 1;
 316    case PIPE_CAP_VIDEO_MEMORY:
 317       return 0;
 318    case PIPE_CAP_UMA:
 319       return 1;
 320    }
 321
 322    debug_printf("unknown param %d", param);
 323    return 0;
 324 }
 325
 326 static float
 327 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 328 {
 329    switch (param) {
 330    case PIPE_CAPF_MAX_LINE_WIDTH:
 331    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 332    case PIPE_CAPF_MAX_POINT_WIDTH:
 333    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 334       return 8192.0f;
 335    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 336       return 16.0f;
 337    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 338       return 16.0f;
 339    case PIPE_CAPF_GUARD_BAND_LEFT:
 340    case PIPE_CAPF_GUARD_BAND_TOP:
 341    case PIPE_CAPF_GUARD_BAND_RIGHT:
 342    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 343       return 0.0f;
 344    }
 345
 346    debug_printf("unknown paramf %d", param);
 347    return 0;
 348 }
 349
 350 static int
 351 etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 352                              enum pipe_shader_cap param)
 353 {
 354    struct etna_screen *screen = etna_screen(pscreen);
 355
 356    switch (shader) {
 357    case PIPE_SHADER_FRAGMENT:
 358    case PIPE_SHADER_VERTEX:
 359       break;
 360    case PIPE_SHADER_COMPUTE:
 361    case PIPE_SHADER_GEOMETRY:
 362    case PIPE_SHADER_TESS_CTRL:
 363    case PIPE_SHADER_TESS_EVAL:
 364       return 0;
 365    default:
 366       DBG("unknown shader type %d", shader);
 367       return 0;
 368    }
 369
 370    switch (param) {
 371    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 372    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 373    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 374    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 375       return ETNA_MAX_TOKENS;
 376    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 377       return ETNA_MAX_DEPTH; /* XXX */
 378    case PIPE_SHADER_CAP_MAX_INPUTS:
 379       /* Maximum number of inputs for the vertex shader is the number
 380        * of vertex elements - each element defines one vertex shader
 381        * input register.  For the fragment shader, this is the number
 382        * of varyings. */
 383       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 384                                             : screen->specs.vertex_max_elements;
 385    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 386       return 16; /* see VIVS_VS_OUTPUT */
 387    case PIPE_SHADER_CAP_MAX_TEMPS:
 388       return 64; /* Max native temporaries. */
 389    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 390       return 1;
 391    case PIPE_SHADER_CAP_MAX_PREDS:
 392       return 0; /* nothing uses this */
 393    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 394       return 1;
 395    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 396    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 397    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 398    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 399       return 1;
 400    case PIPE_SHADER_CAP_SUBROUTINES:
 401       return 0;
 402    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 403       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 404    case PIPE_SHADER_CAP_INTEGERS:
 405       return 0;
 406    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 407    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 408       return shader == PIPE_SHADER_FRAGMENT
 409                 ? screen->specs.fragment_sampler_count
 410                 : screen->specs.vertex_sampler_count;
 411    case PIPE_SHADER_CAP_PREFERRED_IR:
 412       return PIPE_SHADER_IR_TGSI;
 413    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 414       return 4096;
 415    case PIPE_SHADER_CAP_DOUBLES:
 416    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 417    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 418    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 419    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 420       return false;
 421    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 422       return 0;
 423    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 424       return 32;
 425    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 426    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 427    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 428       return 0;
 429    }
 430
 431    debug_printf("unknown shader param %d", param);
 432    return 0;
 433 }
 434
 435 static uint64_t
 436 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 437 {
 438    return os_time_get_nano();
 439 }
 440
 441 static bool
 442 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
 443 {
 444    if (fmt == TEXTURE_FORMAT_ETC1)
 445       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 446
 447    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 448       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 449
 450    return true;
 451 }
 452
 453 static boolean
 454 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 455                                 enum pipe_format format,
 456                                 enum pipe_texture_target target,
 457                                 unsigned sample_count, unsigned usage)
 458 {
 459    struct etna_screen *screen = etna_screen(pscreen);
 460    unsigned allowed = 0;
 461
 462    if (target != PIPE_BUFFER &&
 463        target != PIPE_TEXTURE_1D &&
 464        target != PIPE_TEXTURE_2D &&
 465        target != PIPE_TEXTURE_3D &&
 466        target != PIPE_TEXTURE_CUBE &&
 467        target != PIPE_TEXTURE_RECT)
 468       return FALSE;
 469
 470    if (usage & PIPE_BIND_RENDER_TARGET) {
 471       /* if render target, must be RS-supported format */
 472       if (translate_rs_format(format) != ETNA_NO_MATCH) {
 473          /* Validate MSAA; number of samples must be allowed, and render target
 474           * must have MSAA'able format. */
 475          if (sample_count > 1) {
 476             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 477                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 478                allowed |= PIPE_BIND_RENDER_TARGET;
 479             }
 480          } else {
 481             allowed |= PIPE_BIND_RENDER_TARGET;
 482          }
 483       }
 484    }
 485
 486    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 487       if (translate_depth_format(format) != ETNA_NO_MATCH)
 488          allowed |= PIPE_BIND_DEPTH_STENCIL;
 489    }
 490
 491    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 492       uint32_t fmt = translate_texture_format(format);
 493
 494       if (!gpu_supports_texure_format(screen, fmt))
 495          fmt = ETNA_NO_MATCH;
 496
 497       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 498          allowed |= PIPE_BIND_SAMPLER_VIEW;
 499    }
 500
 501    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 502       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 503          allowed |= PIPE_BIND_VERTEX_BUFFER;
 504    }
 505
 506    if (usage & PIPE_BIND_INDEX_BUFFER) {
 507       /* must be supported index format */
 508       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 509           (format == PIPE_FORMAT_I32_UINT &&
 510            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 511          allowed |= PIPE_BIND_INDEX_BUFFER;
 512       }
 513    }
 514
 515    /* Always allowed */
 516    allowed |=
 517       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 518
 519    if (usage != allowed) {
 520       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 521           "usage=%x, allowed=%x",
 522           util_format_name(format), target, sample_count, usage, allowed);
 523    }
 524
 525    return usage == allowed;
 526 }
 527
 528 static boolean
 529 etna_get_specs(struct etna_screen *screen)
 530 {
 531    uint64_t val;
 532    uint32_t instruction_count;
 533
 534    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 535       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 536       goto fail;
 537    }
 538    instruction_count = val;
 539
 540    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 541                           &val)) {
 542       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 543       goto fail;
 544    }
 545    screen->specs.vertex_output_buffer_size = val;
 546
 547    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 548       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 549       goto fail;
 550    }
 551    screen->specs.vertex_cache_size = val;
 552
 553    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 554       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 555       goto fail;
 556    }
 557    screen->specs.shader_core_count = val;
 558
 559    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 560       DBG("could not get ETNA_GPU_STREAM_COUNT");
 561       goto fail;
 562    }
 563    screen->specs.stream_count = val;
 564
 565    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 566       DBG("could not get ETNA_GPU_REGISTER_MAX");
 567       goto fail;
 568    }
 569    screen->specs.max_registers = val;
 570
 571    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 572       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 573       goto fail;
 574    }
 575    if (val < 1 && val > ETNA_MAX_PIXELPIPES) {
 576       if (val == 0) {
 577          fprintf(stderr, "Warning: zero pixel pipes (update kernel?)\n");
 578          val = 1;
 579       } else {
 580          fprintf(stderr, "Error: bad pixel pipes value %u\n",
 581                  (unsigned int)val);
 582          goto fail;
 583       }
 584    }
 585    screen->specs.pixel_pipes = val;
 586
 587    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 588       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 589       goto fail;
 590    }
 591    if (val == 0) {
 592       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 593       val = 168;
 594    }
 595    screen->specs.num_constants = val;
 596
 597    screen->specs.can_supertile =
 598       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 599    screen->specs.bits_per_tile =
 600       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 601    screen->specs.ts_clear_value =
 602       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 603                                                            : 0x11111111;
 604
 605    /* vertex and fragment samplers live in one address space */
 606    screen->specs.vertex_sampler_offset = 8;
 607    screen->specs.fragment_sampler_count = 8;
 608    screen->specs.vertex_sampler_count = 4;
 609    screen->specs.vs_need_z_div =
 610       screen->model < 0x1000 && screen->model != 0x880;
 611    screen->specs.has_sin_cos_sqrt =
 612       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 613    screen->specs.has_sign_floor_ceil =
 614       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 615    screen->specs.has_shader_range_registers =
 616       screen->model >= 0x1000 || screen->model == 0x880;
 617    screen->specs.npot_tex_any_wrap =
 618       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 619
 620    if (instruction_count > 256) { /* unified instruction memory? */
 621       screen->specs.vs_offset = 0xC000;
 622       screen->specs.ps_offset = 0xD000; /* like vivante driver */
 623       screen->specs.max_instructions = 256;
 624    } else {
 625       screen->specs.vs_offset = 0x4000;
 626       screen->specs.ps_offset = 0x6000;
 627       screen->specs.max_instructions = instruction_count / 2;
 628    }
 629
 630    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 631       screen->specs.max_varyings = 12;
 632       screen->specs.vertex_max_elements = 16;
 633    } else {
 634       screen->specs.max_varyings = 8;
 635       /* Etna_viv documentation seems confused over the correct value
 636        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 637        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 638       screen->specs.vertex_max_elements = 10;
 639    }
 640
 641    /* Etna_viv documentation does not indicate where varyings above 8 are
 642     * stored. Moreover, if we are passed more than 8 varyings, we will
 643     * walk off the end of some arrays. Limit the maximum number of varyings. */
 644    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 645       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 646
 647    /* from QueryShaderCaps in kernel driver */
 648    if (screen->model < chipModel_GC4000) {
 649       screen->specs.max_vs_uniforms = 168;
 650       screen->specs.max_ps_uniforms = 64;
 651    } else {
 652       screen->specs.max_vs_uniforms = 256;
 653       screen->specs.max_ps_uniforms = 256;
 654    }
 655
 656    screen->specs.max_texture_size =
 657       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 658    screen->specs.max_rendertarget_size =
 659       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 660
 661    return true;
 662
 663 fail:
 664    return false;
 665 }
 666
 667 boolean
 668 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
 669                           unsigned stride, struct winsys_handle *whandle)
 670 {
 671    whandle->stride = stride;
 672
 673    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 674       return etna_bo_get_name(bo, &whandle->handle) == 0;
 675    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 676       whandle->handle = etna_bo_handle(bo);
 677       return TRUE;
 678    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 679       whandle->handle = etna_bo_dmabuf(bo);
 680       return TRUE;
 681    } else {
 682       return FALSE;
 683    }
 684 }
 685
 686 struct etna_bo *
 687 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 688                            struct winsys_handle *whandle, unsigned *out_stride)
 689 {
 690    struct etna_screen *screen = etna_screen(pscreen);
 691    struct etna_bo *bo;
 692
 693    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 694       bo = etna_bo_from_name(screen->dev, whandle->handle);
 695    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 696       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 697    } else {
 698       DBG("Attempt to import unsupported handle type %d", whandle->type);
 699       return NULL;
 700    }
 701
 702    if (!bo) {
 703       DBG("ref name 0x%08x failed", whandle->handle);
 704       return NULL;
 705    }
 706
 707    *out_stride = whandle->stride;
 708
 709    return bo;
 710 }
 711
 712 struct pipe_screen *
 713 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 714                    struct renderonly *ro)
 715 {
 716    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 717    struct pipe_screen *pscreen;
 718    uint64_t val;
 719
 720    if (!screen)
 721       return NULL;
 722
 723    pscreen = &screen->base;
 724    screen->dev = dev;
 725    screen->gpu = gpu;
 726    screen->ro = renderonly_dup(ro);
 727
 728    if (!screen->ro) {
 729       DBG("could not create renderonly object");
 730       goto fail;
 731    }
 732
 733    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 734
 735    /* FIXME: Disable tile status for stability at the moment */
 736    etna_mesa_debug |= ETNA_DBG_NO_TS;
 737
 738    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 739    if (!screen->pipe) {
 740       DBG("could not create 3d pipe");
 741       goto fail;
 742    }
 743
 744    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 745       DBG("could not get ETNA_GPU_MODEL");
 746       goto fail;
 747    }
 748    screen->model = val;
 749
 750    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 751       DBG("could not get ETNA_GPU_REVISION");
 752       goto fail;
 753    }
 754    screen->revision = val;
 755
 756    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 757       DBG("could not get ETNA_GPU_FEATURES_0");
 758       goto fail;
 759    }
 760    screen->features[0] = val;
 761
 762    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 763       DBG("could not get ETNA_GPU_FEATURES_1");
 764       goto fail;
 765    }
 766    screen->features[1] = val;
 767
 768    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 769       DBG("could not get ETNA_GPU_FEATURES_2");
 770       goto fail;
 771    }
 772    screen->features[2] = val;
 773
 774    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 775       DBG("could not get ETNA_GPU_FEATURES_3");
 776       goto fail;
 777    }
 778    screen->features[3] = val;
 779
 780    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 781       DBG("could not get ETNA_GPU_FEATURES_4");
 782       goto fail;
 783    }
 784    screen->features[4] = val;
 785
 786    if (!etna_get_specs(screen))
 787       goto fail;
 788
 789    pscreen->destroy = etna_screen_destroy;
 790    pscreen->get_param = etna_screen_get_param;
 791    pscreen->get_paramf = etna_screen_get_paramf;
 792    pscreen->get_shader_param = etna_screen_get_shader_param;
 793
 794    pscreen->get_name = etna_screen_get_name;
 795    pscreen->get_vendor = etna_screen_get_vendor;
 796    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 797
 798    pscreen->get_timestamp = etna_screen_get_timestamp;
 799    pscreen->context_create = etna_context_create;
 800    pscreen->is_format_supported = etna_screen_is_format_supported;
 801
 802    etna_fence_screen_init(pscreen);
 803    etna_query_screen_init(pscreen);
 804    etna_resource_screen_init(pscreen);
 805
 806    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 807
 808    return pscreen;
 809
 810 fail:
 811    etna_screen_destroy(pscreen);
 812    return NULL;
 813 }