src/gallium/drivers/etnaviv/etnaviv_screen.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_screen.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_compiler.h"
  33 #include "etnaviv_context.h"
  34 #include "etnaviv_debug.h"
  35 #include "etnaviv_fence.h"
  36 #include "etnaviv_format.h"
  37 #include "etnaviv_query.h"
  38 #include "etnaviv_resource.h"
  39 #include "etnaviv_translate.h"
  40
  41 #include "os/os_time.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44 #include "util/u_string.h"
  45
  46 #include "state_tracker/drm_driver.h"
  47
  48 static const struct debug_named_value debug_options[] = {
  49    {"dbg_msgs",       ETNA_DBG_MSGS, "Print debug messages"},
  50    {"frame_msgs",     ETNA_DBG_FRAME_MSGS, "Print frame messages"},
  51    {"resource_msgs",  ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
  52    {"compiler_msgs",  ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
  53    {"linker_msgs",    ETNA_DBG_LINKER_MSGS, "Print linker messages"},
  54    {"dump_shaders",   ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
  55    {"no_ts",          ETNA_DBG_NO_TS, "Disable TS"},
  56    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
  57    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
  58    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
  59    {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
  60    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
  61    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
  62    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
  63    {"zero",           ETNA_DBG_ZERO, "Zero all resources after allocation"},
  64    {"draw_stall",     ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
  65    {"shaderdb",       ETNA_DBG_SHADERDB, "Enable shaderdb output"},
  66    DEBUG_NAMED_VALUE_END
  67 };
  68
  69 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
  70 int etna_mesa_debug = 0;
  71
  72 static void
  73 etna_screen_destroy(struct pipe_screen *pscreen)
  74 {
  75    struct etna_screen *screen = etna_screen(pscreen);
  76
  77    if (screen->pipe)
  78       etna_pipe_del(screen->pipe);
  79
  80    if (screen->gpu)
  81       etna_gpu_del(screen->gpu);
  82
  83    if (screen->ro)
  84       FREE(screen->ro);
  85
  86    if (screen->dev)
  87       etna_device_del(screen->dev);
  88
  89    FREE(screen);
  90 }
  91
  92 static const char *
  93 etna_screen_get_name(struct pipe_screen *pscreen)
  94 {
  95    struct etna_screen *priv = etna_screen(pscreen);
  96    static char buffer[128];
  97
  98    util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
  99                  priv->revision);
 100
 101    return buffer;
 102 }
 103
 104 static const char *
 105 etna_screen_get_vendor(struct pipe_screen *pscreen)
 106 {
 107    return "etnaviv";
 108 }
 109
 110 static const char *
 111 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
 112 {
 113    return "Vivante";
 114 }
 115
 116 static int
 117 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 118 {
 119    struct etna_screen *screen = etna_screen(pscreen);
 120
 121    switch (param) {
 122    /* Supported features (boolean caps). */
 123    case PIPE_CAP_TWO_SIDED_STENCIL:
 124    case PIPE_CAP_ANISOTROPIC_FILTER:
 125    case PIPE_CAP_POINT_SPRITE:
 126    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 127    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 128    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 129    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 130    case PIPE_CAP_SM3:
 131    case PIPE_CAP_TEXTURE_BARRIER:
 132    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 133    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 134    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 135    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 136    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 137    case PIPE_CAP_TGSI_TEXCOORD:
 138    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 139       return 1;
 140
 141    /* Memory */
 142    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 143       return 256;
 144    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 145       return 4; /* XXX could easily be supported */
 146    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 147       return 120;
 148
 149    case PIPE_CAP_NPOT_TEXTURES:
 150       return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
 151                       NON_POWER_OF_TWO); */
 152
 153    case PIPE_CAP_PRIMITIVE_RESTART:
 154       return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 155
 156    case PIPE_CAP_ENDIANNESS:
 157       return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
 158                                     ENDIANNESS_CONFIG) */
 159
 160    /* Unsupported features. */
 161    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 162    case PIPE_CAP_TEXTURE_SWIZZLE: /* XXX supported on gc2000 */
 163    case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
 164    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
 165    case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
 166    case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
 167    case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
 168    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
 169    case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
 170    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
 171    case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
 172    case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
 173    case PIPE_CAP_INDEP_BLEND_ENABLE:
 174    case PIPE_CAP_INDEP_BLEND_FUNC:
 175    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 176    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 177    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 178    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 179    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
 180    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 181    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 182    case PIPE_CAP_USER_VERTEX_BUFFERS:
 183    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 184    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 185    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 186    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
 187    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 188    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 189    case PIPE_CAP_TEXTURE_GATHER_SM5:
 190    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 191    case PIPE_CAP_FAKE_SW_MSAA:
 192    case PIPE_CAP_TEXTURE_QUERY_LOD:
 193    case PIPE_CAP_SAMPLE_SHADING:
 194    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 195    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 196    case PIPE_CAP_DRAW_INDIRECT:
 197    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 198    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 199    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 200    case PIPE_CAP_CLIP_HALFZ:
 201    case PIPE_CAP_VERTEXID_NOBASE:
 202    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 203    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 204    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 205    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 206    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 207    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 208    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 209    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 210    case PIPE_CAP_TGSI_TXQS:
 211    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 212    case PIPE_CAP_SHAREABLE_SHADERS:
 213    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 214    case PIPE_CAP_CLEAR_TEXTURE:
 215    case PIPE_CAP_DRAW_PARAMETERS:
 216    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 217    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 218    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 219    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 220    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 221    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 222    case PIPE_CAP_INVALIDATE_BUFFER:
 223    case PIPE_CAP_GENERATE_MIPMAP:
 224    case PIPE_CAP_STRING_MARKER:
 225    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 226    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 227    case PIPE_CAP_QUERY_MEMORY_INFO:
 228    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 229    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 230    case PIPE_CAP_CULL_DISTANCE:
 231    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 232    case PIPE_CAP_TGSI_VOTE:
 233    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 234    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 235    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 236    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 237    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 238    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 239    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 240    case PIPE_CAP_NATIVE_FENCE_FD:
 241    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 242    case PIPE_CAP_TGSI_FS_FBFETCH:
 243    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 244    case PIPE_CAP_DOUBLES:
 245    case PIPE_CAP_INT64:
 246    case PIPE_CAP_INT64_DIVMOD:
 247    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 248    case PIPE_CAP_TGSI_CLOCK:
 249       return 0;
 250
 251    /* Stream output. */
 252    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 253    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 254    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 255    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 256       return 0;
 257
 258    /* Geometry shader output, unsupported. */
 259    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 260    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 261    case PIPE_CAP_MAX_VERTEX_STREAMS:
 262       return 0;
 263
 264    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 265       return 128;
 266
 267    /* Texturing. */
 268    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 269    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 270    {
 271       int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
 272       assert(log2_max_tex_size > 0);
 273       return log2_max_tex_size;
 274    }
 275    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
 276       return 5;
 277    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 278       return 0;
 279    case PIPE_CAP_CUBE_MAP_ARRAY:
 280       return 0;
 281    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 282    case PIPE_CAP_MIN_TEXEL_OFFSET:
 283       return -8;
 284    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 285    case PIPE_CAP_MAX_TEXEL_OFFSET:
 286       return 7;
 287    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 288       return 0;
 289    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 290       return 65536;
 291
 292    /* Render targets. */
 293    case PIPE_CAP_MAX_RENDER_TARGETS:
 294       return 1;
 295
 296    /* Viewports and scissors. */
 297    case PIPE_CAP_MAX_VIEWPORTS:
 298       return 1;
 299
 300    /* Timer queries. */
 301    case PIPE_CAP_QUERY_TIME_ELAPSED:
 302    case PIPE_CAP_OCCLUSION_QUERY:
 303       return 0;
 304    case PIPE_CAP_QUERY_TIMESTAMP:
 305       return 1;
 306    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 307       return 0;
 308
 309    /* Preferences */
 310    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 311       return 0;
 312
 313    case PIPE_CAP_PCI_GROUP:
 314    case PIPE_CAP_PCI_BUS:
 315    case PIPE_CAP_PCI_DEVICE:
 316    case PIPE_CAP_PCI_FUNCTION:
 317       return 0;
 318    case PIPE_CAP_VENDOR_ID:
 319    case PIPE_CAP_DEVICE_ID:
 320       return 0xFFFFFFFF;
 321    case PIPE_CAP_ACCELERATED:
 322       return 1;
 323    case PIPE_CAP_VIDEO_MEMORY:
 324       return 0;
 325    case PIPE_CAP_UMA:
 326       return 1;
 327    }
 328
 329    debug_printf("unknown param %d", param);
 330    return 0;
 331 }
 332
 333 static float
 334 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 335 {
 336    switch (param) {
 337    case PIPE_CAPF_MAX_LINE_WIDTH:
 338    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 339    case PIPE_CAPF_MAX_POINT_WIDTH:
 340    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 341       return 8192.0f;
 342    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 343       return 16.0f;
 344    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 345       return 16.0f;
 346    case PIPE_CAPF_GUARD_BAND_LEFT:
 347    case PIPE_CAPF_GUARD_BAND_TOP:
 348    case PIPE_CAPF_GUARD_BAND_RIGHT:
 349    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 350       return 0.0f;
 351    }
 352
 353    debug_printf("unknown paramf %d", param);
 354    return 0;
 355 }
 356
 357 static int
 358 etna_screen_get_shader_param(struct pipe_screen *pscreen,
 359                              enum pipe_shader_type shader,
 360                              enum pipe_shader_cap param)
 361 {
 362    struct etna_screen *screen = etna_screen(pscreen);
 363
 364    switch (shader) {
 365    case PIPE_SHADER_FRAGMENT:
 366    case PIPE_SHADER_VERTEX:
 367       break;
 368    case PIPE_SHADER_COMPUTE:
 369    case PIPE_SHADER_GEOMETRY:
 370    case PIPE_SHADER_TESS_CTRL:
 371    case PIPE_SHADER_TESS_EVAL:
 372       return 0;
 373    default:
 374       DBG("unknown shader type %d", shader);
 375       return 0;
 376    }
 377
 378    switch (param) {
 379    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 380    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 381    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 382    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 383       return ETNA_MAX_TOKENS;
 384    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 385       return ETNA_MAX_DEPTH; /* XXX */
 386    case PIPE_SHADER_CAP_MAX_INPUTS:
 387       /* Maximum number of inputs for the vertex shader is the number
 388        * of vertex elements - each element defines one vertex shader
 389        * input register.  For the fragment shader, this is the number
 390        * of varyings. */
 391       return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
 392                                             : screen->specs.vertex_max_elements;
 393    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 394       return 16; /* see VIVS_VS_OUTPUT */
 395    case PIPE_SHADER_CAP_MAX_TEMPS:
 396       return 64; /* Max native temporaries. */
 397    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 398       return 1;
 399    case PIPE_SHADER_CAP_MAX_PREDS:
 400       return 0; /* nothing uses this */
 401    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 402       return 1;
 403    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 404    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 405    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 406    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 407       return 1;
 408    case PIPE_SHADER_CAP_SUBROUTINES:
 409       return 0;
 410    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 411       return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 412    case PIPE_SHADER_CAP_INTEGERS:
 413       return 0;
 414    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 415    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 416       return shader == PIPE_SHADER_FRAGMENT
 417                 ? screen->specs.fragment_sampler_count
 418                 : screen->specs.vertex_sampler_count;
 419    case PIPE_SHADER_CAP_PREFERRED_IR:
 420       return PIPE_SHADER_IR_TGSI;
 421    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 422       return 4096;
 423    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 424    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 425    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 426    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 427       return false;
 428    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 429       return 0;
 430    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 431       return 32;
 432    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 433    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 434    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 435       return 0;
 436    }
 437
 438    debug_printf("unknown shader param %d", param);
 439    return 0;
 440 }
 441
 442 static uint64_t
 443 etna_screen_get_timestamp(struct pipe_screen *pscreen)
 444 {
 445    return os_time_get_nano();
 446 }
 447
 448 static bool
 449 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt)
 450 {
 451    if (fmt == TEXTURE_FORMAT_ETC1)
 452       return VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
 453
 454    if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
 455       return VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 456
 457    return true;
 458 }
 459
 460 static boolean
 461 etna_screen_is_format_supported(struct pipe_screen *pscreen,
 462                                 enum pipe_format format,
 463                                 enum pipe_texture_target target,
 464                                 unsigned sample_count, unsigned usage)
 465 {
 466    struct etna_screen *screen = etna_screen(pscreen);
 467    unsigned allowed = 0;
 468
 469    if (target != PIPE_BUFFER &&
 470        target != PIPE_TEXTURE_1D &&
 471        target != PIPE_TEXTURE_2D &&
 472        target != PIPE_TEXTURE_3D &&
 473        target != PIPE_TEXTURE_CUBE &&
 474        target != PIPE_TEXTURE_RECT)
 475       return FALSE;
 476
 477    if (usage & PIPE_BIND_RENDER_TARGET) {
 478       /* If render target, must be RS-supported format that is not rb swapped.
 479        * Exposing rb swapped (or other swizzled) formats for rendering would
 480        * involve swizzing in the pixel shader.
 481        */
 482       if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) {
 483          /* Validate MSAA; number of samples must be allowed, and render target
 484           * must have MSAA'able format. */
 485          if (sample_count > 1) {
 486             if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
 487                 translate_msaa_format(format) != ETNA_NO_MATCH) {
 488                allowed |= PIPE_BIND_RENDER_TARGET;
 489             }
 490          } else {
 491             allowed |= PIPE_BIND_RENDER_TARGET;
 492          }
 493       }
 494    }
 495
 496    if (usage & PIPE_BIND_DEPTH_STENCIL) {
 497       if (translate_depth_format(format) != ETNA_NO_MATCH)
 498          allowed |= PIPE_BIND_DEPTH_STENCIL;
 499    }
 500
 501    if (usage & PIPE_BIND_SAMPLER_VIEW) {
 502       uint32_t fmt = translate_texture_format(format);
 503
 504       if (!gpu_supports_texure_format(screen, fmt))
 505          fmt = ETNA_NO_MATCH;
 506
 507       if (sample_count < 2 && fmt != ETNA_NO_MATCH)
 508          allowed |= PIPE_BIND_SAMPLER_VIEW;
 509    }
 510
 511    if (usage & PIPE_BIND_VERTEX_BUFFER) {
 512       if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
 513          allowed |= PIPE_BIND_VERTEX_BUFFER;
 514    }
 515
 516    if (usage & PIPE_BIND_INDEX_BUFFER) {
 517       /* must be supported index format */
 518       if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
 519           (format == PIPE_FORMAT_I32_UINT &&
 520            VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
 521          allowed |= PIPE_BIND_INDEX_BUFFER;
 522       }
 523    }
 524
 525    /* Always allowed */
 526    allowed |=
 527       usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
 528
 529    if (usage != allowed) {
 530       DBG("not supported: format=%s, target=%d, sample_count=%d, "
 531           "usage=%x, allowed=%x",
 532           util_format_name(format), target, sample_count, usage, allowed);
 533    }
 534
 535    return usage == allowed;
 536 }
 537
 538 static boolean
 539 etna_get_specs(struct etna_screen *screen)
 540 {
 541    uint64_t val;
 542    uint32_t instruction_count;
 543
 544    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
 545       DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
 546       goto fail;
 547    }
 548    instruction_count = val;
 549
 550    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
 551                           &val)) {
 552       DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
 553       goto fail;
 554    }
 555    screen->specs.vertex_output_buffer_size = val;
 556
 557    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
 558       DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
 559       goto fail;
 560    }
 561    screen->specs.vertex_cache_size = val;
 562
 563    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
 564       DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
 565       goto fail;
 566    }
 567    screen->specs.shader_core_count = val;
 568
 569    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
 570       DBG("could not get ETNA_GPU_STREAM_COUNT");
 571       goto fail;
 572    }
 573    screen->specs.stream_count = val;
 574
 575    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
 576       DBG("could not get ETNA_GPU_REGISTER_MAX");
 577       goto fail;
 578    }
 579    screen->specs.max_registers = val;
 580
 581    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
 582       DBG("could not get ETNA_GPU_PIXEL_PIPES");
 583       goto fail;
 584    }
 585    screen->specs.pixel_pipes = val;
 586
 587    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
 588       DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
 589       goto fail;
 590    }
 591    if (val == 0) {
 592       fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
 593       val = 168;
 594    }
 595    screen->specs.num_constants = val;
 596
 597    screen->specs.can_supertile =
 598       VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
 599    screen->specs.bits_per_tile =
 600       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
 601    screen->specs.ts_clear_value =
 602       VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
 603                                                            : 0x11111111;
 604
 605    /* vertex and fragment samplers live in one address space */
 606    screen->specs.vertex_sampler_offset = 8;
 607    screen->specs.fragment_sampler_count = 8;
 608    screen->specs.vertex_sampler_count = 4;
 609    screen->specs.vs_need_z_div =
 610       screen->model < 0x1000 && screen->model != 0x880;
 611    screen->specs.has_sin_cos_sqrt =
 612       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
 613    screen->specs.has_sign_floor_ceil =
 614       VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
 615    screen->specs.has_shader_range_registers =
 616       screen->model >= 0x1000 || screen->model == 0x880;
 617    screen->specs.npot_tex_any_wrap =
 618       VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
 619    screen->specs.has_new_sin_cos =
 620       VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
 621
 622    if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
 623       /* GC3000 - this core is capable of loading shaders from
 624        * memory. It can also run shaders from registers, as a fallback, but
 625        * "max_instructions" does not have the correct value. It has place for
 626        * 2*256 instructions just like GC2000, but the offsets are slightly
 627        * different.
 628        */
 629       screen->specs.vs_offset = 0xC000;
 630       /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
 631        * this mirror for writing PS instructions, probably safest to do the
 632        * same.
 633        */
 634       screen->specs.ps_offset = 0x8000 + 0x1000;
 635       screen->specs.max_instructions = 256;
 636    } else {
 637       if (instruction_count > 256) { /* unified instruction memory? */
 638          screen->specs.vs_offset = 0xC000;
 639          screen->specs.ps_offset = 0xD000; /* like vivante driver */
 640          screen->specs.max_instructions = 256;
 641       } else {
 642          screen->specs.vs_offset = 0x4000;
 643          screen->specs.ps_offset = 0x6000;
 644          screen->specs.max_instructions = instruction_count / 2;
 645       }
 646    }
 647
 648    if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
 649       screen->specs.max_varyings = 12;
 650       screen->specs.vertex_max_elements = 16;
 651    } else {
 652       screen->specs.max_varyings = 8;
 653       /* Etna_viv documentation seems confused over the correct value
 654        * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
 655        * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
 656       screen->specs.vertex_max_elements = 10;
 657    }
 658
 659    /* Etna_viv documentation does not indicate where varyings above 8 are
 660     * stored. Moreover, if we are passed more than 8 varyings, we will
 661     * walk off the end of some arrays. Limit the maximum number of varyings. */
 662    if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
 663       screen->specs.max_varyings = ETNA_NUM_VARYINGS;
 664
 665    /* from QueryShaderCaps in kernel driver */
 666    if (screen->model < chipModel_GC4000) {
 667       screen->specs.max_vs_uniforms = 168;
 668       screen->specs.max_ps_uniforms = 64;
 669    } else {
 670       screen->specs.max_vs_uniforms = 256;
 671       screen->specs.max_ps_uniforms = 256;
 672    }
 673
 674    screen->specs.max_texture_size =
 675       VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
 676    screen->specs.max_rendertarget_size =
 677       VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
 678
 679    return true;
 680
 681 fail:
 682    return false;
 683 }
 684
 685 boolean
 686 etna_screen_bo_get_handle(struct pipe_screen *pscreen, struct etna_bo *bo,
 687                           unsigned stride, struct winsys_handle *whandle)
 688 {
 689    whandle->stride = stride;
 690
 691    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 692       return etna_bo_get_name(bo, &whandle->handle) == 0;
 693    } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
 694       whandle->handle = etna_bo_handle(bo);
 695       return TRUE;
 696    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 697       whandle->handle = etna_bo_dmabuf(bo);
 698       return TRUE;
 699    } else {
 700       return FALSE;
 701    }
 702 }
 703
 704 struct etna_bo *
 705 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
 706                            struct winsys_handle *whandle, unsigned *out_stride)
 707 {
 708    struct etna_screen *screen = etna_screen(pscreen);
 709    struct etna_bo *bo;
 710
 711    if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 712       bo = etna_bo_from_name(screen->dev, whandle->handle);
 713    } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
 714       bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
 715    } else {
 716       DBG("Attempt to import unsupported handle type %d", whandle->type);
 717       return NULL;
 718    }
 719
 720    if (!bo) {
 721       DBG("ref name 0x%08x failed", whandle->handle);
 722       return NULL;
 723    }
 724
 725    *out_stride = whandle->stride;
 726
 727    return bo;
 728 }
 729
 730 struct pipe_screen *
 731 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
 732                    struct renderonly *ro)
 733 {
 734    struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
 735    struct pipe_screen *pscreen;
 736    uint64_t val;
 737
 738    if (!screen)
 739       return NULL;
 740
 741    pscreen = &screen->base;
 742    screen->dev = dev;
 743    screen->gpu = gpu;
 744    screen->ro = renderonly_dup(ro);
 745
 746    if (!screen->ro) {
 747       DBG("could not create renderonly object");
 748       goto fail;
 749    }
 750
 751    etna_mesa_debug = debug_get_option_etna_mesa_debug();
 752
 753    /* FIXME: Disable tile status for stability at the moment */
 754    etna_mesa_debug |= ETNA_DBG_NO_TS;
 755
 756    screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
 757    if (!screen->pipe) {
 758       DBG("could not create 3d pipe");
 759       goto fail;
 760    }
 761
 762    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
 763       DBG("could not get ETNA_GPU_MODEL");
 764       goto fail;
 765    }
 766    screen->model = val;
 767
 768    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
 769       DBG("could not get ETNA_GPU_REVISION");
 770       goto fail;
 771    }
 772    screen->revision = val;
 773
 774    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
 775       DBG("could not get ETNA_GPU_FEATURES_0");
 776       goto fail;
 777    }
 778    screen->features[0] = val;
 779
 780    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
 781       DBG("could not get ETNA_GPU_FEATURES_1");
 782       goto fail;
 783    }
 784    screen->features[1] = val;
 785
 786    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
 787       DBG("could not get ETNA_GPU_FEATURES_2");
 788       goto fail;
 789    }
 790    screen->features[2] = val;
 791
 792    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
 793       DBG("could not get ETNA_GPU_FEATURES_3");
 794       goto fail;
 795    }
 796    screen->features[3] = val;
 797
 798    if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
 799       DBG("could not get ETNA_GPU_FEATURES_4");
 800       goto fail;
 801    }
 802    screen->features[4] = val;
 803
 804    if (!etna_get_specs(screen))
 805       goto fail;
 806
 807    pscreen->destroy = etna_screen_destroy;
 808    pscreen->get_param = etna_screen_get_param;
 809    pscreen->get_paramf = etna_screen_get_paramf;
 810    pscreen->get_shader_param = etna_screen_get_shader_param;
 811
 812    pscreen->get_name = etna_screen_get_name;
 813    pscreen->get_vendor = etna_screen_get_vendor;
 814    pscreen->get_device_vendor = etna_screen_get_device_vendor;
 815
 816    pscreen->get_timestamp = etna_screen_get_timestamp;
 817    pscreen->context_create = etna_context_create;
 818    pscreen->is_format_supported = etna_screen_is_format_supported;
 819
 820    etna_fence_screen_init(pscreen);
 821    etna_query_screen_init(pscreen);
 822    etna_resource_screen_init(pscreen);
 823
 824    slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
 825
 826    return pscreen;
 827
 828 fail:
 829    etna_screen_destroy(pscreen);
 830    return NULL;
 831 }