src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_helpers.h"
  41 #include "util/u_inlines.h"
  42 #include "util/u_math.h"
  43 #include "util/u_memory.h"
  44
  45 static void
  46 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  47 {
  48    struct etna_context *ctx = etna_context(pctx);
  49    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  50
  51    ctx->stencil_ref_s = *sr;
  52
  53    cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
  54    /* rest of bits weaved in from depth_stencil_alpha */
  55    cs->PE_STENCIL_CONFIG_EXT =
  56       VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
  57    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  58 }
  59
  60 static void
  61 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  62 {
  63    /* NOOP */
  64 }
  65
  66 static void
  67 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  68 {
  69    struct etna_context *ctx = etna_context(pctx);
  70
  71    ctx->sample_mask = sample_mask;
  72    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  73 }
  74
  75 static void
  76 etna_set_constant_buffer(struct pipe_context *pctx,
  77       enum pipe_shader_type shader, uint index,
  78       const struct pipe_constant_buffer *cb)
  79 {
  80    struct etna_context *ctx = etna_context(pctx);
  81
  82    if (unlikely(index > 0)) {
  83       DBG("Unhandled buffer index %i", index);
  84       return;
  85    }
  86
  87
  88    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
  89
  90    /* Note that the state tracker can unbind constant buffers by
  91     * passing NULL here. */
  92    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  93       return;
  94
  95    /* there is no support for ARB_uniform_buffer_object */
  96    assert(cb->buffer == NULL && cb->user_buffer != NULL);
  97
  98    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
  99 }
 100
 101 static void
 102 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 103 {
 104    struct etna_resource *res = etna_resource(pres);
 105
 106    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 107       /* The render buffer is older than the texture buffer. Copy it over. */
 108       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 109       res->seqno = etna_resource(res->texture)->seqno;
 110    }
 111 }
 112
 113 static void
 114 etna_set_framebuffer_state(struct pipe_context *pctx,
 115       const struct pipe_framebuffer_state *sv)
 116 {
 117    struct etna_context *ctx = etna_context(pctx);
 118    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 119    int nr_samples_color = -1;
 120    int nr_samples_depth = -1;
 121
 122    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 123    uint32_t ts_mem_config = 0;
 124
 125    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 126       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 127       struct etna_resource *res = etna_resource(cbuf->base.texture);
 128       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 129
 130       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 131       etna_update_render_resource(pctx, cbuf->base.texture);
 132
 133       pipe_surface_reference(&cs->cbuf, &cbuf->base);
 134       cs->PE_COLOR_FORMAT =
 135          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 136          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 137          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 138          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 139          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 140       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 141        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 142        * but only if we set the bits above. */
 143       /* merged with depth_stencil_alpha */
 144       if ((cbuf->surf.offset & 63) ||
 145           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 146          /* XXX Must make temporary surface here.
 147           * Need the same mechanism on gc2000 when we want to do mipmap
 148           * generation by
 149           * rendering to levels > 1 due to multitiled / tiled conversion. */
 150          BUG("Alignment error, trying to render to offset %08x with tile "
 151              "stride %i",
 152              cbuf->surf.offset, cbuf->surf.stride * 4);
 153       }
 154
 155       if (ctx->specs.pixel_pipes == 1) {
 156          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 157          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 158       } else {
 159          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 160          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 161          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 162             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 163             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 164          }
 165       }
 166       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 167
 168       if (cbuf->surf.ts_size) {
 169          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 170
 171          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 172          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 173
 174          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 175          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 176       }
 177
 178       /* MSAA */
 179       if (cbuf->base.texture->nr_samples > 1)
 180          ts_mem_config |=
 181             VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION | translate_msaa_format(cbuf->base.format);
 182
 183       nr_samples_color = cbuf->base.texture->nr_samples;
 184    } else {
 185       pipe_surface_reference(&cs->cbuf, NULL);
 186       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 187        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 188        * color target */
 189       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 190       cs->PE_COLOR_STRIDE = 0;
 191       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 192       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 193
 194       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 195       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 196          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 197    }
 198
 199    if (sv->zsbuf != NULL) {
 200       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 201       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 202
 203       etna_update_render_resource(pctx, zsbuf->base.texture);
 204
 205       pipe_surface_reference(&cs->zsbuf, &zsbuf->base);
 206       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 207
 208       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 209       unsigned depth_bits =
 210          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 211       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 212
 213       cs->PE_DEPTH_CONFIG =
 214          depth_format |
 215          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 216          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 217          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 218          ;
 219       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 220       /* merged with depth_stencil_alpha */
 221
 222       if (ctx->specs.pixel_pipes == 1) {
 223          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 224          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 225       } else {
 226          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 227             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 228             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 229          }
 230       }
 231
 232       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 233       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 234       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 235
 236       if (zsbuf->surf.ts_size) {
 237          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 238
 239          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 240          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 241
 242          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 243          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 244       }
 245
 246       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 247
 248       /* MSAA */
 249       if (zsbuf->base.texture->nr_samples > 1)
 250          /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 251           * Disable without MSAA for now, as it causes corruption in glquake. */
 252          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 253
 254       nr_samples_depth = zsbuf->base.texture->nr_samples;
 255    } else {
 256       pipe_surface_reference(&cs->zsbuf, NULL);
 257       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 258       cs->PE_DEPTH_ADDR.bo = NULL;
 259       cs->PE_DEPTH_STRIDE = 0;
 260       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 261       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 262
 263       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 264          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 265    }
 266
 267    /* MSAA setup */
 268    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 269        nr_samples_depth != nr_samples_color) {
 270       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 271           nr_samples_color, nr_samples_depth);
 272    }
 273
 274    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 275    case 0:
 276    case 1: /* Are 0 and 1 samples allowed? */
 277       cs->GL_MULTI_SAMPLE_CONFIG =
 278          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 279       cs->msaa_mode = false;
 280       break;
 281    case 2:
 282       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 283       cs->msaa_mode = true; /* Add input to PS */
 284       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 285       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 286       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 287       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 288       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 289       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 290       break;
 291    case 4:
 292       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 293       cs->msaa_mode = true; /* Add input to PS */
 294       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 295       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 296       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 297       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 298       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 299       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 300       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 301       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 302       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 303       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 304       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 305       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 306       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 307       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 308       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 309       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 310       break;
 311    }
 312
 313    /* Scissor setup */
 314    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 315    cs->SE_SCISSOR_TOP = 0;
 316    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 317    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 318    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 319    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 320
 321    cs->TS_MEM_CONFIG = ts_mem_config;
 322
 323    /* Single buffer setup. There is only one switch for this, not a separate
 324     * one per color buffer / depth buffer. To keep the logic simple always use
 325     * single buffer when this feature is available.
 326     */
 327    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 328
 329    ctx->framebuffer_s = *sv; /* keep copy of original structure */
 330    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 331 }
 332
 333 static void
 334 etna_set_polygon_stipple(struct pipe_context *pctx,
 335       const struct pipe_poly_stipple *stipple)
 336 {
 337    /* NOP */
 338 }
 339
 340 static void
 341 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 342       unsigned num_scissors, const struct pipe_scissor_state *ss)
 343 {
 344    struct etna_context *ctx = etna_context(pctx);
 345    struct compiled_scissor_state *cs = &ctx->scissor;
 346    assert(ss->minx <= ss->maxx);
 347    assert(ss->miny <= ss->maxy);
 348
 349    /* note that this state is only used when rasterizer_state->scissor is on */
 350    ctx->scissor_s = *ss;
 351    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 352    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 353    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 354    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 355    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 356    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 357
 358    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 359 }
 360
 361 static void
 362 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 363       unsigned num_scissors, const struct pipe_viewport_state *vs)
 364 {
 365    struct etna_context *ctx = etna_context(pctx);
 366    struct compiled_viewport_state *cs = &ctx->viewport;
 367
 368    ctx->viewport_s = *vs;
 369    /**
 370     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 371     * -1..1 to 0..1.
 372     * scaling and translation to 0..1 already happened, so remove that
 373     *
 374     * z' = (z * 2 - 1) * scale + translate
 375     *    = z * (2 * scale) + (translate - scale)
 376     *
 377     * scale' = 2 * scale
 378     * translate' = translate - scale
 379     */
 380
 381    /* must be fixp as v4 state deltas assume it is */
 382    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 383    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 384    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 385    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 386    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 387    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 388
 389    /* Compute scissor rectangle (fixp) from viewport.
 390     * Make sure left is always < right and top always < bottom.
 391     */
 392    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 393    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 394    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 395    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 396    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 397    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 398    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 399    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 400
 401    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 402    cs->PE_DEPTH_FAR = fui(1.0);
 403    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 404 }
 405
 406 static void
 407 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 408       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 409 {
 410    struct etna_context *ctx = etna_context(pctx);
 411    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 412
 413    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 414    so->count = util_last_bit(so->enabled_mask);
 415
 416    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 417       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 418       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 419
 420       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 421                                        etna_usermem_map */
 422
 423       if (vbi->buffer.resource) { /* GPU buffer */
 424          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 425          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 426          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 427          cs->FE_VERTEX_STREAM_CONTROL =
 428             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 429       } else {
 430          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 431          cs->FE_VERTEX_STREAM_CONTROL = 0;
 432       }
 433    }
 434
 435    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 436 }
 437
 438 static void
 439 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 440 {
 441    struct etna_context *ctx = etna_context(pctx);
 442
 443    ctx->blend = bs;
 444    ctx->dirty |= ETNA_DIRTY_BLEND;
 445 }
 446
 447 static void
 448 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 449 {
 450    FREE(bs);
 451 }
 452
 453 static void
 454 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 455 {
 456    struct etna_context *ctx = etna_context(pctx);
 457
 458    ctx->rasterizer = rs;
 459    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 460 }
 461
 462 static void
 463 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 464 {
 465    FREE(rs);
 466 }
 467
 468 static void
 469 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 470 {
 471    struct etna_context *ctx = etna_context(pctx);
 472
 473    ctx->zsa = zs;
 474    ctx->dirty |= ETNA_DIRTY_ZSA;
 475 }
 476
 477 static void
 478 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 479 {
 480    FREE(zs);
 481 }
 482
 483 /** Create vertex element states, which define a layout for fetching
 484  * vertices for rendering.
 485  */
 486 static void *
 487 etna_vertex_elements_state_create(struct pipe_context *pctx,
 488       unsigned num_elements, const struct pipe_vertex_element *elements)
 489 {
 490    struct etna_context *ctx = etna_context(pctx);
 491    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 492
 493    if (!cs)
 494       return NULL;
 495
 496    if (num_elements > ctx->specs.vertex_max_elements) {
 497       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 498           ctx->specs.vertex_max_elements);
 499       return NULL;
 500    }
 501
 502    /* XXX could minimize number of consecutive stretches here by sorting, and
 503     * permuting the inputs in shader or does Mesa do this already? */
 504
 505    /* Check that vertex element binding is compatible with hardware; thus
 506     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 507     * uses more streams than is supported, and u_vbuf should have done some
 508     * reorganization for compatibility. */
 509
 510    /* TODO: does mesa this for us? */
 511    bool incompatible = false;
 512    for (unsigned idx = 0; idx < num_elements; ++idx) {
 513       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 514          incompatible = true;
 515    }
 516
 517    cs->num_elements = num_elements;
 518    if (incompatible || num_elements == 0) {
 519       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 520       FREE(cs);
 521       return NULL;
 522    }
 523
 524    unsigned start_offset = 0; /* start of current consecutive stretch */
 525    bool nonconsecutive = true; /* previous value of nonconsecutive */
 526
 527    for (unsigned idx = 0; idx < num_elements; ++idx) {
 528       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 529       unsigned end_offset = elements[idx].src_offset + element_size;
 530       uint32_t format_type, normalize;
 531
 532       if (nonconsecutive)
 533          start_offset = elements[idx].src_offset;
 534
 535       /* maximum vertex size is 256 bytes */
 536       assert(element_size != 0 && end_offset <= 256);
 537
 538       /* check whether next element is consecutive to this one */
 539       nonconsecutive = (idx == (num_elements - 1)) ||
 540                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 541                        end_offset != elements[idx + 1].src_offset;
 542
 543       format_type = translate_vertex_format_type(elements[idx].src_format);
 544       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 545
 546       assert(format_type != ETNA_NO_MATCH);
 547       assert(normalize != ETNA_NO_MATCH);
 548
 549       if (ctx->specs.halti < 5) {
 550          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 551             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 552             format_type |
 553             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 554             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 555             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 556             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 557             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 558       } else { /* HALTI5 spread vertex attrib config over two registers */
 559          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 560             format_type |
 561             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 562             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 563             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) |
 564             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 565          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 566             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 567             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 568       }
 569       cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */
 570    }
 571
 572    return cs;
 573 }
 574
 575 static void
 576 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 577 {
 578    FREE(ve);
 579 }
 580
 581 static void
 582 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 583 {
 584    struct etna_context *ctx = etna_context(pctx);
 585
 586    ctx->vertex_elements = ve;
 587    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 588 }
 589
 590 static bool
 591 etna_update_ts_config(struct etna_context *ctx)
 592 {
 593    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 594
 595    if (ctx->framebuffer_s.nr_cbufs > 0) {
 596       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 597
 598       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 599          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 600       } else {
 601          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 602       }
 603    }
 604
 605    if (ctx->framebuffer_s.zsbuf) {
 606       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 607
 608       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 609          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 610       } else {
 611          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 612       }
 613    }
 614
 615    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 616        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 617       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 618       ctx->dirty |= ETNA_DIRTY_TS;
 619    }
 620
 621    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 622
 623    return true;
 624 }
 625
 626 struct etna_state_updater {
 627    bool (*update)(struct etna_context *ctx);
 628    uint32_t dirty;
 629 };
 630
 631 static const struct etna_state_updater etna_state_updates[] = {
 632    {
 633       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 634    },
 635    {
 636       etna_shader_link, ETNA_DIRTY_SHADER,
 637    },
 638    {
 639       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 640    },
 641    {
 642       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 643    },
 644    {
 645       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 646    }
 647 };
 648
 649 bool
 650 etna_state_update(struct etna_context *ctx)
 651 {
 652    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 653       if (ctx->dirty & etna_state_updates[i].dirty)
 654          if (!etna_state_updates[i].update(ctx))
 655             return false;
 656
 657    return true;
 658 }
 659
 660 void
 661 etna_state_init(struct pipe_context *pctx)
 662 {
 663    pctx->set_blend_color = etna_set_blend_color;
 664    pctx->set_stencil_ref = etna_set_stencil_ref;
 665    pctx->set_clip_state = etna_set_clip_state;
 666    pctx->set_sample_mask = etna_set_sample_mask;
 667    pctx->set_constant_buffer = etna_set_constant_buffer;
 668    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 669    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 670    pctx->set_scissor_states = etna_set_scissor_states;
 671    pctx->set_viewport_states = etna_set_viewport_states;
 672
 673    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 674
 675    pctx->bind_blend_state = etna_blend_state_bind;
 676    pctx->delete_blend_state = etna_blend_state_delete;
 677
 678    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 679    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 680
 681    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 682    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 683
 684    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 685    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 686    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 687 }