src/gallium/drivers/etnaviv/etnaviv_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  *    Christian Gmeiner <christian.gmeiner@gmail.com>
  26  */
  27
  28 #include "etnaviv_state.h"
  29
  30 #include "hw/common.xml.h"
  31
  32 #include "etnaviv_blend.h"
  33 #include "etnaviv_clear_blit.h"
  34 #include "etnaviv_context.h"
  35 #include "etnaviv_format.h"
  36 #include "etnaviv_shader.h"
  37 #include "etnaviv_surface.h"
  38 #include "etnaviv_translate.h"
  39 #include "etnaviv_util.h"
  40 #include "util/u_framebuffer.h"
  41 #include "util/u_helpers.h"
  42 #include "util/u_inlines.h"
  43 #include "util/u_math.h"
  44 #include "util/u_memory.h"
  45
  46 static void
  47 etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *sr)
  48 {
  49    struct etna_context *ctx = etna_context(pctx);
  50    struct compiled_stencil_ref *cs = &ctx->stencil_ref;
  51
  52    ctx->stencil_ref_s = *sr;
  53
  54    cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
  55    /* rest of bits weaved in from depth_stencil_alpha */
  56    cs->PE_STENCIL_CONFIG_EXT =
  57       VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
  58    ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
  59 }
  60
  61 static void
  62 etna_set_clip_state(struct pipe_context *pctx, const struct pipe_clip_state *pcs)
  63 {
  64    /* NOOP */
  65 }
  66
  67 static void
  68 etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  69 {
  70    struct etna_context *ctx = etna_context(pctx);
  71
  72    ctx->sample_mask = sample_mask;
  73    ctx->dirty |= ETNA_DIRTY_SAMPLE_MASK;
  74 }
  75
  76 static void
  77 etna_set_constant_buffer(struct pipe_context *pctx,
  78       enum pipe_shader_type shader, uint index,
  79       const struct pipe_constant_buffer *cb)
  80 {
  81    struct etna_context *ctx = etna_context(pctx);
  82
  83    if (unlikely(index > 0)) {
  84       DBG("Unhandled buffer index %i", index);
  85       return;
  86    }
  87
  88
  89    util_copy_constant_buffer(&ctx->constant_buffer[shader], cb);
  90
  91    /* Note that the state tracker can unbind constant buffers by
  92     * passing NULL here. */
  93    if (unlikely(!cb || (!cb->buffer && !cb->user_buffer)))
  94       return;
  95
  96    /* there is no support for ARB_uniform_buffer_object */
  97    assert(cb->buffer == NULL && cb->user_buffer != NULL);
  98
  99    ctx->dirty |= ETNA_DIRTY_CONSTBUF;
 100 }
 101
 102 static void
 103 etna_update_render_resource(struct pipe_context *pctx, struct pipe_resource *pres)
 104 {
 105    struct etna_resource *res = etna_resource(pres);
 106
 107    if (res->texture && etna_resource_older(res, etna_resource(res->texture))) {
 108       /* The render buffer is older than the texture buffer. Copy it over. */
 109       etna_copy_resource(pctx, pres, res->texture, 0, pres->last_level);
 110       res->seqno = etna_resource(res->texture)->seqno;
 111    }
 112 }
 113
 114 static void
 115 etna_set_framebuffer_state(struct pipe_context *pctx,
 116       const struct pipe_framebuffer_state *sv)
 117 {
 118    struct etna_context *ctx = etna_context(pctx);
 119    struct compiled_framebuffer_state *cs = &ctx->framebuffer;
 120    int nr_samples_color = -1;
 121    int nr_samples_depth = -1;
 122
 123    /* Set up TS as well. Warning: this state is used by both the RS and PE */
 124    uint32_t ts_mem_config = 0;
 125    uint32_t pe_mem_config = 0;
 126
 127    if (sv->nr_cbufs > 0) { /* at least one color buffer? */
 128       struct etna_surface *cbuf = etna_surface(sv->cbufs[0]);
 129       struct etna_resource *res = etna_resource(cbuf->base.texture);
 130       bool color_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 131
 132       assert(res->layout & ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 133       etna_update_render_resource(pctx, cbuf->base.texture);
 134
 135       cs->PE_COLOR_FORMAT =
 136          VIVS_PE_COLOR_FORMAT_FORMAT(translate_rs_format(cbuf->base.format)) |
 137          VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
 138          VIVS_PE_COLOR_FORMAT_OVERWRITE |
 139          COND(color_supertiled, VIVS_PE_COLOR_FORMAT_SUPER_TILED) |
 140          COND(color_supertiled && ctx->specs.halti >= 5, VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW);
 141       /* VIVS_PE_COLOR_FORMAT_COMPONENTS() and
 142        * VIVS_PE_COLOR_FORMAT_OVERWRITE comes from blend_state
 143        * but only if we set the bits above. */
 144       /* merged with depth_stencil_alpha */
 145       if ((cbuf->surf.offset & 63) ||
 146           (((cbuf->surf.stride * 4) & 63) && cbuf->surf.height > 4)) {
 147          /* XXX Must make temporary surface here.
 148           * Need the same mechanism on gc2000 when we want to do mipmap
 149           * generation by
 150           * rendering to levels > 1 due to multitiled / tiled conversion. */
 151          BUG("Alignment error, trying to render to offset %08x with tile "
 152              "stride %i",
 153              cbuf->surf.offset, cbuf->surf.stride * 4);
 154       }
 155
 156       if (ctx->specs.pixel_pipes == 1) {
 157          cs->PE_COLOR_ADDR = cbuf->reloc[0];
 158          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 159       } else {
 160          /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
 161          assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
 162          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 163             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
 164             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 165          }
 166       }
 167       cs->PE_COLOR_STRIDE = cbuf->surf.stride;
 168
 169       if (cbuf->surf.ts_size) {
 170          cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
 171
 172          cs->TS_COLOR_STATUS_BASE = cbuf->ts_reloc;
 173          cs->TS_COLOR_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 174
 175          cs->TS_COLOR_SURFACE_BASE = cbuf->reloc[0];
 176          cs->TS_COLOR_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 177
 178          pe_mem_config |= VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(cbuf->level->ts_mode);
 179       }
 180
 181       /* MSAA */
 182       if (cbuf->base.texture->nr_samples > 1) {
 183          ts_mem_config |=
 184             VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
 185             VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(translate_msaa_format(cbuf->base.format));
 186       }
 187
 188       nr_samples_color = cbuf->base.texture->nr_samples;
 189    } else {
 190       /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and
 191        * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the
 192        * color target */
 193       cs->PE_COLOR_FORMAT = VIVS_PE_COLOR_FORMAT_OVERWRITE;
 194       cs->PE_COLOR_STRIDE = 0;
 195       cs->TS_COLOR_STATUS_BASE.bo = NULL;
 196       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 197
 198       cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
 199       for (int i = 0; i < ctx->specs.pixel_pipes; i++)
 200          cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
 201    }
 202
 203    if (sv->zsbuf != NULL) {
 204       struct etna_surface *zsbuf = etna_surface(sv->zsbuf);
 205       struct etna_resource *res = etna_resource(zsbuf->base.texture);
 206
 207       etna_update_render_resource(pctx, zsbuf->base.texture);
 208
 209       assert(res->layout &ETNA_LAYOUT_BIT_TILE); /* Cannot render to linear surfaces */
 210
 211       uint32_t depth_format = translate_depth_format(zsbuf->base.format);
 212       unsigned depth_bits =
 213          depth_format == VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 ? 16 : 24;
 214       bool depth_supertiled = (res->layout & ETNA_LAYOUT_BIT_SUPER) != 0;
 215
 216       cs->PE_DEPTH_CONFIG =
 217          depth_format |
 218          COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
 219          VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
 220          COND(ctx->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
 221          ;
 222       /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
 223       /* merged with depth_stencil_alpha */
 224
 225       if (ctx->specs.pixel_pipes == 1) {
 226          cs->PE_DEPTH_ADDR = zsbuf->reloc[0];
 227          cs->PE_DEPTH_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 228       } else {
 229          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
 230             cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
 231             cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 232          }
 233       }
 234
 235       cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
 236       cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
 237       cs->PE_DEPTH_NORMALIZE = fui(exp2f(depth_bits) - 1.0f);
 238
 239       if (zsbuf->surf.ts_size) {
 240          cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
 241
 242          cs->TS_DEPTH_STATUS_BASE = zsbuf->ts_reloc;
 243          cs->TS_DEPTH_STATUS_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 244
 245          cs->TS_DEPTH_SURFACE_BASE = zsbuf->reloc[0];
 246          cs->TS_DEPTH_SURFACE_BASE.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
 247
 248          pe_mem_config |= VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(zsbuf->level->ts_mode);
 249       }
 250
 251       ts_mem_config |= COND(depth_bits == 16, VIVS_TS_MEM_CONFIG_DEPTH_16BPP);
 252
 253       /* MSAA */
 254       if (zsbuf->base.texture->nr_samples > 1)
 255          /* XXX VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 256           * Disable without MSAA for now, as it causes corruption in glquake. */
 257          ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION;
 258
 259       nr_samples_depth = zsbuf->base.texture->nr_samples;
 260    } else {
 261       cs->PE_DEPTH_CONFIG = VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE;
 262       cs->PE_DEPTH_ADDR.bo = NULL;
 263       cs->PE_DEPTH_STRIDE = 0;
 264       cs->TS_DEPTH_STATUS_BASE.bo = NULL;
 265       cs->TS_DEPTH_SURFACE_BASE.bo = NULL;
 266
 267       for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
 268          cs->PE_PIPE_DEPTH_ADDR[i].bo = NULL;
 269    }
 270
 271    /* MSAA setup */
 272    if (nr_samples_depth != -1 && nr_samples_color != -1 &&
 273        nr_samples_depth != nr_samples_color) {
 274       BUG("Number of samples in color and depth texture must match (%i and %i respectively)",
 275           nr_samples_color, nr_samples_depth);
 276    }
 277
 278    switch (MAX2(nr_samples_depth, nr_samples_color)) {
 279    case 0:
 280    case 1: /* Are 0 and 1 samples allowed? */
 281       cs->GL_MULTI_SAMPLE_CONFIG =
 282          VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE;
 283       cs->msaa_mode = false;
 284       break;
 285    case 2:
 286       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X;
 287       cs->msaa_mode = true; /* Add input to PS */
 288       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 289       cs->RA_MULTISAMPLE_UNK00E10[0] = 0x0000aa22;
 290       cs->RA_CENTROID_TABLE[0] = 0x66aa2288;
 291       cs->RA_CENTROID_TABLE[1] = 0x88558800;
 292       cs->RA_CENTROID_TABLE[2] = 0x88881100;
 293       cs->RA_CENTROID_TABLE[3] = 0x33888800;
 294       break;
 295    case 4:
 296       cs->GL_MULTI_SAMPLE_CONFIG = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X;
 297       cs->msaa_mode = true; /* Add input to PS */
 298       cs->RA_MULTISAMPLE_UNK00E04 = 0x0;
 299       cs->RA_MULTISAMPLE_UNK00E10[0] = 0xeaa26e26;
 300       cs->RA_MULTISAMPLE_UNK00E10[1] = 0xe6ae622a;
 301       cs->RA_MULTISAMPLE_UNK00E10[2] = 0xaaa22a22;
 302       cs->RA_CENTROID_TABLE[0] = 0x4a6e2688;
 303       cs->RA_CENTROID_TABLE[1] = 0x888888a2;
 304       cs->RA_CENTROID_TABLE[2] = 0x888888ea;
 305       cs->RA_CENTROID_TABLE[3] = 0x888888c6;
 306       cs->RA_CENTROID_TABLE[4] = 0x46622a88;
 307       cs->RA_CENTROID_TABLE[5] = 0x888888ae;
 308       cs->RA_CENTROID_TABLE[6] = 0x888888e6;
 309       cs->RA_CENTROID_TABLE[7] = 0x888888ca;
 310       cs->RA_CENTROID_TABLE[8] = 0x262a2288;
 311       cs->RA_CENTROID_TABLE[9] = 0x886688a2;
 312       cs->RA_CENTROID_TABLE[10] = 0x888866aa;
 313       cs->RA_CENTROID_TABLE[11] = 0x668888a6;
 314       break;
 315    }
 316
 317    /* Scissor setup */
 318    cs->SE_SCISSOR_LEFT = 0; /* affected by rasterizer and scissor state as well */
 319    cs->SE_SCISSOR_TOP = 0;
 320    cs->SE_SCISSOR_RIGHT = (sv->width << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 321    cs->SE_SCISSOR_BOTTOM = (sv->height << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 322    cs->SE_CLIP_RIGHT = (sv->width << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 323    cs->SE_CLIP_BOTTOM = (sv->height << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 324
 325    cs->TS_MEM_CONFIG = ts_mem_config;
 326    cs->PE_MEM_CONFIG = pe_mem_config;
 327
 328    /* Single buffer setup. There is only one switch for this, not a separate
 329     * one per color buffer / depth buffer. To keep the logic simple always use
 330     * single buffer when this feature is available.
 331     */
 332    cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 3 : 0);
 333
 334    /* keep copy of original structure */
 335    util_copy_framebuffer_state(&ctx->framebuffer_s, sv);
 336    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
 337 }
 338
 339 static void
 340 etna_set_polygon_stipple(struct pipe_context *pctx,
 341       const struct pipe_poly_stipple *stipple)
 342 {
 343    /* NOP */
 344 }
 345
 346 static void
 347 etna_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
 348       unsigned num_scissors, const struct pipe_scissor_state *ss)
 349 {
 350    struct etna_context *ctx = etna_context(pctx);
 351    struct compiled_scissor_state *cs = &ctx->scissor;
 352    assert(ss->minx <= ss->maxx);
 353    assert(ss->miny <= ss->maxy);
 354
 355    /* note that this state is only used when rasterizer_state->scissor is on */
 356    ctx->scissor_s = *ss;
 357    cs->SE_SCISSOR_LEFT = (ss->minx << 16);
 358    cs->SE_SCISSOR_TOP = (ss->miny << 16);
 359    cs->SE_SCISSOR_RIGHT = (ss->maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 360    cs->SE_SCISSOR_BOTTOM = (ss->maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 361    cs->SE_CLIP_RIGHT = (ss->maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT;
 362    cs->SE_CLIP_BOTTOM = (ss->maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM;
 363
 364    ctx->dirty |= ETNA_DIRTY_SCISSOR;
 365 }
 366
 367 static void
 368 etna_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
 369       unsigned num_scissors, const struct pipe_viewport_state *vs)
 370 {
 371    struct etna_context *ctx = etna_context(pctx);
 372    struct compiled_viewport_state *cs = &ctx->viewport;
 373
 374    ctx->viewport_s = *vs;
 375    /**
 376     * For Vivante GPU, viewport z transformation is 0..1 to 0..1 instead of
 377     * -1..1 to 0..1.
 378     * scaling and translation to 0..1 already happened, so remove that
 379     *
 380     * z' = (z * 2 - 1) * scale + translate
 381     *    = z * (2 * scale) + (translate - scale)
 382     *
 383     * scale' = 2 * scale
 384     * translate' = translate - scale
 385     */
 386
 387    /* must be fixp as v4 state deltas assume it is */
 388    cs->PA_VIEWPORT_SCALE_X = etna_f32_to_fixp16(vs->scale[0]);
 389    cs->PA_VIEWPORT_SCALE_Y = etna_f32_to_fixp16(vs->scale[1]);
 390    cs->PA_VIEWPORT_SCALE_Z = fui(vs->scale[2] * 2.0f);
 391    cs->PA_VIEWPORT_OFFSET_X = etna_f32_to_fixp16(vs->translate[0]);
 392    cs->PA_VIEWPORT_OFFSET_Y = etna_f32_to_fixp16(vs->translate[1]);
 393    cs->PA_VIEWPORT_OFFSET_Z = fui(vs->translate[2] - vs->scale[2]);
 394
 395    /* Compute scissor rectangle (fixp) from viewport.
 396     * Make sure left is always < right and top always < bottom.
 397     */
 398    cs->SE_SCISSOR_LEFT = etna_f32_to_fixp16(MAX2(vs->translate[0] - fabsf(vs->scale[0]), 0.0f));
 399    cs->SE_SCISSOR_TOP = etna_f32_to_fixp16(MAX2(vs->translate[1] - fabsf(vs->scale[1]), 0.0f));
 400    uint32_t right_fixp = etna_f32_to_fixp16(MAX2(vs->translate[0] + fabsf(vs->scale[0]), 0.0f));
 401    uint32_t bottom_fixp = etna_f32_to_fixp16(MAX2(vs->translate[1] + fabsf(vs->scale[1]), 0.0f));
 402    cs->SE_SCISSOR_RIGHT = right_fixp + ETNA_SE_SCISSOR_MARGIN_RIGHT;
 403    cs->SE_SCISSOR_BOTTOM = bottom_fixp + ETNA_SE_SCISSOR_MARGIN_BOTTOM;
 404    cs->SE_CLIP_RIGHT = right_fixp + ETNA_SE_CLIP_MARGIN_RIGHT;
 405    cs->SE_CLIP_BOTTOM = bottom_fixp + ETNA_SE_CLIP_MARGIN_BOTTOM;
 406
 407    cs->PE_DEPTH_NEAR = fui(0.0); /* not affected if depth mode is Z (as in GL) */
 408    cs->PE_DEPTH_FAR = fui(1.0);
 409    ctx->dirty |= ETNA_DIRTY_VIEWPORT;
 410 }
 411
 412 static void
 413 etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
 414       unsigned num_buffers, const struct pipe_vertex_buffer *vb)
 415 {
 416    struct etna_context *ctx = etna_context(pctx);
 417    struct etna_vertexbuf_state *so = &ctx->vertex_buffer;
 418
 419    util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
 420    so->count = util_last_bit(so->enabled_mask);
 421
 422    for (unsigned idx = start_slot; idx < start_slot + num_buffers; ++idx) {
 423       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
 424       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 425
 426       assert(!vbi->is_user_buffer); /* XXX support user_buffer using
 427                                        etna_usermem_map */
 428
 429       if (vbi->buffer.resource) { /* GPU buffer */
 430          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
 431          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
 432          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
 433          cs->FE_VERTEX_STREAM_CONTROL =
 434             FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
 435       } else {
 436          cs->FE_VERTEX_STREAM_BASE_ADDR.bo = NULL;
 437          cs->FE_VERTEX_STREAM_CONTROL = 0;
 438       }
 439    }
 440
 441    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 442 }
 443
 444 static void
 445 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 446 {
 447    struct etna_context *ctx = etna_context(pctx);
 448
 449    ctx->blend = bs;
 450    ctx->dirty |= ETNA_DIRTY_BLEND;
 451 }
 452
 453 static void
 454 etna_blend_state_delete(struct pipe_context *pctx, void *bs)
 455 {
 456    FREE(bs);
 457 }
 458
 459 static void
 460 etna_rasterizer_state_bind(struct pipe_context *pctx, void *rs)
 461 {
 462    struct etna_context *ctx = etna_context(pctx);
 463
 464    ctx->rasterizer = rs;
 465    ctx->dirty |= ETNA_DIRTY_RASTERIZER;
 466 }
 467
 468 static void
 469 etna_rasterizer_state_delete(struct pipe_context *pctx, void *rs)
 470 {
 471    FREE(rs);
 472 }
 473
 474 static void
 475 etna_zsa_state_bind(struct pipe_context *pctx, void *zs)
 476 {
 477    struct etna_context *ctx = etna_context(pctx);
 478
 479    ctx->zsa = zs;
 480    ctx->dirty |= ETNA_DIRTY_ZSA;
 481 }
 482
 483 static void
 484 etna_zsa_state_delete(struct pipe_context *pctx, void *zs)
 485 {
 486    FREE(zs);
 487 }
 488
 489 /** Create vertex element states, which define a layout for fetching
 490  * vertices for rendering.
 491  */
 492 static void *
 493 etna_vertex_elements_state_create(struct pipe_context *pctx,
 494       unsigned num_elements, const struct pipe_vertex_element *elements)
 495 {
 496    struct etna_context *ctx = etna_context(pctx);
 497    struct compiled_vertex_elements_state *cs = CALLOC_STRUCT(compiled_vertex_elements_state);
 498
 499    if (!cs)
 500       return NULL;
 501
 502    if (num_elements > ctx->specs.vertex_max_elements) {
 503       BUG("number of elements (%u) exceeds chip maximum (%u)", num_elements,
 504           ctx->specs.vertex_max_elements);
 505       return NULL;
 506    }
 507
 508    /* XXX could minimize number of consecutive stretches here by sorting, and
 509     * permuting the inputs in shader or does Mesa do this already? */
 510
 511    /* Check that vertex element binding is compatible with hardware; thus
 512     * elements[idx].vertex_buffer_index are < stream_count. If not, the binding
 513     * uses more streams than is supported, and u_vbuf should have done some
 514     * reorganization for compatibility. */
 515
 516    /* TODO: does mesa this for us? */
 517    bool incompatible = false;
 518    for (unsigned idx = 0; idx < num_elements; ++idx) {
 519       if (elements[idx].vertex_buffer_index >= ctx->specs.stream_count || elements[idx].instance_divisor > 0)
 520          incompatible = true;
 521    }
 522
 523    cs->num_elements = num_elements;
 524    if (incompatible || num_elements == 0) {
 525       DBG("Error: zero vertex elements, or more vertex buffers used than supported");
 526       FREE(cs);
 527       return NULL;
 528    }
 529
 530    unsigned start_offset = 0; /* start of current consecutive stretch */
 531    bool nonconsecutive = true; /* previous value of nonconsecutive */
 532
 533    for (unsigned idx = 0; idx < num_elements; ++idx) {
 534       unsigned element_size = util_format_get_blocksize(elements[idx].src_format);
 535       unsigned end_offset = elements[idx].src_offset + element_size;
 536       uint32_t format_type, normalize;
 537
 538       if (nonconsecutive)
 539          start_offset = elements[idx].src_offset;
 540
 541       /* maximum vertex size is 256 bytes */
 542       assert(element_size != 0 && end_offset <= 256);
 543
 544       /* check whether next element is consecutive to this one */
 545       nonconsecutive = (idx == (num_elements - 1)) ||
 546                        elements[idx + 1].vertex_buffer_index != elements[idx].vertex_buffer_index ||
 547                        end_offset != elements[idx + 1].src_offset;
 548
 549       format_type = translate_vertex_format_type(elements[idx].src_format);
 550       normalize = translate_vertex_format_normalize(elements[idx].src_format);
 551
 552       assert(format_type != ETNA_NO_MATCH);
 553       assert(normalize != ETNA_NO_MATCH);
 554
 555       if (ctx->specs.halti < 5) {
 556          cs->FE_VERTEX_ELEMENT_CONFIG[idx] =
 557             COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) |
 558             format_type |
 559             VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 560             normalize | VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 561             VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(elements[idx].vertex_buffer_index) |
 562             VIVS_FE_VERTEX_ELEMENT_CONFIG_START(elements[idx].src_offset) |
 563             VIVS_FE_VERTEX_ELEMENT_CONFIG_END(end_offset - start_offset);
 564       } else { /* HALTI5 spread vertex attrib config over two registers */
 565          cs->NFE_GENERIC_ATTRIB_CONFIG0[idx] =
 566             format_type |
 567             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(util_format_get_nr_components(elements[idx].src_format)) |
 568             normalize | VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(ENDIAN_MODE_NO_SWAP) |
 569             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(elements[idx].vertex_buffer_index) |
 570             VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(elements[idx].src_offset);
 571          cs->NFE_GENERIC_ATTRIB_CONFIG1[idx] =
 572             COND(nonconsecutive, VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE) |
 573             VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(end_offset - start_offset);
 574       }
 575       cs->NFE_GENERIC_ATTRIB_SCALE[idx] = 0x3f800000; /* 1 for integer, 1.0 for float */
 576    }
 577
 578    return cs;
 579 }
 580
 581 static void
 582 etna_vertex_elements_state_delete(struct pipe_context *pctx, void *ve)
 583 {
 584    FREE(ve);
 585 }
 586
 587 static void
 588 etna_vertex_elements_state_bind(struct pipe_context *pctx, void *ve)
 589 {
 590    struct etna_context *ctx = etna_context(pctx);
 591
 592    ctx->vertex_elements = ve;
 593    ctx->dirty |= ETNA_DIRTY_VERTEX_ELEMENTS;
 594 }
 595
 596 static bool
 597 etna_update_ts_config(struct etna_context *ctx)
 598 {
 599    uint32_t new_ts_config = ctx->framebuffer.TS_MEM_CONFIG;
 600
 601    if (ctx->framebuffer_s.nr_cbufs > 0) {
 602       struct etna_surface *c_surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
 603
 604       if(c_surf->level->ts_size && c_surf->level->ts_valid) {
 605          new_ts_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 606       } else {
 607          new_ts_config &= ~VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
 608       }
 609    }
 610
 611    if (ctx->framebuffer_s.zsbuf) {
 612       struct etna_surface *zs_surf = etna_surface(ctx->framebuffer_s.zsbuf);
 613
 614       if(zs_surf->level->ts_size && zs_surf->level->ts_valid) {
 615          new_ts_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 616       } else {
 617          new_ts_config &= ~VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
 618       }
 619    }
 620
 621    if (new_ts_config != ctx->framebuffer.TS_MEM_CONFIG ||
 622        (ctx->dirty & ETNA_DIRTY_FRAMEBUFFER)) {
 623       ctx->framebuffer.TS_MEM_CONFIG = new_ts_config;
 624       ctx->dirty |= ETNA_DIRTY_TS;
 625    }
 626
 627    ctx->dirty &= ~ETNA_DIRTY_DERIVE_TS;
 628
 629    return true;
 630 }
 631
 632 struct etna_state_updater {
 633    bool (*update)(struct etna_context *ctx);
 634    uint32_t dirty;
 635 };
 636
 637 static const struct etna_state_updater etna_state_updates[] = {
 638    {
 639       etna_shader_update_vertex, ETNA_DIRTY_SHADER | ETNA_DIRTY_VERTEX_ELEMENTS,
 640    },
 641    {
 642       etna_shader_link, ETNA_DIRTY_SHADER,
 643    },
 644    {
 645       etna_update_blend, ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER
 646    },
 647    {
 648       etna_update_blend_color, ETNA_DIRTY_BLEND_COLOR | ETNA_DIRTY_FRAMEBUFFER,
 649    },
 650    {
 651       etna_update_ts_config, ETNA_DIRTY_DERIVE_TS,
 652    }
 653 };
 654
 655 bool
 656 etna_state_update(struct etna_context *ctx)
 657 {
 658    for (unsigned int i = 0; i < ARRAY_SIZE(etna_state_updates); i++)
 659       if (ctx->dirty & etna_state_updates[i].dirty)
 660          if (!etna_state_updates[i].update(ctx))
 661             return false;
 662
 663    return true;
 664 }
 665
 666 void
 667 etna_state_init(struct pipe_context *pctx)
 668 {
 669    pctx->set_blend_color = etna_set_blend_color;
 670    pctx->set_stencil_ref = etna_set_stencil_ref;
 671    pctx->set_clip_state = etna_set_clip_state;
 672    pctx->set_sample_mask = etna_set_sample_mask;
 673    pctx->set_constant_buffer = etna_set_constant_buffer;
 674    pctx->set_framebuffer_state = etna_set_framebuffer_state;
 675    pctx->set_polygon_stipple = etna_set_polygon_stipple;
 676    pctx->set_scissor_states = etna_set_scissor_states;
 677    pctx->set_viewport_states = etna_set_viewport_states;
 678
 679    pctx->set_vertex_buffers = etna_set_vertex_buffers;
 680
 681    pctx->bind_blend_state = etna_blend_state_bind;
 682    pctx->delete_blend_state = etna_blend_state_delete;
 683
 684    pctx->bind_rasterizer_state = etna_rasterizer_state_bind;
 685    pctx->delete_rasterizer_state = etna_rasterizer_state_delete;
 686
 687    pctx->bind_depth_stencil_alpha_state = etna_zsa_state_bind;
 688    pctx->delete_depth_stencil_alpha_state = etna_zsa_state_delete;
 689
 690    pctx->create_vertex_elements_state = etna_vertex_elements_state_create;
 691    pctx->delete_vertex_elements_state = etna_vertex_elements_state_delete;
 692    pctx->bind_vertex_elements_state = etna_vertex_elements_state_bind;
 693 }