2 * Copyright (c) 2012-2013 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_surface.h"
28 #include "etnaviv_screen.h"
30 #include "etnaviv_clear_blit.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_translate.h"
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "util/u_inlines.h"
36 #include "util/u_memory.h"
38 #include "hw/common.xml.h"
40 #include "drm-uapi/drm_fourcc.h"
42 static struct etna_resource
*
43 etna_render_handle_incompatible(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
45 struct etna_context
*ctx
= etna_context(pctx
);
46 struct etna_resource
*res
= etna_resource(prsc
);
47 bool need_multitiled
= ctx
->specs
.pixel_pipes
> 1 && !ctx
->specs
.single_buffer
;
48 bool want_supertiled
= ctx
->specs
.can_supertile
;
50 /* Resource is compatible if it is tiled and has multi tiling when required
51 * TODO: LINEAR_PE feature means render to linear is possible ?
53 if (res
->layout
!= ETNA_LAYOUT_LINEAR
&&
54 (!need_multitiled
|| (res
->layout
& ETNA_LAYOUT_BIT_MULTI
)))
58 struct pipe_resource templat
= *prsc
;
59 unsigned layout
= ETNA_LAYOUT_TILED
;
61 layout
|= ETNA_LAYOUT_BIT_MULTI
;
63 layout
|= ETNA_LAYOUT_BIT_SUPER
;
65 templat
.bind
&= (PIPE_BIND_DEPTH_STENCIL
| PIPE_BIND_RENDER_TARGET
|
68 etna_resource_alloc(pctx
->screen
, layout
,
69 DRM_FORMAT_MOD_LINEAR
, &templat
);
72 return etna_resource(res
->render
);
75 static struct pipe_surface
*
76 etna_create_surface(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
77 const struct pipe_surface
*templat
)
79 struct etna_context
*ctx
= etna_context(pctx
);
80 struct etna_resource
*rsc
= etna_render_handle_incompatible(pctx
, prsc
);
81 struct etna_surface
*surf
= CALLOC_STRUCT(etna_surface
);
86 assert(templat
->u
.tex
.first_layer
== templat
->u
.tex
.last_layer
);
87 unsigned layer
= templat
->u
.tex
.first_layer
;
88 unsigned level
= templat
->u
.tex
.level
;
89 assert(layer
< rsc
->base
.array_size
);
91 surf
->base
.context
= pctx
;
93 pipe_reference_init(&surf
->base
.reference
, 1);
94 pipe_resource_reference(&surf
->base
.texture
, &rsc
->base
);
95 pipe_resource_reference(&surf
->prsc
, prsc
);
97 /* Allocate a TS for the resource if there isn't one yet,
98 * and it is allowed by the hw (width is a multiple of 16).
99 * Avoid doing this for GPUs with MC1.0, as kernel sources
100 * indicate the tile status module bypasses the memory
103 if (VIV_FEATURE(ctx
->screen
, chipFeatures
, FAST_CLEAR
) &&
104 VIV_FEATURE(ctx
->screen
, chipMinorFeatures0
, MC20
) &&
106 /* needs to be RS/BLT compatible for transfer_map/unmap */
107 (rsc
->levels
[level
].padded_width
& ETNA_RS_WIDTH_MASK
) == 0 &&
108 (rsc
->levels
[level
].padded_height
& ETNA_RS_HEIGHT_MASK
) == 0 &&
109 etna_resource_hw_tileable(ctx
->specs
.use_blt
, prsc
)) {
110 etna_screen_resource_alloc_ts(pctx
->screen
, rsc
);
113 surf
->base
.texture
= &rsc
->base
;
114 surf
->base
.format
= templat
->format
;
115 surf
->base
.width
= rsc
->levels
[level
].width
;
116 surf
->base
.height
= rsc
->levels
[level
].height
;
117 surf
->base
.writable
= templat
->writable
; /* what is this for anyway */
118 surf
->base
.u
= templat
->u
;
120 surf
->level
= &rsc
->levels
[level
]; /* Keep pointer to actual level to set
121 * clear color on underlying resource
122 * instead of surface */
123 surf
->surf
= rsc
->levels
[level
]; /* Make copy of level to narrow down
124 * address to layer */
126 /* XXX we don't really need a copy but it's convenient */
127 surf
->surf
.offset
+= layer
* surf
->surf
.layer_stride
;
129 struct etna_resource_level
*lev
= &rsc
->levels
[level
];
131 /* Setup template relocations for this surface */
132 for (unsigned pipe
= 0; pipe
< ctx
->specs
.pixel_pipes
; ++pipe
) {
133 surf
->reloc
[pipe
].bo
= rsc
->bo
;
134 surf
->reloc
[pipe
].offset
= surf
->surf
.offset
;
135 surf
->reloc
[pipe
].flags
= 0;
138 /* In single buffer mode, both pixel pipes must point to the same address,
139 * for multi-tiled surfaces on the other hand the second pipe is expected to
140 * point halfway the image vertically.
142 if (rsc
->layout
& ETNA_LAYOUT_BIT_MULTI
)
143 surf
->reloc
[1].offset
= surf
->surf
.offset
+ lev
->stride
* lev
->padded_height
/ 2;
145 if (surf
->surf
.ts_size
) {
146 unsigned int layer_offset
= layer
* surf
->surf
.ts_layer_stride
;
147 assert(layer_offset
< surf
->surf
.ts_size
);
149 surf
->surf
.ts_offset
+= layer_offset
;
150 surf
->surf
.ts_size
-= layer_offset
;
151 surf
->surf
.ts_valid
= false;
153 surf
->ts_reloc
.bo
= rsc
->ts_bo
;
154 surf
->ts_reloc
.offset
= surf
->surf
.ts_offset
;
155 surf
->ts_reloc
.flags
= 0;
157 if (!ctx
->specs
.use_blt
) {
158 /* This (ab)uses the RS as a plain buffer memset().
159 * Currently uses a fixed row size of 64 bytes. Some benchmarking with
160 * different sizes may be in order. */
161 struct etna_bo
*ts_bo
= etna_resource(surf
->base
.texture
)->ts_bo
;
162 etna_compile_rs_state(ctx
, &surf
->clear_command
, &(struct rs_state
) {
163 .source_format
= RS_FORMAT_A8R8G8B8
,
164 .dest_format
= RS_FORMAT_A8R8G8B8
,
166 .dest_offset
= surf
->surf
.ts_offset
,
168 .dest_tiling
= ETNA_LAYOUT_TILED
,
169 .dither
= {0xffffffff, 0xffffffff},
171 .height
= etna_align_up(surf
->surf
.ts_size
/ 0x40, 4),
172 .clear_value
= {ctx
->specs
.ts_clear_value
},
173 .clear_mode
= VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1
,
178 if (!ctx
->specs
.use_blt
)
179 etna_rs_gen_clear_surface(ctx
, surf
, surf
->level
->clear_value
);
186 etna_surface_destroy(struct pipe_context
*pctx
, struct pipe_surface
*psurf
)
188 pipe_resource_reference(&psurf
->texture
, NULL
);
189 pipe_resource_reference(&etna_surface(psurf
)->prsc
, NULL
);
194 etna_surface_init(struct pipe_context
*pctx
)
196 pctx
->create_surface
= etna_create_surface
;
197 pctx
->surface_destroy
= etna_surface_destroy
;