etnaviv: update Android build files
[mesa.git] / src / gallium / drivers / etnaviv / etnaviv_surface.c
1 /*
2 * Copyright (c) 2012-2013 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_surface.h"
28 #include "etnaviv_screen.h"
29
30 #include "etnaviv_clear_blit.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_translate.h"
33 #include "pipe/p_defines.h"
34 #include "pipe/p_state.h"
35 #include "util/u_inlines.h"
36 #include "util/u_memory.h"
37
38 #include "hw/common.xml.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 static struct etna_resource *
43 etna_render_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc)
44 {
45 struct etna_context *ctx = etna_context(pctx);
46 struct etna_resource *res = etna_resource(prsc);
47 bool need_multitiled = ctx->specs.pixel_pipes > 1 && !ctx->specs.single_buffer;
48 bool want_supertiled = ctx->specs.can_supertile;
49
50 /* Resource is compatible if it is tiled and has multi tiling when required
51 * TODO: LINEAR_PE feature means render to linear is possible ?
52 */
53 if (res->layout != ETNA_LAYOUT_LINEAR &&
54 (!need_multitiled || (res->layout & ETNA_LAYOUT_BIT_MULTI)))
55 return res;
56
57 if (!res->render) {
58 struct pipe_resource templat = *prsc;
59 unsigned layout = ETNA_LAYOUT_TILED;
60 if (need_multitiled)
61 layout |= ETNA_LAYOUT_BIT_MULTI;
62 if (want_supertiled)
63 layout |= ETNA_LAYOUT_BIT_SUPER;
64
65 templat.bind &= (PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET |
66 PIPE_BIND_BLENDABLE);
67 res->render =
68 etna_resource_alloc(pctx->screen, layout,
69 DRM_FORMAT_MOD_LINEAR, &templat);
70 assert(res->render);
71 }
72 return etna_resource(res->render);
73 }
74
75 static struct pipe_surface *
76 etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
77 const struct pipe_surface *templat)
78 {
79 struct etna_context *ctx = etna_context(pctx);
80 struct etna_resource *rsc = etna_render_handle_incompatible(pctx, prsc);
81 struct etna_surface *surf = CALLOC_STRUCT(etna_surface);
82
83 if (!surf)
84 return NULL;
85
86 assert(templat->u.tex.first_layer == templat->u.tex.last_layer);
87 unsigned layer = templat->u.tex.first_layer;
88 unsigned level = templat->u.tex.level;
89 assert(layer < rsc->base.array_size);
90
91 surf->base.context = pctx;
92
93 pipe_reference_init(&surf->base.reference, 1);
94 pipe_resource_reference(&surf->base.texture, &rsc->base);
95 pipe_resource_reference(&surf->prsc, prsc);
96
97 /* Allocate a TS for the resource if there isn't one yet,
98 * and it is allowed by the hw (width is a multiple of 16).
99 * Avoid doing this for GPUs with MC1.0, as kernel sources
100 * indicate the tile status module bypasses the memory
101 * offset and MMU. */
102
103 if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) &&
104 VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) &&
105 !rsc->ts_bo &&
106 /* needs to be RS/BLT compatible for transfer_map/unmap */
107 (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
108 (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0 &&
109 etna_resource_hw_tileable(ctx->specs.use_blt, prsc)) {
110 etna_screen_resource_alloc_ts(pctx->screen, rsc);
111 }
112
113 surf->base.texture = &rsc->base;
114 surf->base.format = templat->format;
115 surf->base.width = rsc->levels[level].width;
116 surf->base.height = rsc->levels[level].height;
117 surf->base.writable = templat->writable; /* what is this for anyway */
118 surf->base.u = templat->u;
119
120 surf->level = &rsc->levels[level]; /* Keep pointer to actual level to set
121 * clear color on underlying resource
122 * instead of surface */
123 surf->surf = rsc->levels [level]; /* Make copy of level to narrow down
124 * address to layer */
125
126 /* XXX we don't really need a copy but it's convenient */
127 surf->surf.offset += layer * surf->surf.layer_stride;
128
129 struct etna_resource_level *lev = &rsc->levels[level];
130
131 /* Setup template relocations for this surface */
132 for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
133 surf->reloc[pipe].bo = rsc->bo;
134 surf->reloc[pipe].offset = surf->surf.offset;
135 surf->reloc[pipe].flags = 0;
136 }
137
138 /* In single buffer mode, both pixel pipes must point to the same address,
139 * for multi-tiled surfaces on the other hand the second pipe is expected to
140 * point halfway the image vertically.
141 */
142 if (rsc->layout & ETNA_LAYOUT_BIT_MULTI)
143 surf->reloc[1].offset = surf->surf.offset + lev->stride * lev->padded_height / 2;
144
145 if (surf->surf.ts_size) {
146 unsigned int layer_offset = layer * surf->surf.ts_layer_stride;
147 assert(layer_offset < surf->surf.ts_size);
148
149 surf->surf.ts_offset += layer_offset;
150 surf->surf.ts_size -= layer_offset;
151 surf->surf.ts_valid = false;
152
153 surf->ts_reloc.bo = rsc->ts_bo;
154 surf->ts_reloc.offset = surf->surf.ts_offset;
155 surf->ts_reloc.flags = 0;
156
157 if (!ctx->specs.use_blt) {
158 /* This (ab)uses the RS as a plain buffer memset().
159 * Currently uses a fixed row size of 64 bytes. Some benchmarking with
160 * different sizes may be in order. */
161 struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
162 etna_compile_rs_state(ctx, &surf->clear_command, &(struct rs_state) {
163 .source_format = RS_FORMAT_A8R8G8B8,
164 .dest_format = RS_FORMAT_A8R8G8B8,
165 .dest = ts_bo,
166 .dest_offset = surf->surf.ts_offset,
167 .dest_stride = 0x40,
168 .dest_tiling = ETNA_LAYOUT_TILED,
169 .dither = {0xffffffff, 0xffffffff},
170 .width = 16,
171 .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
172 .clear_value = {ctx->specs.ts_clear_value},
173 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
174 .clear_bits = 0xffff
175 });
176 }
177 } else {
178 if (!ctx->specs.use_blt)
179 etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
180 }
181
182 return &surf->base;
183 }
184
185 static void
186 etna_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
187 {
188 pipe_resource_reference(&psurf->texture, NULL);
189 pipe_resource_reference(&etna_surface(psurf)->prsc, NULL);
190 FREE(psurf);
191 }
192
193 void
194 etna_surface_init(struct pipe_context *pctx)
195 {
196 pctx->create_surface = etna_create_surface;
197 pctx->surface_destroy = etna_surface_destroy;
198 }