src/gallium/drivers/etnaviv/etnaviv_texture_state.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_texture_state.h"
  28
  29 #include "hw/common.xml.h"
  30
  31 #include "etnaviv_clear_blit.h"
  32 #include "etnaviv_context.h"
  33 #include "etnaviv_emit.h"
  34 #include "etnaviv_format.h"
  35 #include "etnaviv_texture.h"
  36 #include "etnaviv_translate.h"
  37 #include "util/u_inlines.h"
  38 #include "util/u_memory.h"
  39
  40 #include "drm-uapi/drm_fourcc.h"
  41
  42 static void *
  43 etna_create_sampler_state_state(struct pipe_context *pipe,
  44                           const struct pipe_sampler_state *ss)
  45 {
  46    struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
  47
  48    if (!cs)
  49       return NULL;
  50
  51    cs->TE_SAMPLER_CONFIG0 =
  52       VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
  53       VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
  54       VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
  55       VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
  56       VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter)) |
  57       COND(ss->normalized_coords, VIVS_TE_SAMPLER_CONFIG0_ROUND_UV);
  58
  59    cs->TE_SAMPLER_CONFIG1 =
  60       COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP);
  61
  62    cs->TE_SAMPLER_LOD_CONFIG =
  63       COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
  64       VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
  65
  66    if (ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
  67       cs->min_lod = etna_float_to_fixp55(ss->min_lod);
  68       cs->max_lod = etna_float_to_fixp55(ss->max_lod);
  69    } else {
  70       /* when not mipmapping, we need to set max/min lod so that always
  71        * lowest LOD is selected */
  72       cs->min_lod = cs->max_lod = etna_float_to_fixp55(ss->min_lod);
  73    }
  74
  75    return cs;
  76 }
  77
  78 static void
  79 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
  80 {
  81    FREE(ss);
  82 }
  83
  84 static struct pipe_sampler_view *
  85 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
  86                          const struct pipe_sampler_view *so)
  87 {
  88    struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
  89    struct etna_context *ctx = etna_context(pctx);
  90    const uint32_t format = translate_texture_format(so->format);
  91    const bool ext = !!(format & EXT_FORMAT);
  92    const bool astc = !!(format & ASTC_FORMAT);
  93    const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
  94                                           so->swizzle_g, so->swizzle_b,
  95                                           so->swizzle_a);
  96
  97    if (!sv)
  98       return NULL;
  99
 100    struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
 101    if (!res) {
 102       free(sv);
 103       return NULL;
 104    }
 105
 106    sv->base = *so;
 107    pipe_reference_init(&sv->base.reference, 1);
 108    sv->base.texture = NULL;
 109    pipe_resource_reference(&sv->base.texture, prsc);
 110    sv->base.context = pctx;
 111
 112    /* merged with sampler state */
 113    sv->TE_SAMPLER_CONFIG0 = COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
 114    sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
 115
 116    switch (sv->base.target) {
 117    case PIPE_TEXTURE_1D:
 118       /* For 1D textures, we will have a height of 1, so we can use 2D
 119        * but set T wrap to repeat */
 120       sv->TE_SAMPLER_CONFIG0_MASK = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
 121       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
 122       /* fallthrough */
 123    case PIPE_TEXTURE_2D:
 124    case PIPE_TEXTURE_RECT:
 125       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D);
 126       break;
 127    case PIPE_TEXTURE_CUBE:
 128       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_CUBE_MAP);
 129       break;
 130    default:
 131       BUG("Unhandled texture target");
 132       free(sv);
 133       return NULL;
 134    }
 135
 136    if (res->addressing_mode == ETNA_ADDRESSING_MODE_LINEAR) {
 137       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
 138
 139       for (int lod = 0; lod <= res->base.last_level; ++lod)
 140          sv->TE_SAMPLER_LINEAR_STRIDE[lod] = res->levels[lod].stride;
 141
 142    } else {
 143       sv->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
 144       memset(&sv->TE_SAMPLER_LINEAR_STRIDE, 0, sizeof(sv->TE_SAMPLER_LINEAR_STRIDE));
 145    }
 146
 147    sv->TE_SAMPLER_CONFIG1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
 148                              COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
 149                              VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
 150    sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
 151                           VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
 152                           VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
 153                           VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
 154    sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
 155                          VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
 156    sv->TE_SAMPLER_LOG_SIZE =
 157       VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
 158       VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0)) |
 159       COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
 160       COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
 161
 162    /* Set up levels-of-detail */
 163    for (int lod = 0; lod <= res->base.last_level; ++lod) {
 164       sv->TE_SAMPLER_LOD_ADDR[lod].bo = res->bo;
 165       sv->TE_SAMPLER_LOD_ADDR[lod].offset = res->levels[lod].offset;
 166       sv->TE_SAMPLER_LOD_ADDR[lod].flags = ETNA_RELOC_READ;
 167    }
 168    sv->min_lod = sv->base.u.tex.first_level << 5;
 169    sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
 170
 171    /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
 172     * supported when the appropriate capability is not set. */
 173    if (!ctx->specs.npot_tex_any_wrap &&
 174        (!util_is_power_of_two_or_zero(res->base.width0) ||
 175         !util_is_power_of_two_or_zero(res->base.height0))) {
 176       sv->TE_SAMPLER_CONFIG0_MASK = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
 177                                       VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
 178       sv->TE_SAMPLER_CONFIG0 |=
 179          VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
 180          VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
 181    }
 182
 183    return &sv->base;
 184 }
 185
 186 static void
 187 etna_sampler_view_state_destroy(struct pipe_context *pctx,
 188                           struct pipe_sampler_view *view)
 189 {
 190    pipe_resource_reference(&view->texture, NULL);
 191    FREE(view);
 192 }
 193
 194 #define EMIT_STATE(state_name, src_value) \
 195    etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
 196
 197 #define EMIT_STATE_FIXP(state_name, src_value) \
 198    etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
 199
 200 #define EMIT_STATE_RELOC(state_name, src_value) \
 201    etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
 202
 203 /* Emit plain (non-descriptor) texture state */
 204 static void
 205 etna_emit_texture_state(struct etna_context *ctx)
 206 {
 207    struct etna_cmd_stream *stream = ctx->stream;
 208    uint32_t active_samplers = active_samplers_bits(ctx);
 209    uint32_t dirty = ctx->dirty;
 210    struct etna_coalesce coalesce;
 211
 212    etna_coalesce_start(stream, &coalesce);
 213
 214    if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
 215       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 216          if ((1 << x) & active_samplers) {
 217             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 218             /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
 219          }
 220       }
 221       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 222          if ((1 << x) & active_samplers) {
 223             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 224             /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
 225          }
 226       }
 227       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 228          if ((1 << x) & active_samplers) {
 229             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 230             /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
 231          }
 232       }
 233       for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
 234          if ((1 << x) & active_samplers) {
 235             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 236             /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
 237          }
 238       }
 239    }
 240    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
 241       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 242          uint32_t val = 0; /* 0 == sampler inactive */
 243
 244          /* set active samplers to their configuration value (determined by both
 245           * the sampler state and sampler view) */
 246          if ((1 << x) & active_samplers) {
 247             struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
 248             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 249
 250             val = (ss->TE_SAMPLER_CONFIG0 & sv->TE_SAMPLER_CONFIG0_MASK) |
 251                   sv->TE_SAMPLER_CONFIG0;
 252          }
 253
 254          /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
 255       }
 256    }
 257    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 258       struct etna_sampler_view *sv;
 259
 260       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 261          if ((1 << x) & active_samplers) {
 262             sv = etna_sampler_view(ctx->sampler_view[x]);
 263             /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->TE_SAMPLER_SIZE);
 264          }
 265       }
 266       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 267          if ((1 << x) & active_samplers) {
 268             sv = etna_sampler_view(ctx->sampler_view[x]);
 269             /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), sv->TE_SAMPLER_LOG_SIZE);
 270          }
 271       }
 272    }
 273    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
 274       struct etna_sampler_state *ss;
 275       struct etna_sampler_view *sv;
 276
 277       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 278          if ((1 << x) & active_samplers) {
 279             ss = etna_sampler_state(ctx->sampler[x]);
 280             sv = etna_sampler_view(ctx->sampler_view[x]);
 281
 282             /* min and max lod is determined both by the sampler and the view */
 283             /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
 284                                  ss->TE_SAMPLER_LOD_CONFIG |
 285                                  VIVS_TE_SAMPLER_LOD_CONFIG_MAX(MIN2(ss->max_lod, sv->max_lod)) |
 286                                  VIVS_TE_SAMPLER_LOD_CONFIG_MIN(MAX2(ss->min_lod, sv->min_lod)));
 287          }
 288       }
 289       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 290          if ((1 << x) & active_samplers) {
 291             ss = etna_sampler_state(ctx->sampler[x]);
 292             sv = etna_sampler_view(ctx->sampler_view[x]);
 293
 294             /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->TE_SAMPLER_CONFIG1 |
 295                                                         sv->TE_SAMPLER_CONFIG1 |
 296                                                         COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
 297          }
 298       }
 299    }
 300    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 301       for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
 302          for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 303             if ((1 << x) & active_samplers) {
 304                struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 305                /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y),&sv->TE_SAMPLER_LOD_ADDR[y]);
 306             }
 307          }
 308       }
 309    }
 310    if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
 311       for (int y = 0; y < VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN; ++y) {
 312          for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 313             if ((1 << x) & active_samplers) {
 314                struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 315                /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(x, y), sv->TE_SAMPLER_LINEAR_STRIDE[y]);
 316             }
 317          }
 318       }
 319    }
 320    if (unlikely(ctx->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
 321       for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
 322          if ((1 << x) & active_samplers) {
 323             struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
 324             /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
 325          }
 326       }
 327    }
 328    etna_coalesce_end(stream, &coalesce);
 329 }
 330
 331 #undef EMIT_STATE
 332 #undef EMIT_STATE_FIXP
 333 #undef EMIT_STATE_RELOC
 334
 335 static struct etna_sampler_ts*
 336 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
 337 {
 338    struct etna_sampler_view *sv = etna_sampler_view(pview);
 339    return &sv->ts;
 340 }
 341
 342 void
 343 etna_texture_state_init(struct pipe_context *pctx)
 344 {
 345    struct etna_context *ctx = etna_context(pctx);
 346    DBG("etnaviv: Using state-based texturing");
 347    ctx->base.create_sampler_state = etna_create_sampler_state_state;
 348    ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
 349    ctx->base.create_sampler_view = etna_create_sampler_view_state;
 350    ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
 351    ctx->emit_texture_state = etna_emit_texture_state;
 352    ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
 353 }