2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_transfer.h"
28 #include "etnaviv_clear_blit.h"
29 #include "etnaviv_context.h"
30 #include "etnaviv_debug.h"
32 #include "pipe/p_defines.h"
33 #include "pipe/p_format.h"
34 #include "pipe/p_screen.h"
35 #include "pipe/p_state.h"
36 #include "util/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39 #include "util/u_surface.h"
40 #include "util/u_transfer.h"
42 /* Compute offset into a 1D/2D/3D buffer of a certain box.
43 * This box must be aligned to the block width and height of the
44 * underlying format. */
46 etna_compute_offset(enum pipe_format format
, const struct pipe_box
*box
,
47 size_t stride
, size_t layer_stride
)
49 return box
->z
* layer_stride
+
50 box
->y
/ util_format_get_blockheight(format
) * stride
+
51 box
->x
/ util_format_get_blockwidth(format
) *
52 util_format_get_blocksize(format
);
56 etna_transfer_unmap(struct pipe_context
*pctx
, struct pipe_transfer
*ptrans
)
58 struct etna_context
*ctx
= etna_context(pctx
);
59 struct etna_transfer
*trans
= etna_transfer(ptrans
);
60 struct etna_resource
*rsc
= etna_resource(ptrans
->resource
);
63 * When writing to a resource that is already in use, replace the resource
64 * with a completely new buffer
65 * and free the old one using a fenced free.
66 * The most tricky case to implement will be: tiled or supertiled surface,
67 * partial write, target not aligned to 4/64. */
68 assert(ptrans
->level
<= rsc
->base
.last_level
);
70 if (rsc
->texture
&& !etna_resource_newer(rsc
, etna_resource(rsc
->texture
)))
71 rsc
= etna_resource(rsc
->texture
); /* switch to using the texture resource */
74 * Temporary resources are always pulled into the CPU domain, must push them
75 * back into GPU domain before the RS execs the blit to the base resource.
78 etna_bo_cpu_fini(etna_resource(trans
->rsc
)->bo
);
80 if (ptrans
->usage
& PIPE_TRANSFER_WRITE
) {
82 /* We have a temporary resource due to either tile status or
83 * tiling format. Write back the updated buffer contents.
84 * FIXME: we need to invalidate the tile status. */
85 etna_copy_resource(pctx
, ptrans
->resource
, trans
->rsc
, ptrans
->level
,
86 trans
->rsc
->last_level
);
87 } else if (trans
->staging
) {
88 /* map buffer object */
89 struct etna_resource_level
*res_level
= &rsc
->levels
[ptrans
->level
];
90 void *mapped
= etna_bo_map(rsc
->bo
) + res_level
->offset
;
92 if (rsc
->layout
== ETNA_LAYOUT_TILED
) {
94 mapped
+ ptrans
->box
.z
* res_level
->layer_stride
,
95 trans
->staging
, ptrans
->box
.x
, ptrans
->box
.y
,
96 res_level
->stride
, ptrans
->box
.width
, ptrans
->box
.height
,
97 ptrans
->stride
, util_format_get_blocksize(rsc
->base
.format
));
98 } else if (rsc
->layout
== ETNA_LAYOUT_LINEAR
) {
99 util_copy_box(mapped
, rsc
->base
.format
, res_level
->stride
,
100 res_level
->layer_stride
, ptrans
->box
.x
,
101 ptrans
->box
.y
, ptrans
->box
.z
, ptrans
->box
.width
,
102 ptrans
->box
.height
, ptrans
->box
.depth
,
103 trans
->staging
, ptrans
->stride
,
104 ptrans
->layer_stride
, 0, 0, 0 /* src x,y,z */);
106 BUG("unsupported tiling %i", rsc
->layout
);
109 FREE(trans
->staging
);
114 if (rsc
->base
.bind
& PIPE_BIND_SAMPLER_VIEW
) {
115 ctx
->dirty
|= ETNA_DIRTY_TEXTURE_CACHES
;
120 * Transfers without a temporary are only pulled into the CPU domain if they
121 * are not mapped unsynchronized. If they are, must push them back into GPU
122 * domain after CPU access is finished.
124 if (!trans
->rsc
&& !(ptrans
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
))
125 etna_bo_cpu_fini(rsc
->bo
);
127 pipe_resource_reference(&trans
->rsc
, NULL
);
128 pipe_resource_reference(&ptrans
->resource
, NULL
);
129 slab_free(&ctx
->transfer_pool
, trans
);
133 etna_transfer_map(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
136 const struct pipe_box
*box
,
137 struct pipe_transfer
**out_transfer
)
139 struct etna_context
*ctx
= etna_context(pctx
);
140 struct etna_resource
*rsc
= etna_resource(prsc
);
141 struct etna_transfer
*trans
;
142 struct pipe_transfer
*ptrans
;
143 enum pipe_format format
= prsc
->format
;
145 trans
= slab_alloc(&ctx
->transfer_pool
);
149 /* slab_alloc() doesn't zero */
150 memset(trans
, 0, sizeof(*trans
));
152 ptrans
= &trans
->base
;
153 pipe_resource_reference(&ptrans
->resource
, prsc
);
154 ptrans
->level
= level
;
155 ptrans
->usage
= usage
;
158 assert(level
<= prsc
->last_level
);
160 /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
161 * being mapped. If we add buffer reallocation to avoid CPU/GPU sync this
162 * check needs to be extended to coherent mappings and shared resources.
164 if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
165 !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
166 prsc
->last_level
== 0 &&
167 prsc
->width0
== box
->width
&&
168 prsc
->height0
== box
->height
&&
169 prsc
->depth0
== box
->depth
&&
170 prsc
->array_size
== 1) {
171 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
174 if (rsc
->texture
&& !etna_resource_newer(rsc
, etna_resource(rsc
->texture
))) {
175 /* We have a texture resource which is the same age or newer than the
176 * render resource. Use the texture resource, which avoids bouncing
177 * pixels between the two resources, and we can de-tile it in s/w. */
178 rsc
= etna_resource(rsc
->texture
);
179 } else if (rsc
->ts_bo
||
180 (rsc
->layout
!= ETNA_LAYOUT_LINEAR
&&
181 util_format_get_blocksize(format
) > 1 &&
182 /* HALIGN 4 resources are incompatible with the resolve engine,
183 * so fall back to using software to detile this resource. */
184 rsc
->halign
!= TEXTURE_HALIGN_FOUR
)) {
185 /* If the surface has tile status, we need to resolve it first.
186 * The strategy we implement here is to use the RS to copy the
187 * depth buffer, filling in the "holes" where the tile status
188 * indicates that it's clear. We also do this for tiled
189 * resources, but only if the RS can blit them. */
190 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
) {
191 slab_free(&ctx
->transfer_pool
, trans
);
192 BUG("unsupported transfer flags %#x with tile status/tiled layout", usage
);
196 if (prsc
->depth0
> 1) {
197 slab_free(&ctx
->transfer_pool
, trans
);
198 BUG("resource has depth >1 with tile status");
202 struct pipe_resource templ
= *prsc
;
203 templ
.nr_samples
= 0;
204 templ
.bind
= PIPE_BIND_RENDER_TARGET
;
206 trans
->rsc
= etna_resource_alloc(pctx
->screen
, ETNA_LAYOUT_LINEAR
, &templ
);
208 slab_free(&ctx
->transfer_pool
, trans
);
212 if (!(usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
))
213 etna_copy_resource(pctx
, trans
->rsc
, prsc
, level
,
214 trans
->rsc
->last_level
);
216 /* Switch to using the temporary resource instead */
217 rsc
= etna_resource(trans
->rsc
);
220 struct etna_resource_level
*res_level
= &rsc
->levels
[level
];
222 /* Always sync if we have the temporary resource. The PIPE_TRANSFER_READ
223 * case could be optimised if we knew whether the resource has outstanding
225 if ((usage
& PIPE_TRANSFER_READ
|| trans
->rsc
) &&
226 rsc
->status
& ETNA_PENDING_WRITE
)
227 pctx
->flush(pctx
, NULL
, 0);
229 /* XXX we don't handle PIPE_TRANSFER_FLUSH_EXPLICIT; this flag can be ignored
230 * when mapping in-place,
231 * but when not in place we need to fire off the copy operation in
232 * transfer_flush_region (currently
233 * a no-op) instead of unmap. Need to handle this to support
234 * ARB_map_buffer_range extension at least.
236 /* XXX we don't take care of current operations on the resource; which can
237 be, at some point in the pipeline
238 which is not yet executed:
241 - bound through vertex buffer
242 - bound through index buffer
243 - bound in sampler view
244 - used in clear_render_target / clear_depth_stencil operation
246 - used in resource_copy_region
248 How do other drivers record this information over course of the rendering
250 Is it necessary at all? Only in case we want to provide a fast path and
251 map the resource directly
252 (and for PIPE_TRANSFER_MAP_DIRECTLY) and we don't want to force a sync.
253 We also need to know whether the resource is in use to determine if a sync
254 is needed (or just do it
255 always, but that comes at the expense of performance).
257 A conservative approximation without too much overhead would be to mark
258 all resources that have
259 been bound at some point as busy. A drawback would be that accessing
261 been bound but are no longer in use for a while still carry a performance
262 penalty. On the other hand,
263 the program could be using PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE or
264 PIPE_TRANSFER_UNSYNCHRONIZED to
265 avoid this in the first place...
267 A) We use an in-pipe copy engine, and queue the copy operation after unmap
269 will be performed when all current commands have been executed.
270 Using the RS is possible, not sure if always efficient. This can also
271 do any kind of tiling for us.
272 Only possible when PIPE_TRANSFER_DISCARD_RANGE is set.
273 B) We discard the entire resource (or at least, the mipmap level) and
274 allocate new memory for it.
275 Only possible when mapping the entire resource or
276 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set.
280 * Pull resources into the CPU domain. Only skipped for unsynchronized
281 * transfers without a temporary resource.
283 if (trans
->rsc
|| !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
284 uint32_t prep_flags
= 0;
286 if (usage
& PIPE_TRANSFER_READ
)
287 prep_flags
|= DRM_ETNA_PREP_READ
;
288 if (usage
& PIPE_TRANSFER_WRITE
)
289 prep_flags
|= DRM_ETNA_PREP_WRITE
;
291 if (etna_bo_cpu_prep(rsc
->bo
, prep_flags
))
295 /* map buffer object */
296 void *mapped
= etna_bo_map(rsc
->bo
);
300 *out_transfer
= ptrans
;
302 if (rsc
->layout
== ETNA_LAYOUT_LINEAR
) {
303 ptrans
->stride
= res_level
->stride
;
304 ptrans
->layer_stride
= res_level
->layer_stride
;
306 return mapped
+ res_level
->offset
+
307 etna_compute_offset(prsc
->format
, box
, res_level
->stride
,
308 res_level
->layer_stride
);
310 unsigned divSizeX
= util_format_get_blockwidth(format
);
311 unsigned divSizeY
= util_format_get_blockheight(format
);
313 /* No direct mappings of tiled, since we need to manually
316 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)
319 mapped
+= res_level
->offset
;
320 ptrans
->stride
= align(box
->width
, divSizeX
) * util_format_get_blocksize(format
); /* row stride in bytes */
321 ptrans
->layer_stride
= align(box
->height
, divSizeY
) * ptrans
->stride
;
322 size_t size
= ptrans
->layer_stride
* box
->depth
;
324 trans
->staging
= MALLOC(size
);
328 if (usage
& PIPE_TRANSFER_READ
) {
329 if (rsc
->layout
== ETNA_LAYOUT_TILED
) {
330 etna_texture_untile(trans
->staging
,
331 mapped
+ ptrans
->box
.z
* res_level
->layer_stride
,
332 ptrans
->box
.x
, ptrans
->box
.y
, res_level
->stride
,
333 ptrans
->box
.width
, ptrans
->box
.height
, ptrans
->stride
,
334 util_format_get_blocksize(rsc
->base
.format
));
335 } else if (rsc
->layout
== ETNA_LAYOUT_LINEAR
) {
336 util_copy_box(trans
->staging
, rsc
->base
.format
, ptrans
->stride
,
337 ptrans
->layer_stride
, 0, 0, 0, /* dst x,y,z */
338 ptrans
->box
.width
, ptrans
->box
.height
,
339 ptrans
->box
.depth
, mapped
, res_level
->stride
,
340 res_level
->layer_stride
, ptrans
->box
.x
,
341 ptrans
->box
.y
, ptrans
->box
.z
);
343 /* TODO supertiling */
344 BUG("unsupported tiling %i for reading", rsc
->layout
);
348 return trans
->staging
;
352 etna_bo_cpu_fini(rsc
->bo
);
354 etna_transfer_unmap(pctx
, ptrans
);
359 etna_transfer_flush_region(struct pipe_context
*pctx
,
360 struct pipe_transfer
*transfer
,
361 const struct pipe_box
*box
)
367 etna_transfer_init(struct pipe_context
*pctx
)
369 pctx
->transfer_map
= etna_transfer_map
;
370 pctx
->transfer_flush_region
= etna_transfer_flush_region
;
371 pctx
->transfer_unmap
= etna_transfer_unmap
;
372 pctx
->buffer_subdata
= u_default_buffer_subdata
;
373 pctx
->texture_subdata
= u_default_texture_subdata
;