2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
27 #include "etnaviv_transfer.h"
28 #include "etnaviv_clear_blit.h"
29 #include "etnaviv_context.h"
30 #include "etnaviv_debug.h"
32 #include "pipe/p_defines.h"
33 #include "pipe/p_format.h"
34 #include "pipe/p_screen.h"
35 #include "pipe/p_state.h"
36 #include "util/u_format.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39 #include "util/u_surface.h"
40 #include "util/u_transfer.h"
42 #include <drm_fourcc.h>
44 /* Compute offset into a 1D/2D/3D buffer of a certain box.
45 * This box must be aligned to the block width and height of the
46 * underlying format. */
48 etna_compute_offset(enum pipe_format format
, const struct pipe_box
*box
,
49 size_t stride
, size_t layer_stride
)
51 return box
->z
* layer_stride
+
52 box
->y
/ util_format_get_blockheight(format
) * stride
+
53 box
->x
/ util_format_get_blockwidth(format
) *
54 util_format_get_blocksize(format
);
58 etna_transfer_unmap(struct pipe_context
*pctx
, struct pipe_transfer
*ptrans
)
60 struct etna_context
*ctx
= etna_context(pctx
);
61 struct etna_transfer
*trans
= etna_transfer(ptrans
);
62 struct etna_resource
*rsc
= etna_resource(ptrans
->resource
);
65 * When writing to a resource that is already in use, replace the resource
66 * with a completely new buffer
67 * and free the old one using a fenced free.
68 * The most tricky case to implement will be: tiled or supertiled surface,
69 * partial write, target not aligned to 4/64. */
70 assert(ptrans
->level
<= rsc
->base
.last_level
);
72 if (rsc
->texture
&& !etna_resource_newer(rsc
, etna_resource(rsc
->texture
)))
73 rsc
= etna_resource(rsc
->texture
); /* switch to using the texture resource */
76 * Temporary resources are always pulled into the CPU domain, must push them
77 * back into GPU domain before the RS execs the blit to the base resource.
80 etna_bo_cpu_fini(etna_resource(trans
->rsc
)->bo
);
82 if (ptrans
->usage
& PIPE_TRANSFER_WRITE
) {
84 /* We have a temporary resource due to either tile status or
85 * tiling format. Write back the updated buffer contents.
86 * FIXME: we need to invalidate the tile status. */
87 etna_copy_resource(pctx
, ptrans
->resource
, trans
->rsc
, ptrans
->level
,
88 trans
->rsc
->last_level
);
89 } else if (trans
->staging
) {
90 /* map buffer object */
91 struct etna_resource_level
*res_level
= &rsc
->levels
[ptrans
->level
];
92 void *mapped
= etna_bo_map(rsc
->bo
) + res_level
->offset
;
94 if (rsc
->layout
== ETNA_LAYOUT_TILED
) {
96 mapped
+ ptrans
->box
.z
* res_level
->layer_stride
,
97 trans
->staging
, ptrans
->box
.x
, ptrans
->box
.y
,
98 res_level
->stride
, ptrans
->box
.width
, ptrans
->box
.height
,
99 ptrans
->stride
, util_format_get_blocksize(rsc
->base
.format
));
100 } else if (rsc
->layout
== ETNA_LAYOUT_LINEAR
) {
101 util_copy_box(mapped
, rsc
->base
.format
, res_level
->stride
,
102 res_level
->layer_stride
, ptrans
->box
.x
,
103 ptrans
->box
.y
, ptrans
->box
.z
, ptrans
->box
.width
,
104 ptrans
->box
.height
, ptrans
->box
.depth
,
105 trans
->staging
, ptrans
->stride
,
106 ptrans
->layer_stride
, 0, 0, 0 /* src x,y,z */);
108 BUG("unsupported tiling %i", rsc
->layout
);
111 FREE(trans
->staging
);
116 if (rsc
->base
.bind
& PIPE_BIND_SAMPLER_VIEW
) {
117 ctx
->dirty
|= ETNA_DIRTY_TEXTURE_CACHES
;
122 * Transfers without a temporary are only pulled into the CPU domain if they
123 * are not mapped unsynchronized. If they are, must push them back into GPU
124 * domain after CPU access is finished.
126 if (!trans
->rsc
&& !(ptrans
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
))
127 etna_bo_cpu_fini(rsc
->bo
);
129 pipe_resource_reference(&trans
->rsc
, NULL
);
130 pipe_resource_reference(&ptrans
->resource
, NULL
);
131 slab_free(&ctx
->transfer_pool
, trans
);
135 etna_transfer_map(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
138 const struct pipe_box
*box
,
139 struct pipe_transfer
**out_transfer
)
141 struct etna_context
*ctx
= etna_context(pctx
);
142 struct etna_resource
*rsc
= etna_resource(prsc
);
143 struct etna_transfer
*trans
;
144 struct pipe_transfer
*ptrans
;
145 enum pipe_format format
= prsc
->format
;
147 trans
= slab_alloc(&ctx
->transfer_pool
);
151 /* slab_alloc() doesn't zero */
152 memset(trans
, 0, sizeof(*trans
));
154 ptrans
= &trans
->base
;
155 pipe_resource_reference(&ptrans
->resource
, prsc
);
156 ptrans
->level
= level
;
157 ptrans
->usage
= usage
;
160 assert(level
<= prsc
->last_level
);
162 /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
163 * being mapped. If we add buffer reallocation to avoid CPU/GPU sync this
164 * check needs to be extended to coherent mappings and shared resources.
166 if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
167 !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
) &&
168 prsc
->last_level
== 0 &&
169 prsc
->width0
== box
->width
&&
170 prsc
->height0
== box
->height
&&
171 prsc
->depth0
== box
->depth
&&
172 prsc
->array_size
== 1) {
173 usage
|= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
;
176 if (rsc
->texture
&& !etna_resource_newer(rsc
, etna_resource(rsc
->texture
))) {
177 /* We have a texture resource which is the same age or newer than the
178 * render resource. Use the texture resource, which avoids bouncing
179 * pixels between the two resources, and we can de-tile it in s/w. */
180 rsc
= etna_resource(rsc
->texture
);
181 } else if (rsc
->ts_bo
||
182 (rsc
->layout
!= ETNA_LAYOUT_LINEAR
&&
183 util_format_get_blocksize(format
) > 1 &&
184 /* HALIGN 4 resources are incompatible with the resolve engine,
185 * so fall back to using software to detile this resource. */
186 rsc
->halign
!= TEXTURE_HALIGN_FOUR
)) {
187 /* If the surface has tile status, we need to resolve it first.
188 * The strategy we implement here is to use the RS to copy the
189 * depth buffer, filling in the "holes" where the tile status
190 * indicates that it's clear. We also do this for tiled
191 * resources, but only if the RS can blit them. */
192 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
) {
193 slab_free(&ctx
->transfer_pool
, trans
);
194 BUG("unsupported transfer flags %#x with tile status/tiled layout", usage
);
198 if (prsc
->depth0
> 1) {
199 slab_free(&ctx
->transfer_pool
, trans
);
200 BUG("resource has depth >1 with tile status");
204 struct pipe_resource templ
= *prsc
;
205 templ
.nr_samples
= 0;
206 templ
.bind
= PIPE_BIND_RENDER_TARGET
;
208 trans
->rsc
= etna_resource_alloc(pctx
->screen
, ETNA_LAYOUT_LINEAR
,
209 DRM_FORMAT_MOD_LINEAR
, &templ
);
211 slab_free(&ctx
->transfer_pool
, trans
);
215 if (!(usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
))
216 etna_copy_resource(pctx
, trans
->rsc
, prsc
, level
,
217 trans
->rsc
->last_level
);
219 /* Switch to using the temporary resource instead */
220 rsc
= etna_resource(trans
->rsc
);
223 struct etna_resource_level
*res_level
= &rsc
->levels
[level
];
225 /* Always sync if we have the temporary resource. The PIPE_TRANSFER_READ
226 * case could be optimised if we knew whether the resource has outstanding
228 if ((usage
& PIPE_TRANSFER_READ
|| trans
->rsc
) &&
229 rsc
->status
& ETNA_PENDING_WRITE
)
230 pctx
->flush(pctx
, NULL
, 0);
232 /* XXX we don't handle PIPE_TRANSFER_FLUSH_EXPLICIT; this flag can be ignored
233 * when mapping in-place,
234 * but when not in place we need to fire off the copy operation in
235 * transfer_flush_region (currently
236 * a no-op) instead of unmap. Need to handle this to support
237 * ARB_map_buffer_range extension at least.
239 /* XXX we don't take care of current operations on the resource; which can
240 be, at some point in the pipeline
241 which is not yet executed:
244 - bound through vertex buffer
245 - bound through index buffer
246 - bound in sampler view
247 - used in clear_render_target / clear_depth_stencil operation
249 - used in resource_copy_region
251 How do other drivers record this information over course of the rendering
253 Is it necessary at all? Only in case we want to provide a fast path and
254 map the resource directly
255 (and for PIPE_TRANSFER_MAP_DIRECTLY) and we don't want to force a sync.
256 We also need to know whether the resource is in use to determine if a sync
257 is needed (or just do it
258 always, but that comes at the expense of performance).
260 A conservative approximation without too much overhead would be to mark
261 all resources that have
262 been bound at some point as busy. A drawback would be that accessing
264 been bound but are no longer in use for a while still carry a performance
265 penalty. On the other hand,
266 the program could be using PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE or
267 PIPE_TRANSFER_UNSYNCHRONIZED to
268 avoid this in the first place...
270 A) We use an in-pipe copy engine, and queue the copy operation after unmap
272 will be performed when all current commands have been executed.
273 Using the RS is possible, not sure if always efficient. This can also
274 do any kind of tiling for us.
275 Only possible when PIPE_TRANSFER_DISCARD_RANGE is set.
276 B) We discard the entire resource (or at least, the mipmap level) and
277 allocate new memory for it.
278 Only possible when mapping the entire resource or
279 PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is set.
283 * Pull resources into the CPU domain. Only skipped for unsynchronized
284 * transfers without a temporary resource.
286 if (trans
->rsc
|| !(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
287 uint32_t prep_flags
= 0;
289 if (usage
& PIPE_TRANSFER_READ
)
290 prep_flags
|= DRM_ETNA_PREP_READ
;
291 if (usage
& PIPE_TRANSFER_WRITE
)
292 prep_flags
|= DRM_ETNA_PREP_WRITE
;
294 if (etna_bo_cpu_prep(rsc
->bo
, prep_flags
))
298 /* map buffer object */
299 void *mapped
= etna_bo_map(rsc
->bo
);
303 *out_transfer
= ptrans
;
305 if (rsc
->layout
== ETNA_LAYOUT_LINEAR
) {
306 ptrans
->stride
= res_level
->stride
;
307 ptrans
->layer_stride
= res_level
->layer_stride
;
309 return mapped
+ res_level
->offset
+
310 etna_compute_offset(prsc
->format
, box
, res_level
->stride
,
311 res_level
->layer_stride
);
313 unsigned divSizeX
= util_format_get_blockwidth(format
);
314 unsigned divSizeY
= util_format_get_blockheight(format
);
316 /* No direct mappings of tiled, since we need to manually
319 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)
322 mapped
+= res_level
->offset
;
323 ptrans
->stride
= align(box
->width
, divSizeX
) * util_format_get_blocksize(format
); /* row stride in bytes */
324 ptrans
->layer_stride
= align(box
->height
, divSizeY
) * ptrans
->stride
;
325 size_t size
= ptrans
->layer_stride
* box
->depth
;
327 trans
->staging
= MALLOC(size
);
331 if (usage
& PIPE_TRANSFER_READ
) {
332 if (rsc
->layout
== ETNA_LAYOUT_TILED
) {
333 etna_texture_untile(trans
->staging
,
334 mapped
+ ptrans
->box
.z
* res_level
->layer_stride
,
335 ptrans
->box
.x
, ptrans
->box
.y
, res_level
->stride
,
336 ptrans
->box
.width
, ptrans
->box
.height
, ptrans
->stride
,
337 util_format_get_blocksize(rsc
->base
.format
));
338 } else if (rsc
->layout
== ETNA_LAYOUT_LINEAR
) {
339 util_copy_box(trans
->staging
, rsc
->base
.format
, ptrans
->stride
,
340 ptrans
->layer_stride
, 0, 0, 0, /* dst x,y,z */
341 ptrans
->box
.width
, ptrans
->box
.height
,
342 ptrans
->box
.depth
, mapped
, res_level
->stride
,
343 res_level
->layer_stride
, ptrans
->box
.x
,
344 ptrans
->box
.y
, ptrans
->box
.z
);
346 /* TODO supertiling */
347 BUG("unsupported tiling %i for reading", rsc
->layout
);
351 return trans
->staging
;
355 etna_bo_cpu_fini(rsc
->bo
);
357 etna_transfer_unmap(pctx
, ptrans
);
362 etna_transfer_flush_region(struct pipe_context
*pctx
,
363 struct pipe_transfer
*transfer
,
364 const struct pipe_box
*box
)
370 etna_transfer_init(struct pipe_context
*pctx
)
372 pctx
->transfer_map
= etna_transfer_map
;
373 pctx
->transfer_flush_region
= etna_transfer_flush_region
;
374 pctx
->transfer_unmap
= etna_transfer_unmap
;
375 pctx
->buffer_subdata
= u_default_buffer_subdata
;
376 pctx
->texture_subdata
= u_default_texture_subdata
;