src/gallium/drivers/etnaviv/etnaviv_zsa.c

   1 /*
   2  * Copyright (c) 2012-2015 Etnaviv Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Wladimir J. van der Laan <laanwj@gmail.com>
  25  */
  26
  27 #include "etnaviv_zsa.h"
  28
  29 #include "etnaviv_context.h"
  30 #include "etnaviv_screen.h"
  31 #include "etnaviv_translate.h"
  32 #include "util/u_half.h"
  33 #include "util/u_memory.h"
  34
  35 #include "hw/common.xml.h"
  36
  37 void *
  38 etna_zsa_state_create(struct pipe_context *pctx,
  39                       const struct pipe_depth_stencil_alpha_state *so)
  40 {
  41    struct etna_context *ctx = etna_context(pctx);
  42    struct etna_screen *screen = ctx->screen;
  43    struct etna_zsa_state *cs = CALLOC_STRUCT(etna_zsa_state);
  44
  45    if (!cs)
  46       return NULL;
  47
  48    cs->base = *so;
  49
  50    /* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */
  51    bool early_z = !VIV_FEATURE(ctx->screen, chipFeatures, NO_EARLY_Z);
  52    bool disable_zs =
  53       (!so->depth.enabled || so->depth.func == PIPE_FUNC_ALWAYS) &&
  54       !so->depth.writemask;
  55
  56 /* Set operations to KEEP if write mask is 0.
  57  * When we don't do this, the depth buffer is written for the entire primitive
  58  * instead of just where the stencil condition holds (GC600 rev 0x0019, without
  59  * feature CORRECT_STENCIL).
  60  * Not sure if this is a hardware bug or just a strange edge case. */
  61 #if 0 /* TODO: It looks like a hardware bug */
  62     for(int i=0; i<2; ++i)
  63     {
  64         if(so->stencil[i].writemask == 0)
  65         {
  66             so->stencil[i].fail_op = so->stencil[i].zfail_op = so->stencil[i].zpass_op = PIPE_STENCIL_OP_KEEP;
  67         }
  68     }
  69 #endif
  70
  71    /* Determine whether to enable early z reject. Don't enable it when any of
  72     * the stencil-modifying functions is used. */
  73    if (so->stencil[0].enabled) {
  74       if (so->stencil[0].func != PIPE_FUNC_ALWAYS ||
  75           (so->stencil[1].enabled && so->stencil[1].func != PIPE_FUNC_ALWAYS))
  76          disable_zs = false;
  77
  78       if (so->stencil[0].fail_op != PIPE_STENCIL_OP_KEEP ||
  79           so->stencil[0].zfail_op != PIPE_STENCIL_OP_KEEP ||
  80           so->stencil[0].zpass_op != PIPE_STENCIL_OP_KEEP) {
  81          disable_zs = early_z = false;
  82       } else if (so->stencil[1].enabled) {
  83          if (so->stencil[1].fail_op != PIPE_STENCIL_OP_KEEP ||
  84              so->stencil[1].zfail_op != PIPE_STENCIL_OP_KEEP ||
  85              so->stencil[1].zpass_op != PIPE_STENCIL_OP_KEEP) {
  86             disable_zs = early_z = false;
  87          }
  88       }
  89    }
  90
  91    /* Disable early z reject when no depth test is enabled.
  92     * This avoids having to sample depth even though we know it's going to
  93     * succeed. */
  94    if (so->depth.enabled == false || so->depth.func == PIPE_FUNC_ALWAYS)
  95       early_z = false;
  96
  97    /* calculate extra_reference value */
  98    uint32_t extra_reference = 0;
  99
 100    if (VIV_FEATURE(screen, chipMinorFeatures1, HALF_FLOAT))
 101       extra_reference = util_float_to_half(CLAMP(so->alpha.ref_value, 0.0f, 1.0f));
 102
 103    cs->PE_STENCIL_CONFIG_EXT =
 104       VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(extra_reference);
 105
 106    /* compare funcs have 1 to 1 mapping */
 107    cs->PE_DEPTH_CONFIG =
 108       VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(so->depth.enabled ? so->depth.func
 109                                                         : PIPE_FUNC_ALWAYS) |
 110       COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
 111       COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
 112       /* this bit changed meaning with HALTI5: */
 113       COND(disable_zs && screen->specs.halti < 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
 114    cs->PE_ALPHA_OP =
 115       COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
 116       VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha.func) |
 117       VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so->alpha.ref_value));
 118
 119    for (unsigned i = 0; i < 2; i++) {
 120       const struct pipe_stencil_state *stencil_front = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[i] : &so->stencil[0];
 121       const struct pipe_stencil_state *stencil_back = (so->stencil[1].enabled && so->stencil[1].valuemask) ? &so->stencil[!i] : &so->stencil[0];
 122       cs->PE_STENCIL_OP[i] =
 123          VIVS_PE_STENCIL_OP_FUNC_FRONT(stencil_front->func) |
 124          VIVS_PE_STENCIL_OP_FUNC_BACK(stencil_back->func) |
 125          VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(stencil_front->fail_op)) |
 126          VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(stencil_back->fail_op)) |
 127          VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(stencil_front->zfail_op)) |
 128          VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(stencil_back->zfail_op)) |
 129          VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(stencil_front->zpass_op)) |
 130          VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(stencil_back->zpass_op));
 131       cs->PE_STENCIL_CONFIG[i] =
 132          translate_stencil_mode(so->stencil[0].enabled, so->stencil[0].enabled) |
 133          VIVS_PE_STENCIL_CONFIG_MASK_FRONT(stencil_front->valuemask) |
 134          VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(stencil_front->writemask);
 135       cs->PE_STENCIL_CONFIG_EXT2[i] =
 136          VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(stencil_back->valuemask) |
 137          VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(stencil_back->writemask);
 138    }
 139
 140    /* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
 141    return cs;
 142 }