etnaviv: update headers from rnndb
[mesa.git] / src / gallium / drivers / etnaviv / hw / state.xml.h
1 #ifndef STATE_XML
2 #define STATE_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9
10 The rules-ng-ng source files this header was generated from are:
11 - state.xml ( 26666 bytes, from 2019-08-19 14:35:07)
12 - common.xml ( 35468 bytes, from 2019-01-07 09:52:31)
13 - common_3d.xml ( 14322 bytes, from 2019-08-19 14:35:07)
14 - state_hi.xml ( 30232 bytes, from 2019-01-07 09:52:31)
15 - copyright.xml ( 1597 bytes, from 2019-01-07 09:52:31)
16 - state_2d.xml ( 51552 bytes, from 2019-01-07 09:52:31)
17 - state_3d.xml ( 83505 bytes, from 2019-08-19 14:46:17)
18 - state_blt.xml ( 14252 bytes, from 2019-08-19 14:35:07)
19 - state_vg.xml ( 5975 bytes, from 2019-01-07 09:52:31)
20
21 Copyright (C) 2012-2019 by the following authors:
22 - Wladimir J. van der Laan <laanwj@gmail.com>
23 - Christian Gmeiner <christian.gmeiner@gmail.com>
24 - Lucas Stach <l.stach@pengutronix.de>
25 - Russell King <rmk@arm.linux.org.uk>
26
27 Permission is hereby granted, free of charge, to any person obtaining a
28 copy of this software and associated documentation files (the "Software"),
29 to deal in the Software without restriction, including without limitation
30 the rights to use, copy, modify, merge, publish, distribute, sub license,
31 and/or sell copies of the Software, and to permit persons to whom the
32 Software is furnished to do so, subject to the following conditions:
33
34 The above copyright notice and this permission notice (including the
35 next paragraph) shall be included in all copies or substantial portions
36 of the Software.
37
38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
41 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
44 DEALINGS IN THE SOFTWARE.
45 */
46
47
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
56 #define FE_DATA_TYPE_INT 0x00000004
57 #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005
58 #define FE_DATA_TYPE_INT_2_10_10_10_REV 0x00000006
59 #define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x00000007
60 #define FE_DATA_TYPE_FLOAT 0x00000008
61 #define FE_DATA_TYPE_HALF_FLOAT 0x00000009
62 #define FE_DATA_TYPE_FIXED 0x0000000b
63 #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c
64 #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d
65 #define FE_DATA_TYPE_BYTE_I 0x0000000e
66 #define FE_DATA_TYPE_SHORT_I 0x0000000f
67 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff
68 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0
69 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
70 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000
71 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16
72 #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK)
73 #define VIVS_FE 0x00000000
74
75 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0))
76 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x00000004
77 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010
78 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f
79 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0
80 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)
81 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030
82 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4
83 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
84 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x00000080
85 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x00000700
86 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT 8
87 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)
88 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x00003000
89 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT 12
90 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK)
91 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000
92 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14
93 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000
94 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x00004000
95 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000
96 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000
97 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16
98 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)
99 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000
100 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT 24
101 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)
102
103 #define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640
104
105 #define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644
106
107 #define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648
108 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003
109 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0
110 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000
111 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001
112 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002
113 #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100
114
115 #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c
116
117 #define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650
118
119 #define VIVS_FE_COMMAND_ADDRESS 0x00000654
120
121 #define VIVS_FE_COMMAND_CONTROL 0x00000658
122 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff
123 #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0
124 #define VIVS_FE_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)
125 #define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000
126
127 #define VIVS_FE_DMA_STATUS 0x0000065c
128
129 #define VIVS_FE_DMA_DEBUG_STATE 0x00000660
130 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f
131 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0
132 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000
133 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001
134 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002
135 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003
136 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004
137 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005
138 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006
139 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007
140 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008
141 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009
142 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a
143 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b
144 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c
145 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d
146 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e
147 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f
148 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010
149 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011
150 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012
151 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013
152 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014
153 #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015
154 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300
155 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT 8
156 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000
157 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100
158 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200
159 #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300
160 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00
161 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT 10
162 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000
163 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400
164 #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800
165 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000
166 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT 12
167 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000
168 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000
169 #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000
170 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000
171 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT 14
172 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000
173 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000
174 #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000
175 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000
176 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT 16
177 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000
178 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000
179 #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000
180
181 #define VIVS_FE_DMA_ADDRESS 0x00000664
182
183 #define VIVS_FE_DMA_LOW 0x00000668
184
185 #define VIVS_FE_DMA_HIGH 0x0000066c
186
187 #define VIVS_FE_AUTO_FLUSH 0x00000670
188
189 #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674
190
191 #define VIVS_FE_UNK00678 0x00000678
192
193 #define VIVS_FE_UNK0067C 0x0000067c
194
195 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))
196 #define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004
197 #define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008
198
199 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0))
200
201 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0))
202
203 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
204 #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004
205 #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010
206
207 #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0))
208
209 #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0))
210
211 #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0))
212
213 #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))
214
215 #define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4
216 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001
217 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002
218 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00
219 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8
220 #define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK)
221 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000
222 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16
223 #define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK)
224
225 #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))
226 #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004
227 #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002
228
229 #define VIVS_FE_HALTI5_UNK007D8 0x000007d8
230
231 #define VIVS_FE_DESC_START 0x000007dc
232
233 #define VIVS_FE_DESC_END 0x000007e0
234
235 #define VIVS_FE_DESC_AVAIL 0x000007e4
236 #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f
237 #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0
238 #define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
239
240 #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8
241
242 #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4
243
244 #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
245
246 #define VIVS_GL 0x00000000
247
248 #define VIVS_GL_PIPE_SELECT 0x00003800
249 #define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001
250 #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0
251 #define VIVS_GL_PIPE_SELECT_PIPE(x) (((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)
252
253 #define VIVS_GL_EVENT 0x00003804
254 #define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f
255 #define VIVS_GL_EVENT_EVENT_ID__SHIFT 0
256 #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
257 #define VIVS_GL_EVENT_FROM_FE 0x00000020
258 #define VIVS_GL_EVENT_FROM_PE 0x00000040
259 #define VIVS_GL_EVENT_FROM_BLT 0x00000080
260 #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00
261 #define VIVS_GL_EVENT_SOURCE__SHIFT 8
262 #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)
263
264 #define VIVS_GL_SEMAPHORE_TOKEN 0x00003808
265 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f
266 #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0
267 #define VIVS_GL_SEMAPHORE_TOKEN_FROM(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)
268 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00
269 #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8
270 #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
271 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000
272 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28
273 #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
274
275 #define VIVS_GL_FLUSH_CACHE 0x0000380c
276 #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001
277 #define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002
278 #define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004
279 #define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008
280 #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010
281 #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020
282 #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040
283 #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400
284 #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
285 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
286 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
287
288 #define VIVS_GL_FLUSH_MMU 0x00003810
289 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
290 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002
291 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004
292 #define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008
293 #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010
294
295 #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814
296
297 #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818
298 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003
299 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0
300 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000
301 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001
302 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002
303 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008
304 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0
305 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT 4
306 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)
307 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100
308 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000
309 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT 12
310 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)
311 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000
312 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000
313 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT 16
314 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)
315 #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000
316
317 #define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c
318 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff
319 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0
320 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
321
322 #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820
323
324 #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824
325
326 #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0))
327 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004
328 #define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002
329 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003
330 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0
331 #define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)
332 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c
333 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT 2
334 #define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)
335 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030
336 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT 4
337 #define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)
338 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0
339 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT 6
340 #define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)
341 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300
342 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT 8
343 #define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)
344 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00
345 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT 10
346 #define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)
347 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000
348 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT 12
349 #define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)
350 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000
351 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT 14
352 #define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)
353 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000
354 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT 16
355 #define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)
356 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000
357 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT 18
358 #define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)
359 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000
360 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT 20
361 #define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)
362 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000
363 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT 22
364 #define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)
365 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000
366 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT 24
367 #define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)
368 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000
369 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT 26
370 #define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)
371 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000
372 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT 28
373 #define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)
374 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000
375 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30
376 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
377
378 #define VIVS_GL_UNK0382C 0x0000382c
379
380 #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830
381
382 #define VIVS_GL_UNK03834 0x00003834
383
384 #define VIVS_GL_UNK03838 0x00003838
385
386 #define VIVS_GL_API_MODE 0x0000384c
387 #define VIVS_GL_API_MODE_OPENGL 0x00000000
388 #define VIVS_GL_API_MODE_OPENVG 0x00000001
389 #define VIVS_GL_API_MODE_OPENCL 0x00000002
390
391 #define VIVS_GL_CONTEXT_POINTER 0x00003850
392
393 #define VIVS_GL_UNK03854 0x00003854
394
395 #define VIVS_GL_BUG_FIXES 0x00003860
396
397 #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868
398
399 #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c
400
401 #define VIVS_GL_HALTI5_UNK03884 0x00003884
402
403 #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888
404 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f
405 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0
406 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK)
407 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00
408 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8
409 #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK)
410 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000
411 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16
412 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK)
413 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000
414 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24
415 #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK)
416
417 #define VIVS_GL_GS_UNK0388C 0x0000388c
418
419 #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898
420
421 #define VIVS_GL_SHADER_INDEX 0x0000389c
422
423 #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0))
424 #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004
425 #define VIVS_GL_GS_UNK038A0__LEN 0x00000008
426
427 #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0))
428 #define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004
429 #define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010
430
431 #define VIVS_GL_SECURITY_UNK3900 0x00003900
432
433 #define VIVS_GL_SECURITY_UNK3904 0x00003904
434
435 #define VIVS_GL_UNK03A00 0x00003a00
436
437 #define VIVS_GL_UNK03A04 0x00003a04
438
439 #define VIVS_GL_UNK03A08 0x00003a08
440
441 #define VIVS_GL_UNK03A0C 0x00003a0c
442
443 #define VIVS_GL_UNK03A10 0x00003a10
444
445 #define VIVS_GL_STALL_TOKEN 0x00003c00
446 #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f
447 #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0
448 #define VIVS_GL_STALL_TOKEN_FROM(x) (((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)
449 #define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00
450 #define VIVS_GL_STALL_TOKEN_TO__SHIFT 8
451 #define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)
452 #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000
453 #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000
454
455 #define VIVS_NFE 0x00000000
456
457 #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0))
458 #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004
459 #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010
460
461 #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0))
462
463 #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0))
464
465 #define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0))
466
467 #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))
468
469 #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0))
470 #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004
471 #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020
472
473 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0))
474 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f
475 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0
476 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)
477 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030
478 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4
479 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)
480 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700
481 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8
482 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)
483 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000
484 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12
485 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)
486 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000
487 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14
488 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000
489 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000
490 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000
491 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16
492 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)
493
494 #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0))
495
496 #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0))
497
498 #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0))
499
500 #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0))
501
502 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0))
503 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff
504 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0
505 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)
506 #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800
507
508 #define VIVS_DUMMY 0x00000000
509
510 #define VIVS_DUMMY_DUMMY 0x0003fffc
511
512
513 #endif /* STATE_XML */