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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / gallium / drivers / freedreno / a2xx / ir2_nir.c
1 /*
2 * Copyright (C) 2018 Jonathan Marek <jonathan@marek.ca>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jonathan Marek <jonathan@marek.ca>
25 */
26
27 #include "ir2_private.h"
28
29 #include "freedreno_util.h"
30 #include "fd2_program.h"
31
32 static const nir_shader_compiler_options options = {
33 .lower_fpow = true,
34 .lower_flrp32 = true,
35 .lower_fmod = true,
36 .lower_fdiv = true,
37 .lower_fceil = true,
38 .fuse_ffma = true,
39 /* .fdot_replicates = true, it is replicated, but it makes things worse */
40 .lower_all_io_to_temps = true,
41 .vertex_id_zero_based = true, /* its not implemented anyway */
42 .lower_bitops = true,
43 .lower_rotate = true,
44 .lower_vector_cmp = true,
45 .lower_fdph = true,
46 };
47
48 const nir_shader_compiler_options *
49 ir2_get_compiler_options(void)
50 {
51 return &options;
52 }
53
54 #define OPT(nir, pass, ...) ({ \
55 bool this_progress = false; \
56 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
57 this_progress; \
58 })
59 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
60
61 static void
62 ir2_optimize_loop(nir_shader *s)
63 {
64 bool progress;
65 do {
66 progress = false;
67
68 OPT_V(s, nir_lower_vars_to_ssa);
69 progress |= OPT(s, nir_opt_copy_prop_vars);
70 progress |= OPT(s, nir_copy_prop);
71 progress |= OPT(s, nir_opt_dce);
72 progress |= OPT(s, nir_opt_cse);
73 /* progress |= OPT(s, nir_opt_gcm, true); */
74 progress |= OPT(s, nir_opt_peephole_select, UINT_MAX, true, true);
75 progress |= OPT(s, nir_opt_intrinsics);
76 progress |= OPT(s, nir_opt_algebraic);
77 progress |= OPT(s, nir_opt_constant_folding);
78 progress |= OPT(s, nir_opt_dead_cf);
79 if (OPT(s, nir_opt_trivial_continues)) {
80 progress |= true;
81 /* If nir_opt_trivial_continues makes progress, then we need to clean
82 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
83 * to make progress.
84 */
85 OPT(s, nir_copy_prop);
86 OPT(s, nir_opt_dce);
87 }
88 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
89 progress |= OPT(s, nir_opt_if, false);
90 progress |= OPT(s, nir_opt_remove_phis);
91 progress |= OPT(s, nir_opt_undef);
92
93 }
94 while (progress);
95 }
96
97 /* trig workarounds is the same as ir3.. but we don't want to include ir3 */
98 bool ir3_nir_apply_trig_workarounds(nir_shader * shader);
99
100 int
101 ir2_optimize_nir(nir_shader *s, bool lower)
102 {
103 struct nir_lower_tex_options tex_options = {
104 .lower_txp = ~0u,
105 .lower_rect = 0,
106 };
107
108 if (fd_mesa_debug & FD_DBG_DISASM) {
109 debug_printf("----------------------\n");
110 nir_print_shader(s, stdout);
111 debug_printf("----------------------\n");
112 }
113
114 OPT_V(s, nir_lower_regs_to_ssa);
115 OPT_V(s, nir_lower_vars_to_ssa);
116 OPT_V(s, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out, UINT32_MAX);
117
118 if (lower) {
119 OPT_V(s, ir3_nir_apply_trig_workarounds);
120 OPT_V(s, nir_lower_tex, &tex_options);
121 }
122
123 ir2_optimize_loop(s);
124
125 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
126 OPT_V(s, nir_opt_sink, nir_move_const_undef);
127
128 /* TODO we dont want to get shaders writing to depth for depth textures */
129 if (s->info.stage == MESA_SHADER_FRAGMENT) {
130 nir_foreach_shader_out_variable(var, s) {
131 if (var->data.location == FRAG_RESULT_DEPTH)
132 return -1;
133 }
134 }
135
136 return 0;
137 }
138
139 static struct ir2_src
140 load_const(struct ir2_context *ctx, float *value_f, unsigned ncomp)
141 {
142 struct fd2_shader_stateobj *so = ctx->so;
143 unsigned imm_ncomp, swiz, idx, i, j;
144 uint32_t *value = (uint32_t*) value_f;
145
146 /* try to merge with existing immediate (TODO: try with neg) */
147 for (idx = 0; idx < so->num_immediates; idx++) {
148 swiz = 0;
149 imm_ncomp = so->immediates[idx].ncomp;
150 for (i = 0; i < ncomp; i++) {
151 for (j = 0; j < imm_ncomp; j++) {
152 if (value[i] == so->immediates[idx].val[j])
153 break;
154 }
155 if (j == imm_ncomp) {
156 if (j == 4)
157 break;
158 so->immediates[idx].val[imm_ncomp++] = value[i];
159 }
160 swiz |= swiz_set(j, i);
161 }
162 /* matched all components */
163 if (i == ncomp)
164 break;
165 }
166
167 /* need to allocate new immediate */
168 if (idx == so->num_immediates) {
169 swiz = 0;
170 imm_ncomp = 0;
171 for (i = 0; i < ncomp; i++) {
172 for (j = 0; j < imm_ncomp; j++) {
173 if (value[i] == ctx->so->immediates[idx].val[j])
174 break;
175 }
176 if (j == imm_ncomp) {
177 so->immediates[idx].val[imm_ncomp++] = value[i];
178 }
179 swiz |= swiz_set(j, i);
180 }
181 so->num_immediates++;
182 }
183 so->immediates[idx].ncomp = imm_ncomp;
184
185 if (ncomp == 1)
186 swiz = swiz_merge(swiz, IR2_SWIZZLE_XXXX);
187
188 return ir2_src(so->first_immediate + idx, swiz, IR2_SRC_CONST);
189 }
190
191 struct ir2_src
192 ir2_zero(struct ir2_context *ctx)
193 {
194 return load_const(ctx, (float[]) {0.0f}, 1);
195 }
196
197 static void
198 update_range(struct ir2_context *ctx, struct ir2_reg *reg)
199 {
200 if (!reg->initialized) {
201 reg->initialized = true;
202 reg->loop_depth = ctx->loop_depth;
203 }
204
205 if (ctx->loop_depth > reg->loop_depth) {
206 reg->block_idx_free = ctx->loop_last_block[reg->loop_depth + 1];
207 } else {
208 reg->loop_depth = ctx->loop_depth;
209 reg->block_idx_free = -1;
210 }
211
212 /* for regs we want to free at the end of the loop in any case
213 * XXX dont do this for ssa
214 */
215 if (reg->loop_depth)
216 reg->block_idx_free = ctx->loop_last_block[reg->loop_depth];
217 }
218
219 static struct ir2_src
220 make_src(struct ir2_context *ctx, nir_src src)
221 {
222 struct ir2_src res = {};
223 struct ir2_reg *reg;
224
225 nir_const_value *const_value = nir_src_as_const_value(src);
226
227 if (const_value) {
228 assert(src.is_ssa);
229 float c[src.ssa->num_components];
230 nir_const_value_to_array(c, const_value, src.ssa->num_components, f32);
231 return load_const(ctx, c, src.ssa->num_components);
232 }
233
234 if (!src.is_ssa) {
235 res.num = src.reg.reg->index;
236 res.type = IR2_SRC_REG;
237 reg = &ctx->reg[res.num];
238 } else {
239 assert(ctx->ssa_map[src.ssa->index] >= 0);
240 res.num = ctx->ssa_map[src.ssa->index];
241 res.type = IR2_SRC_SSA;
242 reg = &ctx->instr[res.num].ssa;
243 }
244
245 update_range(ctx, reg);
246 return res;
247 }
248
249 static void
250 set_index(struct ir2_context *ctx, nir_dest * dst,
251 struct ir2_instr *instr)
252 {
253 struct ir2_reg *reg = &instr->ssa;
254
255 if (dst->is_ssa) {
256 ctx->ssa_map[dst->ssa.index] = instr->idx;
257 } else {
258 assert(instr->is_ssa);
259 reg = &ctx->reg[dst->reg.reg->index];
260
261 instr->is_ssa = false;
262 instr->reg = reg;
263 }
264 update_range(ctx, reg);
265 }
266
267 static struct ir2_instr *
268 ir2_instr_create(struct ir2_context *ctx, int type)
269 {
270 struct ir2_instr *instr;
271
272 instr = &ctx->instr[ctx->instr_count++];
273 instr->idx = ctx->instr_count - 1;
274 instr->type = type;
275 instr->block_idx = ctx->block_idx;
276 instr->pred = ctx->pred;
277 instr->is_ssa = true;
278 return instr;
279 }
280
281 static struct ir2_instr *
282 instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
283 {
284 /* emit_alu will fixup instrs that don't map directly */
285 static const struct ir2_opc {
286 int8_t scalar, vector;
287 } nir_ir2_opc[nir_num_opcodes+1] = {
288 [0 ... nir_num_opcodes - 1] = {-1, -1},
289
290 [nir_op_mov] = {MAXs, MAXv},
291 [nir_op_fneg] = {MAXs, MAXv},
292 [nir_op_fabs] = {MAXs, MAXv},
293 [nir_op_fsat] = {MAXs, MAXv},
294 [nir_op_fsign] = {-1, CNDGTEv},
295 [nir_op_fadd] = {ADDs, ADDv},
296 [nir_op_fsub] = {ADDs, ADDv},
297 [nir_op_fmul] = {MULs, MULv},
298 [nir_op_ffma] = {-1, MULADDv},
299 [nir_op_fmax] = {MAXs, MAXv},
300 [nir_op_fmin] = {MINs, MINv},
301 [nir_op_ffloor] = {FLOORs, FLOORv},
302 [nir_op_ffract] = {FRACs, FRACv},
303 [nir_op_ftrunc] = {TRUNCs, TRUNCv},
304 [nir_op_fdot2] = {-1, DOT2ADDv},
305 [nir_op_fdot3] = {-1, DOT3v},
306 [nir_op_fdot4] = {-1, DOT4v},
307 [nir_op_sge] = {-1, SETGTEv},
308 [nir_op_slt] = {-1, SETGTv},
309 [nir_op_sne] = {-1, SETNEv},
310 [nir_op_seq] = {-1, SETEv},
311 [nir_op_fcsel] = {-1, CNDEv},
312 [nir_op_frsq] = {RECIPSQ_IEEE, -1},
313 [nir_op_frcp] = {RECIP_IEEE, -1},
314 [nir_op_flog2] = {LOG_IEEE, -1},
315 [nir_op_fexp2] = {EXP_IEEE, -1},
316 [nir_op_fsqrt] = {SQRT_IEEE, -1},
317 [nir_op_fcos] = {COS, -1},
318 [nir_op_fsin] = {SIN, -1},
319 /* no fsat, fneg, fabs since source mods deal with those */
320
321 /* so we can use this function with non-nir op */
322 #define ir2_op_cube nir_num_opcodes
323 [ir2_op_cube] = {-1, CUBEv},
324 };
325
326 struct ir2_opc op = nir_ir2_opc[opcode];
327 assert(op.vector >= 0 || op.scalar >= 0);
328
329 struct ir2_instr *instr = ir2_instr_create(ctx, IR2_ALU);
330 instr->alu.vector_opc = op.vector;
331 instr->alu.scalar_opc = op.scalar;
332 instr->alu.export = -1;
333 instr->alu.write_mask = (1 << ncomp) - 1;
334 instr->src_count = opcode == ir2_op_cube ? 2 :
335 nir_op_infos[opcode].num_inputs;
336 instr->ssa.ncomp = ncomp;
337 return instr;
338 }
339
340 static struct ir2_instr *
341 instr_create_alu_reg(struct ir2_context *ctx, nir_op opcode,
342 uint8_t write_mask, struct ir2_instr *share_reg)
343 {
344 struct ir2_instr *instr;
345 struct ir2_reg *reg;
346
347 reg = share_reg ? share_reg->reg : &ctx->reg[ctx->reg_count++];
348 reg->ncomp = MAX2(reg->ncomp, util_logbase2(write_mask) + 1);
349
350 instr = instr_create_alu(ctx, opcode, util_bitcount(write_mask));
351 instr->alu.write_mask = write_mask;
352 instr->reg = reg;
353 instr->is_ssa = false;
354 return instr;
355 }
356
357
358 static struct ir2_instr *
359 instr_create_alu_dest(struct ir2_context *ctx, nir_op opcode, nir_dest *dst)
360 {
361 struct ir2_instr *instr;
362 instr = instr_create_alu(ctx, opcode, nir_dest_num_components(*dst));
363 set_index(ctx, dst, instr);
364 return instr;
365 }
366
367 static struct ir2_instr *
368 ir2_instr_create_fetch(struct ir2_context *ctx, nir_dest *dst,
369 instr_fetch_opc_t opc)
370 {
371 struct ir2_instr *instr = ir2_instr_create(ctx, IR2_FETCH);
372 instr->fetch.opc = opc;
373 instr->src_count = 1;
374 instr->ssa.ncomp = nir_dest_num_components(*dst);
375 set_index(ctx, dst, instr);
376 return instr;
377 }
378
379 static struct ir2_src
380 make_src_noconst(struct ir2_context *ctx, nir_src src)
381 {
382 struct ir2_instr *instr;
383
384 if (nir_src_as_const_value(src)) {
385 assert(src.is_ssa);
386 instr = instr_create_alu(ctx, nir_op_mov, src.ssa->num_components);
387 instr->src[0] = make_src(ctx, src);
388 return ir2_src(instr->idx, 0, IR2_SRC_SSA);
389 }
390
391 return make_src(ctx, src);
392 }
393
394 static void
395 emit_alu(struct ir2_context *ctx, nir_alu_instr * alu)
396 {
397 const nir_op_info *info = &nir_op_infos[alu->op];
398 nir_dest *dst = &alu->dest.dest;
399 struct ir2_instr *instr;
400 struct ir2_src tmp;
401 unsigned ncomp;
402
403 /* get the number of dst components */
404 if (dst->is_ssa) {
405 ncomp = dst->ssa.num_components;
406 } else {
407 ncomp = 0;
408 for (int i = 0; i < 4; i++)
409 ncomp += !!(alu->dest.write_mask & 1 << i);
410 }
411
412 instr = instr_create_alu(ctx, alu->op, ncomp);
413 set_index(ctx, dst, instr);
414 instr->alu.saturate = alu->dest.saturate;
415 instr->alu.write_mask = alu->dest.write_mask;
416
417 for (int i = 0; i < info->num_inputs; i++) {
418 nir_alu_src *src = &alu->src[i];
419
420 /* compress swizzle with writemask when applicable */
421 unsigned swiz = 0, j = 0;
422 for (int i = 0; i < 4; i++) {
423 if (!(alu->dest.write_mask & 1 << i) && !info->output_size)
424 continue;
425 swiz |= swiz_set(src->swizzle[i], j++);
426 }
427
428 instr->src[i] = make_src(ctx, src->src);
429 instr->src[i].swizzle = swiz_merge(instr->src[i].swizzle, swiz);
430 instr->src[i].negate = src->negate;
431 instr->src[i].abs = src->abs;
432 }
433
434 /* workarounds for NIR ops that don't map directly to a2xx ops */
435 switch (alu->op) {
436 case nir_op_fneg:
437 instr->src[0].negate = 1;
438 break;
439 case nir_op_fabs:
440 instr->src[0].abs = 1;
441 break;
442 case nir_op_fsat:
443 instr->alu.saturate = 1;
444 break;
445 case nir_op_slt:
446 tmp = instr->src[0];
447 instr->src[0] = instr->src[1];
448 instr->src[1] = tmp;
449 break;
450 case nir_op_fcsel:
451 tmp = instr->src[1];
452 instr->src[1] = instr->src[2];
453 instr->src[2] = tmp;
454 break;
455 case nir_op_fsub:
456 instr->src[1].negate = !instr->src[1].negate;
457 break;
458 case nir_op_fdot2:
459 instr->src_count = 3;
460 instr->src[2] = ir2_zero(ctx);
461 break;
462 case nir_op_fsign: {
463 /* we need an extra instruction to deal with the zero case */
464 struct ir2_instr *tmp;
465
466 /* tmp = x == 0 ? 0 : 1 */
467 tmp = instr_create_alu(ctx, nir_op_fcsel, ncomp);
468 tmp->src[0] = instr->src[0];
469 tmp->src[1] = ir2_zero(ctx);
470 tmp->src[2] = load_const(ctx, (float[]) {1.0f}, 1);
471
472 /* result = x >= 0 ? tmp : -tmp */
473 instr->src[1] = ir2_src(tmp->idx, 0, IR2_SRC_SSA);
474 instr->src[2] = instr->src[1];
475 instr->src[2].negate = true;
476 instr->src_count = 3;
477 } break;
478 default:
479 break;
480 }
481 }
482
483 static void
484 load_input(struct ir2_context *ctx, nir_dest *dst, unsigned idx)
485 {
486 struct ir2_instr *instr;
487 int slot = -1;
488
489 if (ctx->so->type == MESA_SHADER_VERTEX) {
490 instr = ir2_instr_create_fetch(ctx, dst, 0);
491 instr->src[0] = ir2_src(0, 0, IR2_SRC_INPUT);
492 instr->fetch.vtx.const_idx = 20 + (idx / 3);
493 instr->fetch.vtx.const_idx_sel = idx % 3;
494 return;
495 }
496
497 /* get slot from idx */
498 nir_foreach_shader_in_variable(var, ctx->nir) {
499 if (var->data.driver_location == idx) {
500 slot = var->data.location;
501 break;
502 }
503 }
504 assert(slot >= 0);
505
506 switch (slot) {
507 case VARYING_SLOT_POS:
508 /* need to extract xy with abs and add tile offset on a20x
509 * zw from fragcoord input (w inverted in fragment shader)
510 * TODO: only components that are required by fragment shader
511 */
512 instr = instr_create_alu_reg(ctx,
513 ctx->so->is_a20x ? nir_op_fadd : nir_op_mov, 3, NULL);
514 instr->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
515 instr->src[0].abs = true;
516 /* on a20x, C64 contains the tile offset */
517 instr->src[1] = ir2_src(64, 0, IR2_SRC_CONST);
518
519 instr = instr_create_alu_reg(ctx, nir_op_mov, 4, instr);
520 instr->src[0] = ir2_src(ctx->f->fragcoord, 0, IR2_SRC_INPUT);
521
522 instr = instr_create_alu_reg(ctx, nir_op_frcp, 8, instr);
523 instr->src[0] = ir2_src(ctx->f->fragcoord, IR2_SWIZZLE_Y, IR2_SRC_INPUT);
524
525 unsigned reg_idx = instr->reg - ctx->reg; /* XXX */
526 instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
527 instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
528 break;
529 default:
530 instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
531 instr->src[0] = ir2_src(idx, 0, IR2_SRC_INPUT);
532 break;
533 }
534 }
535
536 static unsigned
537 output_slot(struct ir2_context *ctx, nir_intrinsic_instr *intr)
538 {
539 int slot = -1;
540 unsigned idx = nir_intrinsic_base(intr);
541 nir_foreach_shader_out_variable(var, ctx->nir) {
542 if (var->data.driver_location == idx) {
543 slot = var->data.location;
544 break;
545 }
546 }
547 assert(slot != -1);
548 return slot;
549 }
550
551 static void
552 store_output(struct ir2_context *ctx, nir_src src, unsigned slot, unsigned ncomp)
553 {
554 struct ir2_instr *instr;
555 unsigned idx = 0;
556
557 if (ctx->so->type == MESA_SHADER_VERTEX) {
558 switch (slot) {
559 case VARYING_SLOT_POS:
560 ctx->position = make_src(ctx, src);
561 idx = 62;
562 break;
563 case VARYING_SLOT_PSIZ:
564 ctx->so->writes_psize = true;
565 idx = 63;
566 break;
567 default:
568 /* find matching slot from fragment shader input */
569 for (idx = 0; idx < ctx->f->inputs_count; idx++)
570 if (ctx->f->inputs[idx].slot == slot)
571 break;
572 if (idx == ctx->f->inputs_count)
573 return;
574 }
575 } else if (slot != FRAG_RESULT_COLOR && slot != FRAG_RESULT_DATA0) {
576 /* only color output is implemented */
577 return;
578 }
579
580 instr = instr_create_alu(ctx, nir_op_mov, ncomp);
581 instr->src[0] = make_src(ctx, src);
582 instr->alu.export = idx;
583 }
584
585 static void
586 emit_intrinsic(struct ir2_context *ctx, nir_intrinsic_instr *intr)
587 {
588 struct ir2_instr *instr;
589 nir_const_value *const_offset;
590 unsigned idx;
591
592 switch (intr->intrinsic) {
593 case nir_intrinsic_load_input:
594 load_input(ctx, &intr->dest, nir_intrinsic_base(intr));
595 break;
596 case nir_intrinsic_store_output:
597 store_output(ctx, intr->src[0], output_slot(ctx, intr), intr->num_components);
598 break;
599 case nir_intrinsic_load_uniform:
600 const_offset = nir_src_as_const_value(intr->src[0]);
601 assert(const_offset); /* TODO can be false in ES2? */
602 idx = nir_intrinsic_base(intr);
603 idx += (uint32_t) nir_src_as_const_value(intr->src[0])[0].f32;
604 instr = instr_create_alu_dest(ctx, nir_op_mov, &intr->dest);
605 instr->src[0] = ir2_src(idx, 0, IR2_SRC_CONST);
606 break;
607 case nir_intrinsic_discard:
608 case nir_intrinsic_discard_if:
609 instr = ir2_instr_create(ctx, IR2_ALU);
610 instr->alu.vector_opc = VECTOR_NONE;
611 if (intr->intrinsic == nir_intrinsic_discard_if) {
612 instr->alu.scalar_opc = KILLNEs;
613 instr->src[0] = make_src(ctx, intr->src[0]);
614 } else {
615 instr->alu.scalar_opc = KILLEs;
616 instr->src[0] = ir2_zero(ctx);
617 }
618 instr->alu.export = -1;
619 instr->src_count = 1;
620 ctx->so->has_kill = true;
621 break;
622 case nir_intrinsic_load_front_face:
623 /* gl_FrontFacing is in the sign of param.x
624 * rcp required because otherwise we can't differentiate -0.0 and +0.0
625 */
626 ctx->so->need_param = true;
627
628 struct ir2_instr *tmp = instr_create_alu(ctx, nir_op_frcp, 1);
629 tmp->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
630
631 instr = instr_create_alu_dest(ctx, nir_op_sge, &intr->dest);
632 instr->src[0] = ir2_src(tmp->idx, 0, IR2_SRC_SSA);
633 instr->src[1] = ir2_zero(ctx);
634 break;
635 case nir_intrinsic_load_point_coord:
636 /* param.zw (note: abs might be needed like fragcoord in param.xy?) */
637 ctx->so->need_param = true;
638
639 instr = instr_create_alu_dest(ctx, nir_op_mov, &intr->dest);
640 instr->src[0] = ir2_src(ctx->f->inputs_count, IR2_SWIZZLE_ZW, IR2_SRC_INPUT);
641 break;
642 default:
643 compile_error(ctx, "unimplemented intr %d\n", intr->intrinsic);
644 break;
645 }
646 }
647
648 static void
649 emit_tex(struct ir2_context *ctx, nir_tex_instr * tex)
650 {
651 bool is_rect = false, is_cube = false;
652 struct ir2_instr *instr;
653 nir_src *coord, *lod_bias;
654
655 coord = lod_bias = NULL;
656
657 for (unsigned i = 0; i < tex->num_srcs; i++) {
658 switch (tex->src[i].src_type) {
659 case nir_tex_src_coord:
660 coord = &tex->src[i].src;
661 break;
662 case nir_tex_src_bias:
663 case nir_tex_src_lod:
664 assert(!lod_bias);
665 lod_bias = &tex->src[i].src;
666 break;
667 default:
668 compile_error(ctx, "Unhandled NIR tex src type: %d\n",
669 tex->src[i].src_type);
670 return;
671 }
672 }
673
674 switch (tex->op) {
675 case nir_texop_tex:
676 case nir_texop_txb:
677 case nir_texop_txl:
678 break;
679 default:
680 compile_error(ctx, "unimplemented texop %d\n", tex->op);
681 return;
682 }
683
684 switch (tex->sampler_dim) {
685 case GLSL_SAMPLER_DIM_2D:
686 break;
687 case GLSL_SAMPLER_DIM_RECT:
688 is_rect = true;
689 break;
690 case GLSL_SAMPLER_DIM_CUBE:
691 is_cube = true;
692 break;
693 default:
694 compile_error(ctx, "unimplemented sampler %d\n", tex->sampler_dim);
695 return;
696 }
697
698 struct ir2_src src_coord = make_src_noconst(ctx, *coord);
699
700 /* for cube maps
701 * tmp = cube(coord)
702 * tmp.xy = tmp.xy / |tmp.z| + 1.5
703 * coord = tmp.xyw
704 */
705 if (is_cube) {
706 struct ir2_instr *rcp, *coord_xy;
707 unsigned reg_idx;
708
709 instr = instr_create_alu_reg(ctx, ir2_op_cube, 15, NULL);
710 instr->src[0] = src_coord;
711 instr->src[0].swizzle = IR2_SWIZZLE_ZZXY;
712 instr->src[1] = src_coord;
713 instr->src[1].swizzle = IR2_SWIZZLE_YXZZ;
714
715 reg_idx = instr->reg - ctx->reg; /* hacky */
716
717 rcp = instr_create_alu(ctx, nir_op_frcp, 1);
718 rcp->src[0] = ir2_src(reg_idx, IR2_SWIZZLE_Z, IR2_SRC_REG);
719 rcp->src[0].abs = true;
720
721 coord_xy = instr_create_alu_reg(ctx, nir_op_ffma, 3, instr);
722 coord_xy->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
723 coord_xy->src[1] = ir2_src(rcp->idx, IR2_SWIZZLE_XXXX, IR2_SRC_SSA);
724 coord_xy->src[2] = load_const(ctx, (float[]) {1.5f}, 1);
725
726 src_coord = ir2_src(reg_idx, 0, IR2_SRC_REG);
727 /* TODO: lod/bias transformed by src_coord.z ? */
728 }
729
730 instr = ir2_instr_create_fetch(ctx, &tex->dest, TEX_FETCH);
731 instr->src[0] = src_coord;
732 instr->src[0].swizzle = is_cube ? IR2_SWIZZLE_YXW : 0;
733 instr->fetch.tex.is_cube = is_cube;
734 instr->fetch.tex.is_rect = is_rect;
735 instr->fetch.tex.samp_id = tex->sampler_index;
736
737 /* for lod/bias, we insert an extra src for the backend to deal with */
738 if (lod_bias) {
739 instr->src[1] = make_src_noconst(ctx, *lod_bias);
740 /* backend will use 2-3 components so apply swizzle */
741 swiz_merge_p(&instr->src[1].swizzle, IR2_SWIZZLE_XXXX);
742 instr->src_count = 2;
743 }
744 }
745
746 static void
747 setup_input(struct ir2_context *ctx, nir_variable * in)
748 {
749 struct fd2_shader_stateobj *so = ctx->so;
750 unsigned array_len = MAX2(glsl_get_length(in->type), 1);
751 unsigned n = in->data.driver_location;
752 unsigned slot = in->data.location;
753
754 assert(array_len == 1);
755
756 /* handle later */
757 if (ctx->so->type == MESA_SHADER_VERTEX)
758 return;
759
760 if (ctx->so->type != MESA_SHADER_FRAGMENT)
761 compile_error(ctx, "unknown shader type: %d\n", ctx->so->type);
762
763 n = ctx->f->inputs_count++;
764
765 /* half of fragcoord from param reg, half from a varying */
766 if (slot == VARYING_SLOT_POS) {
767 ctx->f->fragcoord = n;
768 so->need_param = true;
769 }
770
771 ctx->f->inputs[n].slot = slot;
772 ctx->f->inputs[n].ncomp = glsl_get_components(in->type);
773
774 /* in->data.interpolation?
775 * opengl ES 2.0 can't do flat mode, but we still get it from GALLIUM_HUD
776 */
777 }
778
779 static void
780 emit_undef(struct ir2_context *ctx, nir_ssa_undef_instr * undef)
781 {
782 /* TODO we don't want to emit anything for undefs */
783
784 struct ir2_instr *instr;
785
786 instr = instr_create_alu_dest(ctx, nir_op_mov,
787 &(nir_dest) {.ssa = undef->def,.is_ssa = true});
788 instr->src[0] = ir2_src(0, 0, IR2_SRC_CONST);
789 }
790
791 static void
792 emit_instr(struct ir2_context *ctx, nir_instr * instr)
793 {
794 switch (instr->type) {
795 case nir_instr_type_alu:
796 emit_alu(ctx, nir_instr_as_alu(instr));
797 break;
798 case nir_instr_type_deref:
799 /* ignored, handled as part of the intrinsic they are src to */
800 break;
801 case nir_instr_type_intrinsic:
802 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
803 break;
804 case nir_instr_type_load_const:
805 /* dealt with when using nir_src */
806 break;
807 case nir_instr_type_tex:
808 emit_tex(ctx, nir_instr_as_tex(instr));
809 break;
810 case nir_instr_type_jump:
811 ctx->block_has_jump[ctx->block_idx] = true;
812 break;
813 case nir_instr_type_ssa_undef:
814 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
815 break;
816 default:
817 break;
818 }
819 }
820
821 /* fragcoord.zw and a20x hw binning outputs */
822 static void
823 extra_position_exports(struct ir2_context *ctx, bool binning)
824 {
825 struct ir2_instr *instr, *rcp, *sc, *wincoord, *off;
826
827 if (ctx->f->fragcoord < 0 && !binning)
828 return;
829
830 instr = instr_create_alu(ctx, nir_op_fmax, 1);
831 instr->src[0] = ctx->position;
832 instr->src[0].swizzle = IR2_SWIZZLE_W;
833 instr->src[1] = ir2_zero(ctx);
834
835 rcp = instr_create_alu(ctx, nir_op_frcp, 1);
836 rcp->src[0] = ir2_src(instr->idx, 0, IR2_SRC_SSA);
837
838 sc = instr_create_alu(ctx, nir_op_fmul, 4);
839 sc->src[0] = ctx->position;
840 sc->src[1] = ir2_src(rcp->idx, IR2_SWIZZLE_XXXX, IR2_SRC_SSA);
841
842 wincoord = instr_create_alu(ctx, nir_op_ffma, 4);
843 wincoord->src[0] = ir2_src(66, 0, IR2_SRC_CONST);
844 wincoord->src[1] = ir2_src(sc->idx, 0, IR2_SRC_SSA);
845 wincoord->src[2] = ir2_src(65, 0, IR2_SRC_CONST);
846
847 /* fragcoord z/w */
848 if (ctx->f->fragcoord >= 0 && !binning) {
849 instr = instr_create_alu(ctx, nir_op_mov, 1);
850 instr->src[0] = ir2_src(wincoord->idx, IR2_SWIZZLE_Z, IR2_SRC_SSA);
851 instr->alu.export = ctx->f->fragcoord;
852
853 instr = instr_create_alu(ctx, nir_op_mov, 1);
854 instr->src[0] = ctx->position;
855 instr->src[0].swizzle = IR2_SWIZZLE_W;
856 instr->alu.export = ctx->f->fragcoord;
857 instr->alu.write_mask = 2;
858 }
859
860 if (!binning)
861 return;
862
863 off = instr_create_alu(ctx, nir_op_fadd, 1);
864 off->src[0] = ir2_src(64, 0, IR2_SRC_CONST);
865 off->src[1] = ir2_src(2, 0, IR2_SRC_INPUT);
866
867 /* 8 max set in freedreno_screen.. unneeded instrs patched out */
868 for (int i = 0; i < 8; i++) {
869 instr = instr_create_alu(ctx, nir_op_ffma, 4);
870 instr->src[0] = ir2_src(1, IR2_SWIZZLE_WYWW, IR2_SRC_CONST);
871 instr->src[1] = ir2_src(off->idx, IR2_SWIZZLE_XXXX, IR2_SRC_SSA);
872 instr->src[2] = ir2_src(3 + i, 0, IR2_SRC_CONST);
873 instr->alu.export = 32;
874
875 instr = instr_create_alu(ctx, nir_op_ffma, 4);
876 instr->src[0] = ir2_src(68 + i * 2, 0, IR2_SRC_CONST);
877 instr->src[1] = ir2_src(wincoord->idx, 0, IR2_SRC_SSA);
878 instr->src[2] = ir2_src(67 + i * 2, 0, IR2_SRC_CONST);
879 instr->alu.export = 33;
880 }
881 }
882
883 static bool emit_cf_list(struct ir2_context *ctx, struct exec_list *list);
884
885 static bool
886 emit_block(struct ir2_context *ctx, nir_block * block)
887 {
888 struct ir2_instr *instr;
889 nir_block *succs = block->successors[0];
890
891 ctx->block_idx = block->index;
892
893 nir_foreach_instr(instr, block)
894 emit_instr(ctx, instr);
895
896 if (!succs || !succs->index)
897 return false;
898
899 /* we want to be smart and always jump and have the backend cleanup
900 * but we are not, so there are two cases where jump is needed:
901 * loops (succs index lower)
902 * jumps (jump instruction seen in block)
903 */
904 if (succs->index > block->index && !ctx->block_has_jump[block->index])
905 return false;
906
907 assert(block->successors[1] == NULL);
908
909 instr = ir2_instr_create(ctx, IR2_CF);
910 instr->cf.block_idx = succs->index;
911 /* XXX can't jump to a block with different predicate */
912 return true;
913 }
914
915 static void
916 emit_if(struct ir2_context *ctx, nir_if * nif)
917 {
918 unsigned pred = ctx->pred, pred_idx = ctx->pred_idx;
919 struct ir2_instr *instr;
920
921 /* XXX: blob seems to always use same register for condition */
922
923 instr = ir2_instr_create(ctx, IR2_ALU);
924 instr->src[0] = make_src(ctx, nif->condition);
925 instr->src_count = 1;
926 instr->ssa.ncomp = 1;
927 instr->alu.vector_opc = VECTOR_NONE;
928 instr->alu.scalar_opc = SCALAR_NONE;
929 instr->alu.export = -1;
930 instr->alu.write_mask = 1;
931 instr->pred = 0;
932
933 /* if nested, use PRED_SETNE_PUSHv */
934 if (pred) {
935 instr->alu.vector_opc = PRED_SETNE_PUSHv;
936 instr->src[1] = instr->src[0];
937 instr->src[0] = ir2_src(pred_idx, 0, IR2_SRC_SSA);
938 instr->src[0].swizzle = IR2_SWIZZLE_XXXX;
939 instr->src[1].swizzle = IR2_SWIZZLE_XXXX;
940 instr->src_count = 2;
941 } else {
942 instr->alu.scalar_opc = PRED_SETNEs;
943 }
944
945 ctx->pred_idx = instr->idx;
946 ctx->pred = 3;
947
948 emit_cf_list(ctx, &nif->then_list);
949
950 /* TODO: if these is no else branch we don't need this
951 * and if the else branch is simple, can just flip ctx->pred instead
952 */
953 instr = ir2_instr_create(ctx, IR2_ALU);
954 instr->src[0] = ir2_src(ctx->pred_idx, 0, IR2_SRC_SSA);
955 instr->src_count = 1;
956 instr->ssa.ncomp = 1;
957 instr->alu.vector_opc = VECTOR_NONE;
958 instr->alu.scalar_opc = PRED_SET_INVs;
959 instr->alu.export = -1;
960 instr->alu.write_mask = 1;
961 instr->pred = 0;
962 ctx->pred_idx = instr->idx;
963
964 emit_cf_list(ctx, &nif->else_list);
965
966 /* restore predicate for nested predicates */
967 if (pred) {
968 instr = ir2_instr_create(ctx, IR2_ALU);
969 instr->src[0] = ir2_src(ctx->pred_idx, 0, IR2_SRC_SSA);
970 instr->src_count = 1;
971 instr->ssa.ncomp = 1;
972 instr->alu.vector_opc = VECTOR_NONE;
973 instr->alu.scalar_opc = PRED_SET_POPs;
974 instr->alu.export = -1;
975 instr->alu.write_mask = 1;
976 instr->pred = 0;
977 ctx->pred_idx = instr->idx;
978 }
979
980 /* restore ctx->pred */
981 ctx->pred = pred;
982 }
983
984 /* get the highest block idx in the loop, so we know when
985 * we can free registers that are allocated outside the loop
986 */
987 static unsigned
988 loop_last_block(struct exec_list *list)
989 {
990 nir_cf_node *node =
991 exec_node_data(nir_cf_node, exec_list_get_tail(list), node);
992 switch (node->type) {
993 case nir_cf_node_block:
994 return nir_cf_node_as_block(node)->index;
995 case nir_cf_node_if:
996 assert(0); /* XXX could this ever happen? */
997 return 0;
998 case nir_cf_node_loop:
999 return loop_last_block(&nir_cf_node_as_loop(node)->body);
1000 default:
1001 compile_error(ctx, "Not supported\n");
1002 return 0;
1003 }
1004 }
1005
1006 static void
1007 emit_loop(struct ir2_context *ctx, nir_loop *nloop)
1008 {
1009 ctx->loop_last_block[++ctx->loop_depth] = loop_last_block(&nloop->body);
1010 emit_cf_list(ctx, &nloop->body);
1011 ctx->loop_depth--;
1012 }
1013
1014 static bool
1015 emit_cf_list(struct ir2_context *ctx, struct exec_list *list)
1016 {
1017 bool ret = false;
1018 foreach_list_typed(nir_cf_node, node, node, list) {
1019 ret = false;
1020 switch (node->type) {
1021 case nir_cf_node_block:
1022 ret = emit_block(ctx, nir_cf_node_as_block(node));
1023 break;
1024 case nir_cf_node_if:
1025 emit_if(ctx, nir_cf_node_as_if(node));
1026 break;
1027 case nir_cf_node_loop:
1028 emit_loop(ctx, nir_cf_node_as_loop(node));
1029 break;
1030 case nir_cf_node_function:
1031 compile_error(ctx, "Not supported\n");
1032 break;
1033 }
1034 }
1035 return ret;
1036 }
1037
1038 static void cleanup_binning(struct ir2_context *ctx)
1039 {
1040 assert(ctx->so->type == MESA_SHADER_VERTEX);
1041
1042 /* kill non-position outputs for binning variant */
1043 nir_foreach_block(block, nir_shader_get_entrypoint(ctx->nir)) {
1044 nir_foreach_instr_safe(instr, block) {
1045 if (instr->type != nir_instr_type_intrinsic)
1046 continue;
1047
1048 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
1049 if (intr->intrinsic != nir_intrinsic_store_output)
1050 continue;
1051
1052 if (output_slot(ctx, intr) != VARYING_SLOT_POS)
1053 nir_instr_remove(instr);
1054 }
1055 }
1056
1057 ir2_optimize_nir(ctx->nir, false);
1058 }
1059
1060 static bool
1061 ir2_alu_to_scalar_filter_cb(const nir_instr *instr, const void *data)
1062 {
1063 if (instr->type != nir_instr_type_alu)
1064 return false;
1065
1066 nir_alu_instr *alu = nir_instr_as_alu(instr);
1067 switch (alu->op) {
1068 case nir_op_frsq:
1069 case nir_op_frcp:
1070 case nir_op_flog2:
1071 case nir_op_fexp2:
1072 case nir_op_fsqrt:
1073 case nir_op_fcos:
1074 case nir_op_fsin:
1075 return true;
1076 default:
1077 break;
1078 }
1079
1080 return false;
1081 }
1082
1083 void
1084 ir2_nir_compile(struct ir2_context *ctx, bool binning)
1085 {
1086 struct fd2_shader_stateobj *so = ctx->so;
1087
1088 memset(ctx->ssa_map, 0xff, sizeof(ctx->ssa_map));
1089
1090 ctx->nir = nir_shader_clone(NULL, so->nir);
1091
1092 if (binning)
1093 cleanup_binning(ctx);
1094
1095 OPT_V(ctx->nir, nir_copy_prop);
1096 OPT_V(ctx->nir, nir_opt_dce);
1097 OPT_V(ctx->nir, nir_opt_move, nir_move_comparisons);
1098
1099 OPT_V(ctx->nir, nir_lower_int_to_float);
1100 OPT_V(ctx->nir, nir_lower_bool_to_float);
1101 while(OPT(ctx->nir, nir_opt_algebraic));
1102 OPT_V(ctx->nir, nir_opt_algebraic_late);
1103 OPT_V(ctx->nir, nir_lower_to_source_mods, nir_lower_all_source_mods);
1104
1105 OPT_V(ctx->nir, nir_lower_alu_to_scalar, ir2_alu_to_scalar_filter_cb, NULL);
1106
1107 OPT_V(ctx->nir, nir_lower_locals_to_regs);
1108
1109 OPT_V(ctx->nir, nir_convert_from_ssa, true);
1110
1111 OPT_V(ctx->nir, nir_move_vec_src_uses_to_dest);
1112 OPT_V(ctx->nir, nir_lower_vec_to_movs);
1113
1114 OPT_V(ctx->nir, nir_opt_dce);
1115
1116 nir_sweep(ctx->nir);
1117
1118 if (fd_mesa_debug & FD_DBG_DISASM) {
1119 debug_printf("----------------------\n");
1120 nir_print_shader(ctx->nir, stdout);
1121 debug_printf("----------------------\n");
1122 }
1123
1124 /* fd2_shader_stateobj init */
1125 if (so->type == MESA_SHADER_FRAGMENT) {
1126 ctx->f->fragcoord = -1;
1127 ctx->f->inputs_count = 0;
1128 memset(ctx->f->inputs, 0, sizeof(ctx->f->inputs));
1129 }
1130
1131 /* Setup inputs: */
1132 nir_foreach_shader_in_variable(in, ctx->nir)
1133 setup_input(ctx, in);
1134
1135 if (so->type == MESA_SHADER_FRAGMENT) {
1136 unsigned idx;
1137 for (idx = 0; idx < ctx->f->inputs_count; idx++) {
1138 ctx->input[idx].ncomp = ctx->f->inputs[idx].ncomp;
1139 update_range(ctx, &ctx->input[idx]);
1140 }
1141 /* assume we have param input and kill it later if not */
1142 ctx->input[idx].ncomp = 4;
1143 update_range(ctx, &ctx->input[idx]);
1144 } else {
1145 ctx->input[0].ncomp = 1;
1146 ctx->input[2].ncomp = 1;
1147 update_range(ctx, &ctx->input[0]);
1148 update_range(ctx, &ctx->input[2]);
1149 }
1150
1151 /* And emit the body: */
1152 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->nir);
1153
1154 nir_foreach_register(reg, &fxn->registers) {
1155 ctx->reg[reg->index].ncomp = reg->num_components;
1156 ctx->reg_count = MAX2(ctx->reg_count, reg->index + 1);
1157 }
1158
1159 nir_metadata_require(fxn, nir_metadata_block_index);
1160 emit_cf_list(ctx, &fxn->body);
1161 /* TODO emit_block(ctx, fxn->end_block); */
1162
1163 if (so->type == MESA_SHADER_VERTEX)
1164 extra_position_exports(ctx, binning);
1165
1166 ralloc_free(ctx->nir);
1167
1168 /* kill unused param input */
1169 if (so->type == MESA_SHADER_FRAGMENT && !so->need_param)
1170 ctx->input[ctx->f->inputs_count].initialized = false;
1171 }