projects / mesa.git / blob
? search:


0758b40bf8c57c9d035574cb9a0f76c8e9c6c2d2
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 #include "ir3_const.h"
47
48 static const enum adreno_state_block sb[] = {
49 [MESA_SHADER_VERTEX] = SB_VERT_SHADER,
50 [MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
51 };
52
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
56 */
57 static void
58 fd3_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
59 uint32_t regid, uint32_t offset, uint32_t sizedwords,
60 const uint32_t *dwords, struct pipe_resource *prsc)
61 {
62 uint32_t i, sz;
63 enum adreno_state_src src;
64
65 debug_assert((regid % 4) == 0);
66 debug_assert((sizedwords % 4) == 0);
67
68 if (prsc) {
69 sz = 0;
70 src = SS_INDIRECT;
71 } else {
72 sz = sizedwords;
73 src = SS_DIRECT;
74 }
75
76 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
81 if (prsc) {
82 struct fd_bo *bo = fd_resource(prsc)->bo;
83 OUT_RELOC(ring, bo, offset,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
85 } else {
86 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
88 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
89 }
90 for (i = 0; i < sz; i++) {
91 OUT_RING(ring, dwords[i]);
92 }
93 }
94
95 static void
96 fd3_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type,
97 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
98 {
99 uint32_t anum = align(num, 4);
100 uint32_t i;
101
102 debug_assert((regid % 4) == 0);
103
104 OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
108 CP_LOAD_STATE_0_NUM_UNIT(anum/2));
109 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
111
112 for (i = 0; i < num; i++) {
113 if (prscs[i]) {
114 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
115 } else {
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++)
121 OUT_RING(ring, 0xffffffff);
122 }
123
124 static bool
125 is_stateobj(struct fd_ringbuffer *ring)
126 {
127 return false;
128 }
129
130 void
131 emit_const(struct fd_ringbuffer *ring,
132 const struct ir3_shader_variant *v, uint32_t dst_offset,
133 uint32_t offset, uint32_t size, const void *user_buffer,
134 struct pipe_resource *buffer)
135 {
136 /* TODO inline this */
137 assert(dst_offset + size <= v->constlen * 4);
138 fd3_emit_const(ring, v->type, dst_offset,
139 offset, size, user_buffer, buffer);
140 }
141
142 static void
143 emit_const_bo(struct fd_ringbuffer *ring,
144 const struct ir3_shader_variant *v, uint32_t dst_offset,
145 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
146 {
147 /* TODO inline this */
148 assert(dst_offset + num <= v->constlen * 4);
149 fd3_emit_const_bo(ring, v->type, dst_offset, num, prscs, offsets);
150 }
151
152 #define VERT_TEX_OFF 0
153 #define FRAG_TEX_OFF 16
154 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
155
156 static void
157 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
158 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
159 {
160 static const unsigned tex_off[] = {
161 [SB_VERT_TEX] = VERT_TEX_OFF,
162 [SB_FRAG_TEX] = FRAG_TEX_OFF,
163 };
164 static const enum adreno_state_block mipaddr[] = {
165 [SB_VERT_TEX] = SB_VERT_MIPADDR,
166 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
167 };
168 static const uint32_t bcolor_reg[] = {
169 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
170 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
171 };
172 struct fd3_context *fd3_ctx = fd3_context(ctx);
173 bool needs_border = false;
174 unsigned i, j;
175
176 if (tex->num_samplers > 0) {
177 /* output sampler state: */
178 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
179 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
180 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
181 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
182 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
183 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
184 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
185 for (i = 0; i < tex->num_samplers; i++) {
186 static const struct fd3_sampler_stateobj dummy_sampler = {};
187 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
188 fd3_sampler_stateobj(tex->samplers[i]) :
189 &dummy_sampler;
190
191 OUT_RING(ring, sampler->texsamp0);
192 OUT_RING(ring, sampler->texsamp1);
193
194 needs_border |= sampler->needs_border;
195 }
196 }
197
198 if (tex->num_textures > 0) {
199 /* emit texture state: */
200 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
201 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
202 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
203 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
204 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
205 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
206 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
207 for (i = 0; i < tex->num_textures; i++) {
208 static const struct fd3_pipe_sampler_view dummy_view = {};
209 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
210 fd3_pipe_sampler_view(tex->textures[i]) :
211 &dummy_view;
212 OUT_RING(ring, view->texconst0);
213 OUT_RING(ring, view->texconst1);
214 OUT_RING(ring, view->texconst2 |
215 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
216 OUT_RING(ring, view->texconst3);
217 }
218
219 /* emit mipaddrs: */
220 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
221 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
222 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
223 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
224 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
225 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
226 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
227 for (i = 0; i < tex->num_textures; i++) {
228 static const struct fd3_pipe_sampler_view dummy_view = {
229 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
230 .base.u.tex.first_level = 1,
231 };
232 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
233 fd3_pipe_sampler_view(tex->textures[i]) :
234 &dummy_view;
235 struct fd_resource *rsc = fd_resource(view->base.texture);
236 if (rsc && rsc->base.target == PIPE_BUFFER) {
237 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
238 j = 1;
239 } else {
240 unsigned start = fd_sampler_first_level(&view->base);
241 unsigned end = fd_sampler_last_level(&view->base);
242
243 for (j = 0; j < (end - start + 1); j++) {
244 struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
245 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
246 }
247 }
248
249 /* pad the remaining entries w/ null: */
250 for (; j < BASETABLE_SZ; j++) {
251 OUT_RING(ring, 0x00000000);
252 }
253 }
254 }
255
256 if (needs_border) {
257 unsigned off;
258 void *ptr;
259
260 u_upload_alloc(fd3_ctx->border_color_uploader,
261 0, BORDER_COLOR_UPLOAD_SIZE,
262 BORDER_COLOR_UPLOAD_SIZE, &off,
263 &fd3_ctx->border_color_buf,
264 &ptr);
265
266 fd_setup_border_colors(tex, ptr, tex_off[sb]);
267
268 OUT_PKT0(ring, bcolor_reg[sb], 1);
269 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
270
271 u_upload_unmap(fd3_ctx->border_color_uploader);
272 }
273 }
274
275 /* emit texture state for mem->gmem restore operation.. eventually it would
276 * be good to get rid of this and use normal CSO/etc state for more of these
277 * special cases, but for now the compiler is not sufficient..
278 *
279 * Also, for using normal state, not quite sure how to handle the special
280 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
281 */
282 void
283 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
284 struct pipe_surface **psurf,
285 int bufs)
286 {
287 int i, j;
288
289 /* output sampler state: */
290 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
291 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
292 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
293 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
294 CP_LOAD_STATE_0_NUM_UNIT(bufs));
295 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
296 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
297 for (i = 0; i < bufs; i++) {
298 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
299 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
300 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
301 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
302 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
303 OUT_RING(ring, 0x00000000);
304 }
305
306 /* emit texture state: */
307 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
308 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
309 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
310 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
311 CP_LOAD_STATE_0_NUM_UNIT(bufs));
312 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
313 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
314 for (i = 0; i < bufs; i++) {
315 if (!psurf[i]) {
316 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
317 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
318 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
319 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
320 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
321 OUT_RING(ring, 0x00000000);
322 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
323 OUT_RING(ring, 0x00000000);
324 continue;
325 }
326
327 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
328 enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
329 /* The restore blit_zs shader expects stencil in sampler 0, and depth
330 * in sampler 1
331 */
332 if (rsc->stencil && i == 0) {
333 rsc = rsc->stencil;
334 format = fd_gmem_restore_format(rsc->base.format);
335 }
336
337 /* note: PIPE_BUFFER disallowed for surfaces */
338 unsigned lvl = psurf[i]->u.tex.level;
339 struct fdl_slice *slice = fd_resource_slice(rsc, lvl);
340
341 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
342
343 OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
344 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
345 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
346 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
347 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
348 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
349 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
350 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
351 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch) |
352 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
353 OUT_RING(ring, 0x00000000);
354 }
355
356 /* emit mipaddrs: */
357 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
358 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
359 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
360 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
361 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
362 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
363 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
364 for (i = 0; i < bufs; i++) {
365 if (psurf[i]) {
366 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
367 /* Matches above logic for blit_zs shader */
368 if (rsc->stencil && i == 0)
369 rsc = rsc->stencil;
370 unsigned lvl = psurf[i]->u.tex.level;
371 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
372 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
373 } else {
374 OUT_RING(ring, 0x00000000);
375 }
376
377 /* pad the remaining entries w/ null: */
378 for (j = 1; j < BASETABLE_SZ; j++) {
379 OUT_RING(ring, 0x00000000);
380 }
381 }
382 }
383
384 void
385 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
386 {
387 int32_t i, j, last = -1;
388 uint32_t total_in = 0;
389 const struct fd_vertex_state *vtx = emit->vtx;
390 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
391 unsigned vertex_regid = regid(63, 0);
392 unsigned instance_regid = regid(63, 0);
393 unsigned vtxcnt_regid = regid(63, 0);
394
395 /* Note that sysvals come *after* normal inputs: */
396 for (i = 0; i < vp->inputs_count; i++) {
397 if (!vp->inputs[i].compmask)
398 continue;
399 if (vp->inputs[i].sysval) {
400 switch(vp->inputs[i].slot) {
401 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
402 vertex_regid = vp->inputs[i].regid;
403 break;
404 case SYSTEM_VALUE_INSTANCE_ID:
405 instance_regid = vp->inputs[i].regid;
406 break;
407 case SYSTEM_VALUE_VERTEX_CNT:
408 vtxcnt_regid = vp->inputs[i].regid;
409 break;
410 default:
411 unreachable("invalid system value");
412 break;
413 }
414 } else if (i < vtx->vtx->num_elements) {
415 last = i;
416 }
417 }
418
419 for (i = 0, j = 0; i <= last; i++) {
420 assert(!vp->inputs[i].sysval);
421 if (vp->inputs[i].compmask) {
422 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
423 const struct pipe_vertex_buffer *vb =
424 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
425 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
426 enum pipe_format pfmt = elem->src_format;
427 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
428 bool switchnext = (i != last) ||
429 (vertex_regid != regid(63, 0)) ||
430 (instance_regid != regid(63, 0)) ||
431 (vtxcnt_regid != regid(63, 0));
432 bool isint = util_format_is_pure_integer(pfmt);
433 uint32_t off = vb->buffer_offset + elem->src_offset;
434 uint32_t fs = util_format_get_blocksize(pfmt);
435
436 #ifdef DEBUG
437 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
438 * should mesa/st be protecting us from this?
439 */
440 if (off > fd_bo_size(rsc->bo))
441 continue;
442 #endif
443
444 debug_assert(fmt != VFMT_NONE);
445
446 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
447 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
448 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
449 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
450 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
451 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
452 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
453 OUT_RELOC(ring, rsc->bo, off, 0, 0);
454
455 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
456 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
457 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
458 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
459 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
460 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
461 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
462 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
463 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
464 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
465
466 total_in += util_bitcount(vp->inputs[i].compmask);
467 j++;
468 }
469 }
470
471 /* hw doesn't like to be configured for zero vbo's, it seems: */
472 if (last < 0) {
473 /* just recycle the shader bo, we just need to point to *something*
474 * valid:
475 */
476 struct fd_bo *dummy_vbo = vp->bo;
477 bool switchnext = (vertex_regid != regid(63, 0)) ||
478 (instance_regid != regid(63, 0)) ||
479 (vtxcnt_regid != regid(63, 0));
480
481 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
482 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
483 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
484 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
485 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
486 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
487 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
488
489 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
490 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
491 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
492 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
493 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
494 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
495 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
496 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
497 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
498
499 total_in = 1;
500 j = 1;
501 }
502
503 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
504 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
505 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
506 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
507 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
508 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
509 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
510 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
511
512 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
513 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
514 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
515 }
516
517 void
518 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
519 struct fd3_emit *emit)
520 {
521 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
522 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
523 const enum fd_dirty_3d_state dirty = emit->dirty;
524
525 emit_marker(ring, 5);
526
527 if (dirty & FD_DIRTY_SAMPLE_MASK) {
528 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
529 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
530 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
531 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
532 }
533
534 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
535 !emit->binning_pass) {
536 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
537 fd3_blend_stateobj(ctx->blend)->rb_render_control;
538
539 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
540 val |= COND(fp->fragcoord_compmask != 0,
541 A3XX_RB_RENDER_CONTROL_COORD_MASK(fp->fragcoord_compmask));
542 val |= COND(ctx->rasterizer->rasterizer_discard,
543 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
544
545 /* I suppose if we needed to (which I don't *think* we need
546 * to), we could emit this for binning pass too. But we
547 * would need to keep a different patch-list for binning
548 * vs render pass.
549 */
550
551 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
552 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
553 }
554
555 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
556 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
557 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
558
559 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
560 OUT_RING(ring, zsa->rb_alpha_ref);
561
562 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
563 OUT_RING(ring, zsa->rb_stencil_control);
564
565 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
566 OUT_RING(ring, zsa->rb_stencilrefmask |
567 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
568 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
569 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
570 }
571
572 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
573 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
574 if (fp->writes_pos) {
575 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
576 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
577 }
578 if (fp->no_earlyz || fp->has_kill) {
579 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
580 }
581 if (!ctx->rasterizer->depth_clip_near) {
582 val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
583 }
584 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
585 OUT_RING(ring, val);
586 }
587
588 if (dirty & FD_DIRTY_RASTERIZER) {
589 struct fd3_rasterizer_stateobj *rasterizer =
590 fd3_rasterizer_stateobj(ctx->rasterizer);
591
592 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
593 OUT_RING(ring, rasterizer->gras_su_mode_control);
594
595 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
596 OUT_RING(ring, rasterizer->gras_su_point_minmax);
597 OUT_RING(ring, rasterizer->gras_su_point_size);
598
599 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
600 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
601 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
602 }
603
604 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
605 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
606 ->gras_cl_clip_cntl;
607 uint8_t planes = ctx->rasterizer->clip_plane_enable;
608 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
609 val |= COND(fp->fragcoord_compmask != 0, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
610 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
611 if (!emit->key.ucp_enables)
612 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
613 MIN2(util_bitcount(planes), 6));
614 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
615 OUT_RING(ring, val);
616 }
617
618 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
619 uint32_t planes = ctx->rasterizer->clip_plane_enable;
620 int count = 0;
621
622 if (emit->key.ucp_enables)
623 planes = 0;
624
625 while (planes && count < 6) {
626 int i = ffs(planes) - 1;
627
628 planes &= ~(1U << i);
629 fd_wfi(ctx->batch, ring);
630 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
631 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
632 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
633 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
634 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
635 }
636 }
637
638 /* NOTE: since primitive_restart is not actually part of any
639 * state object, we need to make sure that we always emit
640 * PRIM_VTX_CNTL.. either that or be more clever and detect
641 * when it changes.
642 */
643 if (emit->info) {
644 const struct pipe_draw_info *info = emit->info;
645 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
646 ->pc_prim_vtx_cntl;
647
648 if (!emit->binning_pass) {
649 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
650 if (stride_in_vpc > 0)
651 stride_in_vpc = MAX2(stride_in_vpc, 2);
652 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
653 }
654
655 if (info->index_size && info->primitive_restart) {
656 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
657 }
658
659 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
660
661 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
662 OUT_RING(ring, val);
663 }
664
665 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
666 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
667 int minx = scissor->minx;
668 int miny = scissor->miny;
669 int maxx = scissor->maxx;
670 int maxy = scissor->maxy;
671
672 /* Unfortunately there is no separate depth clip disable, only an all
673 * or nothing deal. So when we disable clipping, we must handle the
674 * viewport clip via scissors.
675 */
676 if (!ctx->rasterizer->depth_clip_near) {
677 struct pipe_viewport_state *vp = &ctx->viewport;
678 minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
679 miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
680 maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
681 maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
682 }
683
684 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
685 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
686 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
687 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
688 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
689
690 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
691 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
692 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
693 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
694 }
695
696 if (dirty & FD_DIRTY_VIEWPORT) {
697 fd_wfi(ctx->batch, ring);
698 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
699 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
700 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
701 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
702 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
703 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
704 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
705 }
706
707 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
708 float zmin, zmax;
709 int depth = 24;
710 if (ctx->batch->framebuffer.zsbuf) {
711 depth = util_format_get_component_bits(
712 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
713 UTIL_FORMAT_COLORSPACE_ZS, 0);
714 }
715 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
716 &zmin, &zmax);
717
718 OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
719 if (depth == 32) {
720 OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
721 OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
722 } else if (depth == 16) {
723 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
724 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
725 } else {
726 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
727 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
728 }
729 }
730
731 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
732 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
733 int nr_cbufs = pfb->nr_cbufs;
734 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
735 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
736 nr_cbufs++;
737 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
738 }
739
740 /* TODO we should not need this or fd_wfi() before emit_constants():
741 */
742 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
743 OUT_RING(ring, HLSQ_FLUSH);
744
745 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
746 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
747 if (!emit->binning_pass)
748 ir3_emit_fs_consts(fp, ring, ctx);
749 }
750
751 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
752 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
753 uint32_t i;
754
755 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
756 enum pipe_format format =
757 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
758 const struct util_format_description *desc =
759 util_format_description(format);
760 bool is_float = util_format_is_float(format);
761 bool is_int = util_format_is_pure_integer(format);
762 bool has_alpha = util_format_has_alpha(format);
763 uint32_t control = blend->rb_mrt[i].control;
764
765 if (is_int) {
766 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
767 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
768 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
769 }
770
771 if (format == PIPE_FORMAT_NONE)
772 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
773
774 if (!has_alpha) {
775 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
776 }
777
778 if (format && util_format_get_component_bits(
779 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
780 const struct pipe_rt_blend_state *rt;
781 if (ctx->blend->independent_blend_enable)
782 rt = &ctx->blend->rt[i];
783 else
784 rt = &ctx->blend->rt[0];
785
786 if (!util_format_colormask_full(desc, rt->colormask))
787 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
788 }
789
790 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
791 OUT_RING(ring, control);
792
793 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
794 OUT_RING(ring, blend->rb_mrt[i].blend_control |
795 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
796 }
797 }
798
799 if (dirty & FD_DIRTY_BLEND_COLOR) {
800 struct pipe_blend_color *bcolor = &ctx->blend_color;
801 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
802 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
803 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
804 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
805 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
806 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
807 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
808 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
809 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
810 }
811
812 if (dirty & FD_DIRTY_TEX)
813 fd_wfi(ctx->batch, ring);
814
815 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
816 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
817
818 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
819 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
820 }
821
822 /* emit setup at begin of new cmdstream buffer (don't rely on previous
823 * state, there could have been a context switch between ioctls):
824 */
825 void
826 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
827 {
828 struct fd_context *ctx = batch->ctx;
829 struct fd3_context *fd3_ctx = fd3_context(ctx);
830 int i;
831
832 if (ctx->screen->gpu_id == 320) {
833 OUT_PKT3(ring, CP_REG_RMW, 3);
834 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
835 OUT_RING(ring, 0xfffcffff);
836 OUT_RING(ring, 0x00000000);
837 }
838
839 fd_wfi(batch, ring);
840 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
841 OUT_RING(ring, 0x00007fff);
842
843 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
844 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
845 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
846 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
847
848 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
849 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
850 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
851 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
852
853 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
854 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
855
856 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
857 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
858 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
859 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
860
861 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
862 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
863 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
864 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
865 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
866
867 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
868 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
869 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
870
871 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
872 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
873
874 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
875 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
876 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
877 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
878
879 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
880 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
881 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
882 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
883
884 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
885 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
886 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
887
888 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
889 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
890
891 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
892 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
893
894 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
895 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
896
897 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
898 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
899
900 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
901 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
902
903 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
904 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
905 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
906 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
907 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
908
909 fd3_emit_cache_flush(batch, ring);
910
911 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
912 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
913
914 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
915 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
916 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
917
918 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
919 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
920
921 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
922 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
923 A3XX_RB_WINDOW_OFFSET_Y(0));
924
925 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
926 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
927 A3XX_RB_BLEND_RED_FLOAT(0.0));
928 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
929 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
930 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
931 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
932 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
933 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
934
935 for (i = 0; i < 6; i++) {
936 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
937 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
938 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
939 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
940 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
941 }
942
943 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
944 OUT_RING(ring, 0x00000000);
945
946 fd_event_write(batch, ring, CACHE_FLUSH);
947
948 if (is_a3xx_p0(ctx->screen)) {
949 OUT_PKT3(ring, CP_DRAW_INDX, 3);
950 OUT_RING(ring, 0x00000000);
951 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
952 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
953 OUT_RING(ring, 0); /* NumIndices */
954 }
955
956 OUT_PKT3(ring, CP_NOP, 4);
957 OUT_RING(ring, 0x00000000);
958 OUT_RING(ring, 0x00000000);
959 OUT_RING(ring, 0x00000000);
960 OUT_RING(ring, 0x00000000);
961
962 fd_wfi(batch, ring);
963
964 fd_hw_query_enable(batch, ring);
965 }
966
967 void
968 fd3_emit_init_screen(struct pipe_screen *pscreen)
969 {
970 struct fd_screen *screen = fd_screen(pscreen);
971 screen->emit_ib = fd3_emit_ib;
972 }
973
974 void
975 fd3_emit_init(struct pipe_context *pctx)
976 {
977 }