2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
46 #include "ir3_const.h"
48 static const enum adreno_state_block sb
[] = {
49 [MESA_SHADER_VERTEX
] = SB_VERT_SHADER
,
50 [MESA_SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
58 fd3_emit_const(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
59 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
60 const uint32_t *dwords
, struct pipe_resource
*prsc
)
63 enum adreno_state_src src
;
65 debug_assert((regid
% 4) == 0);
66 debug_assert((sizedwords
% 4) == 0);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/2));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 fd3_emit_const_bo(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
97 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
99 uint32_t anum
= align(num
, 4);
102 debug_assert((regid
% 4) == 0);
104 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + anum
);
105 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/2) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
108 CP_LOAD_STATE_0_NUM_UNIT(anum
/2));
109 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
112 for (i
= 0; i
< num
; i
++) {
114 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
116 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
120 for (; i
< anum
; i
++)
121 OUT_RING(ring
, 0xffffffff);
125 is_stateobj(struct fd_ringbuffer
*ring
)
131 emit_const(struct fd_ringbuffer
*ring
,
132 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
133 uint32_t offset
, uint32_t size
, const void *user_buffer
,
134 struct pipe_resource
*buffer
)
136 /* TODO inline this */
137 assert(dst_offset
+ size
<= v
->constlen
* 4);
138 fd3_emit_const(ring
, v
->type
, dst_offset
,
139 offset
, size
, user_buffer
, buffer
);
143 emit_const_bo(struct fd_ringbuffer
*ring
,
144 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
145 uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
147 /* TODO inline this */
148 assert(dst_offset
+ num
<= v
->constlen
* 4);
149 fd3_emit_const_bo(ring
, v
->type
, dst_offset
, num
, prscs
, offsets
);
152 #define VERT_TEX_OFF 0
153 #define FRAG_TEX_OFF 16
154 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
157 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
158 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
160 static const unsigned tex_off
[] = {
161 [SB_VERT_TEX
] = VERT_TEX_OFF
,
162 [SB_FRAG_TEX
] = FRAG_TEX_OFF
,
164 static const enum adreno_state_block mipaddr
[] = {
165 [SB_VERT_TEX
] = SB_VERT_MIPADDR
,
166 [SB_FRAG_TEX
] = SB_FRAG_MIPADDR
,
168 static const uint32_t bcolor_reg
[] = {
169 [SB_VERT_TEX
] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
170 [SB_FRAG_TEX
] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
172 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
173 bool needs_border
= false;
176 if (tex
->num_samplers
> 0) {
177 /* output sampler state: */
178 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * tex
->num_samplers
));
179 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
180 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
181 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
182 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_samplers
));
183 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
184 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
185 for (i
= 0; i
< tex
->num_samplers
; i
++) {
186 static const struct fd3_sampler_stateobj dummy_sampler
= {};
187 const struct fd3_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
188 fd3_sampler_stateobj(tex
->samplers
[i
]) :
191 OUT_RING(ring
, sampler
->texsamp0
);
192 OUT_RING(ring
, sampler
->texsamp1
);
194 needs_border
|= sampler
->needs_border
;
198 if (tex
->num_textures
> 0) {
199 /* emit texture state: */
200 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (4 * tex
->num_textures
));
201 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(tex_off
[sb
]) |
202 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
203 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
204 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
205 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
206 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
207 for (i
= 0; i
< tex
->num_textures
; i
++) {
208 static const struct fd3_pipe_sampler_view dummy_view
= {};
209 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
210 fd3_pipe_sampler_view(tex
->textures
[i
]) :
212 OUT_RING(ring
, view
->texconst0
);
213 OUT_RING(ring
, view
->texconst1
);
214 OUT_RING(ring
, view
->texconst2
|
215 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
216 OUT_RING(ring
, view
->texconst3
);
220 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (BASETABLE_SZ
* tex
->num_textures
));
221 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* tex_off
[sb
]) |
222 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
223 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr
[sb
]) |
224 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* tex
->num_textures
));
225 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
226 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
227 for (i
= 0; i
< tex
->num_textures
; i
++) {
228 static const struct fd3_pipe_sampler_view dummy_view
= {
229 .base
.target
= PIPE_TEXTURE_1D
, /* anything !PIPE_BUFFER */
230 .base
.u
.tex
.first_level
= 1,
232 const struct fd3_pipe_sampler_view
*view
= tex
->textures
[i
] ?
233 fd3_pipe_sampler_view(tex
->textures
[i
]) :
235 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
236 if (rsc
&& rsc
->base
.target
== PIPE_BUFFER
) {
237 OUT_RELOC(ring
, rsc
->bo
, view
->base
.u
.buf
.offset
, 0, 0);
240 unsigned start
= fd_sampler_first_level(&view
->base
);
241 unsigned end
= fd_sampler_last_level(&view
->base
);
243 for (j
= 0; j
< (end
- start
+ 1); j
++) {
244 struct fdl_slice
*slice
= fd_resource_slice(rsc
, j
+ start
);
245 OUT_RELOC(ring
, rsc
->bo
, slice
->offset
, 0, 0);
249 /* pad the remaining entries w/ null: */
250 for (; j
< BASETABLE_SZ
; j
++) {
251 OUT_RING(ring
, 0x00000000);
260 u_upload_alloc(fd3_ctx
->border_color_uploader
,
261 0, BORDER_COLOR_UPLOAD_SIZE
,
262 BORDER_COLOR_UPLOAD_SIZE
, &off
,
263 &fd3_ctx
->border_color_buf
,
266 fd_setup_border_colors(tex
, ptr
, tex_off
[sb
]);
268 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
269 OUT_RELOC(ring
, fd_resource(fd3_ctx
->border_color_buf
)->bo
, off
, 0, 0);
271 u_upload_unmap(fd3_ctx
->border_color_uploader
);
275 /* emit texture state for mem->gmem restore operation.. eventually it would
276 * be good to get rid of this and use normal CSO/etc state for more of these
277 * special cases, but for now the compiler is not sufficient..
279 * Also, for using normal state, not quite sure how to handle the special
280 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
283 fd3_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
,
284 struct pipe_surface
**psurf
,
289 /* output sampler state: */
290 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 2 * bufs
);
291 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
292 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
293 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
294 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
295 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
296 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
297 for (i
= 0; i
< bufs
; i
++) {
298 OUT_RING(ring
, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST
) |
299 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST
) |
300 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE
) |
301 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE
) |
302 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT
));
303 OUT_RING(ring
, 0x00000000);
306 /* emit texture state: */
307 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + 4 * bufs
);
308 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF
) |
309 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
310 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
311 CP_LOAD_STATE_0_NUM_UNIT(bufs
));
312 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
313 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
314 for (i
= 0; i
< bufs
; i
++) {
316 OUT_RING(ring
, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
317 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE
) |
318 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE
) |
319 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE
) |
320 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE
));
321 OUT_RING(ring
, 0x00000000);
322 OUT_RING(ring
, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
323 OUT_RING(ring
, 0x00000000);
327 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
328 enum pipe_format format
= fd_gmem_restore_format(psurf
[i
]->format
);
329 /* The restore blit_zs shader expects stencil in sampler 0, and depth
332 if (rsc
->stencil
&& i
== 0) {
334 format
= fd_gmem_restore_format(rsc
->base
.format
);
337 /* note: PIPE_BUFFER disallowed for surfaces */
338 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
340 debug_assert(psurf
[i
]->u
.tex
.first_layer
== psurf
[i
]->u
.tex
.last_layer
);
342 OUT_RING(ring
, A3XX_TEX_CONST_0_TILE_MODE(rsc
->layout
.tile_mode
) |
343 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format
)) |
344 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D
) |
345 fd3_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
346 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
347 OUT_RING(ring
, A3XX_TEX_CONST_1_WIDTH(psurf
[i
]->width
) |
348 A3XX_TEX_CONST_1_HEIGHT(psurf
[i
]->height
));
349 OUT_RING(ring
, A3XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc
, lvl
)) |
350 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ
* i
));
351 OUT_RING(ring
, 0x00000000);
355 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + BASETABLE_SZ
* bufs
);
356 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ
* FRAG_TEX_OFF
) |
357 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
358 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR
) |
359 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ
* bufs
));
360 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
361 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
362 for (i
= 0; i
< bufs
; i
++) {
364 struct fd_resource
*rsc
= fd_resource(psurf
[i
]->texture
);
365 /* Matches above logic for blit_zs shader */
366 if (rsc
->stencil
&& i
== 0)
368 unsigned lvl
= psurf
[i
]->u
.tex
.level
;
369 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
[i
]->u
.tex
.first_layer
);
370 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
372 OUT_RING(ring
, 0x00000000);
375 /* pad the remaining entries w/ null: */
376 for (j
= 1; j
< BASETABLE_SZ
; j
++) {
377 OUT_RING(ring
, 0x00000000);
383 fd3_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
385 int32_t i
, j
, last
= -1;
386 uint32_t total_in
= 0;
387 const struct fd_vertex_state
*vtx
= emit
->vtx
;
388 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
389 unsigned vertex_regid
= regid(63, 0);
390 unsigned instance_regid
= regid(63, 0);
391 unsigned vtxcnt_regid
= regid(63, 0);
393 /* Note that sysvals come *after* normal inputs: */
394 for (i
= 0; i
< vp
->inputs_count
; i
++) {
395 if (!vp
->inputs
[i
].compmask
)
397 if (vp
->inputs
[i
].sysval
) {
398 switch(vp
->inputs
[i
].slot
) {
399 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
400 vertex_regid
= vp
->inputs
[i
].regid
;
402 case SYSTEM_VALUE_INSTANCE_ID
:
403 instance_regid
= vp
->inputs
[i
].regid
;
405 case SYSTEM_VALUE_VERTEX_CNT
:
406 vtxcnt_regid
= vp
->inputs
[i
].regid
;
409 unreachable("invalid system value");
412 } else if (i
< vtx
->vtx
->num_elements
) {
417 for (i
= 0, j
= 0; i
<= last
; i
++) {
418 assert(!vp
->inputs
[i
].sysval
);
419 if (vp
->inputs
[i
].compmask
) {
420 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
421 const struct pipe_vertex_buffer
*vb
=
422 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
423 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
424 enum pipe_format pfmt
= elem
->src_format
;
425 enum a3xx_vtx_fmt fmt
= fd3_pipe2vtx(pfmt
);
426 bool switchnext
= (i
!= last
) ||
427 (vertex_regid
!= regid(63, 0)) ||
428 (instance_regid
!= regid(63, 0)) ||
429 (vtxcnt_regid
!= regid(63, 0));
430 bool isint
= util_format_is_pure_integer(pfmt
);
431 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
432 uint32_t fs
= util_format_get_blocksize(pfmt
);
435 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
436 * should mesa/st be protecting us from this?
438 if (off
> fd_bo_size(rsc
->bo
))
442 debug_assert(fmt
!= VFMT_NONE
);
444 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(j
), 2);
445 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
446 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
447 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
448 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j
) |
449 COND(elem
->instance_divisor
, A3XX_VFD_FETCH_INSTR_0_INSTANCED
) |
450 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem
->instance_divisor
)));
451 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
453 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(j
), 1);
454 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
455 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
456 A3XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
457 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt
)) |
458 A3XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
459 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
460 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
461 COND(isint
, A3XX_VFD_DECODE_INSTR_INT
) |
462 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
464 total_in
+= util_bitcount(vp
->inputs
[i
].compmask
);
469 /* hw doesn't like to be configured for zero vbo's, it seems: */
471 /* just recycle the shader bo, we just need to point to *something*
474 struct fd_bo
*dummy_vbo
= vp
->bo
;
475 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
476 (instance_regid
!= regid(63, 0)) ||
477 (vtxcnt_regid
!= regid(63, 0));
479 OUT_PKT0(ring
, REG_A3XX_VFD_FETCH(0), 2);
480 OUT_RING(ring
, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
481 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
482 COND(switchnext
, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT
) |
483 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
484 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
485 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
487 OUT_PKT0(ring
, REG_A3XX_VFD_DECODE_INSTR(0), 1);
488 OUT_RING(ring
, A3XX_VFD_DECODE_INSTR_CONSTFILL
|
489 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
490 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM
) |
491 A3XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
492 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
493 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
494 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
495 COND(switchnext
, A3XX_VFD_DECODE_INSTR_SWITCHNEXT
));
501 OUT_PKT0(ring
, REG_A3XX_VFD_CONTROL_0
, 2);
502 OUT_RING(ring
, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
503 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
504 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
505 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
506 OUT_RING(ring
, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
507 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
508 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
510 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
511 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
512 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid
));
516 fd3_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
517 struct fd3_emit
*emit
)
519 const struct ir3_shader_variant
*vp
= fd3_emit_get_vp(emit
);
520 const struct ir3_shader_variant
*fp
= fd3_emit_get_fp(emit
);
521 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
523 emit_marker(ring
, 5);
525 if (dirty
& FD_DIRTY_SAMPLE_MASK
) {
526 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 1);
527 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
528 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
529 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx
->sample_mask
));
532 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
| FD_DIRTY_BLEND_DUAL
)) &&
533 !emit
->binning_pass
) {
534 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_render_control
|
535 fd3_blend_stateobj(ctx
->blend
)->rb_render_control
;
537 val
|= COND(fp
->frag_face
, A3XX_RB_RENDER_CONTROL_FACENESS
);
538 val
|= COND(fp
->fragcoord_compmask
!= 0,
539 A3XX_RB_RENDER_CONTROL_COORD_MASK(fp
->fragcoord_compmask
));
540 val
|= COND(ctx
->rasterizer
->rasterizer_discard
,
541 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
);
543 /* I suppose if we needed to (which I don't *think* we need
544 * to), we could emit this for binning pass too. But we
545 * would need to keep a different patch-list for binning
549 OUT_PKT0(ring
, REG_A3XX_RB_RENDER_CONTROL
, 1);
550 OUT_RINGP(ring
, val
, &ctx
->batch
->rbrc_patches
);
553 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
554 struct fd3_zsa_stateobj
*zsa
= fd3_zsa_stateobj(ctx
->zsa
);
555 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
557 OUT_PKT0(ring
, REG_A3XX_RB_ALPHA_REF
, 1);
558 OUT_RING(ring
, zsa
->rb_alpha_ref
);
560 OUT_PKT0(ring
, REG_A3XX_RB_STENCIL_CONTROL
, 1);
561 OUT_RING(ring
, zsa
->rb_stencil_control
);
563 OUT_PKT0(ring
, REG_A3XX_RB_STENCILREFMASK
, 2);
564 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
565 A3XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
566 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
567 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
570 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
571 uint32_t val
= fd3_zsa_stateobj(ctx
->zsa
)->rb_depth_control
;
572 if (fp
->writes_pos
) {
573 val
|= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z
;
574 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
576 if (fp
->no_earlyz
|| fp
->has_kill
) {
577 val
|= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
;
579 if (!ctx
->rasterizer
->depth_clip_near
) {
580 val
|= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
;
582 OUT_PKT0(ring
, REG_A3XX_RB_DEPTH_CONTROL
, 1);
586 if (dirty
& FD_DIRTY_RASTERIZER
) {
587 struct fd3_rasterizer_stateobj
*rasterizer
=
588 fd3_rasterizer_stateobj(ctx
->rasterizer
);
590 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_MODE_CONTROL
, 1);
591 OUT_RING(ring
, rasterizer
->gras_su_mode_control
);
593 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
594 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
595 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
597 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
598 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
599 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
602 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
603 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
605 uint8_t planes
= ctx
->rasterizer
->clip_plane_enable
;
606 val
|= CONDREG(ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
),
607 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER
);
608 val
|= CONDREG(ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
),
609 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER
);
610 val
|= CONDREG(ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
),
611 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID
);
612 val
|= CONDREG(ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID
),
613 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID
);
614 /* docs say enable at least one of IJ_PERSP_CENTER/CENTROID when fragcoord is used */
615 val
|= CONDREG(ir3_find_sysval_regid(fp
, SYSTEM_VALUE_FRAG_COORD
),
616 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER
);
617 val
|= COND(fp
->writes_pos
, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE
);
618 val
|= COND(fp
->fragcoord_compmask
!= 0, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD
|
619 A3XX_GRAS_CL_CLIP_CNTL_WCOORD
);
620 if (!emit
->key
.ucp_enables
)
621 val
|= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
622 MIN2(util_bitcount(planes
), 6));
623 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
627 if (dirty
& (FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
| FD_DIRTY_UCP
)) {
628 uint32_t planes
= ctx
->rasterizer
->clip_plane_enable
;
631 if (emit
->key
.ucp_enables
)
634 while (planes
&& count
< 6) {
635 int i
= ffs(planes
) - 1;
637 planes
&= ~(1U << i
);
638 fd_wfi(ctx
->batch
, ring
);
639 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(count
++), 4);
640 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][0]));
641 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][1]));
642 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][2]));
643 OUT_RING(ring
, fui(ctx
->ucp
.ucp
[i
][3]));
647 /* NOTE: since primitive_restart is not actually part of any
648 * state object, we need to make sure that we always emit
649 * PRIM_VTX_CNTL.. either that or be more clever and detect
653 const struct pipe_draw_info
*info
= emit
->info
;
654 uint32_t val
= fd3_rasterizer_stateobj(ctx
->rasterizer
)
657 if (!emit
->binning_pass
) {
658 uint32_t stride_in_vpc
= align(fp
->total_in
, 4) / 4;
659 if (stride_in_vpc
> 0)
660 stride_in_vpc
= MAX2(stride_in_vpc
, 2);
661 val
|= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc
);
664 if (info
->index_size
&& info
->primitive_restart
) {
665 val
|= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
668 val
|= COND(vp
->writes_psize
, A3XX_PC_PRIM_VTX_CNTL_PSIZE
);
670 OUT_PKT0(ring
, REG_A3XX_PC_PRIM_VTX_CNTL
, 1);
674 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
| FD_DIRTY_VIEWPORT
)) {
675 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
676 int minx
= scissor
->minx
;
677 int miny
= scissor
->miny
;
678 int maxx
= scissor
->maxx
;
679 int maxy
= scissor
->maxy
;
681 /* Unfortunately there is no separate depth clip disable, only an all
682 * or nothing deal. So when we disable clipping, we must handle the
683 * viewport clip via scissors.
685 if (!ctx
->rasterizer
->depth_clip_near
) {
686 struct pipe_viewport_state
*vp
= &ctx
->viewport
;
687 minx
= MAX2(minx
, (int)floorf(vp
->translate
[0] - fabsf(vp
->scale
[0])));
688 miny
= MAX2(miny
, (int)floorf(vp
->translate
[1] - fabsf(vp
->scale
[1])));
689 maxx
= MIN2(maxx
, (int)ceilf(vp
->translate
[0] + fabsf(vp
->scale
[0])));
690 maxy
= MIN2(maxy
, (int)ceilf(vp
->translate
[1] + fabsf(vp
->scale
[1])));
693 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
694 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx
) |
695 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny
));
696 OUT_RING(ring
, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx
- 1) |
697 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy
- 1));
699 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, minx
);
700 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, miny
);
701 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, maxx
);
702 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, maxy
);
705 if (dirty
& FD_DIRTY_VIEWPORT
) {
706 fd_wfi(ctx
->batch
, ring
);
707 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_VPORT_XOFFSET
, 6);
708 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XOFFSET(ctx
->viewport
.translate
[0] - 0.5));
709 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_XSCALE(ctx
->viewport
.scale
[0]));
710 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YOFFSET(ctx
->viewport
.translate
[1] - 0.5));
711 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_YSCALE(ctx
->viewport
.scale
[1]));
712 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx
->viewport
.translate
[2]));
713 OUT_RING(ring
, A3XX_GRAS_CL_VPORT_ZSCALE(ctx
->viewport
.scale
[2]));
716 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
719 if (ctx
->batch
->framebuffer
.zsbuf
) {
720 depth
= util_format_get_component_bits(
721 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
722 UTIL_FORMAT_COLORSPACE_ZS
, 0);
724 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
727 OUT_PKT0(ring
, REG_A3XX_RB_Z_CLAMP_MIN
, 2);
729 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffffff));
730 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffffff));
731 } else if (depth
== 16) {
732 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
733 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
735 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
736 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
740 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_BLEND_DUAL
)) {
741 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
742 int nr_cbufs
= pfb
->nr_cbufs
;
743 if (fd3_blend_stateobj(ctx
->blend
)->rb_render_control
&
744 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE
)
746 fd3_program_emit(ring
, emit
, nr_cbufs
, pfb
->cbufs
);
749 /* TODO we should not need this or fd_wfi() before emit_constants():
751 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
752 OUT_RING(ring
, HLSQ_FLUSH
);
754 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
755 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
756 if (!emit
->binning_pass
)
757 ir3_emit_fs_consts(fp
, ring
, ctx
);
760 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_FRAMEBUFFER
)) {
761 struct fd3_blend_stateobj
*blend
= fd3_blend_stateobj(ctx
->blend
);
764 for (i
= 0; i
< ARRAY_SIZE(blend
->rb_mrt
); i
++) {
765 enum pipe_format format
=
766 pipe_surface_format(ctx
->batch
->framebuffer
.cbufs
[i
]);
767 const struct util_format_description
*desc
=
768 util_format_description(format
);
769 bool is_float
= util_format_is_float(format
);
770 bool is_int
= util_format_is_pure_integer(format
);
771 bool has_alpha
= util_format_has_alpha(format
);
772 uint32_t control
= blend
->rb_mrt
[i
].control
;
775 control
&= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
|
776 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK
);
777 control
|= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
780 if (format
== PIPE_FORMAT_NONE
)
781 control
&= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
784 control
&= ~A3XX_RB_MRT_CONTROL_BLEND2
;
787 if (format
&& util_format_get_component_bits(
788 format
, UTIL_FORMAT_COLORSPACE_RGB
, 0) < 8) {
789 const struct pipe_rt_blend_state
*rt
;
790 if (ctx
->blend
->independent_blend_enable
)
791 rt
= &ctx
->blend
->rt
[i
];
793 rt
= &ctx
->blend
->rt
[0];
795 if (!util_format_colormask_full(desc
, rt
->colormask
))
796 control
|= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE
;
799 OUT_PKT0(ring
, REG_A3XX_RB_MRT_CONTROL(i
), 1);
800 OUT_RING(ring
, control
);
802 OUT_PKT0(ring
, REG_A3XX_RB_MRT_BLEND_CONTROL(i
), 1);
803 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
|
804 COND(!is_float
, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE
));
808 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
809 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
810 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
811 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
812 A3XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
813 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
814 A3XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
815 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
816 A3XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
817 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
818 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
821 if (dirty
& FD_DIRTY_TEX
)
822 fd_wfi(ctx
->batch
, ring
);
824 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
)
825 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->tex
[PIPE_SHADER_VERTEX
]);
827 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
)
828 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
831 /* emit setup at begin of new cmdstream buffer (don't rely on previous
832 * state, there could have been a context switch between ioctls):
835 fd3_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
837 struct fd_context
*ctx
= batch
->ctx
;
838 struct fd3_context
*fd3_ctx
= fd3_context(ctx
);
841 if (ctx
->screen
->gpu_id
== 320) {
842 OUT_PKT3(ring
, CP_REG_RMW
, 3);
843 OUT_RING(ring
, REG_A3XX_RBBM_CLOCK_CTL
);
844 OUT_RING(ring
, 0xfffcffff);
845 OUT_RING(ring
, 0x00000000);
849 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
850 OUT_RING(ring
, 0x00007fff);
852 OUT_PKT0(ring
, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
, 3);
853 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
854 OUT_RELOC(ring
, fd3_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
855 OUT_RING(ring
, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
857 OUT_PKT0(ring
, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
, 3);
858 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
859 OUT_RELOC(ring
, fd3_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
860 OUT_RING(ring
, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
862 OUT_PKT0(ring
, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
, 1);
863 OUT_RING(ring
, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
865 OUT_PKT0(ring
, REG_A3XX_GRAS_SC_CONTROL
, 1);
866 OUT_RING(ring
, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
867 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
868 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
870 OUT_PKT0(ring
, REG_A3XX_RB_MSAA_CONTROL
, 2);
871 OUT_RING(ring
, A3XX_RB_MSAA_CONTROL_DISABLE
|
872 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
) |
873 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
874 OUT_RING(ring
, 0x00000000); /* RB_ALPHA_REF */
876 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_GB_CLIP_ADJ
, 1);
877 OUT_RING(ring
, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
878 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
880 OUT_PKT0(ring
, REG_A3XX_GRAS_TSE_DEBUG_ECO
, 1);
881 OUT_RING(ring
, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
883 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_VS_TEX_OFFSET
, 1);
884 OUT_RING(ring
, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF
) |
885 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF
) |
886 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* VERT_TEX_OFF
));
888 OUT_PKT0(ring
, REG_A3XX_TPL1_TP_FS_TEX_OFFSET
, 1);
889 OUT_RING(ring
, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF
) |
890 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF
) |
891 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ
* FRAG_TEX_OFF
));
893 OUT_PKT0(ring
, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
, 2);
894 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
895 OUT_RING(ring
, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
897 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0E43
, 1);
898 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0E43 */
900 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0F03
, 1);
901 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0F03 */
903 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0EE0
, 1);
904 OUT_RING(ring
, 0x00000003); /* UNKNOWN_0EE0 */
906 OUT_PKT0(ring
, REG_A3XX_UNKNOWN_0C3D
, 1);
907 OUT_RING(ring
, 0x00000001); /* UNKNOWN_0C3D */
909 OUT_PKT0(ring
, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
, 1);
910 OUT_RING(ring
, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
912 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
, 2);
913 OUT_RING(ring
, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
914 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
915 OUT_RING(ring
, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
916 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
918 fd3_emit_cache_flush(batch
, ring
);
920 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_CLIP_CNTL
, 1);
921 OUT_RING(ring
, 0x00000000); /* GRAS_CL_CLIP_CNTL */
923 OUT_PKT0(ring
, REG_A3XX_GRAS_SU_POINT_MINMAX
, 2);
924 OUT_RING(ring
, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
925 OUT_RING(ring
, 0x00000008); /* GRAS_SU_POINT_SIZE */
927 OUT_PKT0(ring
, REG_A3XX_PC_RESTART_INDEX
, 1);
928 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
930 OUT_PKT0(ring
, REG_A3XX_RB_WINDOW_OFFSET
, 1);
931 OUT_RING(ring
, A3XX_RB_WINDOW_OFFSET_X(0) |
932 A3XX_RB_WINDOW_OFFSET_Y(0));
934 OUT_PKT0(ring
, REG_A3XX_RB_BLEND_RED
, 4);
935 OUT_RING(ring
, A3XX_RB_BLEND_RED_UINT(0) |
936 A3XX_RB_BLEND_RED_FLOAT(0.0));
937 OUT_RING(ring
, A3XX_RB_BLEND_GREEN_UINT(0) |
938 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
939 OUT_RING(ring
, A3XX_RB_BLEND_BLUE_UINT(0) |
940 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
941 OUT_RING(ring
, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
942 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
944 for (i
= 0; i
< 6; i
++) {
945 OUT_PKT0(ring
, REG_A3XX_GRAS_CL_USER_PLANE(i
), 4);
946 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
947 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
948 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
949 OUT_RING(ring
, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
952 OUT_PKT0(ring
, REG_A3XX_PC_VSTREAM_CONTROL
, 1);
953 OUT_RING(ring
, 0x00000000);
955 fd_event_write(batch
, ring
, CACHE_FLUSH
);
957 if (is_a3xx_p0(ctx
->screen
)) {
958 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
959 OUT_RING(ring
, 0x00000000);
960 OUT_RING(ring
, DRAW(1, DI_SRC_SEL_AUTO_INDEX
,
961 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
, 0));
962 OUT_RING(ring
, 0); /* NumIndices */
965 OUT_PKT3(ring
, CP_NOP
, 4);
966 OUT_RING(ring
, 0x00000000);
967 OUT_RING(ring
, 0x00000000);
968 OUT_RING(ring
, 0x00000000);
969 OUT_RING(ring
, 0x00000000);
973 fd_hw_query_enable(batch
, ring
);
977 fd3_emit_init_screen(struct pipe_screen
*pscreen
)
979 struct fd_screen
*screen
= fd_screen(pscreen
);
980 screen
->emit_ib
= fd3_emit_ib
;
984 fd3_emit_init(struct pipe_context
*pctx
)