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freedreno: Add more asserts for DST_OFF/NUM_UNIT in indirect const uploads.
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 #define emit_const_user fd3_emit_const_user
47 #define emit_const_bo fd3_emit_const_bo
48 #include "ir3_const.h"
49
50 static const enum adreno_state_block sb[] = {
51 [MESA_SHADER_VERTEX] = SB_VERT_SHADER,
52 [MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
53 };
54
55 /* regid: base const register
56 * prsc or dwords: buffer containing constant values
57 * sizedwords: size of const value buffer
58 */
59 static void
60 fd3_emit_const_user(struct fd_ringbuffer *ring,
61 const struct ir3_shader_variant *v,
62 uint32_t regid, uint32_t sizedwords, const uint32_t *dwords)
63 {
64 emit_const_asserts(ring, v, regid, sizedwords);
65
66 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sizedwords);
67 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
68 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
69 CP_LOAD_STATE_0_STATE_BLOCK(sb[v->type]) |
70 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
71 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
72 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
73 for (int i = 0; i < sizedwords; i++)
74 OUT_RING(ring, dwords[i]);
75 }
76
77 static void
78 fd3_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
79 uint32_t regid, uint32_t offset, uint32_t sizedwords,
80 struct fd_bo *bo)
81 {
82 uint32_t dst_off = regid / 2;
83 /* The blob driver aligns all const uploads dst_off to 64. We've been
84 * successfully aligning to 8 vec4s as const_upload_unit so far with no
85 * ill effects.
86 */
87 assert(dst_off % 16 == 0);
88 uint32_t num_unit = sizedwords / 2;
89 assert(num_unit % 2 == 0);
90
91 emit_const_asserts(ring, v, regid, sizedwords);
92
93 OUT_PKT3(ring, CP_LOAD_STATE, 2);
94 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(dst_off) |
95 CP_LOAD_STATE_0_STATE_SRC(SS_INDIRECT) |
96 CP_LOAD_STATE_0_STATE_BLOCK(sb[v->type]) |
97 CP_LOAD_STATE_0_NUM_UNIT(num_unit));
98 OUT_RELOC(ring, bo, offset,
99 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
100 }
101
102 static void
103 fd3_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
104 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
105 {
106 uint32_t anum = align(num, 4);
107 uint32_t i;
108
109 debug_assert((regid % 4) == 0);
110
111 OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
113 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
114 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
115 CP_LOAD_STATE_0_NUM_UNIT(anum/2));
116 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
117 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
118
119 for (i = 0; i < num; i++) {
120 if (prscs[i]) {
121 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
122 } else {
123 OUT_RING(ring, 0xbad00000 | (i << 16));
124 }
125 }
126
127 for (; i < anum; i++)
128 OUT_RING(ring, 0xffffffff);
129 }
130
131 static bool
132 is_stateobj(struct fd_ringbuffer *ring)
133 {
134 return false;
135 }
136
137 static void
138 emit_const_ptrs(struct fd_ringbuffer *ring,
139 const struct ir3_shader_variant *v, uint32_t dst_offset,
140 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
141 {
142 /* TODO inline this */
143 assert(dst_offset + num <= v->constlen * 4);
144 fd3_emit_const_ptrs(ring, v->type, dst_offset, num, prscs, offsets);
145 }
146
147 #define VERT_TEX_OFF 0
148 #define FRAG_TEX_OFF 16
149 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
150
151 static void
152 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
153 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
154 {
155 static const unsigned tex_off[] = {
156 [SB_VERT_TEX] = VERT_TEX_OFF,
157 [SB_FRAG_TEX] = FRAG_TEX_OFF,
158 };
159 static const enum adreno_state_block mipaddr[] = {
160 [SB_VERT_TEX] = SB_VERT_MIPADDR,
161 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
162 };
163 static const uint32_t bcolor_reg[] = {
164 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
165 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
166 };
167 struct fd3_context *fd3_ctx = fd3_context(ctx);
168 bool needs_border = false;
169 unsigned i, j;
170
171 if (tex->num_samplers > 0) {
172 /* output sampler state: */
173 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
174 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
175 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
176 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
177 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
178 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
179 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
180 for (i = 0; i < tex->num_samplers; i++) {
181 static const struct fd3_sampler_stateobj dummy_sampler = {};
182 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
183 fd3_sampler_stateobj(tex->samplers[i]) :
184 &dummy_sampler;
185
186 OUT_RING(ring, sampler->texsamp0);
187 OUT_RING(ring, sampler->texsamp1);
188
189 needs_border |= sampler->needs_border;
190 }
191 }
192
193 if (tex->num_textures > 0) {
194 /* emit texture state: */
195 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
196 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
197 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
198 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
199 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
200 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
201 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
202 for (i = 0; i < tex->num_textures; i++) {
203 static const struct fd3_pipe_sampler_view dummy_view = {};
204 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
205 fd3_pipe_sampler_view(tex->textures[i]) :
206 &dummy_view;
207 OUT_RING(ring, view->texconst0);
208 OUT_RING(ring, view->texconst1);
209 OUT_RING(ring, view->texconst2 |
210 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
211 OUT_RING(ring, view->texconst3);
212 }
213
214 /* emit mipaddrs: */
215 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
216 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
217 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
218 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
219 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
220 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
221 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
222 for (i = 0; i < tex->num_textures; i++) {
223 static const struct fd3_pipe_sampler_view dummy_view = {
224 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
225 .base.u.tex.first_level = 1,
226 };
227 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
228 fd3_pipe_sampler_view(tex->textures[i]) :
229 &dummy_view;
230 struct fd_resource *rsc = fd_resource(view->base.texture);
231 if (rsc && rsc->base.target == PIPE_BUFFER) {
232 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
233 j = 1;
234 } else {
235 unsigned start = fd_sampler_first_level(&view->base);
236 unsigned end = fd_sampler_last_level(&view->base);
237
238 for (j = 0; j < (end - start + 1); j++) {
239 struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
240 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
241 }
242 }
243
244 /* pad the remaining entries w/ null: */
245 for (; j < BASETABLE_SZ; j++) {
246 OUT_RING(ring, 0x00000000);
247 }
248 }
249 }
250
251 if (needs_border) {
252 unsigned off;
253 void *ptr;
254
255 u_upload_alloc(fd3_ctx->border_color_uploader,
256 0, BORDER_COLOR_UPLOAD_SIZE,
257 BORDER_COLOR_UPLOAD_SIZE, &off,
258 &fd3_ctx->border_color_buf,
259 &ptr);
260
261 fd_setup_border_colors(tex, ptr, tex_off[sb]);
262
263 OUT_PKT0(ring, bcolor_reg[sb], 1);
264 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
265
266 u_upload_unmap(fd3_ctx->border_color_uploader);
267 }
268 }
269
270 /* emit texture state for mem->gmem restore operation.. eventually it would
271 * be good to get rid of this and use normal CSO/etc state for more of these
272 * special cases, but for now the compiler is not sufficient..
273 *
274 * Also, for using normal state, not quite sure how to handle the special
275 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
276 */
277 void
278 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
279 struct pipe_surface **psurf,
280 int bufs)
281 {
282 int i, j;
283
284 /* output sampler state: */
285 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
286 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
287 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
288 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
289 CP_LOAD_STATE_0_NUM_UNIT(bufs));
290 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
291 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
292 for (i = 0; i < bufs; i++) {
293 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
294 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
295 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
296 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
297 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
298 OUT_RING(ring, 0x00000000);
299 }
300
301 /* emit texture state: */
302 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
303 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
304 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
305 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
306 CP_LOAD_STATE_0_NUM_UNIT(bufs));
307 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
308 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
309 for (i = 0; i < bufs; i++) {
310 if (!psurf[i]) {
311 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
312 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
313 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
314 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
315 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
316 OUT_RING(ring, 0x00000000);
317 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
318 OUT_RING(ring, 0x00000000);
319 continue;
320 }
321
322 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
323 enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
324 /* The restore blit_zs shader expects stencil in sampler 0, and depth
325 * in sampler 1
326 */
327 if (rsc->stencil && i == 0) {
328 rsc = rsc->stencil;
329 format = fd_gmem_restore_format(rsc->base.format);
330 }
331
332 /* note: PIPE_BUFFER disallowed for surfaces */
333 unsigned lvl = psurf[i]->u.tex.level;
334
335 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
336
337 OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
338 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
339 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
340 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
341 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
342 OUT_RING(ring, A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
343 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
344 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)) |
345 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
346 OUT_RING(ring, 0x00000000);
347 }
348
349 /* emit mipaddrs: */
350 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
351 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
352 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
353 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
354 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
355 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
356 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
357 for (i = 0; i < bufs; i++) {
358 if (psurf[i]) {
359 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
360 /* Matches above logic for blit_zs shader */
361 if (rsc->stencil && i == 0)
362 rsc = rsc->stencil;
363 unsigned lvl = psurf[i]->u.tex.level;
364 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
365 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
366 } else {
367 OUT_RING(ring, 0x00000000);
368 }
369
370 /* pad the remaining entries w/ null: */
371 for (j = 1; j < BASETABLE_SZ; j++) {
372 OUT_RING(ring, 0x00000000);
373 }
374 }
375 }
376
377 void
378 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
379 {
380 int32_t i, j, last = -1;
381 uint32_t total_in = 0;
382 const struct fd_vertex_state *vtx = emit->vtx;
383 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
384 unsigned vertex_regid = regid(63, 0);
385 unsigned instance_regid = regid(63, 0);
386 unsigned vtxcnt_regid = regid(63, 0);
387
388 /* Note that sysvals come *after* normal inputs: */
389 for (i = 0; i < vp->inputs_count; i++) {
390 if (!vp->inputs[i].compmask)
391 continue;
392 if (vp->inputs[i].sysval) {
393 switch(vp->inputs[i].slot) {
394 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
395 vertex_regid = vp->inputs[i].regid;
396 break;
397 case SYSTEM_VALUE_INSTANCE_ID:
398 instance_regid = vp->inputs[i].regid;
399 break;
400 case SYSTEM_VALUE_VERTEX_CNT:
401 vtxcnt_regid = vp->inputs[i].regid;
402 break;
403 default:
404 unreachable("invalid system value");
405 break;
406 }
407 } else if (i < vtx->vtx->num_elements) {
408 last = i;
409 }
410 }
411
412 for (i = 0, j = 0; i <= last; i++) {
413 assert(!vp->inputs[i].sysval);
414 if (vp->inputs[i].compmask) {
415 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
416 const struct pipe_vertex_buffer *vb =
417 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
418 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
419 enum pipe_format pfmt = elem->src_format;
420 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
421 bool switchnext = (i != last) ||
422 (vertex_regid != regid(63, 0)) ||
423 (instance_regid != regid(63, 0)) ||
424 (vtxcnt_regid != regid(63, 0));
425 bool isint = util_format_is_pure_integer(pfmt);
426 uint32_t off = vb->buffer_offset + elem->src_offset;
427 uint32_t fs = util_format_get_blocksize(pfmt);
428
429 #ifdef DEBUG
430 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
431 * should mesa/st be protecting us from this?
432 */
433 if (off > fd_bo_size(rsc->bo))
434 continue;
435 #endif
436
437 debug_assert(fmt != VFMT_NONE);
438
439 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
440 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
441 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
442 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
443 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
444 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
445 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
446 OUT_RELOC(ring, rsc->bo, off, 0, 0);
447
448 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
449 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
450 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
451 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
452 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
453 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
454 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
455 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
456 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
457 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
458
459 total_in += util_bitcount(vp->inputs[i].compmask);
460 j++;
461 }
462 }
463
464 /* hw doesn't like to be configured for zero vbo's, it seems: */
465 if (last < 0) {
466 /* just recycle the shader bo, we just need to point to *something*
467 * valid:
468 */
469 struct fd_bo *dummy_vbo = vp->bo;
470 bool switchnext = (vertex_regid != regid(63, 0)) ||
471 (instance_regid != regid(63, 0)) ||
472 (vtxcnt_regid != regid(63, 0));
473
474 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
475 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
476 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
477 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
478 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
479 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
480 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
481
482 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
483 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
484 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
485 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
486 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
487 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
488 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
489 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
490 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
491
492 total_in = 1;
493 j = 1;
494 }
495
496 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
497 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
498 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
499 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
500 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
501 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
502 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
503 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
504
505 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
506 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
507 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
508 }
509
510 void
511 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
512 struct fd3_emit *emit)
513 {
514 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
515 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
516 const enum fd_dirty_3d_state dirty = emit->dirty;
517
518 emit_marker(ring, 5);
519
520 if (dirty & FD_DIRTY_SAMPLE_MASK) {
521 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
522 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
523 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
524 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
525 }
526
527 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
528 !emit->binning_pass) {
529 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
530 fd3_blend_stateobj(ctx->blend)->rb_render_control;
531
532 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
533 val |= COND(fp->fragcoord_compmask != 0,
534 A3XX_RB_RENDER_CONTROL_COORD_MASK(fp->fragcoord_compmask));
535 val |= COND(ctx->rasterizer->rasterizer_discard,
536 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
537
538 /* I suppose if we needed to (which I don't *think* we need
539 * to), we could emit this for binning pass too. But we
540 * would need to keep a different patch-list for binning
541 * vs render pass.
542 */
543
544 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
545 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
546 }
547
548 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
549 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
550 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
551
552 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
553 OUT_RING(ring, zsa->rb_alpha_ref);
554
555 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
556 OUT_RING(ring, zsa->rb_stencil_control);
557
558 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
559 OUT_RING(ring, zsa->rb_stencilrefmask |
560 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
561 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
562 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
563 }
564
565 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
566 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
567 if (fp->writes_pos) {
568 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
569 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
570 }
571 if (fp->no_earlyz || fp->has_kill) {
572 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
573 }
574 if (!ctx->rasterizer->depth_clip_near) {
575 val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
576 }
577 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
578 OUT_RING(ring, val);
579 }
580
581 if (dirty & FD_DIRTY_RASTERIZER) {
582 struct fd3_rasterizer_stateobj *rasterizer =
583 fd3_rasterizer_stateobj(ctx->rasterizer);
584
585 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
586 OUT_RING(ring, rasterizer->gras_su_mode_control);
587
588 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
589 OUT_RING(ring, rasterizer->gras_su_point_minmax);
590 OUT_RING(ring, rasterizer->gras_su_point_size);
591
592 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
593 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
594 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
595 }
596
597 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
598 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
599 ->gras_cl_clip_cntl;
600 uint8_t planes = ctx->rasterizer->clip_plane_enable;
601 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL),
602 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
603 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL),
604 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER);
605 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID),
606 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID);
607 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID),
608 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID);
609 /* docs say enable at least one of IJ_PERSP_CENTER/CENTROID when fragcoord is used */
610 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD),
611 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
612 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
613 val |= COND(fp->fragcoord_compmask != 0, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
614 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
615 if (!emit->key.ucp_enables)
616 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
617 MIN2(util_bitcount(planes), 6));
618 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
619 OUT_RING(ring, val);
620 }
621
622 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
623 uint32_t planes = ctx->rasterizer->clip_plane_enable;
624 int count = 0;
625
626 if (emit->key.ucp_enables)
627 planes = 0;
628
629 while (planes && count < 6) {
630 int i = ffs(planes) - 1;
631
632 planes &= ~(1U << i);
633 fd_wfi(ctx->batch, ring);
634 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
635 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
636 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
637 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
638 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
639 }
640 }
641
642 /* NOTE: since primitive_restart is not actually part of any
643 * state object, we need to make sure that we always emit
644 * PRIM_VTX_CNTL.. either that or be more clever and detect
645 * when it changes.
646 */
647 if (emit->info) {
648 const struct pipe_draw_info *info = emit->info;
649 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
650 ->pc_prim_vtx_cntl;
651
652 if (!emit->binning_pass) {
653 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
654 if (stride_in_vpc > 0)
655 stride_in_vpc = MAX2(stride_in_vpc, 2);
656 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
657 }
658
659 if (info->index_size && info->primitive_restart) {
660 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
661 }
662
663 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
664
665 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
666 OUT_RING(ring, val);
667 }
668
669 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
670 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
671 int minx = scissor->minx;
672 int miny = scissor->miny;
673 int maxx = scissor->maxx;
674 int maxy = scissor->maxy;
675
676 /* Unfortunately there is no separate depth clip disable, only an all
677 * or nothing deal. So when we disable clipping, we must handle the
678 * viewport clip via scissors.
679 */
680 if (!ctx->rasterizer->depth_clip_near) {
681 struct pipe_viewport_state *vp = &ctx->viewport;
682 minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
683 miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
684 maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
685 maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
686 }
687
688 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
689 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
690 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
691 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
692 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
693
694 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
695 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
696 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
697 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
698 }
699
700 if (dirty & FD_DIRTY_VIEWPORT) {
701 fd_wfi(ctx->batch, ring);
702 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
703 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
704 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
705 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
706 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
707 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
708 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
709 }
710
711 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
712 float zmin, zmax;
713 int depth = 24;
714 if (ctx->batch->framebuffer.zsbuf) {
715 depth = util_format_get_component_bits(
716 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
717 UTIL_FORMAT_COLORSPACE_ZS, 0);
718 }
719 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
720 &zmin, &zmax);
721
722 OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
723 if (depth == 32) {
724 OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
725 OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
726 } else if (depth == 16) {
727 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
728 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
729 } else {
730 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
731 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
732 }
733 }
734
735 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
736 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
737 int nr_cbufs = pfb->nr_cbufs;
738 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
739 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
740 nr_cbufs++;
741 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
742 }
743
744 /* TODO we should not need this or fd_wfi() before emit_constants():
745 */
746 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
747 OUT_RING(ring, HLSQ_FLUSH);
748
749 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
750 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
751 if (!emit->binning_pass)
752 ir3_emit_fs_consts(fp, ring, ctx);
753 }
754
755 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
756 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
757 uint32_t i;
758
759 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
760 enum pipe_format format =
761 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
762 const struct util_format_description *desc =
763 util_format_description(format);
764 bool is_float = util_format_is_float(format);
765 bool is_int = util_format_is_pure_integer(format);
766 bool has_alpha = util_format_has_alpha(format);
767 uint32_t control = blend->rb_mrt[i].control;
768
769 if (is_int) {
770 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
771 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
772 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
773 }
774
775 if (format == PIPE_FORMAT_NONE)
776 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
777
778 if (!has_alpha) {
779 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
780 }
781
782 if (format && util_format_get_component_bits(
783 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
784 const struct pipe_rt_blend_state *rt;
785 if (ctx->blend->independent_blend_enable)
786 rt = &ctx->blend->rt[i];
787 else
788 rt = &ctx->blend->rt[0];
789
790 if (!util_format_colormask_full(desc, rt->colormask))
791 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
792 }
793
794 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
795 OUT_RING(ring, control);
796
797 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
798 OUT_RING(ring, blend->rb_mrt[i].blend_control |
799 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
800 }
801 }
802
803 if (dirty & FD_DIRTY_BLEND_COLOR) {
804 struct pipe_blend_color *bcolor = &ctx->blend_color;
805 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
806 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
807 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
808 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
809 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
810 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
811 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
812 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
813 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
814 }
815
816 if (dirty & FD_DIRTY_TEX)
817 fd_wfi(ctx->batch, ring);
818
819 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
820 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
821
822 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
823 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
824 }
825
826 /* emit setup at begin of new cmdstream buffer (don't rely on previous
827 * state, there could have been a context switch between ioctls):
828 */
829 void
830 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
831 {
832 struct fd_context *ctx = batch->ctx;
833 struct fd3_context *fd3_ctx = fd3_context(ctx);
834 int i;
835
836 if (ctx->screen->gpu_id == 320) {
837 OUT_PKT3(ring, CP_REG_RMW, 3);
838 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
839 OUT_RING(ring, 0xfffcffff);
840 OUT_RING(ring, 0x00000000);
841 }
842
843 fd_wfi(batch, ring);
844 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
845 OUT_RING(ring, 0x00007fff);
846
847 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
848 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
849 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
850 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
851
852 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
853 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
854 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
855 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
856
857 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
858 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
859
860 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
861 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
862 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
863 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
864
865 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
866 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
867 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
868 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
869 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
870
871 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
872 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
873 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
874
875 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
876 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
877
878 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
879 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
880 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
881 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
882
883 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
884 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
885 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
886 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
887
888 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
889 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
890 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
891
892 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
893 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
894
895 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
896 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
897
898 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
899 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
900
901 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
902 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
903
904 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
905 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
906
907 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
908 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
909 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
910 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
911 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
912
913 fd3_emit_cache_flush(batch, ring);
914
915 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
916 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
917
918 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
919 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
920 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
921
922 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
923 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
924
925 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
926 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
927 A3XX_RB_WINDOW_OFFSET_Y(0));
928
929 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
930 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
931 A3XX_RB_BLEND_RED_FLOAT(0.0));
932 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
933 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
934 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
935 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
936 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
937 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
938
939 for (i = 0; i < 6; i++) {
940 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
941 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
942 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
943 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
944 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
945 }
946
947 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
948 OUT_RING(ring, 0x00000000);
949
950 fd_event_write(batch, ring, CACHE_FLUSH);
951
952 if (is_a3xx_p0(ctx->screen)) {
953 OUT_PKT3(ring, CP_DRAW_INDX, 3);
954 OUT_RING(ring, 0x00000000);
955 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
956 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
957 OUT_RING(ring, 0); /* NumIndices */
958 }
959
960 OUT_PKT3(ring, CP_NOP, 4);
961 OUT_RING(ring, 0x00000000);
962 OUT_RING(ring, 0x00000000);
963 OUT_RING(ring, 0x00000000);
964 OUT_RING(ring, 0x00000000);
965
966 fd_wfi(batch, ring);
967
968 fd_hw_query_enable(batch, ring);
969 }
970
971 void
972 fd3_emit_init_screen(struct pipe_screen *pscreen)
973 {
974 struct fd_screen *screen = fd_screen(pscreen);
975 screen->emit_ib = fd3_emit_ib;
976 }
977
978 void
979 fd3_emit_init(struct pipe_context *pctx)
980 {
981 }