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e31acc01655f6a5f129f9fa6fa308d3d27675dc1
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 #include "ir3_const.h"
47
48 static const enum adreno_state_block sb[] = {
49 [MESA_SHADER_VERTEX] = SB_VERT_SHADER,
50 [MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
51 };
52
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
56 */
57 static void
58 fd3_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
59 uint32_t regid, uint32_t offset, uint32_t sizedwords,
60 const uint32_t *dwords, struct pipe_resource *prsc)
61 {
62 uint32_t i, sz;
63 enum adreno_state_src src;
64
65 debug_assert((regid % 4) == 0);
66 debug_assert((sizedwords % 4) == 0);
67
68 if (prsc) {
69 sz = 0;
70 src = SS_INDIRECT;
71 } else {
72 sz = sizedwords;
73 src = SS_DIRECT;
74 }
75
76 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
78 CP_LOAD_STATE_0_STATE_SRC(src) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
81 if (prsc) {
82 struct fd_bo *bo = fd_resource(prsc)->bo;
83 OUT_RELOC(ring, bo, offset,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
85 } else {
86 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
88 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
89 }
90 for (i = 0; i < sz; i++) {
91 OUT_RING(ring, dwords[i]);
92 }
93 }
94
95 static void
96 fd3_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type,
97 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
98 {
99 uint32_t anum = align(num, 4);
100 uint32_t i;
101
102 debug_assert((regid % 4) == 0);
103
104 OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
108 CP_LOAD_STATE_0_NUM_UNIT(anum/2));
109 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
111
112 for (i = 0; i < num; i++) {
113 if (prscs[i]) {
114 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
115 } else {
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++)
121 OUT_RING(ring, 0xffffffff);
122 }
123
124 static bool
125 is_stateobj(struct fd_ringbuffer *ring)
126 {
127 return false;
128 }
129
130 void
131 emit_const(struct fd_ringbuffer *ring,
132 const struct ir3_shader_variant *v, uint32_t dst_offset,
133 uint32_t offset, uint32_t size, const void *user_buffer,
134 struct pipe_resource *buffer)
135 {
136 /* TODO inline this */
137 assert(dst_offset + size <= v->constlen * 4);
138 fd3_emit_const(ring, v->type, dst_offset,
139 offset, size, user_buffer, buffer);
140 }
141
142 static void
143 emit_const_bo(struct fd_ringbuffer *ring,
144 const struct ir3_shader_variant *v, uint32_t dst_offset,
145 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
146 {
147 /* TODO inline this */
148 assert(dst_offset + num <= v->constlen * 4);
149 fd3_emit_const_bo(ring, v->type, dst_offset, num, prscs, offsets);
150 }
151
152 #define VERT_TEX_OFF 0
153 #define FRAG_TEX_OFF 16
154 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
155
156 static void
157 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
158 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
159 {
160 static const unsigned tex_off[] = {
161 [SB_VERT_TEX] = VERT_TEX_OFF,
162 [SB_FRAG_TEX] = FRAG_TEX_OFF,
163 };
164 static const enum adreno_state_block mipaddr[] = {
165 [SB_VERT_TEX] = SB_VERT_MIPADDR,
166 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
167 };
168 static const uint32_t bcolor_reg[] = {
169 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
170 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
171 };
172 struct fd3_context *fd3_ctx = fd3_context(ctx);
173 bool needs_border = false;
174 unsigned i, j;
175
176 if (tex->num_samplers > 0) {
177 /* output sampler state: */
178 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
179 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
180 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
181 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
182 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
183 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
184 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
185 for (i = 0; i < tex->num_samplers; i++) {
186 static const struct fd3_sampler_stateobj dummy_sampler = {};
187 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
188 fd3_sampler_stateobj(tex->samplers[i]) :
189 &dummy_sampler;
190
191 OUT_RING(ring, sampler->texsamp0);
192 OUT_RING(ring, sampler->texsamp1);
193
194 needs_border |= sampler->needs_border;
195 }
196 }
197
198 if (tex->num_textures > 0) {
199 /* emit texture state: */
200 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
201 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
202 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
203 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
204 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
205 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
206 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
207 for (i = 0; i < tex->num_textures; i++) {
208 static const struct fd3_pipe_sampler_view dummy_view = {};
209 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
210 fd3_pipe_sampler_view(tex->textures[i]) :
211 &dummy_view;
212 OUT_RING(ring, view->texconst0);
213 OUT_RING(ring, view->texconst1);
214 OUT_RING(ring, view->texconst2 |
215 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
216 OUT_RING(ring, view->texconst3);
217 }
218
219 /* emit mipaddrs: */
220 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
221 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
222 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
223 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
224 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
225 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
226 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
227 for (i = 0; i < tex->num_textures; i++) {
228 static const struct fd3_pipe_sampler_view dummy_view = {
229 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
230 .base.u.tex.first_level = 1,
231 };
232 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
233 fd3_pipe_sampler_view(tex->textures[i]) :
234 &dummy_view;
235 struct fd_resource *rsc = fd_resource(view->base.texture);
236 if (rsc && rsc->base.target == PIPE_BUFFER) {
237 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
238 j = 1;
239 } else {
240 unsigned start = fd_sampler_first_level(&view->base);
241 unsigned end = fd_sampler_last_level(&view->base);
242
243 for (j = 0; j < (end - start + 1); j++) {
244 struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
245 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
246 }
247 }
248
249 /* pad the remaining entries w/ null: */
250 for (; j < BASETABLE_SZ; j++) {
251 OUT_RING(ring, 0x00000000);
252 }
253 }
254 }
255
256 if (needs_border) {
257 unsigned off;
258 void *ptr;
259
260 u_upload_alloc(fd3_ctx->border_color_uploader,
261 0, BORDER_COLOR_UPLOAD_SIZE,
262 BORDER_COLOR_UPLOAD_SIZE, &off,
263 &fd3_ctx->border_color_buf,
264 &ptr);
265
266 fd_setup_border_colors(tex, ptr, tex_off[sb]);
267
268 OUT_PKT0(ring, bcolor_reg[sb], 1);
269 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
270
271 u_upload_unmap(fd3_ctx->border_color_uploader);
272 }
273 }
274
275 /* emit texture state for mem->gmem restore operation.. eventually it would
276 * be good to get rid of this and use normal CSO/etc state for more of these
277 * special cases, but for now the compiler is not sufficient..
278 *
279 * Also, for using normal state, not quite sure how to handle the special
280 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
281 */
282 void
283 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
284 struct pipe_surface **psurf,
285 int bufs)
286 {
287 int i, j;
288
289 /* output sampler state: */
290 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
291 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
292 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
293 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
294 CP_LOAD_STATE_0_NUM_UNIT(bufs));
295 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
296 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
297 for (i = 0; i < bufs; i++) {
298 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
299 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
300 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
301 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
302 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
303 OUT_RING(ring, 0x00000000);
304 }
305
306 /* emit texture state: */
307 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
308 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
309 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
310 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
311 CP_LOAD_STATE_0_NUM_UNIT(bufs));
312 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
313 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
314 for (i = 0; i < bufs; i++) {
315 if (!psurf[i]) {
316 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
317 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
318 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
319 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
320 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
321 OUT_RING(ring, 0x00000000);
322 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
323 OUT_RING(ring, 0x00000000);
324 continue;
325 }
326
327 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
328 enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
329 /* The restore blit_zs shader expects stencil in sampler 0, and depth
330 * in sampler 1
331 */
332 if (rsc->stencil && i == 0) {
333 rsc = rsc->stencil;
334 format = fd_gmem_restore_format(rsc->base.format);
335 }
336
337 /* note: PIPE_BUFFER disallowed for surfaces */
338 unsigned lvl = psurf[i]->u.tex.level;
339
340 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
341
342 OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
343 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
344 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
345 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
346 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
347 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
348 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
349 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
350 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)) |
351 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
352 OUT_RING(ring, 0x00000000);
353 }
354
355 /* emit mipaddrs: */
356 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
357 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
358 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
359 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
360 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
361 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
362 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
363 for (i = 0; i < bufs; i++) {
364 if (psurf[i]) {
365 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
366 /* Matches above logic for blit_zs shader */
367 if (rsc->stencil && i == 0)
368 rsc = rsc->stencil;
369 unsigned lvl = psurf[i]->u.tex.level;
370 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
371 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
372 } else {
373 OUT_RING(ring, 0x00000000);
374 }
375
376 /* pad the remaining entries w/ null: */
377 for (j = 1; j < BASETABLE_SZ; j++) {
378 OUT_RING(ring, 0x00000000);
379 }
380 }
381 }
382
383 void
384 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
385 {
386 int32_t i, j, last = -1;
387 uint32_t total_in = 0;
388 const struct fd_vertex_state *vtx = emit->vtx;
389 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
390 unsigned vertex_regid = regid(63, 0);
391 unsigned instance_regid = regid(63, 0);
392 unsigned vtxcnt_regid = regid(63, 0);
393
394 /* Note that sysvals come *after* normal inputs: */
395 for (i = 0; i < vp->inputs_count; i++) {
396 if (!vp->inputs[i].compmask)
397 continue;
398 if (vp->inputs[i].sysval) {
399 switch(vp->inputs[i].slot) {
400 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
401 vertex_regid = vp->inputs[i].regid;
402 break;
403 case SYSTEM_VALUE_INSTANCE_ID:
404 instance_regid = vp->inputs[i].regid;
405 break;
406 case SYSTEM_VALUE_VERTEX_CNT:
407 vtxcnt_regid = vp->inputs[i].regid;
408 break;
409 default:
410 unreachable("invalid system value");
411 break;
412 }
413 } else if (i < vtx->vtx->num_elements) {
414 last = i;
415 }
416 }
417
418 for (i = 0, j = 0; i <= last; i++) {
419 assert(!vp->inputs[i].sysval);
420 if (vp->inputs[i].compmask) {
421 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
422 const struct pipe_vertex_buffer *vb =
423 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
424 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
425 enum pipe_format pfmt = elem->src_format;
426 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
427 bool switchnext = (i != last) ||
428 (vertex_regid != regid(63, 0)) ||
429 (instance_regid != regid(63, 0)) ||
430 (vtxcnt_regid != regid(63, 0));
431 bool isint = util_format_is_pure_integer(pfmt);
432 uint32_t off = vb->buffer_offset + elem->src_offset;
433 uint32_t fs = util_format_get_blocksize(pfmt);
434
435 #ifdef DEBUG
436 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
437 * should mesa/st be protecting us from this?
438 */
439 if (off > fd_bo_size(rsc->bo))
440 continue;
441 #endif
442
443 debug_assert(fmt != VFMT_NONE);
444
445 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
446 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
447 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
448 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
449 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
450 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
451 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
452 OUT_RELOC(ring, rsc->bo, off, 0, 0);
453
454 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
455 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
456 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
457 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
458 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
459 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
460 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
461 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
462 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
463 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
464
465 total_in += util_bitcount(vp->inputs[i].compmask);
466 j++;
467 }
468 }
469
470 /* hw doesn't like to be configured for zero vbo's, it seems: */
471 if (last < 0) {
472 /* just recycle the shader bo, we just need to point to *something*
473 * valid:
474 */
475 struct fd_bo *dummy_vbo = vp->bo;
476 bool switchnext = (vertex_regid != regid(63, 0)) ||
477 (instance_regid != regid(63, 0)) ||
478 (vtxcnt_regid != regid(63, 0));
479
480 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
481 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
482 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
483 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
484 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
485 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
486 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
487
488 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
489 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
490 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
491 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
492 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
493 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
494 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
495 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
496 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
497
498 total_in = 1;
499 j = 1;
500 }
501
502 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
503 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
504 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
505 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
506 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
507 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
508 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
509 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
510
511 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
512 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
513 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
514 }
515
516 void
517 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
518 struct fd3_emit *emit)
519 {
520 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
521 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
522 const enum fd_dirty_3d_state dirty = emit->dirty;
523
524 emit_marker(ring, 5);
525
526 if (dirty & FD_DIRTY_SAMPLE_MASK) {
527 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
528 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
529 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
530 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
531 }
532
533 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
534 !emit->binning_pass) {
535 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
536 fd3_blend_stateobj(ctx->blend)->rb_render_control;
537
538 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
539 val |= COND(fp->fragcoord_compmask != 0,
540 A3XX_RB_RENDER_CONTROL_COORD_MASK(fp->fragcoord_compmask));
541 val |= COND(ctx->rasterizer->rasterizer_discard,
542 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
543
544 /* I suppose if we needed to (which I don't *think* we need
545 * to), we could emit this for binning pass too. But we
546 * would need to keep a different patch-list for binning
547 * vs render pass.
548 */
549
550 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
551 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
552 }
553
554 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
555 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
556 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
557
558 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
559 OUT_RING(ring, zsa->rb_alpha_ref);
560
561 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
562 OUT_RING(ring, zsa->rb_stencil_control);
563
564 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
565 OUT_RING(ring, zsa->rb_stencilrefmask |
566 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
567 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
568 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
569 }
570
571 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
572 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
573 if (fp->writes_pos) {
574 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
575 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
576 }
577 if (fp->no_earlyz || fp->has_kill) {
578 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
579 }
580 if (!ctx->rasterizer->depth_clip_near) {
581 val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
582 }
583 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
584 OUT_RING(ring, val);
585 }
586
587 if (dirty & FD_DIRTY_RASTERIZER) {
588 struct fd3_rasterizer_stateobj *rasterizer =
589 fd3_rasterizer_stateobj(ctx->rasterizer);
590
591 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
592 OUT_RING(ring, rasterizer->gras_su_mode_control);
593
594 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
595 OUT_RING(ring, rasterizer->gras_su_point_minmax);
596 OUT_RING(ring, rasterizer->gras_su_point_size);
597
598 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
599 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
600 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
601 }
602
603 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
604 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
605 ->gras_cl_clip_cntl;
606 uint8_t planes = ctx->rasterizer->clip_plane_enable;
607 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL),
608 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
609 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL),
610 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER);
611 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID),
612 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID);
613 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID),
614 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID);
615 /* docs say enable at least one of IJ_PERSP_CENTER/CENTROID when fragcoord is used */
616 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD),
617 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
618 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
619 val |= COND(fp->fragcoord_compmask != 0, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
620 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
621 if (!emit->key.ucp_enables)
622 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
623 MIN2(util_bitcount(planes), 6));
624 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
625 OUT_RING(ring, val);
626 }
627
628 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
629 uint32_t planes = ctx->rasterizer->clip_plane_enable;
630 int count = 0;
631
632 if (emit->key.ucp_enables)
633 planes = 0;
634
635 while (planes && count < 6) {
636 int i = ffs(planes) - 1;
637
638 planes &= ~(1U << i);
639 fd_wfi(ctx->batch, ring);
640 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
641 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
642 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
643 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
644 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
645 }
646 }
647
648 /* NOTE: since primitive_restart is not actually part of any
649 * state object, we need to make sure that we always emit
650 * PRIM_VTX_CNTL.. either that or be more clever and detect
651 * when it changes.
652 */
653 if (emit->info) {
654 const struct pipe_draw_info *info = emit->info;
655 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
656 ->pc_prim_vtx_cntl;
657
658 if (!emit->binning_pass) {
659 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
660 if (stride_in_vpc > 0)
661 stride_in_vpc = MAX2(stride_in_vpc, 2);
662 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
663 }
664
665 if (info->index_size && info->primitive_restart) {
666 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
667 }
668
669 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
670
671 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
672 OUT_RING(ring, val);
673 }
674
675 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
676 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
677 int minx = scissor->minx;
678 int miny = scissor->miny;
679 int maxx = scissor->maxx;
680 int maxy = scissor->maxy;
681
682 /* Unfortunately there is no separate depth clip disable, only an all
683 * or nothing deal. So when we disable clipping, we must handle the
684 * viewport clip via scissors.
685 */
686 if (!ctx->rasterizer->depth_clip_near) {
687 struct pipe_viewport_state *vp = &ctx->viewport;
688 minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
689 miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
690 maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
691 maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
692 }
693
694 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
695 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
696 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
697 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
698 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
699
700 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
701 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
702 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
703 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
704 }
705
706 if (dirty & FD_DIRTY_VIEWPORT) {
707 fd_wfi(ctx->batch, ring);
708 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
709 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
710 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
711 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
712 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
713 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
714 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
715 }
716
717 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
718 float zmin, zmax;
719 int depth = 24;
720 if (ctx->batch->framebuffer.zsbuf) {
721 depth = util_format_get_component_bits(
722 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
723 UTIL_FORMAT_COLORSPACE_ZS, 0);
724 }
725 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
726 &zmin, &zmax);
727
728 OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
729 if (depth == 32) {
730 OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
731 OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
732 } else if (depth == 16) {
733 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
734 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
735 } else {
736 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
737 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
738 }
739 }
740
741 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
742 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
743 int nr_cbufs = pfb->nr_cbufs;
744 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
745 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
746 nr_cbufs++;
747 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
748 }
749
750 /* TODO we should not need this or fd_wfi() before emit_constants():
751 */
752 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
753 OUT_RING(ring, HLSQ_FLUSH);
754
755 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
756 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
757 if (!emit->binning_pass)
758 ir3_emit_fs_consts(fp, ring, ctx);
759 }
760
761 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
762 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
763 uint32_t i;
764
765 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
766 enum pipe_format format =
767 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
768 const struct util_format_description *desc =
769 util_format_description(format);
770 bool is_float = util_format_is_float(format);
771 bool is_int = util_format_is_pure_integer(format);
772 bool has_alpha = util_format_has_alpha(format);
773 uint32_t control = blend->rb_mrt[i].control;
774
775 if (is_int) {
776 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
777 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
778 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
779 }
780
781 if (format == PIPE_FORMAT_NONE)
782 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
783
784 if (!has_alpha) {
785 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
786 }
787
788 if (format && util_format_get_component_bits(
789 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
790 const struct pipe_rt_blend_state *rt;
791 if (ctx->blend->independent_blend_enable)
792 rt = &ctx->blend->rt[i];
793 else
794 rt = &ctx->blend->rt[0];
795
796 if (!util_format_colormask_full(desc, rt->colormask))
797 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
798 }
799
800 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
801 OUT_RING(ring, control);
802
803 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
804 OUT_RING(ring, blend->rb_mrt[i].blend_control |
805 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
806 }
807 }
808
809 if (dirty & FD_DIRTY_BLEND_COLOR) {
810 struct pipe_blend_color *bcolor = &ctx->blend_color;
811 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
812 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
813 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
814 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
815 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
816 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
817 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
818 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
819 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
820 }
821
822 if (dirty & FD_DIRTY_TEX)
823 fd_wfi(ctx->batch, ring);
824
825 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
826 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
827
828 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
829 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
830 }
831
832 /* emit setup at begin of new cmdstream buffer (don't rely on previous
833 * state, there could have been a context switch between ioctls):
834 */
835 void
836 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
837 {
838 struct fd_context *ctx = batch->ctx;
839 struct fd3_context *fd3_ctx = fd3_context(ctx);
840 int i;
841
842 if (ctx->screen->gpu_id == 320) {
843 OUT_PKT3(ring, CP_REG_RMW, 3);
844 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
845 OUT_RING(ring, 0xfffcffff);
846 OUT_RING(ring, 0x00000000);
847 }
848
849 fd_wfi(batch, ring);
850 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
851 OUT_RING(ring, 0x00007fff);
852
853 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
854 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
855 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
856 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
857
858 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
859 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
860 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
861 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
862
863 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
864 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
865
866 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
867 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
868 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
869 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
870
871 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
872 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
873 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
874 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
875 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
876
877 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
878 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
879 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
880
881 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
882 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
883
884 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
885 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
886 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
887 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
888
889 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
890 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
891 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
892 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
893
894 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
895 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
896 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
897
898 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
899 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
900
901 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
902 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
903
904 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
905 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
906
907 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
908 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
909
910 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
911 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
912
913 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
914 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
915 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
916 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
917 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
918
919 fd3_emit_cache_flush(batch, ring);
920
921 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
922 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
923
924 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
925 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
926 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
927
928 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
929 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
930
931 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
932 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
933 A3XX_RB_WINDOW_OFFSET_Y(0));
934
935 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
936 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
937 A3XX_RB_BLEND_RED_FLOAT(0.0));
938 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
939 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
940 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
941 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
942 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
943 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
944
945 for (i = 0; i < 6; i++) {
946 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
947 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
948 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
949 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
950 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
951 }
952
953 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
954 OUT_RING(ring, 0x00000000);
955
956 fd_event_write(batch, ring, CACHE_FLUSH);
957
958 if (is_a3xx_p0(ctx->screen)) {
959 OUT_PKT3(ring, CP_DRAW_INDX, 3);
960 OUT_RING(ring, 0x00000000);
961 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
962 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
963 OUT_RING(ring, 0); /* NumIndices */
964 }
965
966 OUT_PKT3(ring, CP_NOP, 4);
967 OUT_RING(ring, 0x00000000);
968 OUT_RING(ring, 0x00000000);
969 OUT_RING(ring, 0x00000000);
970 OUT_RING(ring, 0x00000000);
971
972 fd_wfi(batch, ring);
973
974 fd_hw_query_enable(batch, ring);
975 }
976
977 void
978 fd3_emit_init_screen(struct pipe_screen *pscreen)
979 {
980 struct fd_screen *screen = fd_screen(pscreen);
981 screen->emit_ib = fd3_emit_ib;
982 }
983
984 void
985 fd3_emit_init(struct pipe_context *pctx)
986 {
987 }