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freedreno: Make the slice pitch be bytes, not pixels.
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_emit.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd3_emit.h"
38 #include "fd3_blend.h"
39 #include "fd3_context.h"
40 #include "fd3_program.h"
41 #include "fd3_rasterizer.h"
42 #include "fd3_texture.h"
43 #include "fd3_format.h"
44 #include "fd3_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [MESA_SHADER_VERTEX] = SB_VERT_SHADER,
48 [MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 static void
56 fd3_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = SS_INDIRECT;
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/2));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd3_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
95 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
96 {
97 uint32_t anum = align(num, 4);
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(anum/2));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (prscs[i]) {
112 if (write) {
113 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121
122 for (; i < anum; i++)
123 OUT_RING(ring, 0xffffffff);
124 }
125
126 #define VERT_TEX_OFF 0
127 #define FRAG_TEX_OFF 16
128 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
129
130 static void
131 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
132 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
133 {
134 static const unsigned tex_off[] = {
135 [SB_VERT_TEX] = VERT_TEX_OFF,
136 [SB_FRAG_TEX] = FRAG_TEX_OFF,
137 };
138 static const enum adreno_state_block mipaddr[] = {
139 [SB_VERT_TEX] = SB_VERT_MIPADDR,
140 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
141 };
142 static const uint32_t bcolor_reg[] = {
143 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
144 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
145 };
146 struct fd3_context *fd3_ctx = fd3_context(ctx);
147 bool needs_border = false;
148 unsigned i, j;
149
150 if (tex->num_samplers > 0) {
151 /* output sampler state: */
152 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
153 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
154 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
155 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
156 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
158 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
159 for (i = 0; i < tex->num_samplers; i++) {
160 static const struct fd3_sampler_stateobj dummy_sampler = {};
161 const struct fd3_sampler_stateobj *sampler = tex->samplers[i] ?
162 fd3_sampler_stateobj(tex->samplers[i]) :
163 &dummy_sampler;
164
165 OUT_RING(ring, sampler->texsamp0);
166 OUT_RING(ring, sampler->texsamp1);
167
168 needs_border |= sampler->needs_border;
169 }
170 }
171
172 if (tex->num_textures > 0) {
173 /* emit texture state: */
174 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
175 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
176 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
177 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
178 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
179 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
180 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
181 for (i = 0; i < tex->num_textures; i++) {
182 static const struct fd3_pipe_sampler_view dummy_view = {};
183 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
184 fd3_pipe_sampler_view(tex->textures[i]) :
185 &dummy_view;
186 OUT_RING(ring, view->texconst0);
187 OUT_RING(ring, view->texconst1);
188 OUT_RING(ring, view->texconst2 |
189 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
190 OUT_RING(ring, view->texconst3);
191 }
192
193 /* emit mipaddrs: */
194 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
195 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
196 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
197 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
198 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
199 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
200 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
201 for (i = 0; i < tex->num_textures; i++) {
202 static const struct fd3_pipe_sampler_view dummy_view = {
203 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
204 .base.u.tex.first_level = 1,
205 };
206 const struct fd3_pipe_sampler_view *view = tex->textures[i] ?
207 fd3_pipe_sampler_view(tex->textures[i]) :
208 &dummy_view;
209 struct fd_resource *rsc = fd_resource(view->base.texture);
210 if (rsc && rsc->base.target == PIPE_BUFFER) {
211 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
212 j = 1;
213 } else {
214 unsigned start = fd_sampler_first_level(&view->base);
215 unsigned end = fd_sampler_last_level(&view->base);
216
217 for (j = 0; j < (end - start + 1); j++) {
218 struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
219 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
220 }
221 }
222
223 /* pad the remaining entries w/ null: */
224 for (; j < BASETABLE_SZ; j++) {
225 OUT_RING(ring, 0x00000000);
226 }
227 }
228 }
229
230 if (needs_border) {
231 unsigned off;
232 void *ptr;
233
234 u_upload_alloc(fd3_ctx->border_color_uploader,
235 0, BORDER_COLOR_UPLOAD_SIZE,
236 BORDER_COLOR_UPLOAD_SIZE, &off,
237 &fd3_ctx->border_color_buf,
238 &ptr);
239
240 fd_setup_border_colors(tex, ptr, tex_off[sb]);
241
242 OUT_PKT0(ring, bcolor_reg[sb], 1);
243 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
244
245 u_upload_unmap(fd3_ctx->border_color_uploader);
246 }
247 }
248
249 /* emit texture state for mem->gmem restore operation.. eventually it would
250 * be good to get rid of this and use normal CSO/etc state for more of these
251 * special cases, but for now the compiler is not sufficient..
252 *
253 * Also, for using normal state, not quite sure how to handle the special
254 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
255 */
256 void
257 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
258 struct pipe_surface **psurf,
259 int bufs)
260 {
261 int i, j;
262
263 /* output sampler state: */
264 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
265 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
266 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
267 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
268 CP_LOAD_STATE_0_NUM_UNIT(bufs));
269 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
270 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
271 for (i = 0; i < bufs; i++) {
272 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
273 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
274 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
275 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
276 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
277 OUT_RING(ring, 0x00000000);
278 }
279
280 /* emit texture state: */
281 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
282 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
283 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
284 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
285 CP_LOAD_STATE_0_NUM_UNIT(bufs));
286 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
287 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
288 for (i = 0; i < bufs; i++) {
289 if (!psurf[i]) {
290 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
291 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
292 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
293 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
294 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
295 OUT_RING(ring, 0x00000000);
296 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
297 OUT_RING(ring, 0x00000000);
298 continue;
299 }
300
301 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
302 enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
303 /* The restore blit_zs shader expects stencil in sampler 0, and depth
304 * in sampler 1
305 */
306 if (rsc->stencil && i == 0) {
307 rsc = rsc->stencil;
308 format = fd_gmem_restore_format(rsc->base.format);
309 }
310
311 /* note: PIPE_BUFFER disallowed for surfaces */
312 unsigned lvl = psurf[i]->u.tex.level;
313 struct fdl_slice *slice = fd_resource_slice(rsc, lvl);
314
315 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
316
317 OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
318 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
319 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
320 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
321 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
322 OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
323 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
324 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
325 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch) |
326 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
327 OUT_RING(ring, 0x00000000);
328 }
329
330 /* emit mipaddrs: */
331 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
332 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
333 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
334 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
335 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
336 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
337 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
338 for (i = 0; i < bufs; i++) {
339 if (psurf[i]) {
340 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
341 /* Matches above logic for blit_zs shader */
342 if (rsc->stencil && i == 0)
343 rsc = rsc->stencil;
344 unsigned lvl = psurf[i]->u.tex.level;
345 uint32_t offset = fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
346 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
347 } else {
348 OUT_RING(ring, 0x00000000);
349 }
350
351 /* pad the remaining entries w/ null: */
352 for (j = 1; j < BASETABLE_SZ; j++) {
353 OUT_RING(ring, 0x00000000);
354 }
355 }
356 }
357
358 void
359 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
360 {
361 int32_t i, j, last = -1;
362 uint32_t total_in = 0;
363 const struct fd_vertex_state *vtx = emit->vtx;
364 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
365 unsigned vertex_regid = regid(63, 0);
366 unsigned instance_regid = regid(63, 0);
367 unsigned vtxcnt_regid = regid(63, 0);
368
369 /* Note that sysvals come *after* normal inputs: */
370 for (i = 0; i < vp->inputs_count; i++) {
371 if (!vp->inputs[i].compmask)
372 continue;
373 if (vp->inputs[i].sysval) {
374 switch(vp->inputs[i].slot) {
375 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
376 vertex_regid = vp->inputs[i].regid;
377 break;
378 case SYSTEM_VALUE_INSTANCE_ID:
379 instance_regid = vp->inputs[i].regid;
380 break;
381 case SYSTEM_VALUE_VERTEX_CNT:
382 vtxcnt_regid = vp->inputs[i].regid;
383 break;
384 default:
385 unreachable("invalid system value");
386 break;
387 }
388 } else if (i < vtx->vtx->num_elements) {
389 last = i;
390 }
391 }
392
393 for (i = 0, j = 0; i <= last; i++) {
394 assert(!vp->inputs[i].sysval);
395 if (vp->inputs[i].compmask) {
396 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
397 const struct pipe_vertex_buffer *vb =
398 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
399 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
400 enum pipe_format pfmt = elem->src_format;
401 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
402 bool switchnext = (i != last) ||
403 (vertex_regid != regid(63, 0)) ||
404 (instance_regid != regid(63, 0)) ||
405 (vtxcnt_regid != regid(63, 0));
406 bool isint = util_format_is_pure_integer(pfmt);
407 uint32_t off = vb->buffer_offset + elem->src_offset;
408 uint32_t fs = util_format_get_blocksize(pfmt);
409
410 #ifdef DEBUG
411 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
412 * should mesa/st be protecting us from this?
413 */
414 if (off > fd_bo_size(rsc->bo))
415 continue;
416 #endif
417
418 debug_assert(fmt != ~0);
419
420 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
421 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
422 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
423 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
424 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
425 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
426 A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor)));
427 OUT_RELOC(ring, rsc->bo, off, 0, 0);
428
429 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
430 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
431 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
432 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
433 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
434 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
435 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
436 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
437 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
438 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
439
440 total_in += util_bitcount(vp->inputs[i].compmask);
441 j++;
442 }
443 }
444
445 /* hw doesn't like to be configured for zero vbo's, it seems: */
446 if (last < 0) {
447 /* just recycle the shader bo, we just need to point to *something*
448 * valid:
449 */
450 struct fd_bo *dummy_vbo = vp->bo;
451 bool switchnext = (vertex_regid != regid(63, 0)) ||
452 (instance_regid != regid(63, 0)) ||
453 (vtxcnt_regid != regid(63, 0));
454
455 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
456 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
457 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
458 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
459 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
460 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
461 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
462
463 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
464 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
465 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
466 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
467 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
468 A3XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
469 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
470 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
471 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
472
473 total_in = 1;
474 j = 1;
475 }
476
477 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
478 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
479 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
480 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
481 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
482 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
483 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
484 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
485
486 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
487 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
488 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
489 }
490
491 void
492 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
493 struct fd3_emit *emit)
494 {
495 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
496 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
497 const enum fd_dirty_3d_state dirty = emit->dirty;
498
499 emit_marker(ring, 5);
500
501 if (dirty & FD_DIRTY_SAMPLE_MASK) {
502 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
503 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
504 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
505 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
506 }
507
508 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG | FD_DIRTY_BLEND_DUAL)) &&
509 !emit->binning_pass) {
510 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
511 fd3_blend_stateobj(ctx->blend)->rb_render_control;
512
513 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
514 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD |
515 A3XX_RB_RENDER_CONTROL_YCOORD |
516 A3XX_RB_RENDER_CONTROL_ZCOORD |
517 A3XX_RB_RENDER_CONTROL_WCOORD);
518
519 /* I suppose if we needed to (which I don't *think* we need
520 * to), we could emit this for binning pass too. But we
521 * would need to keep a different patch-list for binning
522 * vs render pass.
523 */
524
525 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
526 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
527 }
528
529 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
530 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
531 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
532
533 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
534 OUT_RING(ring, zsa->rb_alpha_ref);
535
536 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
537 OUT_RING(ring, zsa->rb_stencil_control);
538
539 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
540 OUT_RING(ring, zsa->rb_stencilrefmask |
541 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
542 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
543 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
544 }
545
546 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
547 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
548 if (fp->writes_pos) {
549 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
550 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
551 }
552 if (fp->no_earlyz) {
553 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
554 }
555 if (!ctx->rasterizer->depth_clip_near) {
556 val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
557 }
558 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
559 OUT_RING(ring, val);
560 }
561
562 if (dirty & FD_DIRTY_RASTERIZER) {
563 struct fd3_rasterizer_stateobj *rasterizer =
564 fd3_rasterizer_stateobj(ctx->rasterizer);
565
566 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
567 OUT_RING(ring, rasterizer->gras_su_mode_control);
568
569 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
570 OUT_RING(ring, rasterizer->gras_su_point_minmax);
571 OUT_RING(ring, rasterizer->gras_su_point_size);
572
573 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
574 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
575 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
576 }
577
578 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
579 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
580 ->gras_cl_clip_cntl;
581 uint8_t planes = ctx->rasterizer->clip_plane_enable;
582 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
583 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
584 A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
585 if (!emit->key.ucp_enables)
586 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
587 MIN2(util_bitcount(planes), 6));
588 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
589 OUT_RING(ring, val);
590 }
591
592 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
593 uint32_t planes = ctx->rasterizer->clip_plane_enable;
594 int count = 0;
595
596 if (emit->key.ucp_enables)
597 planes = 0;
598
599 while (planes && count < 6) {
600 int i = ffs(planes) - 1;
601
602 planes &= ~(1U << i);
603 fd_wfi(ctx->batch, ring);
604 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
605 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
606 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
607 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
608 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
609 }
610 }
611
612 /* NOTE: since primitive_restart is not actually part of any
613 * state object, we need to make sure that we always emit
614 * PRIM_VTX_CNTL.. either that or be more clever and detect
615 * when it changes.
616 */
617 if (emit->info) {
618 const struct pipe_draw_info *info = emit->info;
619 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
620 ->pc_prim_vtx_cntl;
621
622 if (!emit->binning_pass) {
623 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
624 if (stride_in_vpc > 0)
625 stride_in_vpc = MAX2(stride_in_vpc, 2);
626 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
627 }
628
629 if (info->index_size && info->primitive_restart) {
630 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
631 }
632
633 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
634
635 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
636 OUT_RING(ring, val);
637 }
638
639 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
640 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
641 int minx = scissor->minx;
642 int miny = scissor->miny;
643 int maxx = scissor->maxx;
644 int maxy = scissor->maxy;
645
646 /* Unfortunately there is no separate depth clip disable, only an all
647 * or nothing deal. So when we disable clipping, we must handle the
648 * viewport clip via scissors.
649 */
650 if (!ctx->rasterizer->depth_clip_near) {
651 struct pipe_viewport_state *vp = &ctx->viewport;
652 minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
653 miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
654 maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
655 maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
656 }
657
658 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
659 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
660 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
661 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
662 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
663
664 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
665 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
666 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
667 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
668 }
669
670 if (dirty & FD_DIRTY_VIEWPORT) {
671 fd_wfi(ctx->batch, ring);
672 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
673 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
674 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
675 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
676 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
677 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
678 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
679 }
680
681 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
682 float zmin, zmax;
683 int depth = 24;
684 if (ctx->batch->framebuffer.zsbuf) {
685 depth = util_format_get_component_bits(
686 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
687 UTIL_FORMAT_COLORSPACE_ZS, 0);
688 }
689 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
690 &zmin, &zmax);
691
692 OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
693 if (depth == 32) {
694 OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
695 OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
696 } else if (depth == 16) {
697 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
698 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
699 } else {
700 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
701 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
702 }
703 }
704
705 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
706 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
707 int nr_cbufs = pfb->nr_cbufs;
708 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
709 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
710 nr_cbufs++;
711 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
712 }
713
714 /* TODO we should not need this or fd_wfi() before emit_constants():
715 */
716 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
717 OUT_RING(ring, HLSQ_FLUSH);
718
719 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
720 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
721 if (!emit->binning_pass)
722 ir3_emit_fs_consts(fp, ring, ctx);
723 }
724
725 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
726 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
727 uint32_t i;
728
729 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
730 enum pipe_format format =
731 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
732 const struct util_format_description *desc =
733 util_format_description(format);
734 bool is_float = util_format_is_float(format);
735 bool is_int = util_format_is_pure_integer(format);
736 bool has_alpha = util_format_has_alpha(format);
737 uint32_t control = blend->rb_mrt[i].control;
738
739 if (is_int) {
740 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
741 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
742 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
743 }
744
745 if (format == PIPE_FORMAT_NONE)
746 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
747
748 if (!has_alpha) {
749 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
750 }
751
752 if (format && util_format_get_component_bits(
753 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
754 const struct pipe_rt_blend_state *rt;
755 if (ctx->blend->independent_blend_enable)
756 rt = &ctx->blend->rt[i];
757 else
758 rt = &ctx->blend->rt[0];
759
760 if (!util_format_colormask_full(desc, rt->colormask))
761 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
762 }
763
764 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
765 OUT_RING(ring, control);
766
767 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
768 OUT_RING(ring, blend->rb_mrt[i].blend_control |
769 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
770 }
771 }
772
773 if (dirty & FD_DIRTY_BLEND_COLOR) {
774 struct pipe_blend_color *bcolor = &ctx->blend_color;
775 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
776 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
777 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
778 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
779 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
780 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
781 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
782 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
783 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
784 }
785
786 if (dirty & FD_DIRTY_TEX)
787 fd_wfi(ctx->batch, ring);
788
789 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
790 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
791
792 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
793 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
794 }
795
796 /* emit setup at begin of new cmdstream buffer (don't rely on previous
797 * state, there could have been a context switch between ioctls):
798 */
799 void
800 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
801 {
802 struct fd_context *ctx = batch->ctx;
803 struct fd3_context *fd3_ctx = fd3_context(ctx);
804 int i;
805
806 if (ctx->screen->gpu_id == 320) {
807 OUT_PKT3(ring, CP_REG_RMW, 3);
808 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
809 OUT_RING(ring, 0xfffcffff);
810 OUT_RING(ring, 0x00000000);
811 }
812
813 fd_wfi(batch, ring);
814 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
815 OUT_RING(ring, 0x00007fff);
816
817 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
818 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
819 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR_REG */
820 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
821
822 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
823 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
824 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR_REG */
825 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
826
827 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
828 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
829
830 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
831 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
832 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
833 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
834
835 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
836 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
837 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
838 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
839 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
840
841 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
842 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
843 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
844
845 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
846 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
847
848 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
849 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
850 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
851 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * VERT_TEX_OFF));
852
853 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
854 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
855 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
856 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ * FRAG_TEX_OFF));
857
858 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
859 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
860 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
861
862 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
863 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
864
865 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
866 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
867
868 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
869 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
870
871 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
872 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
873
874 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
875 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
876
877 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
878 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
879 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
880 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
881 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
882
883 fd3_emit_cache_flush(batch, ring);
884
885 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
886 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
887
888 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
889 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
890 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
891
892 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
893 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
894
895 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
896 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) |
897 A3XX_RB_WINDOW_OFFSET_Y(0));
898
899 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
900 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) |
901 A3XX_RB_BLEND_RED_FLOAT(0.0));
902 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) |
903 A3XX_RB_BLEND_GREEN_FLOAT(0.0));
904 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) |
905 A3XX_RB_BLEND_BLUE_FLOAT(0.0));
906 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
907 A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
908
909 for (i = 0; i < 6; i++) {
910 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
911 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
912 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
913 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
914 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
915 }
916
917 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
918 OUT_RING(ring, 0x00000000);
919
920 fd_event_write(batch, ring, CACHE_FLUSH);
921
922 if (is_a3xx_p0(ctx->screen)) {
923 OUT_PKT3(ring, CP_DRAW_INDX, 3);
924 OUT_RING(ring, 0x00000000);
925 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
926 INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0));
927 OUT_RING(ring, 0); /* NumIndices */
928 }
929
930 OUT_PKT3(ring, CP_NOP, 4);
931 OUT_RING(ring, 0x00000000);
932 OUT_RING(ring, 0x00000000);
933 OUT_RING(ring, 0x00000000);
934 OUT_RING(ring, 0x00000000);
935
936 fd_wfi(batch, ring);
937
938 fd_hw_query_enable(batch, ring);
939 }
940
941 void
942 fd3_emit_init_screen(struct pipe_screen *pscreen)
943 {
944 struct fd_screen *screen = fd_screen(pscreen);
945 screen->emit_const = fd3_emit_const;
946 screen->emit_const_bo = fd3_emit_const_bo;
947 screen->emit_ib = fd3_emit_ib;
948 }
949
950 void
951 fd3_emit_init(struct pipe_context *pctx)
952 {
953 }