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8ab7cd2cbb6ac560ef122a9a9eafda897fb36f3a
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd3_program.h"
37 #include "fd3_emit.h"
38 #include "fd3_texture.h"
39 #include "fd3_format.h"
40
41 bool
42 fd3_needs_manual_clipping(const struct ir3_shader *shader,
43 const struct pipe_rasterizer_state *rast)
44 {
45 uint64_t outputs = ir3_shader_outputs(shader);
46
47 return (!rast->depth_clip_near ||
48 util_bitcount(rast->clip_plane_enable) > 6 ||
49 outputs & ((1ULL << VARYING_SLOT_CLIP_VERTEX) |
50 (1ULL << VARYING_SLOT_CLIP_DIST0) |
51 (1ULL << VARYING_SLOT_CLIP_DIST1)));
52 }
53
54
55 static void
56 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
57 {
58 const struct ir3_info *si = &so->info;
59 enum adreno_state_block sb;
60 enum adreno_state_src src;
61 uint32_t i, sz, *bin;
62
63 if (so->type == MESA_SHADER_VERTEX) {
64 sb = SB_VERT_SHADER;
65 } else {
66 sb = SB_FRAG_SHADER;
67 }
68
69 if (fd_mesa_debug & FD_DBG_DIRECT) {
70 sz = si->sizedwords;
71 src = SS_DIRECT;
72 bin = fd_bo_map(so->bo);
73 } else {
74 sz = 0;
75 src = SS_INDIRECT;
76 bin = NULL;
77 }
78
79 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
80 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
81 CP_LOAD_STATE_0_STATE_SRC(src) |
82 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
83 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
84 if (bin) {
85 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
87 } else {
88 OUT_RELOC(ring, so->bo, 0,
89 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
90 }
91 for (i = 0; i < sz; i++) {
92 OUT_RING(ring, bin[i]);
93 }
94 }
95
96 void
97 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
98 int nr, struct pipe_surface **bufs)
99 {
100 const struct ir3_shader_variant *vp, *fp;
101 const struct ir3_info *vsi, *fsi;
102 enum a3xx_instrbuffermode fpbuffer, vpbuffer;
103 uint32_t fpbuffersz, vpbuffersz, fsoff;
104 uint32_t pos_regid, posz_regid, psize_regid;
105 uint32_t vcoord_regid, face_regid, coord_regid, zwcoord_regid;
106 uint32_t color_regid[4] = {0};
107 int constmode;
108 int i, j;
109
110 debug_assert(nr <= ARRAY_SIZE(color_regid));
111
112 vp = fd3_emit_get_vp(emit);
113 fp = fd3_emit_get_fp(emit);
114
115 vsi = &vp->info;
116 fsi = &fp->info;
117
118 fpbuffer = BUFFER;
119 vpbuffer = BUFFER;
120 fpbuffersz = fp->instrlen;
121 vpbuffersz = vp->instrlen;
122
123 /*
124 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
125 * appears like 256 is the hard limit, but when the combined size
126 * exceeds 128 then blob will try to keep FS in BUFFER mode and
127 * switch to CACHE for VS until VS is too large. The blob seems
128 * to switch FS out of BUFFER mode at slightly under 128. But
129 * a bit fuzzy on the decision tree, so use slightly conservative
130 * limits.
131 *
132 * TODO check if these thresholds for BUFFER vs CACHE mode are the
133 * same for all a3xx or whether we need to consider the gpuid
134 */
135
136 if ((fpbuffersz + vpbuffersz) > 128) {
137 if (fpbuffersz < 112) {
138 /* FP:BUFFER VP:CACHE */
139 vpbuffer = CACHE;
140 vpbuffersz = 256 - fpbuffersz;
141 } else if (vpbuffersz < 112) {
142 /* FP:CACHE VP:BUFFER */
143 fpbuffer = CACHE;
144 fpbuffersz = 256 - vpbuffersz;
145 } else {
146 /* FP:CACHE VP:CACHE */
147 vpbuffer = fpbuffer = CACHE;
148 vpbuffersz = fpbuffersz = 192;
149 }
150 }
151
152 if (fpbuffer == BUFFER) {
153 fsoff = 128 - fpbuffersz;
154 } else {
155 fsoff = 256 - fpbuffersz;
156 }
157
158 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
159 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
160
161 pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
162 posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
163 psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
164 if (fp->color0_mrt) {
165 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
166 ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
167 } else {
168 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
169 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
170 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
171 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
172 }
173
174 face_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRONT_FACE);
175 coord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD);
176 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
177 vcoord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
178
179 /* adjust regids for alpha output formats. there is no alpha render
180 * format, so it's just treated like red
181 */
182 for (i = 0; i < nr; i++)
183 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
184 color_regid[i] += 3;
185
186 /* we could probably divide this up into things that need to be
187 * emitted if frag-prog is dirty vs if vert-prog is dirty..
188 */
189
190 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
191 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
192 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
193 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
194 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
195 * flush some caches? I think we only need to set those
196 * bits if we have updated const or shader..
197 */
198 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
199 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
200 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
201 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
202 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(coord_regid) |
203 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid));
204 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
205 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid));
206 OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(vcoord_regid));
207 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
208 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
209 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
210 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
211 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
212 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
213
214 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
215 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
216 COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
217 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
218 A3XX_SP_SP_CTRL_REG_L0MODE(0));
219
220 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
221 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
222
223 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
224 OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
225 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
226 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
227 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
228 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
229 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
230 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
231 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
232 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
233 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
234 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen - 1, 0)));
235 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
236 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
237 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
238
239 struct ir3_shader_linkage l = {0};
240 ir3_link_shaders(&l, vp, fp, false);
241
242 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
243 uint32_t reg = 0;
244
245 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
246
247 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
248 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
249 j++;
250
251 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
252 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
253 j++;
254
255 OUT_RING(ring, reg);
256 }
257
258 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
259 uint32_t reg = 0;
260
261 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
262
263 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
264 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
265 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
266 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
267
268 OUT_RING(ring, reg);
269 }
270
271 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
272 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
273 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
274 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
275
276 if (emit->binning_pass) {
277 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
278 OUT_RING(ring, 0x00000000);
279
280 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
281 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
282 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
283 OUT_RING(ring, 0x00000000);
284
285 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
286 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
287 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
288 } else {
289 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
290 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
291
292 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
293 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
294 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
295 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
296 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
297 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
298 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
299 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
300 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
301 COND(fp->need_pixlod, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
302 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
303 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
304 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
305 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen - 1, 0)) |
306 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
307
308 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
309 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
310 MAX2(128, vp->constlen)) |
311 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
312 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
313 }
314
315 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
316 OUT_RING(ring,
317 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
318 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
319 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
320
321 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
322 for (i = 0; i < 4; i++) {
323 uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
324 COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
325
326 if (i < nr) {
327 enum pipe_format fmt = pipe_surface_format(bufs[i]);
328 mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
329 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
330 }
331 OUT_RING(ring, mrt_reg);
332 }
333
334 if (emit->binning_pass) {
335 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
336 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
337 A3XX_VPC_ATTR_LMSIZE(1) |
338 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
339 OUT_RING(ring, 0x00000000);
340 } else {
341 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
342
343 memset(vinterp, 0, sizeof(vinterp));
344 memset(flatshade, 0, sizeof(flatshade));
345 memset(vpsrepl, 0, sizeof(vpsrepl));
346
347 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
348 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
349 /* NOTE: varyings are packed, so if compmask is 0xb
350 * then first, third, and fourth component occupy
351 * three consecutive varying slots:
352 */
353 unsigned compmask = fp->inputs[j].compmask;
354
355 uint32_t inloc = fp->inputs[j].inloc;
356
357 if ((fp->inputs[j].interpolate == INTERP_MODE_FLAT) ||
358 (fp->inputs[j].rasterflat && emit->rasterflat)) {
359 uint32_t loc = inloc;
360
361 for (i = 0; i < 4; i++) {
362 if (compmask & (1 << i)) {
363 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
364 flatshade[loc / 32] |= 1 << (loc % 32);
365 loc++;
366 }
367 }
368 }
369
370 bool coord_mode = emit->sprite_coord_mode;
371 if (ir3_point_sprite(fp, j, emit->sprite_coord_enable, &coord_mode)) {
372 /* mask is two 2-bit fields, where:
373 * '01' -> S
374 * '10' -> T
375 * '11' -> 1 - T (flip mode)
376 */
377 unsigned mask = coord_mode ? 0b1101 : 0b1001;
378 uint32_t loc = inloc;
379 if (compmask & 0x1) {
380 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
381 loc++;
382 }
383 if (compmask & 0x2) {
384 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
385 loc++;
386 }
387 if (compmask & 0x4) {
388 /* .z <- 0.0f */
389 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
390 loc++;
391 }
392 if (compmask & 0x8) {
393 /* .w <- 1.0f */
394 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
395 loc++;
396 }
397 }
398 }
399
400 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
401 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
402 A3XX_VPC_ATTR_THRDASSIGN(1) |
403 A3XX_VPC_ATTR_LMSIZE(1) |
404 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
405 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
406 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
407
408 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
409 OUT_RING(ring, vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
410 OUT_RING(ring, vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
411 OUT_RING(ring, vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
412 OUT_RING(ring, vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
413
414 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
415 OUT_RING(ring, vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
416 OUT_RING(ring, vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
417 OUT_RING(ring, vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
418 OUT_RING(ring, vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
419
420 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
421 OUT_RING(ring, flatshade[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
422 OUT_RING(ring, flatshade[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
423 }
424
425 if (vpbuffer == BUFFER)
426 emit_shader(ring, vp);
427
428 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
429 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
430
431 if (!emit->binning_pass) {
432 if (fpbuffer == BUFFER)
433 emit_shader(ring, fp);
434
435 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
436 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
437 }
438 }
439
440 void
441 fd3_prog_init(struct pipe_context *pctx)
442 {
443 ir3_prog_init(pctx);
444 fd_prog_init(pctx);
445 }