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util: Move gallium's PIPE_FORMAT utils to /util/format/
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd4_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
82 }
83 for (i = 0; i < sz; i++) {
84 OUT_RING(ring, dwords[i]);
85 }
86 }
87
88 static void
89 fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
90 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
91 {
92 uint32_t anum = align(num, 4);
93 uint32_t i;
94
95 debug_assert((regid % 4) == 0);
96
97 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
98 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
99 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
100 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
101 CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
102 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
103 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
104
105 for (i = 0; i < num; i++) {
106 if (prscs[i]) {
107 if (write) {
108 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
109 } else {
110 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 }
112 } else {
113 OUT_RING(ring, 0xbad00000 | (i << 16));
114 }
115 }
116
117 for (; i < anum; i++)
118 OUT_RING(ring, 0xffffffff);
119 }
120
121 static void
122 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
123 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
124 const struct ir3_shader_variant *v)
125 {
126 static const uint32_t bcolor_reg[] = {
127 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
128 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
129 };
130 struct fd4_context *fd4_ctx = fd4_context(ctx);
131 bool needs_border = false;
132 unsigned i;
133
134 if (tex->num_samplers > 0) {
135 int num_samplers;
136
137 /* not sure if this is an a420.0 workaround, but we seem
138 * to need to emit these in pairs.. emit a final dummy
139 * entry if odd # of samplers:
140 */
141 num_samplers = align(tex->num_samplers, 2);
142
143 /* output sampler state: */
144 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
145 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
146 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
147 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
148 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
149 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
150 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
151 for (i = 0; i < tex->num_samplers; i++) {
152 static const struct fd4_sampler_stateobj dummy_sampler = {};
153 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
154 fd4_sampler_stateobj(tex->samplers[i]) :
155 &dummy_sampler;
156 OUT_RING(ring, sampler->texsamp0);
157 OUT_RING(ring, sampler->texsamp1);
158
159 needs_border |= sampler->needs_border;
160 }
161
162 for (; i < num_samplers; i++) {
163 OUT_RING(ring, 0x00000000);
164 OUT_RING(ring, 0x00000000);
165 }
166 }
167
168 if (tex->num_textures > 0) {
169 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
170
171 /* emit texture state: */
172 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
173 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
174 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
175 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
176 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
177 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
178 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
179 for (i = 0; i < tex->num_textures; i++) {
180 static const struct fd4_pipe_sampler_view dummy_view = {};
181 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
182 fd4_pipe_sampler_view(tex->textures[i]) :
183 &dummy_view;
184
185 OUT_RING(ring, view->texconst0);
186 OUT_RING(ring, view->texconst1);
187 OUT_RING(ring, view->texconst2);
188 OUT_RING(ring, view->texconst3);
189 if (view->base.texture) {
190 struct fd_resource *rsc = fd_resource(view->base.texture);
191 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
192 rsc = rsc->stencil;
193 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
194 } else {
195 OUT_RING(ring, 0x00000000);
196 }
197 OUT_RING(ring, 0x00000000);
198 OUT_RING(ring, 0x00000000);
199 OUT_RING(ring, 0x00000000);
200 }
201
202 for (i = 0; i < v->astc_srgb.count; i++) {
203 static const struct fd4_pipe_sampler_view dummy_view = {};
204 const struct fd4_pipe_sampler_view *view;
205 unsigned idx = v->astc_srgb.orig_idx[i];
206
207 view = tex->textures[idx] ?
208 fd4_pipe_sampler_view(tex->textures[idx]) :
209 &dummy_view;
210
211 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
212
213 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
214 OUT_RING(ring, view->texconst1);
215 OUT_RING(ring, view->texconst2);
216 OUT_RING(ring, view->texconst3);
217 if (view->base.texture) {
218 struct fd_resource *rsc = fd_resource(view->base.texture);
219 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
220 } else {
221 OUT_RING(ring, 0x00000000);
222 }
223 OUT_RING(ring, 0x00000000);
224 OUT_RING(ring, 0x00000000);
225 OUT_RING(ring, 0x00000000);
226 }
227 } else {
228 debug_assert(v->astc_srgb.count == 0);
229 }
230
231 if (needs_border) {
232 unsigned off;
233 void *ptr;
234
235 u_upload_alloc(fd4_ctx->border_color_uploader,
236 0, BORDER_COLOR_UPLOAD_SIZE,
237 BORDER_COLOR_UPLOAD_SIZE, &off,
238 &fd4_ctx->border_color_buf,
239 &ptr);
240
241 fd_setup_border_colors(tex, ptr, 0);
242 OUT_PKT0(ring, bcolor_reg[sb], 1);
243 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
244
245 u_upload_unmap(fd4_ctx->border_color_uploader);
246 }
247 }
248
249 /* emit texture state for mem->gmem restore operation.. eventually it would
250 * be good to get rid of this and use normal CSO/etc state for more of these
251 * special cases..
252 */
253 void
254 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
255 struct pipe_surface **bufs)
256 {
257 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
258 int i;
259
260 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
261 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
262 }
263
264 /* output sampler state: */
265 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
266 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
267 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
268 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
269 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
270 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
271 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
272 for (i = 0; i < nr_bufs; i++) {
273 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
274 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
275 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
276 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
277 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
278 OUT_RING(ring, 0x00000000);
279 }
280
281 /* emit texture state: */
282 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
283 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
284 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
285 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
286 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
287 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
288 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
289 for (i = 0; i < nr_bufs; i++) {
290 if (bufs[i]) {
291 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
292 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
293
294 /* The restore blit_zs shader expects stencil in sampler 0,
295 * and depth in sampler 1
296 */
297 if (rsc->stencil && (i == 0)) {
298 rsc = rsc->stencil;
299 format = fd_gmem_restore_format(rsc->base.format);
300 }
301
302 /* note: PIPE_BUFFER disallowed for surfaces */
303 unsigned lvl = bufs[i]->u.tex.level;
304 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
305 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
306
307 /* z32 restore is accomplished using depth write. If there is
308 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
309 * then no render target:
310 *
311 * (The same applies for z32_s8x24, since for stencil sampler
312 * state the above 'if' will replace 'format' with s8)
313 */
314 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
315 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
316 mrt_comp[i] = 0;
317
318 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
319
320 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
321 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
322 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
323 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
324 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
325 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
326 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
327 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
328 OUT_RING(ring, 0x00000000);
329 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
330 OUT_RING(ring, 0x00000000);
331 OUT_RING(ring, 0x00000000);
332 OUT_RING(ring, 0x00000000);
333 } else {
334 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
335 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
336 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
337 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
338 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
339 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
340 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
341 A4XX_TEX_CONST_1_HEIGHT(0));
342 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
343 OUT_RING(ring, 0x00000000);
344 OUT_RING(ring, 0x00000000);
345 OUT_RING(ring, 0x00000000);
346 OUT_RING(ring, 0x00000000);
347 OUT_RING(ring, 0x00000000);
348 }
349 }
350
351 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
352 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
353 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
354 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
355 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
356 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
357 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
358 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
359 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
360 }
361
362 void
363 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
364 {
365 int32_t i, j, last = -1;
366 uint32_t total_in = 0;
367 const struct fd_vertex_state *vtx = emit->vtx;
368 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
369 unsigned vertex_regid = regid(63, 0);
370 unsigned instance_regid = regid(63, 0);
371 unsigned vtxcnt_regid = regid(63, 0);
372
373 /* Note that sysvals come *after* normal inputs: */
374 for (i = 0; i < vp->inputs_count; i++) {
375 if (!vp->inputs[i].compmask)
376 continue;
377 if (vp->inputs[i].sysval) {
378 switch(vp->inputs[i].slot) {
379 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
380 vertex_regid = vp->inputs[i].regid;
381 break;
382 case SYSTEM_VALUE_INSTANCE_ID:
383 instance_regid = vp->inputs[i].regid;
384 break;
385 case SYSTEM_VALUE_VERTEX_CNT:
386 vtxcnt_regid = vp->inputs[i].regid;
387 break;
388 default:
389 unreachable("invalid system value");
390 break;
391 }
392 } else if (i < vtx->vtx->num_elements) {
393 last = i;
394 }
395 }
396
397 for (i = 0, j = 0; i <= last; i++) {
398 assert(!vp->inputs[i].sysval);
399 if (vp->inputs[i].compmask) {
400 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
401 const struct pipe_vertex_buffer *vb =
402 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
403 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
404 enum pipe_format pfmt = elem->src_format;
405 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
406 bool switchnext = (i != last) ||
407 (vertex_regid != regid(63, 0)) ||
408 (instance_regid != regid(63, 0)) ||
409 (vtxcnt_regid != regid(63, 0));
410 bool isint = util_format_is_pure_integer(pfmt);
411 uint32_t fs = util_format_get_blocksize(pfmt);
412 uint32_t off = vb->buffer_offset + elem->src_offset;
413 uint32_t size = fd_bo_size(rsc->bo) - off;
414 debug_assert(fmt != ~0);
415
416 #ifdef DEBUG
417 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
418 */
419 if (off > fd_bo_size(rsc->bo))
420 continue;
421 #endif
422
423 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
424 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
425 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
426 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
427 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
428 OUT_RELOC(ring, rsc->bo, off, 0, 0);
429 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
430 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
431
432 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
433 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
434 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
435 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
436 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
437 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
438 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
439 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
440 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
441 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
442
443 total_in += util_bitcount(vp->inputs[i].compmask);
444 j++;
445 }
446 }
447
448 /* hw doesn't like to be configured for zero vbo's, it seems: */
449 if (last < 0) {
450 /* just recycle the shader bo, we just need to point to *something*
451 * valid:
452 */
453 struct fd_bo *dummy_vbo = vp->bo;
454 bool switchnext = (vertex_regid != regid(63, 0)) ||
455 (instance_regid != regid(63, 0)) ||
456 (vtxcnt_regid != regid(63, 0));
457
458 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
459 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
460 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
461 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
462 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
463 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
464 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
465
466 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
467 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
468 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
469 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
470 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
471 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
472 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
473 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
474 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
475
476 total_in = 1;
477 j = 1;
478 }
479
480 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
481 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
482 0xa0000 | /* XXX */
483 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
484 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
485 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
486 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
487 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
488 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
489 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
490 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
491
492 /* cache invalidate, otherwise vertex fetch could see
493 * stale vbo contents:
494 */
495 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
496 OUT_RING(ring, 0x00000000);
497 OUT_RING(ring, 0x00000012);
498 }
499
500 void
501 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
502 struct fd4_emit *emit)
503 {
504 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
505 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
506 const enum fd_dirty_3d_state dirty = emit->dirty;
507
508 emit_marker(ring, 5);
509
510 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
511 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
512 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
513
514 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
515 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
516 }
517
518 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
519 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
520 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
521 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
522 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
523 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
524 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
525 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
526 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
527 }
528
529 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
530 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
531 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
532 uint32_t rb_alpha_control = zsa->rb_alpha_control;
533
534 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
535 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
536
537 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
538 OUT_RING(ring, rb_alpha_control);
539
540 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
541 OUT_RING(ring, zsa->rb_stencil_control);
542 OUT_RING(ring, zsa->rb_stencil_control2);
543 }
544
545 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
546 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
547 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
548
549 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
550 OUT_RING(ring, zsa->rb_stencilrefmask |
551 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
552 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
553 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
554 }
555
556 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
557 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
558 bool fragz = fp->no_earlyz | fp->writes_pos;
559 bool clamp = !ctx->rasterizer->depth_clip_near;
560
561 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
562 OUT_RING(ring, zsa->rb_depth_control |
563 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
564 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
565 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
566
567 /* maybe this register/bitfield needs a better name.. this
568 * appears to be just disabling early-z
569 */
570 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
571 OUT_RING(ring, zsa->gras_alpha_control |
572 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
573 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
574 }
575
576 if (dirty & FD_DIRTY_RASTERIZER) {
577 struct fd4_rasterizer_stateobj *rasterizer =
578 fd4_rasterizer_stateobj(ctx->rasterizer);
579
580 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
581 OUT_RING(ring, rasterizer->gras_su_mode_control |
582 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
583
584 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
585 OUT_RING(ring, rasterizer->gras_su_point_minmax);
586 OUT_RING(ring, rasterizer->gras_su_point_size);
587
588 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
589 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
590 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
591
592 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
593 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
594 }
595
596 /* NOTE: since primitive_restart is not actually part of any
597 * state object, we need to make sure that we always emit
598 * PRIM_VTX_CNTL.. either that or be more clever and detect
599 * when it changes.
600 */
601 if (emit->info) {
602 const struct pipe_draw_info *info = emit->info;
603 struct fd4_rasterizer_stateobj *rast =
604 fd4_rasterizer_stateobj(ctx->rasterizer);
605 uint32_t val = rast->pc_prim_vtx_cntl;
606
607 if (info->index_size && info->primitive_restart)
608 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
609
610 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
611
612 if (fp->total_in > 0) {
613 uint32_t varout = align(fp->total_in, 16) / 16;
614 if (varout > 1)
615 varout = align(varout, 2);
616 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
617 }
618
619 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
620 OUT_RING(ring, val);
621 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
622 }
623
624 /* NOTE: scissor enabled bit is part of rasterizer state: */
625 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
626 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
627
628 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
629 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
630 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
631 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
632 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
633
634 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
635 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
636 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
637 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
638 }
639
640 if (dirty & FD_DIRTY_VIEWPORT) {
641 fd_wfi(ctx->batch, ring);
642 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
643 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
644 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
645 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
646 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
647 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
648 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
649 }
650
651 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
652 float zmin, zmax;
653 int depth = 24;
654 if (ctx->batch->framebuffer.zsbuf) {
655 depth = util_format_get_component_bits(
656 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
657 UTIL_FORMAT_COLORSPACE_ZS, 0);
658 }
659 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
660 &zmin, &zmax);
661
662 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
663 if (depth == 32) {
664 OUT_RING(ring, fui(zmin));
665 OUT_RING(ring, fui(zmax));
666 } else if (depth == 16) {
667 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
668 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
669 } else {
670 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
671 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
672 }
673 }
674
675 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
676 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
677 unsigned n = pfb->nr_cbufs;
678 /* if we have depth/stencil, we need at least on MRT: */
679 if (pfb->zsbuf)
680 n = MAX2(1, n);
681 fd4_program_emit(ring, emit, n, pfb->cbufs);
682 }
683
684 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
685 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
686 if (!emit->binning_pass)
687 ir3_emit_fs_consts(fp, ring, ctx);
688 }
689
690 if ((dirty & FD_DIRTY_BLEND)) {
691 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
692 uint32_t i;
693
694 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
695 enum pipe_format format = pipe_surface_format(
696 ctx->batch->framebuffer.cbufs[i]);
697 bool is_int = util_format_is_pure_integer(format);
698 bool has_alpha = util_format_has_alpha(format);
699 uint32_t control = blend->rb_mrt[i].control;
700 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
701
702 if (is_int) {
703 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
704 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
705 }
706
707 if (has_alpha) {
708 blend_control |= blend->rb_mrt[i].blend_control_rgb;
709 } else {
710 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
711 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
712 }
713
714 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
715 OUT_RING(ring, control);
716
717 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
718 OUT_RING(ring, blend_control);
719 }
720
721 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
722 OUT_RING(ring, blend->rb_fs_output |
723 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
724 }
725
726 if (dirty & FD_DIRTY_BLEND_COLOR) {
727 struct pipe_blend_color *bcolor = &ctx->blend_color;
728
729 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
730 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
731 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
732 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
733 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
734 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
735 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
736 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
737 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
738 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
739 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
740 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
741 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
742 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
743 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
744 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
745 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
746 }
747
748 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
749 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
750
751 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
752 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
753 }
754
755 /* emit setup at begin of new cmdstream buffer (don't rely on previous
756 * state, there could have been a context switch between ioctls):
757 */
758 void
759 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
760 {
761 struct fd_context *ctx = batch->ctx;
762 struct fd4_context *fd4_ctx = fd4_context(ctx);
763
764 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
765 OUT_RING(ring, 0x00000001);
766
767 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
768 OUT_RING(ring, 0x00000000);
769
770 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
771 OUT_RING(ring, 0x00000006);
772
773 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
774 OUT_RING(ring, 0x0000003a);
775
776 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
777 OUT_RING(ring, 0x00000001);
778
779 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
780 OUT_RING(ring, 0x00000000);
781
782 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
783 OUT_RING(ring, 0x00000007);
784
785 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
786 OUT_RING(ring, 0x00000000);
787
788 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
789 OUT_RING(ring, 0x00000000);
790 OUT_RING(ring, 0x00000012);
791
792 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
793 OUT_RING(ring, 0x00000000);
794
795 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
796 OUT_RING(ring, 0x00000006);
797
798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
799 OUT_RING(ring, 0x00000000);
800
801 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
802 OUT_RING(ring, 0x00040000);
803
804 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
805 OUT_RING(ring, 0x00000000);
806
807 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
808 OUT_RING(ring, 0x00001000);
809
810 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
811 OUT_RING(ring, 0x00000000);
812
813 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
814 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
815 A4XX_RB_BLEND_RED_FLOAT(0.0));
816 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
817 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
818 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
819 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
820 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
821 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
822
823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
824 OUT_RING(ring, 0x00000000);
825
826 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
827 OUT_RING(ring, 0x00000000);
828
829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
830 OUT_RING(ring, 0x00000000);
831
832 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
833 OUT_RING(ring, 0x00000000);
834
835 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
836 OUT_RING(ring, 0x00000000);
837
838 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
839 OUT_RING(ring, 0x00000000);
840
841 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
842 OUT_RING(ring, 0x0000001d);
843
844 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
845 OUT_RING(ring, 0x00000000);
846
847 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
848 OUT_RING(ring, 0x00000001);
849
850 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
851 OUT_RING(ring, 0x00000000);
852
853 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
854 OUT_RING(ring, 0x00000000);
855
856 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
857 OUT_RING(ring, 0x00000000);
858
859 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
860 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
861 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
862 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
863 A4XX_TPL1_TP_TEX_COUNT_GS(0));
864
865 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
866 OUT_RING(ring, 16);
867
868 /* we don't use this yet.. probably best to disable.. */
869 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
870 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
871 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
872 CP_SET_DRAW_STATE__0_GROUP_ID(0));
873 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
874
875 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
876 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
877 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
878
879 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
880 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
881 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
882
883 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
884 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
885 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
886 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
887 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
888
889 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
890 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
891 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
892
893 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
894 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
895 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
896
897 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
898 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
899
900 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
901 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
902
903 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
904 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
905
906 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
907 OUT_RING(ring, 0x0);
908
909 fd_hw_query_enable(batch, ring);
910 }
911
912 static void
913 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
914 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
915 unsigned sizedwords)
916 {
917 struct fd_bo *src_bo = fd_resource(src)->bo;
918 struct fd_bo *dst_bo = fd_resource(dst)->bo;
919 unsigned i;
920
921 for (i = 0; i < sizedwords; i++) {
922 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
923 OUT_RING(ring, 0x00000000);
924 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
925 OUT_RELOC (ring, src_bo, src_off, 0, 0);
926
927 dst_off += 4;
928 src_off += 4;
929 }
930 }
931
932 void
933 fd4_emit_init_screen(struct pipe_screen *pscreen)
934 {
935 struct fd_screen *screen = fd_screen(pscreen);
936
937 screen->emit_const = fd4_emit_const;
938 screen->emit_const_bo = fd4_emit_const_bo;
939 screen->emit_ib = fd4_emit_ib;
940 screen->mem_to_mem = fd4_mem_to_mem;
941 }
942
943 void
944 fd4_emit_init(struct pipe_context *pctx)
945 {
946 }