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freedreno: Split ir3_const's user buffer and indirect upload APIs.
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 #define emit_const_user fd4_emit_const_user
47 #define emit_const_bo fd4_emit_const_bo
48 #include "ir3_const.h"
49
50 /* regid: base const register
51 * prsc or dwords: buffer containing constant values
52 * sizedwords: size of const value buffer
53 */
54 static void
55 fd4_emit_const_user(struct fd_ringbuffer *ring,
56 const struct ir3_shader_variant *v, uint32_t regid, uint32_t sizedwords,
57 const uint32_t *dwords)
58 {
59 emit_const_asserts(ring, v, regid, sizedwords);
60
61 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sizedwords);
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
63 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
64 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
65 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
66 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
67 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
68 for (int i = 0; i < sizedwords; i++)
69 OUT_RING(ring, dwords[i]);
70 }
71
72 static void
73 fd4_emit_const_bo(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
74 uint32_t regid, uint32_t offset, uint32_t sizedwords,
75 struct fd_bo *bo)
76 {
77 emit_const_asserts(ring, v, regid, sizedwords);
78
79 OUT_PKT3(ring, CP_LOAD_STATE4, 2);
80 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
81 CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
82 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
83 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
84 OUT_RELOC(ring, bo, offset,
85 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
86 }
87
88 static void
89 fd4_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
90 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
91 {
92 uint32_t anum = align(num, 4);
93 uint32_t i;
94
95 debug_assert((regid % 4) == 0);
96
97 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
98 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
99 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
100 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
101 CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
102 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
103 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
104
105 for (i = 0; i < num; i++) {
106 if (prscs[i]) {
107 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
108 } else {
109 OUT_RING(ring, 0xbad00000 | (i << 16));
110 }
111 }
112
113 for (; i < anum; i++)
114 OUT_RING(ring, 0xffffffff);
115 }
116
117 static bool
118 is_stateobj(struct fd_ringbuffer *ring)
119 {
120 return false;
121 }
122
123 static void
124 emit_const_ptrs(struct fd_ringbuffer *ring,
125 const struct ir3_shader_variant *v, uint32_t dst_offset,
126 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
127 {
128 /* TODO inline this */
129 assert(dst_offset + num <= v->constlen * 4);
130 fd4_emit_const_ptrs(ring, v->type, dst_offset, num, prscs, offsets);
131 }
132
133 static void
134 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
135 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
136 const struct ir3_shader_variant *v)
137 {
138 static const uint32_t bcolor_reg[] = {
139 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
140 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
141 };
142 struct fd4_context *fd4_ctx = fd4_context(ctx);
143 bool needs_border = false;
144 unsigned i;
145
146 if (tex->num_samplers > 0) {
147 int num_samplers;
148
149 /* not sure if this is an a420.0 workaround, but we seem
150 * to need to emit these in pairs.. emit a final dummy
151 * entry if odd # of samplers:
152 */
153 num_samplers = align(tex->num_samplers, 2);
154
155 /* output sampler state: */
156 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
158 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
159 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
160 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
161 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
162 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
163 for (i = 0; i < tex->num_samplers; i++) {
164 static const struct fd4_sampler_stateobj dummy_sampler = {};
165 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
166 fd4_sampler_stateobj(tex->samplers[i]) :
167 &dummy_sampler;
168 OUT_RING(ring, sampler->texsamp0);
169 OUT_RING(ring, sampler->texsamp1);
170
171 needs_border |= sampler->needs_border;
172 }
173
174 for (; i < num_samplers; i++) {
175 OUT_RING(ring, 0x00000000);
176 OUT_RING(ring, 0x00000000);
177 }
178 }
179
180 if (tex->num_textures > 0) {
181 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
182
183 /* emit texture state: */
184 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
185 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
186 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
187 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
188 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
189 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
190 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
191 for (i = 0; i < tex->num_textures; i++) {
192 static const struct fd4_pipe_sampler_view dummy_view = {};
193 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
194 fd4_pipe_sampler_view(tex->textures[i]) :
195 &dummy_view;
196
197 OUT_RING(ring, view->texconst0);
198 OUT_RING(ring, view->texconst1);
199 OUT_RING(ring, view->texconst2);
200 OUT_RING(ring, view->texconst3);
201 if (view->base.texture) {
202 struct fd_resource *rsc = fd_resource(view->base.texture);
203 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
204 rsc = rsc->stencil;
205 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
206 } else {
207 OUT_RING(ring, 0x00000000);
208 }
209 OUT_RING(ring, 0x00000000);
210 OUT_RING(ring, 0x00000000);
211 OUT_RING(ring, 0x00000000);
212 }
213
214 for (i = 0; i < v->astc_srgb.count; i++) {
215 static const struct fd4_pipe_sampler_view dummy_view = {};
216 const struct fd4_pipe_sampler_view *view;
217 unsigned idx = v->astc_srgb.orig_idx[i];
218
219 view = tex->textures[idx] ?
220 fd4_pipe_sampler_view(tex->textures[idx]) :
221 &dummy_view;
222
223 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
224
225 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
226 OUT_RING(ring, view->texconst1);
227 OUT_RING(ring, view->texconst2);
228 OUT_RING(ring, view->texconst3);
229 if (view->base.texture) {
230 struct fd_resource *rsc = fd_resource(view->base.texture);
231 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
232 } else {
233 OUT_RING(ring, 0x00000000);
234 }
235 OUT_RING(ring, 0x00000000);
236 OUT_RING(ring, 0x00000000);
237 OUT_RING(ring, 0x00000000);
238 }
239 } else {
240 debug_assert(v->astc_srgb.count == 0);
241 }
242
243 if (needs_border) {
244 unsigned off;
245 void *ptr;
246
247 u_upload_alloc(fd4_ctx->border_color_uploader,
248 0, BORDER_COLOR_UPLOAD_SIZE,
249 BORDER_COLOR_UPLOAD_SIZE, &off,
250 &fd4_ctx->border_color_buf,
251 &ptr);
252
253 fd_setup_border_colors(tex, ptr, 0);
254 OUT_PKT0(ring, bcolor_reg[sb], 1);
255 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
256
257 u_upload_unmap(fd4_ctx->border_color_uploader);
258 }
259 }
260
261 /* emit texture state for mem->gmem restore operation.. eventually it would
262 * be good to get rid of this and use normal CSO/etc state for more of these
263 * special cases..
264 */
265 void
266 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
267 struct pipe_surface **bufs)
268 {
269 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
270 int i;
271
272 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
273 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
274 }
275
276 /* output sampler state: */
277 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
278 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
279 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
280 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
281 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
282 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
283 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
284 for (i = 0; i < nr_bufs; i++) {
285 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
286 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
287 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
288 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
289 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
290 OUT_RING(ring, 0x00000000);
291 }
292
293 /* emit texture state: */
294 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
295 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
296 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
297 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
298 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
299 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
300 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
301 for (i = 0; i < nr_bufs; i++) {
302 if (bufs[i]) {
303 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
304 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
305
306 /* The restore blit_zs shader expects stencil in sampler 0,
307 * and depth in sampler 1
308 */
309 if (rsc->stencil && (i == 0)) {
310 rsc = rsc->stencil;
311 format = fd_gmem_restore_format(rsc->base.format);
312 }
313
314 /* note: PIPE_BUFFER disallowed for surfaces */
315 unsigned lvl = bufs[i]->u.tex.level;
316 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
317
318 /* z32 restore is accomplished using depth write. If there is
319 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
320 * then no render target:
321 *
322 * (The same applies for z32_s8x24, since for stencil sampler
323 * state the above 'if' will replace 'format' with s8)
324 */
325 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
326 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
327 mrt_comp[i] = 0;
328
329 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
330
331 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
332 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
333 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
334 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
335 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
336 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
337 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)));
338 OUT_RING(ring, 0x00000000);
339 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
340 OUT_RING(ring, 0x00000000);
341 OUT_RING(ring, 0x00000000);
342 OUT_RING(ring, 0x00000000);
343 } else {
344 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
345 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
346 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
347 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
348 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
349 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
350 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
351 A4XX_TEX_CONST_1_HEIGHT(0));
352 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
353 OUT_RING(ring, 0x00000000);
354 OUT_RING(ring, 0x00000000);
355 OUT_RING(ring, 0x00000000);
356 OUT_RING(ring, 0x00000000);
357 OUT_RING(ring, 0x00000000);
358 }
359 }
360
361 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
362 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
363 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
364 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
365 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
366 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
367 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
368 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
369 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
370 }
371
372 void
373 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
374 {
375 int32_t i, j, last = -1;
376 uint32_t total_in = 0;
377 const struct fd_vertex_state *vtx = emit->vtx;
378 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
379 unsigned vertex_regid = regid(63, 0);
380 unsigned instance_regid = regid(63, 0);
381 unsigned vtxcnt_regid = regid(63, 0);
382
383 /* Note that sysvals come *after* normal inputs: */
384 for (i = 0; i < vp->inputs_count; i++) {
385 if (!vp->inputs[i].compmask)
386 continue;
387 if (vp->inputs[i].sysval) {
388 switch(vp->inputs[i].slot) {
389 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
390 vertex_regid = vp->inputs[i].regid;
391 break;
392 case SYSTEM_VALUE_INSTANCE_ID:
393 instance_regid = vp->inputs[i].regid;
394 break;
395 case SYSTEM_VALUE_VERTEX_CNT:
396 vtxcnt_regid = vp->inputs[i].regid;
397 break;
398 default:
399 unreachable("invalid system value");
400 break;
401 }
402 } else if (i < vtx->vtx->num_elements) {
403 last = i;
404 }
405 }
406
407 for (i = 0, j = 0; i <= last; i++) {
408 assert(!vp->inputs[i].sysval);
409 if (vp->inputs[i].compmask) {
410 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
411 const struct pipe_vertex_buffer *vb =
412 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
413 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
414 enum pipe_format pfmt = elem->src_format;
415 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
416 bool switchnext = (i != last) ||
417 (vertex_regid != regid(63, 0)) ||
418 (instance_regid != regid(63, 0)) ||
419 (vtxcnt_regid != regid(63, 0));
420 bool isint = util_format_is_pure_integer(pfmt);
421 uint32_t fs = util_format_get_blocksize(pfmt);
422 uint32_t off = vb->buffer_offset + elem->src_offset;
423 uint32_t size = fd_bo_size(rsc->bo) - off;
424 debug_assert(fmt != VFMT4_NONE);
425
426 #ifdef DEBUG
427 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
428 */
429 if (off > fd_bo_size(rsc->bo))
430 continue;
431 #endif
432
433 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
434 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
435 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
436 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
437 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
438 OUT_RELOC(ring, rsc->bo, off, 0, 0);
439 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
440 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
441
442 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
443 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
444 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
445 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
446 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
447 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
448 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
449 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
450 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
451 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
452
453 total_in += util_bitcount(vp->inputs[i].compmask);
454 j++;
455 }
456 }
457
458 /* hw doesn't like to be configured for zero vbo's, it seems: */
459 if (last < 0) {
460 /* just recycle the shader bo, we just need to point to *something*
461 * valid:
462 */
463 struct fd_bo *dummy_vbo = vp->bo;
464 bool switchnext = (vertex_regid != regid(63, 0)) ||
465 (instance_regid != regid(63, 0)) ||
466 (vtxcnt_regid != regid(63, 0));
467
468 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
469 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
470 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
471 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
472 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
473 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
474 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
475
476 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
477 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
478 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
479 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
480 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
481 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
482 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
483 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
484 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
485
486 total_in = 1;
487 j = 1;
488 }
489
490 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
491 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
492 0xa0000 | /* XXX */
493 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
494 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
495 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
496 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
497 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
498 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
499 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
500 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
501
502 /* cache invalidate, otherwise vertex fetch could see
503 * stale vbo contents:
504 */
505 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
506 OUT_RING(ring, 0x00000000);
507 OUT_RING(ring, 0x00000012);
508 }
509
510 void
511 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
512 struct fd4_emit *emit)
513 {
514 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
515 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
516 const enum fd_dirty_3d_state dirty = emit->dirty;
517
518 emit_marker(ring, 5);
519
520 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
521 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
522 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
523
524 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
525 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
526 }
527
528 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
529 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
530 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
531 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
532 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
533 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
534 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
535 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
536 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
537 }
538
539 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
540 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
541 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
542 uint32_t rb_alpha_control = zsa->rb_alpha_control;
543
544 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
545 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
546
547 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
548 OUT_RING(ring, rb_alpha_control);
549
550 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
551 OUT_RING(ring, zsa->rb_stencil_control);
552 OUT_RING(ring, zsa->rb_stencil_control2);
553 }
554
555 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
556 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
557 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
558
559 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
560 OUT_RING(ring, zsa->rb_stencilrefmask |
561 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
562 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
563 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
564 }
565
566 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
567 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
568 bool fragz = fp->no_earlyz | fp->has_kill | fp->writes_pos;
569 bool clamp = !ctx->rasterizer->depth_clip_near;
570
571 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
572 OUT_RING(ring, zsa->rb_depth_control |
573 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
574 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
575 COND(fragz && fp->fragcoord_compmask != 0,
576 A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
577
578 /* maybe this register/bitfield needs a better name.. this
579 * appears to be just disabling early-z
580 */
581 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
582 OUT_RING(ring, zsa->gras_alpha_control |
583 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
584 COND(fragz && fp->fragcoord_compmask != 0,
585 A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
586 }
587
588 if (dirty & FD_DIRTY_RASTERIZER) {
589 struct fd4_rasterizer_stateobj *rasterizer =
590 fd4_rasterizer_stateobj(ctx->rasterizer);
591
592 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
593 OUT_RING(ring, rasterizer->gras_su_mode_control |
594 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
595
596 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
597 OUT_RING(ring, rasterizer->gras_su_point_minmax);
598 OUT_RING(ring, rasterizer->gras_su_point_size);
599
600 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
601 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
602 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
603 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
604
605 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
606 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
607 }
608
609 /* NOTE: since primitive_restart is not actually part of any
610 * state object, we need to make sure that we always emit
611 * PRIM_VTX_CNTL.. either that or be more clever and detect
612 * when it changes.
613 */
614 if (emit->info) {
615 const struct pipe_draw_info *info = emit->info;
616 struct fd4_rasterizer_stateobj *rast =
617 fd4_rasterizer_stateobj(ctx->rasterizer);
618 uint32_t val = rast->pc_prim_vtx_cntl;
619
620 if (info->index_size && info->primitive_restart)
621 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
622
623 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
624
625 if (fp->total_in > 0) {
626 uint32_t varout = align(fp->total_in, 16) / 16;
627 if (varout > 1)
628 varout = align(varout, 2);
629 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
630 }
631
632 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
633 OUT_RING(ring, val);
634 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
635 }
636
637 /* NOTE: scissor enabled bit is part of rasterizer state: */
638 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
639 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
640
641 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
642 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
643 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
644 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
645 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
646
647 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
648 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
649 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
650 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
651 }
652
653 if (dirty & FD_DIRTY_VIEWPORT) {
654 fd_wfi(ctx->batch, ring);
655 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
656 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
657 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
658 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
659 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
660 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
661 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
662 }
663
664 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
665 float zmin, zmax;
666 int depth = 24;
667 if (ctx->batch->framebuffer.zsbuf) {
668 depth = util_format_get_component_bits(
669 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
670 UTIL_FORMAT_COLORSPACE_ZS, 0);
671 }
672 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
673 &zmin, &zmax);
674
675 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
676 if (depth == 32) {
677 OUT_RING(ring, fui(zmin));
678 OUT_RING(ring, fui(zmax));
679 } else if (depth == 16) {
680 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
681 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
682 } else {
683 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
684 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
685 }
686 }
687
688 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
689 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
690 unsigned n = pfb->nr_cbufs;
691 /* if we have depth/stencil, we need at least on MRT: */
692 if (pfb->zsbuf)
693 n = MAX2(1, n);
694 fd4_program_emit(ring, emit, n, pfb->cbufs);
695 }
696
697 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
698 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
699 if (!emit->binning_pass)
700 ir3_emit_fs_consts(fp, ring, ctx);
701 }
702
703 if ((dirty & FD_DIRTY_BLEND)) {
704 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
705 uint32_t i;
706
707 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
708 enum pipe_format format = pipe_surface_format(
709 ctx->batch->framebuffer.cbufs[i]);
710 bool is_int = util_format_is_pure_integer(format);
711 bool has_alpha = util_format_has_alpha(format);
712 uint32_t control = blend->rb_mrt[i].control;
713
714 if (is_int) {
715 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
716 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
717 }
718
719 if (!has_alpha) {
720 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
721 }
722
723 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
724 OUT_RING(ring, control);
725
726 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
727 OUT_RING(ring, blend->rb_mrt[i].blend_control);
728 }
729
730 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
731 OUT_RING(ring, blend->rb_fs_output |
732 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
733 }
734
735 if (dirty & FD_DIRTY_BLEND_COLOR) {
736 struct pipe_blend_color *bcolor = &ctx->blend_color;
737
738 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
739 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
740 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
741 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
742 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
743 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
744 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
745 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
746 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
747 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
748 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
749 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
750 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
751 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
752 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
753 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
754 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
755 }
756
757 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
758 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
759
760 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
761 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
762 }
763
764 /* emit setup at begin of new cmdstream buffer (don't rely on previous
765 * state, there could have been a context switch between ioctls):
766 */
767 void
768 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
769 {
770 struct fd_context *ctx = batch->ctx;
771 struct fd4_context *fd4_ctx = fd4_context(ctx);
772
773 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
774 OUT_RING(ring, 0x00000001);
775
776 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
777 OUT_RING(ring, 0x00000000);
778
779 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
780 OUT_RING(ring, 0x00000006);
781
782 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
783 OUT_RING(ring, 0x0000003a);
784
785 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
786 OUT_RING(ring, 0x00000001);
787
788 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
789 OUT_RING(ring, 0x00000000);
790
791 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
792 OUT_RING(ring, 0x00000007);
793
794 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
795 OUT_RING(ring, 0x00000000);
796
797 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
798 OUT_RING(ring, 0x00000000);
799 OUT_RING(ring, 0x00000012);
800
801 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
802 OUT_RING(ring, 0x00000000);
803
804 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
805 OUT_RING(ring, 0x00000006);
806
807 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
808 OUT_RING(ring, 0x00000000);
809
810 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
811 OUT_RING(ring, 0x00040000);
812
813 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
814 OUT_RING(ring, 0x00000000);
815
816 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
817 OUT_RING(ring, 0x00001000);
818
819 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
820 OUT_RING(ring, 0x00000000);
821
822 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
823 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
824 A4XX_RB_BLEND_RED_FLOAT(0.0));
825 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
826 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
827 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
828 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
829 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
830 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
831
832 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
833 OUT_RING(ring, 0x00000000);
834
835 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
836 OUT_RING(ring, 0x00000000);
837
838 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
839 OUT_RING(ring, 0x00000000);
840
841 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
842 OUT_RING(ring, 0x00000000);
843
844 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
845 OUT_RING(ring, 0x00000000);
846
847 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
848 OUT_RING(ring, 0x00000000);
849
850 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
851 OUT_RING(ring, 0x0000001d);
852
853 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
854 OUT_RING(ring, 0x00000000);
855
856 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
857 OUT_RING(ring, 0x00000001);
858
859 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
860 OUT_RING(ring, 0x00000000);
861
862 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
863 OUT_RING(ring, 0x00000000);
864
865 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
866 OUT_RING(ring, 0x00000000);
867
868 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
869 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
870 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
871 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
872 A4XX_TPL1_TP_TEX_COUNT_GS(0));
873
874 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
875 OUT_RING(ring, 16);
876
877 /* we don't use this yet.. probably best to disable.. */
878 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
879 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
880 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
881 CP_SET_DRAW_STATE__0_GROUP_ID(0));
882 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
883
884 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
885 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
886 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
887
888 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
889 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
890 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
891
892 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
893 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
894 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
895 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
896 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
897
898 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
899 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
900 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
901
902 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
903 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
904 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
905
906 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
907 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
908
909 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
910 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
911
912 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
913 OUT_RING(ring, 0x0);
914
915 fd_hw_query_enable(batch, ring);
916 }
917
918 static void
919 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
920 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
921 unsigned sizedwords)
922 {
923 struct fd_bo *src_bo = fd_resource(src)->bo;
924 struct fd_bo *dst_bo = fd_resource(dst)->bo;
925 unsigned i;
926
927 for (i = 0; i < sizedwords; i++) {
928 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
929 OUT_RING(ring, 0x00000000);
930 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
931 OUT_RELOC(ring, src_bo, src_off, 0, 0);
932
933 dst_off += 4;
934 src_off += 4;
935 }
936 }
937
938 void
939 fd4_emit_init_screen(struct pipe_screen *pscreen)
940 {
941 struct fd_screen *screen = fd_screen(pscreen);
942
943 screen->emit_ib = fd4_emit_ib;
944 screen->mem_to_mem = fd4_mem_to_mem;
945 }
946
947 void
948 fd4_emit_init(struct pipe_context *pctx)
949 {
950 }