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freedreno/a5xx: fix crash in dEQP-GLES31.stress.vertex_attribute_binding.buffer_bound...
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34 #include "util/u_viewport.h"
35
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd4_emit.h"
40 #include "fd4_blend.h"
41 #include "fd4_context.h"
42 #include "fd4_program.h"
43 #include "fd4_rasterizer.h"
44 #include "fd4_texture.h"
45 #include "fd4_format.h"
46 #include "fd4_zsa.h"
47
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
51 */
52 static void
53 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
54 uint32_t regid, uint32_t offset, uint32_t sizedwords,
55 const uint32_t *dwords, struct pipe_resource *prsc)
56 {
57 uint32_t i, sz;
58 enum a4xx_state_src src;
59
60 debug_assert((regid % 4) == 0);
61 debug_assert((sizedwords % 4) == 0);
62
63 if (prsc) {
64 sz = 0;
65 src = SS4_INDIRECT;
66 } else {
67 sz = sizedwords;
68 src = SS4_DIRECT;
69 }
70
71 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
72 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
73 CP_LOAD_STATE4_0_STATE_SRC(src) |
74 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
75 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
76 if (prsc) {
77 struct fd_bo *bo = fd_resource(prsc)->bo;
78 OUT_RELOC(ring, bo, offset,
79 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
80 } else {
81 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
82 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
83 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
84 }
85 for (i = 0; i < sz; i++) {
86 OUT_RING(ring, dwords[i]);
87 }
88 }
89
90 static void
91 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
92 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
93 {
94 uint32_t anum = align(num, 4);
95 uint32_t i;
96
97 debug_assert((regid % 4) == 0);
98
99 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
100 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
104 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 }
117 }
118
119 for (; i < anum; i++)
120 OUT_RING(ring, 0xffffffff);
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
126 const struct ir3_shader_variant *v)
127 {
128 static const uint32_t bcolor_reg[] = {
129 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
130 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
131 };
132 struct fd4_context *fd4_ctx = fd4_context(ctx);
133 bool needs_border = false;
134 unsigned i;
135
136 if (tex->num_samplers > 0) {
137 int num_samplers;
138
139 /* not sure if this is an a420.0 workaround, but we seem
140 * to need to emit these in pairs.. emit a final dummy
141 * entry if odd # of samplers:
142 */
143 num_samplers = align(tex->num_samplers, 2);
144
145 /* output sampler state: */
146 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
147 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
148 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
149 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
150 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
151 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
152 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
153 for (i = 0; i < tex->num_samplers; i++) {
154 static const struct fd4_sampler_stateobj dummy_sampler = {};
155 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
156 fd4_sampler_stateobj(tex->samplers[i]) :
157 &dummy_sampler;
158 OUT_RING(ring, sampler->texsamp0);
159 OUT_RING(ring, sampler->texsamp1);
160
161 needs_border |= sampler->needs_border;
162 }
163
164 for (; i < num_samplers; i++) {
165 OUT_RING(ring, 0x00000000);
166 OUT_RING(ring, 0x00000000);
167 }
168 }
169
170 if (tex->num_textures > 0) {
171 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
172
173 /* emit texture state: */
174 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
175 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
176 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
177 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
178 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
179 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
180 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
181 for (i = 0; i < tex->num_textures; i++) {
182 static const struct fd4_pipe_sampler_view dummy_view = {};
183 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
184 fd4_pipe_sampler_view(tex->textures[i]) :
185 &dummy_view;
186
187 OUT_RING(ring, view->texconst0);
188 OUT_RING(ring, view->texconst1);
189 OUT_RING(ring, view->texconst2);
190 OUT_RING(ring, view->texconst3);
191 if (view->base.texture) {
192 struct fd_resource *rsc = fd_resource(view->base.texture);
193 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
194 rsc = rsc->stencil;
195 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
196 } else {
197 OUT_RING(ring, 0x00000000);
198 }
199 OUT_RING(ring, 0x00000000);
200 OUT_RING(ring, 0x00000000);
201 OUT_RING(ring, 0x00000000);
202 }
203
204 for (i = 0; i < v->astc_srgb.count; i++) {
205 static const struct fd4_pipe_sampler_view dummy_view = {};
206 const struct fd4_pipe_sampler_view *view;
207 unsigned idx = v->astc_srgb.orig_idx[i];
208
209 view = tex->textures[idx] ?
210 fd4_pipe_sampler_view(tex->textures[idx]) :
211 &dummy_view;
212
213 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
214
215 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
216 OUT_RING(ring, view->texconst1);
217 OUT_RING(ring, view->texconst2);
218 OUT_RING(ring, view->texconst3);
219 if (view->base.texture) {
220 struct fd_resource *rsc = fd_resource(view->base.texture);
221 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
222 } else {
223 OUT_RING(ring, 0x00000000);
224 }
225 OUT_RING(ring, 0x00000000);
226 OUT_RING(ring, 0x00000000);
227 OUT_RING(ring, 0x00000000);
228 }
229 } else {
230 debug_assert(v->astc_srgb.count == 0);
231 }
232
233 if (needs_border) {
234 unsigned off;
235 void *ptr;
236
237 u_upload_alloc(fd4_ctx->border_color_uploader,
238 0, BORDER_COLOR_UPLOAD_SIZE,
239 BORDER_COLOR_UPLOAD_SIZE, &off,
240 &fd4_ctx->border_color_buf,
241 &ptr);
242
243 fd_setup_border_colors(tex, ptr, 0);
244 OUT_PKT0(ring, bcolor_reg[sb], 1);
245 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
246
247 u_upload_unmap(fd4_ctx->border_color_uploader);
248 }
249 }
250
251 /* emit texture state for mem->gmem restore operation.. eventually it would
252 * be good to get rid of this and use normal CSO/etc state for more of these
253 * special cases..
254 */
255 void
256 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
257 struct pipe_surface **bufs)
258 {
259 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
260 int i;
261
262 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
263 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
264 }
265
266 /* output sampler state: */
267 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
268 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
269 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
270 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
271 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
272 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
273 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
274 for (i = 0; i < nr_bufs; i++) {
275 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
276 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
277 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
278 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
279 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
280 OUT_RING(ring, 0x00000000);
281 }
282
283 /* emit texture state: */
284 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
285 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
286 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
287 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
288 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
289 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
290 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
291 for (i = 0; i < nr_bufs; i++) {
292 if (bufs[i]) {
293 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
294 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
295
296 /* The restore blit_zs shader expects stencil in sampler 0,
297 * and depth in sampler 1
298 */
299 if (rsc->stencil && (i == 0)) {
300 rsc = rsc->stencil;
301 format = fd_gmem_restore_format(rsc->base.format);
302 }
303
304 /* note: PIPE_BUFFER disallowed for surfaces */
305 unsigned lvl = bufs[i]->u.tex.level;
306 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
307 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
308
309 /* z32 restore is accomplished using depth write. If there is
310 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
311 * then no render target:
312 *
313 * (The same applies for z32_s8x24, since for stencil sampler
314 * state the above 'if' will replace 'format' with s8)
315 */
316 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
317 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
318 mrt_comp[i] = 0;
319
320 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
321
322 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
323 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
324 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
325 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
326 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
327 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
328 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
329 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
330 OUT_RING(ring, 0x00000000);
331 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
332 OUT_RING(ring, 0x00000000);
333 OUT_RING(ring, 0x00000000);
334 OUT_RING(ring, 0x00000000);
335 } else {
336 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
337 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
338 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
339 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
340 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
341 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
342 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
343 A4XX_TEX_CONST_1_HEIGHT(0));
344 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
345 OUT_RING(ring, 0x00000000);
346 OUT_RING(ring, 0x00000000);
347 OUT_RING(ring, 0x00000000);
348 OUT_RING(ring, 0x00000000);
349 OUT_RING(ring, 0x00000000);
350 }
351 }
352
353 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
354 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
355 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
356 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
357 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
358 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
359 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
360 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
361 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
362 }
363
364 void
365 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
366 {
367 int32_t i, j, last = -1;
368 uint32_t total_in = 0;
369 const struct fd_vertex_state *vtx = emit->vtx;
370 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
371 unsigned vertex_regid = regid(63, 0);
372 unsigned instance_regid = regid(63, 0);
373 unsigned vtxcnt_regid = regid(63, 0);
374
375 /* Note that sysvals come *after* normal inputs: */
376 for (i = 0; i < vp->inputs_count; i++) {
377 if (!vp->inputs[i].compmask)
378 continue;
379 if (vp->inputs[i].sysval) {
380 switch(vp->inputs[i].slot) {
381 case SYSTEM_VALUE_FIRST_VERTEX:
382 /* handled elsewhere */
383 break;
384 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
385 vertex_regid = vp->inputs[i].regid;
386 break;
387 case SYSTEM_VALUE_INSTANCE_ID:
388 instance_regid = vp->inputs[i].regid;
389 break;
390 case SYSTEM_VALUE_VERTEX_CNT:
391 vtxcnt_regid = vp->inputs[i].regid;
392 break;
393 default:
394 unreachable("invalid system value");
395 break;
396 }
397 } else if (i < vtx->vtx->num_elements) {
398 last = i;
399 }
400 }
401
402 for (i = 0, j = 0; i <= last; i++) {
403 assert(!vp->inputs[i].sysval);
404 if (vp->inputs[i].compmask) {
405 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
406 const struct pipe_vertex_buffer *vb =
407 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
408 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
409 enum pipe_format pfmt = elem->src_format;
410 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
411 bool switchnext = (i != last) ||
412 (vertex_regid != regid(63, 0)) ||
413 (instance_regid != regid(63, 0)) ||
414 (vtxcnt_regid != regid(63, 0));
415 bool isint = util_format_is_pure_integer(pfmt);
416 uint32_t fs = util_format_get_blocksize(pfmt);
417 uint32_t off = vb->buffer_offset + elem->src_offset;
418 uint32_t size = fd_bo_size(rsc->bo) - off;
419 debug_assert(fmt != ~0);
420
421 #ifdef DEBUG
422 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
423 */
424 if (off > fd_bo_size(rsc->bo))
425 continue;
426 #endif
427
428 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
429 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
430 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
431 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
432 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
433 OUT_RELOC(ring, rsc->bo, off, 0, 0);
434 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
435 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
436
437 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
438 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
439 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
440 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
441 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
442 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
443 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
444 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
445 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
446 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
447
448 total_in += vp->inputs[i].ncomp;
449 j++;
450 }
451 }
452
453 /* hw doesn't like to be configured for zero vbo's, it seems: */
454 if (last < 0) {
455 /* just recycle the shader bo, we just need to point to *something*
456 * valid:
457 */
458 struct fd_bo *dummy_vbo = vp->bo;
459 bool switchnext = (vertex_regid != regid(63, 0)) ||
460 (instance_regid != regid(63, 0)) ||
461 (vtxcnt_regid != regid(63, 0));
462
463 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
464 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
465 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
466 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
467 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
468 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
469 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
470
471 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
472 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
473 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
474 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
475 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
476 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
477 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
478 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
479 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
480
481 total_in = 1;
482 j = 1;
483 }
484
485 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
486 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
487 0xa0000 | /* XXX */
488 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
489 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
490 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
491 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
492 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
493 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
494 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
495 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
496
497 /* cache invalidate, otherwise vertex fetch could see
498 * stale vbo contents:
499 */
500 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
501 OUT_RING(ring, 0x00000000);
502 OUT_RING(ring, 0x00000012);
503 }
504
505 void
506 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
507 struct fd4_emit *emit)
508 {
509 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
510 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
511 const enum fd_dirty_3d_state dirty = emit->dirty;
512
513 emit_marker(ring, 5);
514
515 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
516 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
517 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
518
519 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
520 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
521 }
522
523 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
524 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
525 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
526 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
527 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
528 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
529 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
530 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
531 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
532 }
533
534 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
535 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
536 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
537 uint32_t rb_alpha_control = zsa->rb_alpha_control;
538
539 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
540 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
541
542 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
543 OUT_RING(ring, rb_alpha_control);
544
545 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
546 OUT_RING(ring, zsa->rb_stencil_control);
547 OUT_RING(ring, zsa->rb_stencil_control2);
548 }
549
550 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
551 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
552 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
553
554 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
555 OUT_RING(ring, zsa->rb_stencilrefmask |
556 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
557 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
558 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
559 }
560
561 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
562 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
563 bool fragz = fp->has_kill | fp->writes_pos;
564 bool clamp = !ctx->rasterizer->depth_clip;
565
566 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
567 OUT_RING(ring, zsa->rb_depth_control |
568 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
569 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
570 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
571
572 /* maybe this register/bitfield needs a better name.. this
573 * appears to be just disabling early-z
574 */
575 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
576 OUT_RING(ring, zsa->gras_alpha_control |
577 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
578 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
579 }
580
581 if (dirty & FD_DIRTY_RASTERIZER) {
582 struct fd4_rasterizer_stateobj *rasterizer =
583 fd4_rasterizer_stateobj(ctx->rasterizer);
584
585 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
586 OUT_RING(ring, rasterizer->gras_su_mode_control |
587 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
588
589 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
590 OUT_RING(ring, rasterizer->gras_su_point_minmax);
591 OUT_RING(ring, rasterizer->gras_su_point_size);
592
593 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
594 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
595 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
596
597 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
598 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
599 }
600
601 /* NOTE: since primitive_restart is not actually part of any
602 * state object, we need to make sure that we always emit
603 * PRIM_VTX_CNTL.. either that or be more clever and detect
604 * when it changes.
605 */
606 if (emit->info) {
607 const struct pipe_draw_info *info = emit->info;
608 struct fd4_rasterizer_stateobj *rast =
609 fd4_rasterizer_stateobj(ctx->rasterizer);
610 uint32_t val = rast->pc_prim_vtx_cntl;
611
612 if (info->index_size && info->primitive_restart)
613 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
614
615 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
616
617 if (fp->total_in > 0) {
618 uint32_t varout = align(fp->total_in, 16) / 16;
619 if (varout > 1)
620 varout = align(varout, 2);
621 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
622 }
623
624 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
625 OUT_RING(ring, val);
626 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
627 }
628
629 if (dirty & FD_DIRTY_SCISSOR) {
630 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
631
632 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
633 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
634 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
635 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
636 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
637
638 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
639 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
640 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
641 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
642 }
643
644 if (dirty & FD_DIRTY_VIEWPORT) {
645 fd_wfi(ctx->batch, ring);
646 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
647 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
648 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
649 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
650 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
651 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
652 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
653 }
654
655 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
656 float zmin, zmax;
657 int depth = 24;
658 if (ctx->batch->framebuffer.zsbuf) {
659 depth = util_format_get_component_bits(
660 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
661 UTIL_FORMAT_COLORSPACE_ZS, 0);
662 }
663 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
664 &zmin, &zmax);
665
666 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
667 if (depth == 32) {
668 OUT_RING(ring, fui(zmin));
669 OUT_RING(ring, fui(zmax));
670 } else if (depth == 16) {
671 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
672 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
673 } else {
674 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
675 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
676 }
677 }
678
679 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
680 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
681 unsigned n = pfb->nr_cbufs;
682 /* if we have depth/stencil, we need at least on MRT: */
683 if (pfb->zsbuf)
684 n = MAX2(1, n);
685 fd4_program_emit(ring, emit, n, pfb->cbufs);
686 }
687
688 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
689 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
690 if (!emit->key.binning_pass)
691 ir3_emit_fs_consts(fp, ring, ctx);
692 }
693
694 if ((dirty & FD_DIRTY_BLEND)) {
695 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
696 uint32_t i;
697
698 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
699 enum pipe_format format = pipe_surface_format(
700 ctx->batch->framebuffer.cbufs[i]);
701 bool is_int = util_format_is_pure_integer(format);
702 bool has_alpha = util_format_has_alpha(format);
703 uint32_t control = blend->rb_mrt[i].control;
704 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
705
706 if (is_int) {
707 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
708 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
709 }
710
711 if (has_alpha) {
712 blend_control |= blend->rb_mrt[i].blend_control_rgb;
713 } else {
714 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
715 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
716 }
717
718 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
719 OUT_RING(ring, control);
720
721 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
722 OUT_RING(ring, blend_control);
723 }
724
725 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
726 OUT_RING(ring, blend->rb_fs_output |
727 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
728 }
729
730 if (dirty & FD_DIRTY_BLEND_COLOR) {
731 struct pipe_blend_color *bcolor = &ctx->blend_color;
732
733 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
734 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
735 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
736 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
737 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
738 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
739 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
740 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
741 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
742 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
743 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
744 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
745 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
746 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
747 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
748 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
749 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
750 }
751
752 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
753 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
754
755 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
756 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
757 }
758
759 /* emit setup at begin of new cmdstream buffer (don't rely on previous
760 * state, there could have been a context switch between ioctls):
761 */
762 void
763 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
764 {
765 struct fd_context *ctx = batch->ctx;
766 struct fd4_context *fd4_ctx = fd4_context(ctx);
767
768 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
769 OUT_RING(ring, 0x00000001);
770
771 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
772 OUT_RING(ring, 0x00000000);
773
774 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
775 OUT_RING(ring, 0x00000006);
776
777 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
778 OUT_RING(ring, 0x0000003a);
779
780 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
781 OUT_RING(ring, 0x00000001);
782
783 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
784 OUT_RING(ring, 0x00000000);
785
786 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
787 OUT_RING(ring, 0x00000007);
788
789 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
790 OUT_RING(ring, 0x00000000);
791
792 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
793 OUT_RING(ring, 0x00000000);
794 OUT_RING(ring, 0x00000012);
795
796 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
797 OUT_RING(ring, 0x00000000);
798
799 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
800 OUT_RING(ring, 0x00000006);
801
802 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
803 OUT_RING(ring, 0x00000000);
804
805 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
806 OUT_RING(ring, 0x00040000);
807
808 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
809 OUT_RING(ring, 0x00000000);
810
811 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
812 OUT_RING(ring, 0x00001000);
813
814 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
815 OUT_RING(ring, 0x00000000);
816
817 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
818 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
819 A4XX_RB_BLEND_RED_FLOAT(0.0));
820 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
821 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
822 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
823 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
824 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
825 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
826
827 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
828 OUT_RING(ring, 0x00000000);
829
830 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
831 OUT_RING(ring, 0x00000000);
832
833 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
834 OUT_RING(ring, 0x00000000);
835
836 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
837 OUT_RING(ring, 0x00000000);
838
839 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
840 OUT_RING(ring, 0x00000000);
841
842 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
843 OUT_RING(ring, 0x00000000);
844
845 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
846 OUT_RING(ring, 0x0000001d);
847
848 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
849 OUT_RING(ring, 0x00000000);
850
851 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
852 OUT_RING(ring, 0x00000001);
853
854 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
855 OUT_RING(ring, 0x00000000);
856
857 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
858 OUT_RING(ring, 0x00000000);
859
860 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
861 OUT_RING(ring, 0x00000000);
862
863 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
864 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
865 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
866 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
867 A4XX_TPL1_TP_TEX_COUNT_GS(0));
868
869 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
870 OUT_RING(ring, 16);
871
872 /* we don't use this yet.. probably best to disable.. */
873 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
874 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
875 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
876 CP_SET_DRAW_STATE__0_GROUP_ID(0));
877 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
878
879 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
880 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
881 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
882
883 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
884 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
885 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
886
887 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
888 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
889 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
890 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
891 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
892
893 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
894 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
895 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
896
897 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
898 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
899 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
900
901 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
902 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
903
904 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
905 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
906
907 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
908 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
909
910 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
911 OUT_RING(ring, 0x0);
912
913 fd_hw_query_enable(batch, ring);
914 }
915
916 static void
917 fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
918 {
919 __OUT_IB(ring, true, target);
920 }
921
922 static void
923 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
924 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
925 unsigned sizedwords)
926 {
927 struct fd_bo *src_bo = fd_resource(src)->bo;
928 struct fd_bo *dst_bo = fd_resource(dst)->bo;
929 unsigned i;
930
931 for (i = 0; i < sizedwords; i++) {
932 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
933 OUT_RING(ring, 0x00000000);
934 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
935 OUT_RELOC (ring, src_bo, src_off, 0, 0);
936
937 dst_off += 4;
938 src_off += 4;
939 }
940 }
941
942 void
943 fd4_emit_init(struct pipe_context *pctx)
944 {
945 struct fd_context *ctx = fd_context(pctx);
946 ctx->emit_const = fd4_emit_const;
947 ctx->emit_const_bo = fd4_emit_const_bo;
948 ctx->emit_ib = fd4_emit_ib;
949 ctx->mem_to_mem = fd4_mem_to_mem;
950 }